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([2a00:5f00:102:0:6e1d:cfb9:fb12:552d]) by smtp.gmail.com with ESMTPSA id 12sm4714200wmw.43.2021.03.31.10.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 10:35:31 -0700 (PDT) From: Emil Velikov To: kernel@collabora.com, Ezequiel Garcia , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org Cc: emil.l.velikov@gmail.com Subject: [PATCH v3 4/9] media: hantro: imx: remove unused include Date: Wed, 31 Mar 2021 18:35:15 +0100 Message-Id: <20210331173520.184191-5-emil.l.velikov@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210331173520.184191-1-emil.l.velikov@gmail.com> References: <20210331173520.184191-1-emil.l.velikov@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Emil Velikov The current imx8 code does not use the jpeg encoder. Remove the unnecessary include. Fixes: 8e4aaa687863 ("media: hantro: add initial i.MX8MQ support") Acked-by: Nicolas Ferre Reviewed-by: Ezequiel Garcia Reviewed-by: Philipp Zabel Signed-off-by: Emil Velikov --- drivers/staging/media/hantro/imx8m_vpu_hw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index cb1ac02c03d2..f36c1bd681ba 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -9,7 +9,6 @@ #include #include "hantro.h" -#include "hantro_jpeg.h" #include "hantro_g1_regs.h" #define CTRL_SOFT_RESET 0x00 From patchwork Wed Mar 31 17:35:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Velikov X-Patchwork-Id: 413194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0B4BC41602 for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B84E460BD3 for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234573AbhCaRfz (ORCPT ); Wed, 31 Mar 2021 13:35:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234446AbhCaRfe (ORCPT ); Wed, 31 Mar 2021 13:35:34 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BFC6C06175F; Wed, 31 Mar 2021 10:35:34 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 12so10534964wmf.5; Wed, 31 Mar 2021 10:35:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=//s5GXhvTYBFxepTOFjvgKPgNSSVEMfEdoDacbVrJhc=; b=XBrvV9n9AJs9E1BQhtZDtrXx9UpPAV1l5vJVBJuXc1GAQybpM5RG1ww0MM+Sml9UHZ jmusbG5SOFtjUCYUzWuUMwj5lyhlUGKvo4pboTUn/DLDzg3s2OA0B7MzDYIEmmqFtTDy LaXuOxrWpq3wl8W9V6lUH3h5evqrUSID90vcNfv9AJSSO+p+KFz1y7ufuu/LJECD3XVb DFJ79iC3Q2h/zTYgCn2fEFa7UgvZEG9xYoZwbG3KKZsaO+C6L2t9WwWo+6rDRHn1aYpi wHLbCxkkfZmSEDNVB+9Av6qnTaYjpEkl2SX+G1kCDdxv8T6r9rNCnppPLGfn+g/fL/Ah rKFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=//s5GXhvTYBFxepTOFjvgKPgNSSVEMfEdoDacbVrJhc=; b=V+NBPk58Fc4KcdJ+/8Pc1aTOXGcIY5rUdsfRurOuR9hC2vzlccLKRy86VdjRIMDoF/ /XPvnzwdCyskqLxTOd4sAoA/8qcr3pX+npN6U0+fx5RMQbScnv01HyVPK01eyBRZpHa/ NCWpyNywOyt/mHWTxr51Ruh3qb/HMKSIep+yNoDHbbl5zJC/tmYVO/E1i2m7y4Dhz+Nz Mt4ZTmvS+f4c4vft/R3V++WXg54/NuejVISQWx/OHJ+a7ZlofluNEn7ijqbGIMx4cuBV WURQg14qZo0GAtCnyTqpgDtVwNwNlG8ma6wiW4+zzmNarWqkJ713nLvg06aLgQ2zxnH0 CbYQ== X-Gm-Message-State: AOAM530fMLACWUxAz1IJcoggCK+/pQ+E6CgmS+rct+8Adn6MkWhe/pYe EgeRSzy8g1VsZhfJ6YIS3lE= X-Google-Smtp-Source: ABdhPJzpzfKHxYuDZOzO1iYSTGNXPrAYAW6UZYmlK180CUi/eQ+P1EHAiW89z9OPL70TzMXluujRBQ== X-Received: by 2002:a1c:43c5:: with SMTP id q188mr4098708wma.94.1617212132991; Wed, 31 Mar 2021 10:35:32 -0700 (PDT) Received: from arch-x1c3.. ([2a00:5f00:102:0:6e1d:cfb9:fb12:552d]) by smtp.gmail.com with ESMTPSA id 12sm4714200wmw.43.2021.03.31.10.35.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 10:35:32 -0700 (PDT) From: Emil Velikov To: kernel@collabora.com, Ezequiel Garcia , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org Cc: emil.l.velikov@gmail.com Subject: [PATCH v3 5/9] media: hantro: introduce hantro_g1.c for common API Date: Wed, 31 Mar 2021 18:35:16 +0100 Message-Id: <20210331173520.184191-6-emil.l.velikov@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210331173520.184191-1-emil.l.velikov@gmail.com> References: <20210331173520.184191-1-emil.l.velikov@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Emil Velikov The Hantro G1 IRQ and reset handling it pretty standard. I was this close to duplicating it, yet again, before reconsidering and refactoring it to a separate file. Acked-by: Nicolas Ferre Reviewed-by: Ezequiel Garcia Reviewed-by: Philipp Zabel Signed-off-by: Emil Velikov --- drivers/staging/media/hantro/Makefile | 1 + drivers/staging/media/hantro/hantro_g1.c | 39 ++++++++++++++++++++ drivers/staging/media/hantro/hantro_hw.h | 3 ++ drivers/staging/media/hantro/imx8m_vpu_hw.c | 21 +---------- drivers/staging/media/hantro/rk3288_vpu_hw.c | 36 ++---------------- 5 files changed, 48 insertions(+), 52 deletions(-) create mode 100644 drivers/staging/media/hantro/hantro_g1.c diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile index 743ce08eb184..3747a32799b2 100644 --- a/drivers/staging/media/hantro/Makefile +++ b/drivers/staging/media/hantro/Makefile @@ -7,6 +7,7 @@ hantro-vpu-y += \ hantro_v4l2.o \ hantro_postproc.o \ hantro_h1_jpeg_enc.o \ + hantro_g1.o \ hantro_g1_h264_dec.o \ hantro_g1_mpeg2_dec.o \ hantro_g1_vp8_dec.o \ diff --git a/drivers/staging/media/hantro/hantro_g1.c b/drivers/staging/media/hantro/hantro_g1.c new file mode 100644 index 000000000000..0ab1cee62218 --- /dev/null +++ b/drivers/staging/media/hantro/hantro_g1.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hantro VPU codec driver + * + * Copyright (C) 2018 Rockchip Electronics Co., Ltd. + * Jeffy Chen + * Copyright (C) 2019 Pengutronix, Philipp Zabel + * Copyright (C) 2021 Collabora Ltd, Emil Velikov + */ + +#include "hantro.h" +#include "hantro_g1_regs.h" + +irqreturn_t hantro_g1_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status; + + status = vdpu_read(vpu, G1_REG_INTERRUPT); + state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vdpu_write(vpu, 0, G1_REG_INTERRUPT); + vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + +void hantro_g1_reset(struct hantro_ctx *ctx) +{ + struct hantro_dev *vpu = ctx->dev; + + vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); + vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); + vdpu_write(vpu, 1, G1_REG_SOFT_RESET); +} diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 34c9e4649a25..73c71bb2320c 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -164,6 +164,9 @@ void hantro_irq_done(struct hantro_dev *vpu, void hantro_start_prepare_run(struct hantro_ctx *ctx); void hantro_end_prepare_run(struct hantro_ctx *ctx); +irqreturn_t hantro_g1_irq(int irq, void *dev_id); +void hantro_g1_reset(struct hantro_ctx *ctx); + void hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx); void rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx); int hantro_jpeg_enc_init(struct hantro_ctx *ctx); diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index f36c1bd681ba..9eb556460e52 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -9,7 +9,6 @@ #include #include "hantro.h" -#include "hantro_g1_regs.h" #define CTRL_SOFT_RESET 0x00 #define RESET_G1 BIT(1) @@ -129,24 +128,6 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { }, }; -static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) -{ - struct hantro_dev *vpu = dev_id; - enum vb2_buffer_state state; - u32 status; - - status = vdpu_read(vpu, G1_REG_INTERRUPT); - state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - - vdpu_write(vpu, 0, G1_REG_INTERRUPT); - vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); - - hantro_irq_done(vpu, state); - - return IRQ_HANDLED; -} - static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) { vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; @@ -191,7 +172,7 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { */ static const struct hantro_irq imx8mq_irqs[] = { - { "g1", imx8m_vpu_g1_irq }, + { "g1", hantro_g1_irq }, { "g2", NULL /* TODO: imx8m_vpu_g2_irq */ }, }; diff --git a/drivers/staging/media/hantro/rk3288_vpu_hw.c b/drivers/staging/media/hantro/rk3288_vpu_hw.c index 7b299ee3e93d..fefd45269e52 100644 --- a/drivers/staging/media/hantro/rk3288_vpu_hw.c +++ b/drivers/staging/media/hantro/rk3288_vpu_hw.c @@ -10,7 +10,6 @@ #include "hantro.h" #include "hantro_jpeg.h" -#include "hantro_g1_regs.h" #include "hantro_h1_regs.h" #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) @@ -127,24 +126,6 @@ static irqreturn_t rk3288_vepu_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static irqreturn_t rk3288_vdpu_irq(int irq, void *dev_id) -{ - struct hantro_dev *vpu = dev_id; - enum vb2_buffer_state state; - u32 status; - - status = vdpu_read(vpu, G1_REG_INTERRUPT); - state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - - vdpu_write(vpu, 0, G1_REG_INTERRUPT); - vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); - - hantro_irq_done(vpu, state); - - return IRQ_HANDLED; -} - static int rk3288_vpu_hw_init(struct hantro_dev *vpu) { /* Bump ACLK to max. possible freq. to improve performance. */ @@ -161,15 +142,6 @@ static void rk3288_vpu_enc_reset(struct hantro_ctx *ctx) vepu_write(vpu, 0, H1_REG_AXI_CTRL); } -static void rk3288_vpu_dec_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); - vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); - vdpu_write(vpu, 1, G1_REG_SOFT_RESET); -} - /* * Supported codec ops. */ @@ -184,19 +156,19 @@ static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = { }, [HANTRO_MODE_H264_DEC] = { .run = hantro_g1_h264_dec_run, - .reset = rk3288_vpu_dec_reset, + .reset = hantro_g1_reset, .init = hantro_h264_dec_init, .exit = hantro_h264_dec_exit, }, [HANTRO_MODE_MPEG2_DEC] = { .run = hantro_g1_mpeg2_dec_run, - .reset = rk3288_vpu_dec_reset, + .reset = hantro_g1_reset, .init = hantro_mpeg2_dec_init, .exit = hantro_mpeg2_dec_exit, }, [HANTRO_MODE_VP8_DEC] = { .run = hantro_g1_vp8_dec_run, - .reset = rk3288_vpu_dec_reset, + .reset = hantro_g1_reset, .init = hantro_vp8_dec_init, .exit = hantro_vp8_dec_exit, }, @@ -208,7 +180,7 @@ static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = { static const struct hantro_irq rk3288_irqs[] = { { "vepu", rk3288_vepu_irq }, - { "vdpu", rk3288_vdpu_irq }, + { "vdpu", hantro_g1_irq }, }; static const char * const rk3288_clk_names[] = { From patchwork Wed Mar 31 17:35:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Velikov X-Patchwork-Id: 413197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81BC4C4363E for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A2F2610A6 for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234565AbhCaRfz (ORCPT ); Wed, 31 Mar 2021 13:35:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234461AbhCaRfg (ORCPT ); Wed, 31 Mar 2021 13:35:36 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B044C061574; Wed, 31 Mar 2021 10:35:35 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id 12so10534990wmf.5; Wed, 31 Mar 2021 10:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J9QCFckIBAkkMW1HuLQ0Z2D0zukJHxh0rMMA4ARv74o=; b=f7R36IW85JWA3JM042Skzgg63r58U6OiRJmQQL27JFIs4cRGODXhJfXNzD4sR8i1uI I7YT2w1oS7c5gYWglNWdHY43r2LiMDwS4xe7bJottqtAmbwNSlassjVBYxHwjwstxi+j C560wdT4Ksq7xUP6FIKD6W5ktb9QWn4kiJC4PS6Jn0gVunUphGGI2iyZVniPbVBlI8ki cpJTDRN+HwRAocWtNeCCEP+vBbgn0t+RcaAvfdx2r5m+DO/7lV9+OMc9UWdC+gepF+7t wZeTtLFi6CZ2b1ungtOpxJQSfHppxZoefa8rIV7uw1QKJPb+LqalLvYx0w0LVHHDbUAh QTsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J9QCFckIBAkkMW1HuLQ0Z2D0zukJHxh0rMMA4ARv74o=; b=JSqFMvtZkjSndvF1hTKWWEUoOVyCvJw4bb2/TcJB2BRO2YCEW9Y1NKbs8K3cGnNvJq qG8JfBpz+vXZkYzmIL5Qfi7ekeojhTvs9PR8t0f5n408x0N9f58d1WSTD884NFyfF3zF lhzSJoIf9FJbqoLcX8ITxkugf4g+R2kOp5N2VhMERL8TXFC6qcO5aqqT16e4mHY5GwgT YptzcRMGdQvSXo5fYTXi5jpHN4jptpE+YXdsneKgZJDrFPXO1PFBNTgUMhe4uhQia8G+ NyuKJOpcf3IL5g9tgivIf5KIQ2fyDj/gWSxZ3leobpmXZehAKp3aOEEQS9ECOxZVL6kK 1Lig== X-Gm-Message-State: AOAM531xIH0UKBPhWVMZs7hdnvG6ened4Cf4lD0YU/qXcN2+y/YkhNj3 SZcfTWp3+q6GtcVw3+cdIig= X-Google-Smtp-Source: ABdhPJwLSOnWotXARo97qgnF3BxfFU0WQJclwokJkmXaXHWELQ/+b91woIYyzgHcow8388aMYut9kg== X-Received: by 2002:a05:600c:3515:: with SMTP id h21mr4194328wmq.9.1617212134195; Wed, 31 Mar 2021 10:35:34 -0700 (PDT) Received: from arch-x1c3.. ([2a00:5f00:102:0:6e1d:cfb9:fb12:552d]) by smtp.gmail.com with ESMTPSA id 12sm4714200wmw.43.2021.03.31.10.35.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 10:35:33 -0700 (PDT) From: Emil Velikov To: kernel@collabora.com, Ezequiel Garcia , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org Cc: emil.l.velikov@gmail.com Subject: [PATCH v3 6/9] media: hantro: add fallback handling for single irq/clk Date: Wed, 31 Mar 2021 18:35:17 +0100 Message-Id: <20210331173520.184191-7-emil.l.velikov@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210331173520.184191-1-emil.l.velikov@gmail.com> References: <20210331173520.184191-1-emil.l.velikov@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Emil Velikov Currently the driver expects that each irq/clk will have a name specified. A valid point was raised by the DT maintainers - when there is a single interrupt line or clock - the names are not needed. This is handled: - clk - implicitly - ultimately we'll call of_clk_get_hw(..., 0, NULL which will get the first clock from the pmc - irq - explicitly - platform_get_irq(..., 0) To gracefully handle potential bugs, add respective WARN_ON() if we're having more than one irq/clk, yet lacking the respective names. Acked-by: Nicolas Ferre Suggested-by: Ezequiel Garcia Signed-off-by: Emil Velikov --- v3 - New patch --- drivers/staging/media/hantro/hantro_drv.c | 24 +++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index e5f200e64993..d1294eb9cd07 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -752,8 +752,16 @@ static int hantro_probe(struct platform_device *pdev) if (!vpu->clocks) return -ENOMEM; - for (i = 0; i < vpu->variant->num_clocks; i++) + for (i = 0; i < vpu->variant->num_clocks; i++) { vpu->clocks[i].id = vpu->variant->clk_names[i]; + + /* + * Warn and refuse to load if the driver has multiple clocks, + * yet they are lacking the respective names. + */ + if (WARN_ON(!vpu->variant->clk_names[i] && i)) + return -ENXIO; + } ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks, vpu->clocks); if (ret) @@ -791,7 +799,19 @@ static int hantro_probe(struct platform_device *pdev) if (!vpu->variant->irqs[i].handler) continue; - irq = platform_get_irq_byname(vpu->pdev, irq_name); + /* + * If the driver has a single IRQ, chances are there will be no + * actual name in the DT bindings. + */ + if (!irq_name) { + if (WARN_ON(i)) + return -ENXIO; + + irq_name = "default"; + irq = platform_get_irq(vpu->pdev, 0); + } else { + irq = platform_get_irq_byname(vpu->pdev, irq_name); + } if (irq <= 0) return -ENXIO; From patchwork Wed Mar 31 17:35:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Velikov X-Patchwork-Id: 413196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C96AEC4363F for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9E2CF61090 for ; Wed, 31 Mar 2021 17:36:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234580AbhCaRf4 (ORCPT ); Wed, 31 Mar 2021 13:35:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234471AbhCaRfi (ORCPT ); Wed, 31 Mar 2021 13:35:38 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F727C061574; Wed, 31 Mar 2021 10:35:38 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id j4-20020a05600c4104b029010c62bc1e20so1551905wmi.3; Wed, 31 Mar 2021 10:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mAneJlrkY4/IZLQNpt5ahOvEPFy19jWwGdcAjZr3nhE=; b=YmtZQ+LunBSbH82nppx0e1AHv/erPdAV4rYhHMfTZm5/5CB1E3qrRmqrE980tmzGNR wXzZjOHx2GUc+HKIElUWHVymFNmLAIF6i+kNbkOVhrYDrfmgoOwl8N99OtJg1/Y9Q8pu Tr8+IwMJudTRE3xQE+6S9s+psA2EwSL5m4CKNXrvZde05MYUxqbE7wO3Otlz0aXn43OV 6tmMHep/dQZs8QfM+1Vc7j4vl9uVo4Gio2lCukWS1FcBezTZ5SUm8dqQ5xbdyMOSVWIo 6JtQsaIMJO9CF5yWEaeWuiy92EivH7uyscpg4VxO5AKTPwlURVKbnDJF4XDa9Og89ZJu WSrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mAneJlrkY4/IZLQNpt5ahOvEPFy19jWwGdcAjZr3nhE=; b=sbjwVxPAsgUwQ3lsknX5jlCqzUIuaR5pnP4BOKsulzndp2Xq3gnm/iG0qk15DzoylX y1SvQU0hMnrCYxURdb/apN0rP1YN4+bSUXXjkMA1JflqWoAmG28OCF8E2S4JV9UY8kqp L06IVoS3T2EQWbac2qsLtGUNuE+yihPKawf0Dqpxhqrs3B7qeVXRFtEtdqLn8Vak/1Cx 7HGapwN3dzAEu1YB3dcGPbTANFT0RTaFPVbz51b9el9ejw9ooPj6sHJoEs/bLpaxShZ/ lO/ZXW2q67n5Ub4GqJPq3DcNrMSxQiDazFLk31dWc2r2jsqosfkR2cmZJ2pMtDkbDvDJ udOw== X-Gm-Message-State: AOAM533RRnLUeRw8Leh8Nw1wploV03YwMzBwrk6JlGnzu0sJ8rgdSDq7 0CRO+e6CkcD1XiKCMO564v0= X-Google-Smtp-Source: ABdhPJzlxACnhIRQ+AXKJJI1GcyjjGziE0R7NWal5rREJt1JXk2twRrZNDdgHHf0WjBbeLi2WZFJSw== X-Received: by 2002:a05:600c:22cd:: with SMTP id 13mr4137385wmg.90.1617212137004; Wed, 31 Mar 2021 10:35:37 -0700 (PDT) Received: from arch-x1c3.. ([2a00:5f00:102:0:6e1d:cfb9:fb12:552d]) by smtp.gmail.com with ESMTPSA id 12sm4714200wmw.43.2021.03.31.10.35.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Mar 2021 10:35:36 -0700 (PDT) From: Emil Velikov To: kernel@collabora.com, Ezequiel Garcia , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org Cc: emil.l.velikov@gmail.com, Frank Rowand Subject: [PATCH v3 8/9] media: hantro: add initial SAMA5D4 support Date: Wed, 31 Mar 2021 18:35:19 +0100 Message-Id: <20210331173520.184191-9-emil.l.velikov@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210331173520.184191-1-emil.l.velikov@gmail.com> References: <20210331173520.184191-1-emil.l.velikov@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Emil Velikov The SoC features a Hantro G1 compatible video decoder, supporting the MPEG-2, VP8 and H264 codecs with resolutions up-to 1280x720. Post-processing core is also available on the SoC. Cc: Rob Herring Cc: Frank Rowand Cc: devicetree@vger.kernel.org> Acked-by: Nicolas Ferre Reviewed-by: Ezequiel Garcia Signed-off-by: Emil Velikov --- v2 - Split DT and defconfig changes to separate patches (Eze) - s/Atmel/Microchip/ (Nicolas) v3 - Drop the clk/irq names (RobH) --- drivers/staging/media/hantro/Kconfig | 10 +- drivers/staging/media/hantro/Makefile | 3 + drivers/staging/media/hantro/hantro_drv.c | 3 + drivers/staging/media/hantro/hantro_hw.h | 1 + .../staging/media/hantro/sama5d4_vdec_hw.c | 117 ++++++++++++++++++ 5 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/hantro/sama5d4_vdec_hw.c diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig index 5b6cf9f62b1a..20b1f6d7b69c 100644 --- a/drivers/staging/media/hantro/Kconfig +++ b/drivers/staging/media/hantro/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || COMPILE_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || COMPILE_TEST depends on VIDEO_DEV && VIDEO_V4L2 select MEDIA_CONTROLLER select MEDIA_CONTROLLER_REQUEST_API @@ -24,6 +24,14 @@ config VIDEO_HANTRO_IMX8M help Enable support for i.MX8M SoCs. +config VIDEO_HANTRO_SAMA5D4 + bool "Hantro VDEC SAMA5D4 support" + depends on VIDEO_HANTRO + depends on ARCH_AT91 || COMPILE_TEST + default y + help + Enable support for Microchip SAMA5D4 SoCs. + config VIDEO_HANTRO_ROCKCHIP bool "Hantro VPU Rockchip support" depends on VIDEO_HANTRO diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile index 3747a32799b2..f4b99901eeee 100644 --- a/drivers/staging/media/hantro/Makefile +++ b/drivers/staging/media/hantro/Makefile @@ -22,6 +22,9 @@ hantro-vpu-y += \ hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \ imx8m_vpu_hw.o +hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \ + sama5d4_vdec_hw.o + hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ rk3288_vpu_hw.o \ rk3399_vpu_hw.o diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index d1294eb9cd07..74a3d9eab454 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -478,6 +478,9 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 + { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index 73c71bb2320c..4d39da1d1581 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -152,6 +152,7 @@ extern const struct hantro_variant rk3399_vpu_variant; extern const struct hantro_variant rk3328_vpu_variant; extern const struct hantro_variant rk3288_vpu_variant; extern const struct hantro_variant imx8mq_vpu_variant; +extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_postproc_regs hantro_g1_postproc_regs; diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c new file mode 100644 index 000000000000..d52ac626f98a --- /dev/null +++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Hantro VDEC driver + * + * Copyright (C) 2021 Collabora Ltd, Emil Velikov + */ + +#include "hantro.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = HANTRO_MODE_NONE, + }, +}; + +static const struct hantro_fmt sama5d4_vdec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + }, + { + .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, + .codec_mode = HANTRO_MODE_MPEG2_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1280, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 720, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_VP8_FRAME, + .codec_mode = HANTRO_MODE_VP8_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1280, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 720, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 48, + .max_width = 1280, + .step_width = MB_DIM, + .min_height = 48, + .max_height = 720, + .step_height = MB_DIM, + }, + }, +}; + +static int sama5d4_hw_init(struct hantro_dev *vpu) +{ + return 0; +} + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops sama5d4_vdec_codec_ops[] = { + [HANTRO_MODE_MPEG2_DEC] = { + .run = hantro_g1_mpeg2_dec_run, + .reset = hantro_g1_reset, + .init = hantro_mpeg2_dec_init, + .exit = hantro_mpeg2_dec_exit, + }, + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .reset = hantro_g1_reset, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .reset = hantro_g1_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + +static const struct hantro_irq sama5d4_irqs[] = { + { NULL, hantro_g1_irq }, +}; + +static const char * const sama5d4_clk_names[] = { NULL }; + +const struct hantro_variant sama5d4_vdec_variant = { + .dec_fmts = sama5d4_vdec_fmts, + .num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts), + .postproc_fmts = sama5d4_vdec_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts), + .postproc_regs = &hantro_g1_postproc_regs, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = sama5d4_vdec_codec_ops, + .init = sama5d4_hw_init, + .irqs = sama5d4_irqs, + .num_irqs = ARRAY_SIZE(sama5d4_irqs), + .clk_names = sama5d4_clk_names, + .num_clocks = ARRAY_SIZE(sama5d4_clk_names), +};