From patchwork Thu Apr 1 19:37:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 413790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67040C43460 for ; Thu, 1 Apr 2021 19:38:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39F0060725 for ; Thu, 1 Apr 2021 19:38:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235351AbhDATiw (ORCPT ); Thu, 1 Apr 2021 15:38:52 -0400 Received: from smtp-17-i2.italiaonline.it ([213.209.12.17]:53330 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235290AbhDATiv (ORCPT ); Thu, 1 Apr 2021 15:38:51 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id S38SlkFJgtpGHS38Zly35h; Thu, 01 Apr 2021 21:37:51 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1617305871; bh=w5zE/nnncsLL9tS2y4P86qvOqWWWEomS3J6KCrNrdms=; h=From; b=koptiVMx5H2h2giBsZuq0ulg1Xxs2HxqW/G5U0/cBslbmykHQXZGKiVt+CMKs+DmP eVK0a6zUoDeqdx/c6U7iz7styPqSVc4bxOjQhY0UZ6QbqM7cPCuMaF83UpuTpd0uXS Idvo0kCSlKhKNitEu6BlQW4XSwZ1ZSmcLCWBxmAUBCTyNN/2X/Yv7D1YEbs2ieRDJ3 71qMn8yeeqYZeK3UoaO17PZHZ0k2n0zapaIJV5BNR6PaE0wldH1XB2uYNmXbk4EL8U 41qE3hQCCTGK6/97Z40YQ7Ew1WLEFPMLsW5e+JLUT7jP3eStZmlXFSYjK6ybOPr8mf Xdtw3lR2V7FkA== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=6066210f cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=VwQbUJbxAAAA:8 a=IXkOJODCewQtKEFu2i4A:9 a=5yUOnwQy5QICz8m5uxDm:22 a=AjGcO6oz07-iQ99wixmX:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Grygorii Strashko , Dario Binacchi , Michael Turquette , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v4 2/5] dt-bindings: ti: dpll: add spread spectrum support Date: Thu, 1 Apr 2021 21:37:38 +0200 Message-Id: <20210401193741.24639-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401193741.24639-1-dariobin@libero.it> References: <20210401193741.24639-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfBlw2Mp5JJU6vyf14yZAflC6VIrElHTuPW2Z29hVlQ7oe8qgAWXk4e8U5Wsh5yGlzxR2cKRaZBI+LQLOJk3SHrgjfQcIkLEGQzYua+bYSqjH10iJQSj4 7XD/aIhKtMPJeD6btI/4z6ukUU1w9HpWLREBr7a9OLKy8Yq3QJGod3WEmESJBI+72tFgQgcEHqmSqq/5Tqi8Nfl/2roLe7LC6ONBFnN5CzmlFDvC47TdaItP yeLB8p3aFaGaBr+yvfB9/hUMIjmeRohTCbJ4I8SVe4yFjgKg4TV6IVOjrn7Y4um2SydXfYwG6GBTPVJCBbyTthtsGoFEA6Xq8wD+BROkTsu9jYFG5KnbuL0F rjRgU4TVLHCdI0eRMN5Mzvt495iWIwHljgO6+BwhPS2BhLai2kx2oUQXbK4MHxt6tnLWx2Y+0oYZ8cqZ7fRlIComAWMsHLykuzucNEOIxy+Bj3/9HB4Qz11z WiyPiP5Eu6P+hBdx Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DT bindings for enabling and adjusting spread spectrum clocking have been added. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring --- Changes in v4: - Add Rob Herring review tag. Changes in v3: - Add '-hz' suffix to "ti,ssc-modfreq" binding. .../devicetree/bindings/clock/ti/dpll.txt | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt index df57009ff8e7..37a7cb6ad07d 100644 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt @@ -42,6 +42,11 @@ Required properties: "idlest" - contains the idle status register base address "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) + "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains + the frequency spreading register base address (optional) + "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains + the modulation frequency register base address + (optional) ti,am3-* dpll types do not have autoidle register ti,omap2-* dpll type does not support idlest / autoidle registers @@ -51,6 +56,14 @@ Optional properties: - ti,low-power-stop : DPLL supports low power stop mode, gating output - ti,low-power-bypass : DPLL output matches rate of parent bypass clock - ti,lock : DPLL locks in programmed rate + - ti,min-div : the minimum divisor to start from to round the DPLL + target rate + - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency + spreading in permille (10th of a percent) + - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread + spectrum modulation frequency + - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean + to enable the downspread feature Examples: dpll_core_ck: dpll_core_ck@44e00490 { @@ -83,3 +96,10 @@ Examples: clocks = <&sys_ck>, <&sys_ck>; reg = <0x0500>, <0x0540>; }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; + }; From patchwork Thu Apr 1 19:37:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 413791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4DB1C43470 for ; Thu, 1 Apr 2021 19:37:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B345610CB for ; Thu, 1 Apr 2021 19:37:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234781AbhDAThy (ORCPT ); Thu, 1 Apr 2021 15:37:54 -0400 Received: from smtp-17.italiaonline.it ([213.209.10.17]:45205 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S234646AbhDAThx (ORCPT ); Thu, 1 Apr 2021 15:37:53 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([87.20.116.197]) by smtp-17.iol.local with ESMTPA id S38SlkFJgtpGHS38aly35z; Thu, 01 Apr 2021 21:37:52 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1617305872; bh=PPTo8GvjIIsaEKU5B1TIF8N7cm5fuyUf7SEXiLKXv5E=; h=From; b=TJxV+jegUHc5eLgKL/DfXVav+CokGdOwC+xRA0gY3+dQ3Qe6g5/d6E6Lo4S32BzZH kBPGUaJ5gkQFC64qbAufGqBb4qbB6rX/ZCi2hyAQO1HcMhSOmsxKAGti0WIXpKPX+s 6iHDjNaCQPg8bZqfdDEpU32swqaglhFf3j42xuW5L6F6h8maOvH3wu8EQlIUEVDnaj NpV/56TO0TT3IFh0hsGjM3tpKf1KPqbCGYwoT9ZjJlCDmebwEj4Bo17lClPrzs44yE rM/BryDBlbJhOPiYC8/BWMIn+M77tNxRD8+6I/102jFLfJAgqtI9iL38ivBL/lA4yW TrI2v6ksyS5QQ== X-CNFS-Analysis: v=2.4 cv=Q7IXX66a c=1 sm=1 tr=0 ts=60662110 cx=a_exe a=AVqmXbCQpuNSdJmApS5GbQ==:117 a=AVqmXbCQpuNSdJmApS5GbQ==:17 a=2OX5x-OEy5pyK2UBO5QA:9 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Grygorii Strashko , Dario Binacchi , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tony Lindgren , devicetree@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v4 4/5] ARM: dts: am43xx-clocks: add spread spectrum support Date: Thu, 1 Apr 2021 21:37:40 +0200 Message-Id: <20210401193741.24639-5-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210401193741.24639-1-dariobin@libero.it> References: <20210401193741.24639-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfPYtP5YGMi3g0ZQoO0gS6DLWX6tZ4HR38Hcc9oUC1Al0ronS0NYwLxsl9jw8DheUnm3qQ4r8w0SIlriXZ7Tnv9pouGOUuiEwUPfTs2NEfhA2HdSTIAYN uPEIVPUxgxJ4FHO7URkA7AqBTxS/XEBnVrJQ7JSbyryMIaODRI8EB8ayC84daTgy3DWE/1D6zGtZs2lL8Q6Sw2BnyrOoT3UKJ7vgMQtqv9IkAwPkb3TwVhLh DqpfjukPTvqLRTlJzZNCx36XsBId9FbGTqHCopuw9cHWQNqtDhe8cG1d2xX1hRJC9DppNtibrvCBXqOI839RLrFPYMWd/seggXHmxhJVFfzckgK4atGRjc4X +FdAuhYJlVeXQLe1NDka2RQVz0EJoe048jF+vRQJFpToVGpTrW9OFtcJJ0YTXQK0mHoExwUEmgQTTgBVa2vf1gqF2VAxYaqWstVz/sEJ5tzEn9Bv35hegxak nxdrppN/SGjxe7fZ Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruhl7x RM, SSC is supported only for LCD and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP, EXTDEV). Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index c726cd8dbdf1..314fc5975acb 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -250,7 +250,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { @@ -276,7 +276,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; + reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { @@ -294,7 +294,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { @@ -313,7 +313,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; + reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; dpll_per_m2_ck: dpll_per_m2_ck@2df0 { @@ -557,7 +557,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {