From patchwork Thu Apr 8 01:47:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 417371 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp116536jai; Wed, 7 Apr 2021 18:47:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfoKGzk5dRC9uk8BiHL0HJWf8u/anU04K5VIMlp6xgAY5mjOlY+t2Gyc/zRU6kFNs22y0h X-Received: by 2002:a62:77c1:0:b029:244:4080:8c7b with SMTP id s184-20020a6277c10000b029024440808c7bmr1041361pfc.69.1617846470920; Wed, 07 Apr 2021 18:47:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617846470; cv=none; d=google.com; s=arc-20160816; b=O7QdAYeEeb4M3frdTx0DaoQgimLfM6kyoQe6vklPZYC81TC7kUW/hmlbFRlkqhNxxL HItDsONCWZzNVrW7vouJ2CPmrPtF8jX8yYML2iLHhl/dUAwXu6sBoT5zE5ku/nVFS92g 0TEQSX5UpwVhsyzyaFliTvssEsCpbYprv+NmVaTqT6fh8JFqoKRWo1IpD4t/z7X9Hvyr W6PwXe+urzSWbCic3rCvBGe1YE0rF//tMqU7Y16i022Ws6L/iYaODi2SAcZAQ4YWuJYs E/rOXbPyc6g3K7KCDrTxqn3EC4FZmnEgWNDFiObuq8eyhFrcGUmKH4eiKV2fTNZowLaU 22ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D2i8W4m1OuOLC0EiDShXmmsb5dRC8axuc+jtBhnBrsY=; b=xVd3neG3lnIPHPf6JoLM6vCXQeZp9ZM8x3DZrkTphqRleVjmL9qyNgM53S7yDWB0wb /GcqruOumcxsAmNn3szel9fuwJqmjBmIlRAx/CCc2ffi5qIW8uw+V/72QXaLl/RPMXXf 3YJsPKcJkGu8zif8LZlHW0CxH1v8+k8uPVXbd8pjw4X4hcJTgPHGZrQbJPo+AzXddGou 2QcYOcCNCw6BeNQOsN01mQzWRFrqXCXuyM7tqscTbtVnM0k3jrMQFvoKf0FNRT156Re/ VHVwcTxuj3CTaTbKmEUwM6iUuN1TMSccZVlcYJoVIRlU4FJT0QdJ1y3ORI6/rSkQ+jul sO6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ShhChz8m; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z14si10431944pgz.360.2021.04.07.18.47.50; Wed, 07 Apr 2021 18:47:50 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ShhChz8m; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231326AbhDHBr7 (ORCPT + 6 others); Wed, 7 Apr 2021 21:47:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231300AbhDHBr6 (ORCPT ); Wed, 7 Apr 2021 21:47:58 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A1F1C061765 for ; Wed, 7 Apr 2021 18:47:48 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 184so296782ljf.9 for ; Wed, 07 Apr 2021 18:47:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D2i8W4m1OuOLC0EiDShXmmsb5dRC8axuc+jtBhnBrsY=; b=ShhChz8ms6+gHCOH3GLZ6juANUcb6i/XXlP0tGLYHCawUdYhRzhhdy0JJWVJttKnv2 MsXJLK4JN++ZfEsODd+8nWxswsfVXj7kw4lKcfp2wHbLc7mihgR+IYF5Zjd2PgrQzGvA 808eTjFvF9rTIQiHaWX+c0tpgCkA19o5e+9BfUrMzg/XQKg21p7aT2rPRs0Hb0ocVh1f ke5VSZOHGpFeIH9P7OI9RQkXRo+snnqezXC9TwT7Xx9PDpsHar7Dy06He8Adb0ewA06k u4BukmVbD+4UmYIQCmArD8s6lQLepfV2lWkHw4lvakhxlslyKK351gwATbE2ZZIR6dSi gBRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D2i8W4m1OuOLC0EiDShXmmsb5dRC8axuc+jtBhnBrsY=; b=LSQZeXuylaEskFMROKXxNJhVqMnwwwgmHeNXr6QIvyLtIsWwsmMOovpCbeAl+vblUy ugmO2qvDB6vIyR9wefxnCnvqjr8YJP12oJq0Gs8lN41Kz2PdB5AEvPLHoMqsmmdz8SoX 7xsFJ7LUQ+ZCIGOBcFMSozetKfk40zcSr+Klu6q2/Z9krOaPdu56hJQsQWKkTBe59Vkw Ii5ySalEGynIi1Z0hHGIuTTM5OBCZjqJT+EQsDdAfvytAm0hJmpvCIr+pRk6AFbUYfjQ Ox6TNgKcfTm9nY2BJpMuXNK/lsCCKzfftCrSGHjoCLlYkWXRZwEbwlUk3yGHm5wQUH9h TGNQ== X-Gm-Message-State: AOAM530sXknJinHrMiAmaGgLCE8lKIxI0k3pwvWBs0ikAUA8vOD07xLY pOF58uwyTzPg3CNCEfuHsi3xHA== X-Received: by 2002:a2e:b555:: with SMTP id a21mr4027275ljn.69.1617846466751; Wed, 07 Apr 2021 18:47:46 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w24sm2686705ljh.19.2021.04.07.18.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 18:47:46 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: clock: separate SDM845 GCC clock bindings Date: Thu, 8 Apr 2021 04:47:35 +0300 Message-Id: <20210408014737.955979-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408014737.955979-1-dmitry.baryshkov@linaro.org> References: <20210408014737.955979-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Separate qcom,gcc-sdm845 clock bindings from the clock-less qcom,gcc.yaml, so that we can add required clocks and clock-names properties. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,gcc-sdm845.yaml | 82 +++++++++++++++++++ .../devicetree/bindings/clock/qcom,gcc.yaml | 2 - 2 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml new file mode 100644 index 000000000000..4099b09ee9dd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDM845 + + See also: + - dt-bindings/clock/qcom,gcc-sdm845.h + +properties: + compatible: + const: qcom,gcc-sdm845 + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: pcie_0_pipe_clk + - const: pcie_1_pipe_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding. + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + # Example for GCC for MSM8960: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_lane>, + <&pcie1_lane>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index ee0467fb5e31..490edad25830 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -32,7 +32,6 @@ description: | - dt-bindings/clock/qcom,gcc-mdm9615.h - dt-bindings/reset/qcom,gcc-mdm9615.h - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) - - dt-bindings/clock/qcom,gcc-sdm845.h properties: compatible: @@ -52,7 +51,6 @@ properties: - qcom,gcc-mdm9615 - qcom,gcc-sdm630 - qcom,gcc-sdm660 - - qcom,gcc-sdm845 '#clock-cells': const: 1 From patchwork Thu Apr 8 01:47:37 2021 Content-Type: text/plain; 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Wed, 07 Apr 2021 18:47:48 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Stephen Boyd Subject: [PATCH v3 3/4] clk: qcom: gcc-sdm845: get rid of the test clock Date: Thu, 8 Apr 2021 04:47:37 +0300 Message-Id: <20210408014737.955979-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408014737.955979-1-dmitry.baryshkov@linaro.org> References: <20210408014737.955979-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/gcc-sdm845.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 46be43a02bf6..58aa3ec9a7fc 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -28,7 +28,6 @@ enum { P_BI_TCXO, P_AUD_REF_CLK, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_EVEN, P_GPLL0_OUT_MAIN, P_GPLL4_OUT_MAIN, @@ -98,14 +97,12 @@ static const struct parent_map gcc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_0[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_1[] = { @@ -113,7 +110,6 @@ static const struct parent_map gcc_parent_map_1[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_SLEEP_CLK, 5 }, { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_1[] = { @@ -121,41 +117,34 @@ static const struct clk_parent_data gcc_parent_data_1[] = { { .hw = &gpll0.clkr.hw }, { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" }, { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_2[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, { .hw = &gpll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_4[] = { { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_4[] = { { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_6[] = { @@ -163,7 +152,6 @@ static const struct parent_map gcc_parent_map_6[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_AUD_REF_CLK, 2 }, { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_6[] = { @@ -171,7 +159,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { { .hw = &gpll0.clkr.hw }, { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }, { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct clk_parent_data gcc_parent_data_7_ao[] = { @@ -198,7 +185,6 @@ static const struct parent_map gcc_parent_map_10[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL4_OUT_MAIN, 5 }, { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_10[] = { @@ -206,7 +192,6 @@ static const struct clk_parent_data gcc_parent_data_10[] = { { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw }, { .hw = &gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; From patchwork Thu Apr 8 01:47:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 417372 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp116566jai; Wed, 7 Apr 2021 18:47:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw6vF6PHEiRAbX68s6E49v6mc9mT0iMZm2xjAY32x6kWMyl0QGnGwnveQGptrmTPbwhSSvF X-Received: by 2002:a17:90a:d345:: with SMTP id i5mr5904189pjx.107.1617846473214; Wed, 07 Apr 2021 18:47:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1617846473; cv=none; d=google.com; s=arc-20160816; b=0iFvdp+TSPadhosOhIsBSFL9LDacsKoyTX50f2yCKq70jPGKP3pZxCBzNitozcGwdW QSQDF0snSO8pLSAoMaOB6UfL4P6rBk+gCPmjdXolOChrE4Go51Hep/vyp0WNSRYpS347 /NVu8FDhI+CmizBaQw8OS53/bDaQcwubzRgPNI4JQsbDeDrBJ6Xf+9T5C4sITyC1qdIJ 4/VsABeM9O1aHHt25599PguyKBvrxMTfEoyv//PCYz97XPfLxMd4vn7hImWsYNPymE5t pOoWzYXXV8hB5E70Cvv2pdbfAwPxYyCDelNKovinGkdxyKuGAtHG8RCDRBC/SCF5FGwF FYtw== ARC-Message-Signature: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id z14si10431944pgz.360.2021.04.07.18.47.53; Wed, 07 Apr 2021 18:47:53 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KM8+BbdR; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231368AbhDHBsC (ORCPT + 6 others); Wed, 7 Apr 2021 21:48:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231300AbhDHBsB (ORCPT ); Wed, 7 Apr 2021 21:48:01 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24865C061761 for ; Wed, 7 Apr 2021 18:47:51 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id u20so279850lja.13 for ; Wed, 07 Apr 2021 18:47:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E3Z+Q+wmuUr0KYMXECLxkHWsFWhoDF0jH3lckJMwRAY=; b=KM8+BbdRTlLusM2hMlQEQxZBDRLj1WI608H1MUXbvBF1mbUX5XgtNtQNNC7/5WeiGq deil8UqGha9GzcdsS6shTB7HTvi/YMAO/rnmgAbBK1kF/ol70okFyxzF4RJwsCmcNzm7 r8c3kyTKb8GGRwocWmKqVhRxhtR7ukLahnJ5/hXHA3+RClUN6QjU5I+GMh5r7sWD/0Yq Tp/f57Y8odgpXo52Z6SeFSaWDnRZBQsZ8oMwabi2sVeWlgKE06yGFybap/e499JnG9pV 4+hKfykxGap8nqxT3RV+DQVTGA6pYt4XQR1wgbglIWNtp35Rhk6XzFBraSV3CNIwqINJ Mzyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E3Z+Q+wmuUr0KYMXECLxkHWsFWhoDF0jH3lckJMwRAY=; b=sJXDP1PaRkIdRog2JsPV+4Df/Q1Hf3eKFMsf0S9/knUXvpDhwB8sFz/taYjFbXjEZE NFUVd6Jn2687stgiZYZejoPHY95vxqyGWodVygbf8xfsFq4lSucBgiB+7sC6P/zMwFRb jkS+Ox2gVdMgNAF+meIqpBVZ7r+tvod9fDB7jO10R0ke9d93SA2uN8fYMDUGGCZt5o7O npXXFzqDID5s+JawU8ZeAsMxhbEalmdDAxQvySaKv3LJlOsMPDgx8FY6dmrX9wY6dwK3 CAS/63bLWHX7hqoKNgSM0lV9kFVa/DUz3hlwNECQcQCi7T6eFeFninsZyA8TMI/fhQ61 9J9w== X-Gm-Message-State: AOAM530QY+7j/nE/ep8Ptgz7LVYg3o7LvCVN192PrpKxfdq8FacHyVxw O3IjWUC3c3AwEZw9JxpjA3G56g== X-Received: by 2002:a2e:a312:: with SMTP id l18mr4041558lje.106.1617846469666; Wed, 07 Apr 2021 18:47:49 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id w24sm2686705ljh.19.2021.04.07.18.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Apr 2021 18:47:49 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v3 4/4] arm64: dts: qcom: sdm845: add required clocks on the gcc Date: Thu, 8 Apr 2021 04:47:38 +0300 Message-Id: <20210408014737.955979-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408014737.955979-1-dmitry.baryshkov@linaro.org> References: <20210408014737.955979-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Specify input clocks to the SDM845's Global Clock Controller as required by the bindings. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 454f794af547..86f717d5bfb6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1061,6 +1061,16 @@ soc: soc@0 { gcc: clock-controller@100000 { compatible = "qcom,gcc-sdm845"; reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_lane>, + <&pcie1_lane>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -2062,6 +2072,7 @@ pcie0_lane: lanes@1c06200 { clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; + #clock-cells = <0>; #phy-cells = <0>; clock-output-names = "pcie_0_pipe_clk"; }; @@ -2170,6 +2181,7 @@ pcie1_lane: lanes@1c06200 { clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; + #clock-cells = <0>; #phy-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; };