From patchwork Sun Apr 11 13:30:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 419375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED97BC43462 for ; Sun, 11 Apr 2021 13:30:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C9E41611AD for ; Sun, 11 Apr 2021 13:30:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229804AbhDKNbH (ORCPT ); Sun, 11 Apr 2021 09:31:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235592AbhDKNbH (ORCPT ); Sun, 11 Apr 2021 09:31:07 -0400 Received: from mail-qk1-x72f.google.com (mail-qk1-x72f.google.com [IPv6:2607:f8b0:4864:20::72f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7FF3C061574; Sun, 11 Apr 2021 06:30:50 -0700 (PDT) Received: by mail-qk1-x72f.google.com with SMTP id x11so10611879qkp.11; Sun, 11 Apr 2021 06:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fjZkGAV2onA9W0zA2KcPEQhI5/QgShDnA+nmt2xDiXo=; b=JL7y8uJ3qrLnXv0uBLbFYyUhrRSi3qZMIEb9MtYjEU7mG3LNJZhhy5jaBzlHZETg8k 2fB91Su4taYcPp0O+CXH9WagnNawgI5TcrGOCgn8r3d82UXPOAgpoWQ02i8RqAA0q96W sxkNoSsDF18e7afZm5p7C1cLZSoocEb42k98B2VgpqJWtITzIxcXN1J+d+aD228N/XkK g7Pg3mVgjb3kTkia6dPHhsnww/XFynoht1xRSfLKauBZvL2CWm1FF6CaIqwmXsgr6Jn8 HX9MCiBGzwoy+C6eRKxSasfLIhBeiV/iLcnZIlwFou2Cn6QtbIxPr+CmV4Eklv25paU9 ACXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fjZkGAV2onA9W0zA2KcPEQhI5/QgShDnA+nmt2xDiXo=; b=sT1UtYN4T2g524hR6nE/eQdbST4mab1xbwAAk2IgEnFtywFLAFx/6BfV+KvDc/UWYk 3i84UnvW/gBthfGNo5Tbb60HMqzkLlVuFaz1O5nAZ+gaO5JnUY7zgouW+rxWvFIOfyss 3BEtQIAyXdPDI0A+4s5nYzZ6RBKuT/s1SYYXQD8TK589creyfdlEPXWTD3Ul/mkwALDn Uqgwrg/YnyR7NHh9bap31eHKeNkKuhRxhkbN2VPwv0BuKHJWeWdUYZFvoUQAONUeYeD6 SXNOdq0lN0Dbo4XThNZ7fosNrxr4HWqxLUWRUXFJZPa1xzZnPRXWSYL8vtN8NKGbwblk F+Fw== X-Gm-Message-State: AOAM531yeawAKOPEWgToUlxlI+MMn9Zx6Y5CrPzRacRG7sukY8O4ixqQ /p29d0zpdByJERvEALZ106c= X-Google-Smtp-Source: ABdhPJx4m6emyVfwdSgwe7XXc4ccXCP+aQItscdwP5r0OLXK0thS+NBsh27Mdxuy07Kirx+wfB3eLA== X-Received: by 2002:a05:620a:a89:: with SMTP id v9mr5565174qkg.279.1618147849820; Sun, 11 Apr 2021 06:30:49 -0700 (PDT) Received: from master-laptop.sparksnet (c-98-233-193-225.hsd1.md.comcast.net. [98.233.193.225]) by smtp.gmail.com with ESMTPSA id l17sm5734204qtk.60.2021.04.11.06.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Apr 2021 06:30:49 -0700 (PDT) From: Peter Geis To: Jianqun Xu , huangtao@rock-chips.com, kever.yang@rock-chips.com, linus.walleij@linaro.org, heiko@sntech.de Cc: linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] pinctrl/pinctrl-rockchip.h: add pinctrl device to gpio bank struct Date: Sun, 11 Apr 2021 09:30:25 -0400 Message-Id: <20210411133030.1663936-3-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210411133030.1663936-1-pgwipeout@gmail.com> References: <20210411133030.1663936-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Jianqun Xu Store a pointer from the pinctrl device for the gpio bank. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index dba9e9540633..4aa3d2f1fa67 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -81,6 +81,7 @@ struct rockchip_drv { /** * struct rockchip_pin_bank + * @dev: the pinctrl device bind to the bank * @reg_base: register base of the gpio bank * @regmap_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank @@ -105,6 +106,7 @@ struct rockchip_drv { * @route_mask: bits describing the routing pins of per bank */ struct rockchip_pin_bank { + struct device *dev; void __iomem *reg_base; struct regmap *regmap_pull; struct clk *clk; From patchwork Sun Apr 11 13:30:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 419373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A557C4360C for ; Sun, 11 Apr 2021 13:30:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D2FF7611C9 for ; Sun, 11 Apr 2021 13:30:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235661AbhDKNbK (ORCPT ); Sun, 11 Apr 2021 09:31:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235655AbhDKNbJ (ORCPT ); Sun, 11 Apr 2021 09:31:09 -0400 Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19A6DC06138C; Sun, 11 Apr 2021 06:30:53 -0700 (PDT) Received: by mail-qt1-x829.google.com with SMTP id u8so7925615qtq.12; Sun, 11 Apr 2021 06:30:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+e/4E4G777F1WaTkMFE+NA3aUNUv1y8XhGeM5Cgp/bc=; b=OVR6hMBrgWt9Fd1Y45DYP1l9keQMANxdnKGykSAAFfd9L8mlxcgobnjquS/hQe6AcK hERiH6h8SNUkyQ/etos7VGPbwL7OdB6xZCoXXJLQykl95gi56e/B8aFvCULL3dQHlZO+ hOvlNvqxNmAVLP7tGuPeWYDKzZjVA3qW/3XZd2/i7E2tb4Ep8TwmGA9wFn+fKrazXyO3 aTDLlpenC/8ah6ZdZgDMGBr0lqQU5DHyy4VXMT+3eloI7tqmN6NDpQNx+hfpqqzg8tbE PW2HY9GxnpigVWpC9I3G9bfLODg0w02Yt6myRd7EjVW4BsZzXJ3wLD4WzBqdhjJE8vzh 0o9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+e/4E4G777F1WaTkMFE+NA3aUNUv1y8XhGeM5Cgp/bc=; b=KNgb8pQLTW4I4k3e84GlM2sq+3ElLdv5m8Pk7tWzB5DPLTKcDXawqBg8g06At1rI1e 08c+qrFmf7lIeLh8rbi1Xbje51VBO3g3cT9RJ1Awt45lPCvGrojLSv0s75AE1vaQXpl0 APuVjU1Oc8lfN6Q9uGwFmQtvVdyu73yclFC1sfSMVp8KwrPpMzbevzqo2UzzY6Dyq/kP bVYcpcm7VYaKiEdEao8h7ztL3lukvOZaIMNzEz5u0AiQy678a6Vjvde5sHrP8IT65owQ iXVsSdFzfh/C1FrSKwRQpbeD92J2wkHdrA5DxymTL76Q3oUrF906Df/s+ckB6SSOfu7x lUTA== X-Gm-Message-State: AOAM533fOLWUu3f2BsoqtOz4B+e+z0ofQV//77wCzHEh9p+O0IbIXNC7 XqOS3HIDEAKNb9TCuDnPBYg= X-Google-Smtp-Source: ABdhPJzxwItuKaiSssKJvD+NqVr/Lr1LLwmYGhC0QkN4C5Exe5PPT0WhZOvWIULrgzeBH0QaR+5vNg== X-Received: by 2002:ac8:5fc4:: with SMTP id k4mr1063859qta.124.1618147852180; Sun, 11 Apr 2021 06:30:52 -0700 (PDT) Received: from master-laptop.sparksnet (c-98-233-193-225.hsd1.md.comcast.net. [98.233.193.225]) by smtp.gmail.com with ESMTPSA id l17sm5734204qtk.60.2021.04.11.06.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Apr 2021 06:30:51 -0700 (PDT) From: Peter Geis To: Jianqun Xu , huangtao@rock-chips.com, kever.yang@rock-chips.com, linus.walleij@linaro.org, heiko@sntech.de Cc: linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] gpio/rockchip: support next version gpio controller Date: Sun, 11 Apr 2021 09:30:28 -0400 Message-Id: <20210411133030.1663936-6-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210411133030.1663936-1-pgwipeout@gmail.com> References: <20210411133030.1663936-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Jianqun Xu The next version gpio controller on SoCs like rk3568 have more write mask bits for registers. Signed-off-by: Jianqun Xu --- drivers/gpio/gpio-rockchip.c | 280 ++++++++++++++++++++++------- drivers/pinctrl/pinctrl-rockchip.h | 2 + 2 files changed, 215 insertions(+), 67 deletions(-) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index b12db3a523d0..92aaf1848449 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -25,6 +25,7 @@ #include "../pinctrl/pinctrl-rockchip.h" #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ +#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */ static const struct rockchip_gpio_regs gpio_regs_v1 = { .port_dr = 0x00, @@ -40,6 +41,99 @@ static const struct rockchip_gpio_regs gpio_regs_v1 = { .ext_port = 0x50, }; +static const struct rockchip_gpio_regs gpio_regs_v2 = { + .port_dr = 0x00, + .port_ddr = 0x08, + .int_en = 0x10, + .int_mask = 0x18, + .int_type = 0x20, + .int_polarity = 0x28, + .int_bothedge = 0x30, + .int_status = 0x50, + .int_rawstatus = 0x58, + .debounce = 0x38, + .dbclk_div_en = 0x40, + .dbclk_div_con = 0x48, + .port_eoi = 0x60, + .ext_port = 0x70, + .version_id = 0x78, +}; + +static inline void gpio_writel_v2(u32 val, void __iomem *reg) +{ + writel((val & 0xffff) | 0xffff0000, reg); + writel((val >> 16) | 0xffff0000, reg + 0x4); +} + +static inline u32 gpio_readl_v2(void __iomem *reg) +{ + return readl(reg + 0x4) << 16 | readl(reg); +} + +static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, + u32 value, unsigned int offset) +{ + void __iomem *reg = bank->reg_base + offset; + + if (bank->gpio_type == GPIO_TYPE_V2) + gpio_writel_v2(value, reg); + else + writel(value, reg); +} + +static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, + unsigned int offset) +{ + void __iomem *reg = bank->reg_base + offset; + u32 value; + + if (bank->gpio_type == GPIO_TYPE_V2) + value = gpio_readl_v2(reg); + else + value = readl(reg); + + return value; +} + +static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, + u32 bit, u32 value, + unsigned int offset) +{ + void __iomem *reg = bank->reg_base + offset; + u32 data; + + if (bank->gpio_type == GPIO_TYPE_V2) { + if (value) + data = BIT(bit % 16) | BIT(bit % 16 + 16); + else + data = BIT(bit % 16 + 16); + writel(data, bit >= 16 ? reg + 0x4 : reg); + } else { + data = readl(reg); + data &= ~BIT(bit); + if (value) + data |= BIT(bit); + writel(data, reg); + } +} + +static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, + u32 bit, unsigned int offset) +{ + void __iomem *reg = bank->reg_base + offset; + u32 data; + + if (bank->gpio_type == GPIO_TYPE_V2) { + data = readl(bit >= 16 ? reg + 0x4 : reg); + data >>= bit % 16; + } else { + data = readl(reg); + data >>= bit; + } + + return data & (0x1); +} + static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { @@ -53,7 +147,7 @@ static int rockchip_gpio_get_direction(struct gpio_chip *chip, "failed to enable clock for bank %s\n", bank->name); return ret; } - data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); + data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); clk_disable(bank->clk); if (data & BIT(offset)) @@ -67,19 +161,11 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip, { struct rockchip_pin_bank *bank = gpiochip_get_data(chip); unsigned long flags; - u32 data; + u32 data = input ? 0 : 1; clk_enable(bank->clk); raw_spin_lock_irqsave(&bank->slock, flags); - - data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); - /* set bit to 1 for output, 0 for input */ - if (!input) - data |= BIT(offset); - else - data &= ~BIT(offset); - writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr); - + rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(bank->clk); @@ -90,19 +176,11 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) { struct rockchip_pin_bank *bank = gpiochip_get_data(gc); - void __iomem *reg = bank->reg_base + bank->gpio_regs->port_dr; unsigned long flags; - u32 data; clk_enable(bank->clk); raw_spin_lock_irqsave(&bank->slock, flags); - - data = readl(reg); - data &= ~BIT(offset); - if (value) - data |= BIT(offset); - writel(data, reg); - + rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(bank->clk); } @@ -120,26 +198,65 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) return data; } -static void rockchip_gpio_set_debounce(struct gpio_chip *gc, - unsigned int offset, bool enable) +static int rockchip_gpio_set_debounce(struct gpio_chip *gc, + unsigned int offset, + unsigned int debounce) { struct rockchip_pin_bank *bank = gpiochip_get_data(gc); - void __iomem *reg = bank->reg_base + bank->gpio_regs->debounce; - unsigned long flags; - u32 data; + const struct rockchip_gpio_regs *reg = bank->gpio_regs; + unsigned long flags, div_reg, freq, max_debounce; + bool div_debounce_support; + unsigned int cur_div_reg; + u64 div; + + if (!IS_ERR(bank->db_clk)) { + div_debounce_support = true; + freq = clk_get_rate(bank->db_clk); + max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; + if (debounce > max_debounce) + return -EINVAL; + + div = debounce * freq; + div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; + } else { + div_debounce_support = false; + } - clk_enable(bank->clk); raw_spin_lock_irqsave(&bank->slock, flags); - data = readl(reg); - if (enable) - data |= BIT(offset); - else - data &= ~BIT(offset); - writel(data, reg); + /* Only the v1 needs to configure div_en and div_con for dbclk */ + if (debounce) { + if (div_debounce_support) { + /* Configure the max debounce from consumers */ + cur_div_reg = readl(bank->reg_base + + reg->dbclk_div_con); + if (cur_div_reg < div_reg) + writel(div_reg, bank->reg_base + + reg->dbclk_div_con); + rockchip_gpio_writel_bit(bank, offset, 1, + reg->dbclk_div_en); + } + + rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); + } else { + if (div_debounce_support) + rockchip_gpio_writel_bit(bank, offset, 0, + reg->dbclk_div_en); + + rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); + } raw_spin_unlock_irqrestore(&bank->slock, flags); - clk_disable(bank->clk); + + /* Enable or disable dbclk at last */ + if (div_debounce_support) { + if (debounce) + clk_prepare_enable(bank->db_clk); + else + clk_disable_unprepare(bank->db_clk); + } + + return 0; } static int rockchip_gpio_direction_input(struct gpio_chip *gc, @@ -290,13 +407,13 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) u32 level; u32 data; unsigned long flags; + int ret = 0; clk_enable(bank->clk); raw_spin_lock_irqsave(&bank->slock, flags); - data = readl_relaxed(bank->reg_base + bank->gpio_regs->port_ddr); - data &= ~mask; - writel_relaxed(data, bank->reg_base + bank->gpio_regs->port_ddr); + rockchip_gpio_writel_bit(bank, d->hwirq, 0, + bank->gpio_regs->port_ddr); raw_spin_unlock_irqrestore(&bank->slock, flags); @@ -308,23 +425,30 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) raw_spin_lock_irqsave(&bank->slock, flags); irq_gc_lock(gc); - level = readl_relaxed(gc->reg_base + bank->gpio_regs->int_type); - polarity = readl_relaxed(gc->reg_base + bank->gpio_regs->int_polarity); + level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); + polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); switch (type) { case IRQ_TYPE_EDGE_BOTH: - bank->toggle_edge_mode |= mask; - level |= mask; - - /* - * Determine gpio state. If 1 next interrupt should be falling - * otherwise rising. - */ - data = readl(bank->reg_base + bank->gpio_regs->ext_port); - if (data & mask) - polarity &= ~mask; - else - polarity |= mask; + if (bank->gpio_type == GPIO_TYPE_V2) { + bank->toggle_edge_mode &= ~mask; + rockchip_gpio_writel_bit(bank, d->hwirq, 1, + bank->gpio_regs->int_bothedge); + goto out; + } else { + bank->toggle_edge_mode |= mask; + level |= mask; + + /* + * Determine gpio state. If 1 next interrupt should be + * falling otherwise rising. + */ + data = readl(bank->reg_base + bank->gpio_regs->ext_port); + if (data & mask) + polarity &= ~mask; + else + polarity |= mask; + } break; case IRQ_TYPE_EDGE_RISING: bank->toggle_edge_mode &= ~mask; @@ -347,20 +471,18 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) polarity &= ~mask; break; default: - irq_gc_unlock(gc); - raw_spin_unlock_irqrestore(&bank->slock, flags); - clk_disable(bank->clk); - return -EINVAL; + ret = -EINVAL; + goto out; } - writel_relaxed(level, gc->reg_base + bank->gpio_regs->int_type); - writel_relaxed(polarity, gc->reg_base + bank->gpio_regs->int_polarity); - + rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); + rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); +out: irq_gc_unlock(gc); raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(bank->clk); - return 0; + return ret; } static void rockchip_irq_suspend(struct irq_data *d) @@ -437,6 +559,11 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) } gc = irq_get_domain_generic_chip(bank->domain, 0); + if (bank->gpio_type == GPIO_TYPE_V2) { + gc->reg_writel = gpio_writel_v2; + gc->reg_readl = gpio_readl_v2; + } + gc->reg_base = bank->reg_base; gc->private = bank; gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; @@ -457,9 +584,9 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) * Our driver only uses the concept of masked and always keeps * things enabled, so for us that's all masked and all enabled. */ - writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_mask); - writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->port_eoi); - writel_relaxed(0xffffffff, bank->reg_base + bank->gpio_regs->int_en); + rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); + rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); + rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); gc->mask_cache = 0xffffffff; irq_set_chained_handler_and_data(bank->irq, @@ -538,6 +665,7 @@ static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) { struct resource res; + int id = 0; if (of_address_to_resource(bank->of_node, 0, &res)) { dev_err(bank->dev, "cannot find IO resource for bank\n"); @@ -549,15 +677,33 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) return PTR_ERR(bank->reg_base); bank->irq = irq_of_parse_and_map(bank->of_node, 0); - - bank->gpio_regs = &gpio_regs_v1; - bank->gpio_type = GPIO_TYPE_V1; + if (!bank->irq) + return -EINVAL; bank->clk = of_clk_get(bank->of_node, 0); - if (!IS_ERR(bank->clk)) - return clk_prepare(bank->clk); + if (IS_ERR(bank->clk)) + return PTR_ERR(bank->clk); + + clk_prepare_enable(bank->clk); + id = readl(bank->reg_base + gpio_regs_v2.version_id); + + /* If not gpio v2, that is default to v1. */ + if (id == GPIO_TYPE_V2) { + bank->gpio_regs = &gpio_regs_v2; + bank->gpio_type = GPIO_TYPE_V2; + bank->db_clk = of_clk_get(bank->of_node, 1); + if (IS_ERR(bank->db_clk)) { + dev_err(bank->dev, "cannot find debounce clk\n"); + bank->db_clk = NULL; + clk_disable(bank->clk); + return -EINVAL; + } + } else { + bank->gpio_regs = &gpio_regs_v1; + bank->gpio_type = GPIO_TYPE_V1; + } - bank->clk = NULL; + clk_disable(bank->clk); return 0; } diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h index 1b774b6bbc3e..589d4d2a98c9 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -121,6 +121,7 @@ struct rockchip_drv { * @reg_base: register base of the gpio bank * @regmap_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank + * @db_clk: clock of the gpio debounce * @irq: interrupt of the gpio bank * @saved_masks: Saved content of GPIO_INTEN at suspend time. * @pin_base: first pin number @@ -146,6 +147,7 @@ struct rockchip_pin_bank { void __iomem *reg_base; struct regmap *regmap_pull; struct clk *clk; + struct clk *db_clk; int irq; u32 saved_masks; u32 pin_base; From patchwork Sun Apr 11 13:30:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 419374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFFE1C43460 for ; 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[98.233.193.225]) by smtp.gmail.com with ESMTPSA id l17sm5734204qtk.60.2021.04.11.06.30.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Apr 2021 06:30:53 -0700 (PDT) From: Peter Geis To: Jianqun Xu , huangtao@rock-chips.com, kever.yang@rock-chips.com, linus.walleij@linaro.org, heiko@sntech.de Cc: linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type Date: Sun, 11 Apr 2021 09:30:30 -0400 Message-Id: <20210411133030.1663936-8-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210411133030.1663936-1-pgwipeout@gmail.com> References: <20210411133030.1663936-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Jianqun Xu There has spin lock for irq set type already, so drop irq_gc_lock and irq_gc_unlock. Signed-off-by: Jianqun Xu --- drivers/gpio/gpio-rockchip.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c index 048e7eecddba..c9c55614bbef 100644 --- a/drivers/gpio/gpio-rockchip.c +++ b/drivers/gpio/gpio-rockchip.c @@ -406,7 +406,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) irq_set_handler_locked(d, handle_level_irq); raw_spin_lock_irqsave(&bank->slock, flags); - irq_gc_lock(gc); level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); @@ -461,7 +460,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); out: - irq_gc_unlock(gc); raw_spin_unlock_irqrestore(&bank->slock, flags); return ret;