From patchwork Tue Apr 13 07:36:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE27C433ED for ; Tue, 13 Apr 2021 07:36:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B5469613B8 for ; Tue, 13 Apr 2021 07:36:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238682AbhDMHga (ORCPT ); Tue, 13 Apr 2021 03:36:30 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.73.133]:36460 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237250AbhDMHga (ORCPT ); Tue, 13 Apr 2021 03:36:30 -0400 Received: from mailhost.synopsys.com (mdc-mailhost2.synopsys.com [10.225.0.210]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id BCF2D4019F; Tue, 13 Apr 2021 07:36:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618299371; bh=mTMgLw0i3qjR66MH6B8kFrVdfGg0tmxHpkjak79KE64=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=ZvNdIFCGPvHQhlgsVPq1dEptpz3OSCSL3wQCT5pLXOLdT1Iusuy7pIc8I90kjLFsk 4R1643TFb3ArzVitLDbZzPCY6KN8NBvD89d9+Tn5okLBI0+USA7QECxS06/2XtQvKi Tkfkoaoy2i80KyqLDoZvktdG10CiyDGHaJQ1qzyhmdiODdDM0j12IvP51FSfzegvl3 inFANHZe/gi9gfJLZhFOPsEXJvovAdkKPF/xHq0wW0ex0cAv9DTFvspdrUgrRv0MvB Btg5lptMlLN9ferwAKKw6fGygrzqDIO6ncirCvved0N8pndmreTjpKKDTPsA7pes21 1AFok3BVa+/XA== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id F41E8A0094; Tue, 13 Apr 2021 07:36:07 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:36:07 +0400 Date: Tue, 13 Apr 2021 11:36:07 +0400 In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH v2 01/12] usb: dwc2: Add device clock gating support functions To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan , Minas Harutyunyan Message-Id: <20210413073607.F41E8A0094@mailhost.synopsys.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Added device clock gating support functions according programming guide. Moved "bus_suspended" flag to "dwc2_hsotg" struct because we need to set that flag while entering to clock gating in case when the driver is built in peripheral mode. Added function names: dwc2_gadget_enter_clock_gating() dwc2_gadget_exit_clock_gating() Signed-off-by: Artur Petrosyan Acked-by: Minas Harutyunyan --- drivers/usb/dwc2/core.h | 10 ++++-- drivers/usb/dwc2/gadget.c | 71 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 5a7850482e57..e5597796dca4 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -866,6 +866,7 @@ struct dwc2_hregs_backup { * @ll_hw_enabled: Status of low-level hardware resources. * @hibernated: True if core is hibernated * @in_ppd: True if core is partial power down mode. + * @bus_suspended: True if bus is suspended * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a * remote wakeup. * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. @@ -1023,7 +1024,6 @@ struct dwc2_hregs_backup { * a pointer to an array of register definitions, the * array size and the base address where the register bank * is to be found. - * @bus_suspended: True if bus is suspended * @last_frame_num: Number of last frame. Range from 0 to 32768 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is * defined, for missed SOFs tracking. Array holds that @@ -1062,6 +1062,7 @@ struct dwc2_hsotg { unsigned int ll_hw_enabled:1; unsigned int hibernated:1; unsigned int in_ppd:1; + bool bus_suspended; unsigned int reset_phy_on_wake:1; unsigned int need_phy_for_wake:1; unsigned int phy_off_for_suspend:1; @@ -1145,7 +1146,6 @@ struct dwc2_hsotg { unsigned long hs_periodic_bitmap[ DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; u16 periodic_qh_count; - bool bus_suspended; bool new_connection; u16 last_frame_num; @@ -1415,6 +1415,9 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore); +void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); +void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, + int rem_wakeup); int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); @@ -1453,6 +1456,9 @@ static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore) { return 0; } +static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} +static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, + int rem_wakeup) {} static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) { return 0; } static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index e08baee4987b..2f50f3e62caa 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -5483,3 +5483,74 @@ int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n"); return ret; } + +/** + * dwc2_gadget_enter_clock_gating() - Put controller in clock gating. + * + * @hsotg: Programming view of the DWC_otg controller + * + * Return: non-zero if failed to enter device partial power down. + * + * This function is for entering device mode clock gating. + */ +void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) +{ + u32 pcgctl; + + dev_dbg(hsotg->dev, "Entering device clock gating.\n"); + + /* Set the Phy Clock bit as suspend is received. */ + pcgctl = dwc2_readl(hsotg, PCGCTL); + pcgctl |= PCGCTL_STOPPCLK; + dwc2_writel(hsotg, pcgctl, PCGCTL); + udelay(5); + + /* Set the Gate hclk as suspend is received. */ + pcgctl = dwc2_readl(hsotg, PCGCTL); + pcgctl |= PCGCTL_GATEHCLK; + dwc2_writel(hsotg, pcgctl, PCGCTL); + udelay(5); + + hsotg->lx_state = DWC2_L2; + hsotg->bus_suspended = true; +} + +/* + * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating. + * + * @hsotg: Programming view of the DWC_otg controller + * @rem_wakeup: indicates whether remote wake up is enabled. + * + * This function is for exiting from device mode clock gating. + */ +void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup) +{ + u32 pcgctl; + u32 dctl; + + dev_dbg(hsotg->dev, "Exiting device clock gating.\n"); + + /* Clear the Gate hclk. */ + pcgctl = dwc2_readl(hsotg, PCGCTL); + pcgctl &= ~PCGCTL_GATEHCLK; + dwc2_writel(hsotg, pcgctl, PCGCTL); + udelay(5); + + /* Phy Clock bit. */ + pcgctl = dwc2_readl(hsotg, PCGCTL); + pcgctl &= ~PCGCTL_STOPPCLK; + dwc2_writel(hsotg, pcgctl, PCGCTL); + udelay(5); + + if (rem_wakeup) { + /* Set Remote Wakeup Signaling */ + dctl = dwc2_readl(hsotg, DCTL); + dctl |= DCTL_RMTWKUPSIG; + dwc2_writel(hsotg, dctl, DCTL); + } + + /* Change to L0 state */ + call_gadget(hsotg, resume); + hsotg->lx_state = DWC2_L0; + hsotg->bus_suspended = false; +} From patchwork Tue Apr 13 07:36:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7621C433B4 for ; Tue, 13 Apr 2021 07:36:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93C9D613BA for ; Tue, 13 Apr 2021 07:36:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240373AbhDMHgq (ORCPT ); Tue, 13 Apr 2021 03:36:46 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:60516 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240362AbhDMHgp (ORCPT ); Tue, 13 Apr 2021 03:36:45 -0400 Received: from mailhost.synopsys.com (mdc-mailhost1.synopsys.com [10.225.0.209]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 365BFC00BB; Tue, 13 Apr 2021 07:36:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618299386; bh=nj1BeKTbsJpmOWsKzyw4Q4Ak3JprmbRdIDgrwfON3Og=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=NGQXHvEFKJbMpDLaohQbK1OTrPRDGwOQLbjy7v6KYSZ0yRW3zovrwakuF9wlFCp5g gd9l6ynZmWMxCRIa5MYJORVw3Z1GG04ixg0mVjDPQXdPi/c270vrW9E6G9dOtVsjyJ +fMxGzHnlgQCdt1E/4S8OAkI4anrppldRV/BQ+6TBBqx686qGuslPIQnvfci6eXmej TFnF0FC/aPhKOad3k8Gzn+VwxoI2G5KbvwuG+VrdHujhJvUaIvTZnn9DBf9k1zj8w8 njJBqfUrXNjrJaf+Q6A8EdTjADIYZoUG1kBcSYcgXsE9Tfpx3acoRW1JY8XnPuJWFs YRY5j5CEUfGRA== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id 65355A022E; Tue, 13 Apr 2021 07:36:23 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:36:22 +0400 Date: Tue, 13 Apr 2021 11:36:22 +0400 In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH v2 03/12] usb: dwc2: Allow entering clock gating from USB_SUSPEND interrupt To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan , Minas Harutyunyan Message-Id: <20210413073623.65355A022E@mailhost.synopsys.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org If core doesn't support hibernation or partial power down power saving options, power can still be saved using clock gating on all the clocks. - Added entering clock gating state from USB_SUSPEND interrupt. Signed-off-by: Artur Petrosyan Acked-by: Minas Harutyunyan --- drivers/usb/dwc2/core_intr.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c index 8c0152b514be..ab7fe303c0f9 100644 --- a/drivers/usb/dwc2/core_intr.c +++ b/drivers/usb/dwc2/core_intr.c @@ -529,14 +529,18 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) /* Ask phy to be suspended */ if (!IS_ERR_OR_NULL(hsotg->uphy)) usb_phy_set_suspend(hsotg->uphy, true); - } - - if (hsotg->hw_params.hibernation) { + } else if (hsotg->hw_params.hibernation) { ret = dwc2_enter_hibernation(hsotg, 0); if (ret && ret != -ENOTSUPP) dev_err(hsotg->dev, "%s: enter hibernation failed\n", __func__); + } else { + /* + * If not hibernation nor partial power down are supported, + * clock gating is used to save power. + */ + dwc2_gadget_enter_clock_gating(hsotg); } skip_power_saving: /* From patchwork Tue Apr 13 07:36:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B2C9C43460 for ; Tue, 13 Apr 2021 07:36:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5856A613B8 for ; Tue, 13 Apr 2021 07:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240613AbhDMHhD (ORCPT ); Tue, 13 Apr 2021 03:37:03 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:60522 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240497AbhDMHhB (ORCPT ); Tue, 13 Apr 2021 03:37:01 -0400 Received: from mailhost.synopsys.com (mdc-mailhost2.synopsys.com [10.225.0.210]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 4FA91C00BB; Tue, 13 Apr 2021 07:36:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618299401; bh=dKhq2iqRjrY0N9i7U4VKo0N5zELnYfh/gudC2BsyoPY=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=CwL/0OSU1z55QZ4bJIcb7kdUWokwGxr7dS43AXvMlfCC2lW3S00PyGjHFGVkBcadH GJBqz3V24hvCnYUkw2HnoC/Wt5XdH4NhfpMCZMrQc5IrfaFuyORI4zod4KT7/HsHMD Es2jPpwepXwsFp1XFNDJSzSktMgd4TqWaBaeFuDtcxSZQsV1500Z0HEMR2hvVqHfxU 9I5UICyWkkWTZOt+JYjiV70fHP/OSDSqw/4NXj9+Yxo6vBAYQXkzTqzqzSubnUUkJo /dledWB2x4+Py9gBJeBjgpSmcAR6GczyOQmLZ23+phhvNuntOHN7y7/pYe1lbvRnM9 6WZX7vcCcW7iA== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id 921E8A0099; Tue, 13 Apr 2021 07:36:38 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:36:37 +0400 Date: Tue, 13 Apr 2021 11:36:37 +0400 In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH v2 05/12] usb: dwc2: Add exit clock gating from session request interrupt To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan Message-Id: <20210413073638.921E8A0099@mailhost.synopsys.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Added clock gating exit flow from session request interrupt handler according programming guide. Signed-off-by: Artur Petrosyan --- Changes in v2: - None drivers/usb/dwc2/core_intr.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c index c764407e7633..550c52c1a0c7 100644 --- a/drivers/usb/dwc2/core_intr.c +++ b/drivers/usb/dwc2/core_intr.c @@ -316,12 +316,19 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) hsotg->lx_state); if (dwc2_is_device_mode(hsotg)) { - if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd) { - ret = dwc2_exit_partial_power_down(hsotg, 0, - true); - if (ret) - dev_err(hsotg->dev, - "exit power_down failed\n"); + if (hsotg->lx_state == DWC2_L2) { + if (hsotg->in_ppd) { + ret = dwc2_exit_partial_power_down(hsotg, 0, + true); + if (ret) + dev_err(hsotg->dev, + "exit power_down failed\n"); + } + + /* Exit gadget mode clock gating. */ + if (hsotg->params.power_down == + DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) + dwc2_gadget_exit_clock_gating(hsotg, 0); } /* From patchwork Tue Apr 13 07:36:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D470CC433ED for ; Tue, 13 Apr 2021 07:36:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B6D736135C for ; Tue, 13 Apr 2021 07:36:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240919AbhDMHhQ (ORCPT ); Tue, 13 Apr 2021 03:37:16 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.73.133]:36492 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240890AbhDMHhP (ORCPT ); Tue, 13 Apr 2021 03:37:15 -0400 Received: from mailhost.synopsys.com (mdc-mailhost2.synopsys.com [10.225.0.210]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 5D6AE40162; Tue, 13 Apr 2021 07:36:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618299416; bh=8Wm8ArFTDkXMAZMgFkFQMI2XRAMfTrV/2W6Sg9JcQCs=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=jzhJyLzu+Kn9s+Gr7rk8yTQmW9xewZsssP+0tgHceDntnhrGmYZ1bVo51GrJoVfXq BZnjHc+Bw7jKWbSvcDahYw1ebY/mijsRUBWLZyg60GuK3Sm2VCSI2bLcw9qi5JKrtP bptuzk5TqWZbc16cZjcywAJGszKJN6X7gf3kb/jWimIEI2bvZhuqqvORSEPHmwScwh jWiRsyHLQUIDW4qpFLufzRi3epC1I8tLEQuS0hyGXisJHIxPv0HcH67ocNz6NOZv25 H0sRMxDzBDbBg2v95fScxhWeh4q4xfVQ4UKIPWlKDEisXeKxsyq1cFoq8/IOUUNxjT NU6qbvEbhdK+w== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id 9F493A0094; Tue, 13 Apr 2021 07:36:53 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:36:52 +0400 Date: Tue, 13 Apr 2021 11:36:52 +0400 In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH v2 07/12] usb: dwc2: Update enter clock gating when port is suspended To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan Message-Id: <20210413073653.9F493A0094@mailhost.synopsys.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Updates the implementation of entering clock gating mode when core receives port suspend. Instead of setting the required bit fields of the registers inline, called the "dwc2_host_enter_clock_gating()" function. Signed-off-by: Artur Petrosyan --- Changes in v2: - None drivers/usb/dwc2/hcd.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 27f030d5de54..e1225fe6c61a 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -3298,7 +3298,6 @@ static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) { unsigned long flags; - u32 hprt0; u32 pcgctl; u32 gotgctl; int ret = 0; @@ -3323,22 +3322,12 @@ int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) break; case DWC2_POWER_DOWN_PARAM_HIBERNATION: case DWC2_POWER_DOWN_PARAM_NONE: - default: - hprt0 = dwc2_read_hprt0(hsotg); - hprt0 |= HPRT0_SUSP; - dwc2_writel(hsotg, hprt0, HPRT0); - hsotg->bus_suspended = true; /* - * If power_down is supported, Phy clock will be suspended - * after registers are backuped. + * If not hibernation nor partial power down are supported, + * clock gating is used to save power. */ - if (!hsotg->params.power_down) { - /* Suspend the Phy Clock */ - pcgctl = dwc2_readl(hsotg, PCGCTL); - pcgctl |= PCGCTL_STOPPCLK; - dwc2_writel(hsotg, pcgctl, PCGCTL); - udelay(10); - } + dwc2_host_enter_clock_gating(hsotg); + break; } /* For HNP the bus must be suspended for at least 200ms */ From patchwork Tue Apr 13 07:37:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F238AC433ED for ; Tue, 13 Apr 2021 07:37:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C87DF61370 for ; Tue, 13 Apr 2021 07:37:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241546AbhDMHhf (ORCPT ); Tue, 13 Apr 2021 03:37:35 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.73.133]:36512 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241264AbhDMHha (ORCPT ); Tue, 13 Apr 2021 03:37:30 -0400 Received: from mailhost.synopsys.com (mdc-mailhost2.synopsys.com [10.225.0.210]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 6E95940162; Tue, 13 Apr 2021 07:37:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618299431; bh=FU1Pw+VoM93ClV591eCHVeMJ32X04g+FqXMz7vZ5UjI=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=Hcekt9Zl0pJ1Q5uvzt1IbAK9aQO/5zCL3/JKs7wMb+MssqeoVdogqSlpWttOXonjO yG97zZ3mXOpFl9y9yVR6Kn1UnNST5dUqSJXDvGrHODoGSwPymynYLw27TZWPjhuuPU FQPzwqCwxU/IKs2LNqr8AhsOi3iFdzp/7oSbU2ZnU4K7PRiee2QYsNQvdtF5gofzUs iHLi91iM6ugXOVTpt4KJH8ADPboHMJk+gPe/SI5Ks4OVwxKD/2QYafmj7EqyOBZlKA 9wCvA6fd4VhYS2bHtR5LKRRkx3zppKuy1wiDK2CXUhGbMmUoVJut2lypNpkfj11ezF +3g7XlqrtRSBw== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id ADFC6A0094; Tue, 13 Apr 2021 07:37:08 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:37:07 +0400 Date: Tue, 13 Apr 2021 11:37:07 +0400 In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH v2 09/12] usb: dwc2: Allow exit clock gating in urb enqueue To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan Message-Id: <20210413073708.ADFC6A0094@mailhost.synopsys.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org When core is in clock gating state and an external hub is connected, upper layer sends URB enqueue request, which results in port reset issue. Added exit from clock gating state to avoid port reset issue and process upper layer request properly. Signed-off-by: Artur Petrosyan --- Changes in v2: - None drivers/usb/dwc2/hcd.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 8a42675ab94e..31d6a1b87228 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -4597,6 +4597,14 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, "exit partial_power_down failed\n"); } + if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && + hsotg->bus_suspended) { + if (dwc2_is_device_mode(hsotg)) + dwc2_gadget_exit_clock_gating(hsotg, 0); + else + dwc2_host_exit_clock_gating(hsotg, 0); + } + if (!ep) return -EINVAL; From patchwork Tue Apr 13 07:37:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Petrosyan X-Patchwork-Id: 420603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E79D7C433B4 for ; Tue, 13 Apr 2021 07:37:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C5E02613BC for ; Tue, 13 Apr 2021 07:37:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241914AbhDMHiD (ORCPT ); Tue, 13 Apr 2021 03:38:03 -0400 Received: from smtprelay-out1.synopsys.com ([149.117.87.133]:60574 "EHLO smtprelay-out1.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241950AbhDMHhp (ORCPT ); Tue, 13 Apr 2021 03:37:45 -0400 Received: from mailhost.synopsys.com (mdc-mailhost1.synopsys.com [10.225.0.209]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by smtprelay-out1.synopsys.com (Postfix) with ESMTPS id 6FCA7C0114; Tue, 13 Apr 2021 07:37:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1618299446; bh=AZ/oQOAeGT0gsqZk0VXwMupD/Fhho98Hy6eZwRCpkz0=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=Iyx+kiIBne9EeIjR6YIIHTDTIzTwoRI3PSH7rvBliaVc1H3lUlVBYYgvgKoSGmDf+ si8D2RRxrUHtPd2AR/jdNWBw7ieO8Nc7sJZM+FWWmFxNu7w9YOHq44M/x9jvHV47YZ oq/LegX19fAHFOR65pVwR6MAd0YlhOrc5Thyho/oCQzG+2Xu4SEjFpgT3ALjRE81Qf 8uKOA2SNDNA8NALgRSPW0g8zofQfRcHNGrnbZqNU3UwRahj5rqOhV8sl8hhyi+A/EF 7DZeJRhRNvEiqcZMyONFXYtQFnyJwg9U6MgyZ1AyAz/XWzynUI1FcSsC/LgrBGad8E W2eLadOsxakMQ== Received: from razpc-HP (razpc-hp.internal.synopsys.com [10.116.126.207]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailhost.synopsys.com (Postfix) with ESMTPSA id BA0FEA022E; Tue, 13 Apr 2021 07:37:23 +0000 (UTC) Received: by razpc-HP (sSMTP sendmail emulation); Tue, 13 Apr 2021 11:37:22 +0400 Date: Tue, 13 Apr 2021 11:37:22 +0400 In-Reply-To: References: X-SNPS-Relay: synopsys.com From: Artur Petrosyan Subject: [PATCH v2 11/12] usb: dwc2: Add clock gating exiting flow by system resume To: Felipe Balbi , Greg Kroah-Hartman , Minas Harutyunyan , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Cc: John Youn , Artur Petrosyan Message-Id: <20210413073723.BA0FEA022E@mailhost.synopsys.com> Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org If not hibernation nor partial power down are supported, port resume is done using the clock gating programming flow. Adds a new flow of exiting clock gating when PC is resumed. Signed-off-by: Artur Petrosyan --- Changes in v2: - None drivers/usb/dwc2/hcd.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 09dcd37b9ef8..04a1b53d65af 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -4445,6 +4445,28 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) break; case DWC2_POWER_DOWN_PARAM_HIBERNATION: case DWC2_POWER_DOWN_PARAM_NONE: + /* + * If not hibernation nor partial power down are supported, + * port resume is done using the clock gating programming flow. + */ + spin_unlock_irqrestore(&hsotg->lock, flags); + dwc2_host_exit_clock_gating(hsotg, 0); + + /* + * Initialize the Core for Host mode, as after system resume + * the global interrupts are disabled. + */ + dwc2_core_init(hsotg, false); + dwc2_enable_global_interrupts(hsotg); + dwc2_hcd_reinit(hsotg); + spin_lock_irqsave(&hsotg->lock, flags); + + /* + * Set HW accessible bit before powering on the controller + * since an interrupt may rise. + */ + set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); + break; default: hsotg->lx_state = DWC2_L0; goto unlock;