From patchwork Fri Jun 8 08:18:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 137942 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp586423lji; Fri, 8 Jun 2018 01:26:46 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLpZ1pziZBKMfUIC1rpi7SIpLosxcnynSfBMmlz0AJ57WBgWxxeLAxo97tBz8uWEEN3IZ2G X-Received: by 2002:a17:902:aa98:: with SMTP id d24-v6mr5560182plr.185.1528446406432; Fri, 08 Jun 2018 01:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528446406; cv=none; d=google.com; s=arc-20160816; b=PVZN/gCU3wiqsAvztuxS8vZ6FSYF5bDs91jd6ygYH1bsKRxdIsXjSaH+da/FjGRjKj Icpz4ByNT9hVSVMFlxvgSbag1wAPTqVBzhNQzbF7QMUbk/Qvo9FTKfVfaiLDb72fc/TH VT66Km3SGguGAD+O78+3idEbgpX1hNYIct2A+rj6h41xNToF8ZT/+fgG9rZeGKdX1GiG djhhErX9VBXsQ97rugFVa+cQqUrsEgwWEL9uqdbNd0XxnYs94HdN60ceWACzXw+Ci6vS ihZok+LNRviEG2jWXNs1YW5T5n+IMwwCYhiVUJcs4b92/xPFXzx87h27+35JuJoB8QB5 hwjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=3FkQjw0tnznQzkqhNl9915wjCXW19DdBddES+/u0pdI=; b=uwpJD6sVTO17AWN79B9Yxe59U/8JYi6uy5W0iBYmN0NzC+l9/BdE6ySZ+76Z+KFuAb JulD7iXVvQScjHfic1bQzLQh7G+PJxXCqvNASLl8NFDt09nTNfmQ9nGdiCc3+aej6vS8 wgGlJhkuEEGVaTuhIl7lhBuWsAr5HZJsKfS3+7ni/CJ7xT0ef5odubo5ikRkoQ4uKa4U AsuEqmIh+p3z4Bq11vohjr7wTUrXrxGF1qFOXqqYoKEWa6z59VkeTGAXFEK0NSzs+j9S JOR12NsfoS6u2I+iXRWPuPq2jnMoikJbRMCqQDFN6PkQV2fCU1mMJ81bOowoOx93+9lu GGlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D7A11XC9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si37260210ple.308.2018.06.08.01.26.46; Fri, 08 Jun 2018 01:26:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=D7A11XC9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752950AbeFHI0n (ORCPT + 30 others); Fri, 8 Jun 2018 04:26:43 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:39593 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752804AbeFHITE (ORCPT ); Fri, 8 Jun 2018 04:19:04 -0400 Received: by mail-pl0-f65.google.com with SMTP id f1-v6so7865979plt.6 for ; Fri, 08 Jun 2018 01:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3FkQjw0tnznQzkqhNl9915wjCXW19DdBddES+/u0pdI=; b=D7A11XC9NRb0A18pNGJQ+MUULMWZ24DD87PMtK1ouKTtEaJlz5CzywJQni4Xxm2vIS uwCkhELfoXJm29QE7Z3ZpglaARof5Vj4hGciCM/MY1teWI+as2nPpms2bkyrOc2hAT1y njLfAxMsQ90LE+oE64Gghv8Nf1B47XSxJn7AM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3FkQjw0tnznQzkqhNl9915wjCXW19DdBddES+/u0pdI=; b=NRbhH2zZ1KPCmzjusietB8Css/um8CRrxi3hYCkPI4/CcZnNuCprrIlJRTOokN+mIk ubKdkbjQPrs0c4Jo/ePxJHj/CdgRoTrLa1+4Ttre4Qj7KiyaF8qr4plbCbF6/BeD8Mk+ bnH7UW7nOZNOX4Wy0/4ZY4GzRs7QFQJJCc31osOpXBVzjIcZv7MsVOW0r8jMlaTpXGw0 hXp8Trqx1CPF0Wf54Y4U+Q+Jf8gA/y+itaqD8traywHVi4R01dObt4fQP5TnyqIkHOew kcimQdK9bsyN/KqSdmzFCfUJm4Th75XthN5uJC1MnlzDYUX7G3sITFMWytA0UGpjcrsQ euLg== X-Gm-Message-State: APt69E3WpnZXKbiy9KdSyQzrSOpuZuLmb+tq5sTCU5uqggE25lBEWls2 dnqjqQ+D53dyeV7ELj34D9wBvg== X-Received: by 2002:a17:902:6e4:: with SMTP id 91-v6mr5528041plh.63.1528445944162; Fri, 08 Jun 2018 01:19:04 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s4-v6sm72243947pgp.35.2018.06.08.01.19.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 01:19:03 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH 1/6] mmc: sdhci: add sd host v4 mode Date: Fri, 8 Jun 2018 16:18:08 +0800 Message-Id: <1528445893-14530-2-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> References: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduces a flag to record this. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 6 ++++++ drivers/mmc/host/sdhci.h | 6 ++++++ 2 files changed, 12 insertions(+) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 2ededa7f..cf5695f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3302,6 +3302,12 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; + if (host->version >= SDHCI_SPEC_400) { + if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & + SDHCI_CTRL_V4_MODE) + host->v4_mode = true; + } + if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) return; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c95b0a4..128b0ba 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -184,6 +184,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -270,6 +271,8 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 /* * End of controller registers. @@ -551,6 +554,9 @@ struct sdhci_host { u32 sdma_boundary; unsigned long private[0] ____cacheline_aligned; + + /* Host Version 4 Enable */ + bool v4_mode; }; struct sdhci_ops { From patchwork Fri Jun 8 08:18:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 137937 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp580151lji; Fri, 8 Jun 2018 01:19:15 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI0qvlxOgEQg0coA3QLx++PMBXIajFz279FlUcDtHtoX0H6yaMdPWsD6JJ8ygZgHdqumHJ4 X-Received: by 2002:a63:740c:: with SMTP id p12-v6mr4384577pgc.259.1528445955512; Fri, 08 Jun 2018 01:19:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528445955; cv=none; d=google.com; s=arc-20160816; b=lBtZEeackCcngLoZzo0Pah06zEOpPVvL/nesZv67CSaRazvUgFaItpGeNl2PohXDvj KY0TrzoK7ASfPLTyaEgSn/74t9k8xLdeNVORTR8Tut4eWqp94DW1E2g2Loy9gjwa9hx+ RjWwQdskPObXHHFvfDzroBeZIKdS+J0+5JMtwORp3GTkfcPHRfqU7AlZdcV36GdVOxJZ WujF6Ny8bqCA9pKk9OyOlRLpt3V6vHZVBFFDgAFyDTGE9O2AjR+PjSmWLeegEsVgFqPG faPlCVN2W1QbAaGdEh4+uFgRsAOI0a5wp9SYUXPyXWqcvQmTCZUbYdvZlcswMVcUxjL9 hLmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=HweywlkV3W7hX6j4jAziXnB8202QrrYYO0FfXOW5ydM=; b=nDRr6/jOY3K5UiAjsjauMrKWco8FhwOBDlLxfz+nBGCQjhLCkvTQl0HBxQNIyC+t3D 1YknAqDXd0yuGd3nKs+DfMwVBvB4EuM+C9EcUoXdCri3870qOqwCvX8Yuk5nX9T/A3JF i1wljxW5yfpx1Ca6gx2KlC5oISVzeaM8CN5XTUnONuumW4qj4DBS0r+nU7VGFI0fKZ+2 lelo45ArHXD1sUY0Dr839K86HsZu9rvfW6coCQpDbTw9G/O8Y3B2Ub6xWTl/+ABcdwwx 69AtmjfaY6dgJH+NF/MhIk+NGfNHA1TtF3in0hsrMgxix9x6HsoSP6xxIM2XxbP/x3gt HhKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jpYah+g6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b10-v6si57043725pla.282.2018.06.08.01.19.15; Fri, 08 Jun 2018 01:19:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jpYah+g6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752896AbeFHITN (ORCPT + 30 others); Fri, 8 Jun 2018 04:19:13 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:40511 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752326AbeFHITI (ORCPT ); Fri, 8 Jun 2018 04:19:08 -0400 Received: by mail-pf0-f193.google.com with SMTP id z24-v6so6259557pfe.7 for ; Fri, 08 Jun 2018 01:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HweywlkV3W7hX6j4jAziXnB8202QrrYYO0FfXOW5ydM=; b=jpYah+g6bV7iiyUJ0nYKHVkiO4s11rtRN+TAWmZTzk2YGsyugFV8fqtax2Fgkg6wsw kOKCCg4mKNdC0gmZeD+igEMjcmEKJqt2eKn9OCxysFMOl5zZxTVoGp4r03/q/uImtGRO 2VxdFL2wnOwn66W3nOPx15Xb0q+GWFqXYg9X4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HweywlkV3W7hX6j4jAziXnB8202QrrYYO0FfXOW5ydM=; b=h41OZY2fGnn0HKCRbaKB9gVAMR/sK10TOtpb64cJRbccwz04Uwnxtlspumfi5SN4ur 2XGqWP5BtbwypITenTkhnJ8rGMyV/Zbgk2DVWlpk4dziV9uc9n15ylXLk6pqVSg5vaN4 IV7+jmznowVIdem3KxR8k3Ib76sMi1b2Yhn+6EeLeh59125CeydQddZIrh2+XN5xilQW MEYmTQ6tZ3HmSCIFPUs5ZeS9HWM+u/z+iEl1ilWfesJZjeALa++8W5lHh9EQGJBy8uZx XuZx1RfUUDeUVLvBoBzez4VhLCv6mhpLZu0zGt54RImDmnRBswodUUY/xZV0BAd9zbx0 xFqA== X-Gm-Message-State: APt69E19OekY2XHCOQi3PiiZVBBfKWbo5miUYklYCzNOaDdZcrF6gKok jpzqWurTQO0pSY4BBFapiehTNw== X-Received: by 2002:a63:6d0:: with SMTP id 199-v6mr4348329pgg.338.1528445947598; Fri, 08 Jun 2018 01:19:07 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s4-v6sm72243947pgp.35.2018.06.08.01.19.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 01:19:06 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH 2/6] mmc: sdhci: made changes for System Address register of SDMA Date: Fri, 8 Jun 2018 16:18:09 +0800 Message-Id: <1528445893-14530-3-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> References: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index cf5695f..f57201f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -805,6 +805,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { u8 ctrl; + u32 reg; struct mmc_data *data = cmd->data; if (sdhci_data_line_cmd(cmd)) @@ -894,8 +895,10 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) SDHCI_ADMA_ADDRESS_HI); } else { WARN_ON(sg_cnt != 1); + reg = host->v4_mode ? SDHCI_ADMA_ADDRESS : + SDHCI_DMA_ADDRESS; sdhci_writel(host, sdhci_sdma_address(host), - SDHCI_DMA_ADDRESS); + reg); } } @@ -2721,6 +2724,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) */ if (intmask & SDHCI_INT_DMA_END) { u32 dmastart, dmanow; + u32 reg; dmastart = sdhci_sdma_address(host); dmanow = dmastart + host->data->bytes_xfered; @@ -2733,7 +2737,9 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) host->data->bytes_xfered = dmanow - dmastart; DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n", dmastart, host->data->bytes_xfered, dmanow); - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + reg = host->v4_mode ? SDHCI_ADMA_ADDRESS : + SDHCI_DMA_ADDRESS; + sdhci_writel(host, dmanow, reg); } if (intmask & SDHCI_INT_DATA_END) { From patchwork Fri Jun 8 08:18:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 137941 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp585940lji; Fri, 8 Jun 2018 01:26:14 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI+9dFdUQV5KrOx8e8Fp+9J9lmpC2Pi0j0g/nYQQnPWcxwdouzWD3hOxLdfxC503878ET/2 X-Received: by 2002:a63:40c7:: with SMTP id n190-v6mr4497796pga.248.1528446374596; Fri, 08 Jun 2018 01:26:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528446374; cv=none; d=google.com; s=arc-20160816; b=KcZ2GqST8pPV3UPOF5IKscsU4IYv8FIJmRkuRELzK+Bg5DGfmwz783iApADBfWEuHl FiV7C+aA4T3zIZZAUOYPhpRbwaK7jWv2JB7qUNYA1qubTucAiYxWjdULuP8bLoSJ7y0Z pwY0tE8IM7WSGFFNM8/NjWAqx9fBHMPdO5Q6D7iQeCB+TmCEcP2Wl6n6hBiKs6vfrV2V 7TkwZwyMOqijMQeoJ9r5dm5tynlg49Yzgk2E+zvzWTdBpJPirfkcVVLo+igNEzk7RjTZ 3PRK0b5vLmBU+CQ1VEaOugsZf08JQ4WhGym9ogRUhhZz0sx0luW1nakev7By5800YGlo YVGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+3GjdRwaIJtxrpzrWThzILTOwfyJwnhrNFXpyH81hF8=; b=0zxTIqObKYJRRQvv2JCta+RRPRty/fP2aGWnedvtK+Ro+Ga7na1NRwStAS/062k6F6 rrjhL0tp5RkGnm80JpMDjsyuPaWRkKpWYokAgavPDApi+DqswEN2R4dPiVAmy9XikIgH HW0aVfwO4q0C324+m61ihRA0O+REXD+jy0rS/AF2wOV7AfTpdTaCJWJneFfxVHE1YNsY vp2MFmqHmTzLoQy2+doBYPYyTMyZofD4zqrJd3WuDzqz+6wMIG2Y9E1xhmF/eWTUmVTl E984lcotZuyxxsQZKWilNvmbymBnDId2hM8xTtms7G0qiqNnPdDZJTBjGGszYXzcmqpx C89w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UFJ/Mun3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h12-v6si34372897plk.535.2018.06.08.01.26.14; Fri, 08 Jun 2018 01:26:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UFJ/Mun3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932414AbeFHI0L (ORCPT + 30 others); Fri, 8 Jun 2018 04:26:11 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:45806 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752858AbeFHITM (ORCPT ); Fri, 8 Jun 2018 04:19:12 -0400 Received: by mail-pl0-f66.google.com with SMTP id c23-v6so7849593plz.12 for ; Fri, 08 Jun 2018 01:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+3GjdRwaIJtxrpzrWThzILTOwfyJwnhrNFXpyH81hF8=; b=UFJ/Mun3Rav880NZKFXyn60VYo45EZo4FuF0gM5rZeCUvAsN+8Bb94r0mXRybMAvag lHrqn5VvxYqWDC2wvBPRri/LK+u+7gEMh/K18zvbSh1qgoo72Ia5ANclewS57pqyxUjx twul1gwB+RmLuVG/fqAs/Bu4Owbn1czWE3tps= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+3GjdRwaIJtxrpzrWThzILTOwfyJwnhrNFXpyH81hF8=; b=RwN9GhM92VYbplGGxOMnWQ6lY8f8DFuOzasyGfxoJ6WnXR2jQ570YpQG8+6/loBbFx oCsxlT7iZhU0tR3lh9V6pg9Gq1o2/BaZ3owlRfxuNvKSgheWVbm5jJoWSB9GBxeDCCQS ueZTQRO/WxKMyQFIklo2kom0GKuk8kBciThn/KKwSPi3DBBNalErmd+Tae0mkuDZ3wZX CF23LzkEBT+uOMlu5EIzklgCMmE2GSxZavelus2iQ45kXU1HEwPktL0stUeFkcNdxfOm 0u9ptmDWuwrR/plwRk9PQYhpaL0wcuc/e+9HKN5HnVKD/AhYdPlC8d6qMjGM9RCZCID9 Qrrg== X-Gm-Message-State: APt69E1l0H3zklJlILbQnVMYG0iJ/BsYYFq6GzQTcG+LXdOrsHhT5/3E pE9qfKcg6m04ZdEx51b23ZIZLw== X-Received: by 2002:a17:902:380c:: with SMTP id l12-v6mr5606277plc.19.1528445951264; Fri, 08 Jun 2018 01:19:11 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s4-v6sm72243947pgp.35.2018.06.08.01.19.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 01:19:10 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH 3/6] mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode Date: Fri, 8 Jun 2018 16:18:10 +0800 Message-Id: <1528445893-14530-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> References: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 50 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 23 +++++++++++++++++----- 2 files changed, 55 insertions(+), 18 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index f57201f..5d3b0d8 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -585,6 +585,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, void *desc, *align; char *buffer; int len, offset, i; + unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host); + unsigned int adma2_mask = SDHCI_ADMA2_MASK(host); /* * The spec does not specify endianness of descriptor table. @@ -608,8 +610,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, * buffer for the (up to three) bytes that screw up the * alignment. */ - offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & - SDHCI_ADMA2_MASK; + offset = (adma2_align - (addr & adma2_align)) & + adma2_mask; if (offset) { if (data->flags & MMC_DATA_WRITE) { buffer = sdhci_kmap_atomic(sg, &flags); @@ -623,8 +625,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, BUG_ON(offset > 65536); - align += SDHCI_ADMA2_ALIGN; - align_addr += SDHCI_ADMA2_ALIGN; + align += adma2_align; + align_addr += adma2_align; desc += host->desc_sz; @@ -668,13 +670,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host, void *align; char *buffer; unsigned long flags; + unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host); + unsigned int adma2_mask = SDHCI_ADMA2_MASK(host); if (data->flags & MMC_DATA_READ) { bool has_unaligned = false; /* Do a quick scan of the SG list for any unaligned mappings */ for_each_sg(data->sg, sg, host->sg_count, i) - if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { + if (sg_dma_address(sg) & adma2_mask) { has_unaligned = true; break; } @@ -686,15 +690,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host, align = host->align_buffer; for_each_sg(data->sg, sg, host->sg_count, i) { - if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { - size = SDHCI_ADMA2_ALIGN - - (sg_dma_address(sg) & SDHCI_ADMA2_MASK); + if (sg_dma_address(sg) & adma2_mask) { + size = adma2_align - + (sg_dma_address(sg) & adma2_mask); buffer = sdhci_kmap_atomic(sg, &flags); memcpy(buffer, align, size); sdhci_kunmap_atomic(buffer, &flags); - align += SDHCI_ADMA2_ALIGN; + align += adma2_align; } } } @@ -3400,6 +3404,26 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_use_64bit_dma(struct sdhci_host *host) +{ + u32 addr64bit_en; + + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode, 64-bit DMA Addressing for V4 mode + * is enabled only if 64-bit Addressing =1 in the Host Control 2 + * register. + */ + if (host->version == SDHCI_SPEC_410 && host->v4_mode) { + addr64bit_en = (sdhci_readw(host, SDHCI_HOST_CONTROL2) & + SDHCI_CTRL_64BIT_ADDR); + return addr64bit_en && (host->caps & SDHCI_CAN_64BIT_V4); + } + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3471,7 +3495,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_use_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3505,15 +3529,15 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; } - host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; + host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN(host); buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 128b0ba..820a863 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -206,6 +207,7 @@ #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_64BIT_V4 0x8000000 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 @@ -297,9 +299,14 @@ struct sdhci_adma2_32_desc { __le32 addr; } __packed __aligned(4); -/* ADMA2 data alignment */ -#define SDHCI_ADMA2_ALIGN 4 -#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) +/* + * ADMA2 data alignment + * According to SD Host Controller spec v4.10, if Host Version 4 Enable is set + * in the Host Control 2 register, 128-bit Descriptor will be selected which + * shall be aligned 8-byte address boundary. + */ +#define SDHCI_ADMA2_ALIGN(host) ((host)->v4_mode ? 8 : 4) +#define SDHCI_ADMA2_MASK(host) (SDHCI_ADMA2_ALIGN(host) - 1) /* * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte @@ -308,8 +315,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Fri Jun 8 08:18:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 137938 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp580276lji; Fri, 8 Jun 2018 01:19:24 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJfLJ5jI9zm9xzhsjgpXaLUnpHtcSSpboxky9nwoUNIvCBj6X4j7BaxdY6gPfK0h+hEdoD1 X-Received: by 2002:a17:902:224:: with SMTP id 33-v6mr5460001plc.309.1528445964395; Fri, 08 Jun 2018 01:19:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528445964; cv=none; d=google.com; s=arc-20160816; b=VCVjByqUQS1tXurwBEv0CCWaw0UsVe2qcOoZF4AWgYW3VkJGyWdAo0RBXt9C5bpmkP bey+ZVkuh9+FkhFcY71SvtHZgLTPl0ok82OjZCfYlT9DsA4Y0SFz8GOHukm2FJXZEkpW h5i7fZBxg7zCTcG3mXWi6ZelwLHCeWJUv3gIwipDDtR6LMySxSF5EzQlTX3SaZPFovxD E/p7bcHAIeapOHnyy3VSjTYo01wJHZNaw8aHIviLf2tFY8l6271COqjkPdA4cDYQ5iLx gdBgf0XUe5O4sO3nrqeYt7ZiFiw5VN2UHMpqMa24tklT0TgR4y0wb9ppcOzfQZNJSWdE nxcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=2kKdK2qZqm7YxqxQreraVLLw0s8TN4UgsB3k/YpdPQI=; b=L/bB19S+NJPoe2PXxtNl4bRSR982ZcCvD8Re84xDIdZFuc0NhJOlwjdFqB4E/brmH8 5DjagFIqUiFpaMfDkILmpPUebQxnyIlfaFJfcCDZY0QkBGMAhd/7xcK1XK/NWOl4fWuG vJAzxuOd7gsO+UOktkwSOXf+axlnxFAq5p5eqRVWavXDOKQJ6Nn2t3n5r+/A463pJfK/ fd/dT1qotnHDCnOqx9ORIG4+PqCYCaABjvC1acZrzSY2bfzQgwQy1B3meIUTBbveCwkG aavwGi3GBgmoQ1LXwlOEaFCB8TskAYSByaGIQuAmQIIo9IcUhbQ1I/k/jX3+Sh1O6Zc1 8/UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eMu3uV+F; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r7-v6si56442506ple.585.2018.06.08.01.19.24; Fri, 08 Jun 2018 01:19:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eMu3uV+F; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752948AbeFHITV (ORCPT + 30 others); Fri, 8 Jun 2018 04:19:21 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:44239 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752897AbeFHITP (ORCPT ); Fri, 8 Jun 2018 04:19:15 -0400 Received: by mail-pl0-f67.google.com with SMTP id z9-v6so7854833plk.11 for ; Fri, 08 Jun 2018 01:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2kKdK2qZqm7YxqxQreraVLLw0s8TN4UgsB3k/YpdPQI=; b=eMu3uV+FIFUH5dBfHJQiTcF0H8MCPRxIB+C1Z8BezzykBY/c9VijVF7D+18wXIupGp 9aY28w3zMYMd9f4wZZWE//C9ccivy+hltm8SjDk5jBnJGI5a+lUBK1LuAlkY6UTSbi+2 lt+JsJqsQ9mWalp1GrUydWKAmewnFKaXj9XeM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2kKdK2qZqm7YxqxQreraVLLw0s8TN4UgsB3k/YpdPQI=; b=c4zpc+GFUNIe6tBlQNg/q0Qku/FJe2oS73AVap+aWE53uKPq9Ug5Y51oUOsHh6SgAr 9bZLZOtkNKyCj4++w/VrURnXKb0oUz7U7jeRFFsDVVMATSMKTmNxWiSmEWzdVXp9ee5B 26tQdfQ7/thZ/9PbAKDvNPl/NlD4ZwTgWMMxO95zB3C/PPbn3DgYFictaxnNsN50Wt9i 9DTRQfiDrbn2TvQwb/rGni2vxG2wc1kzCmI+QDFTZwWlZnTabeU1tu2TivS3baENv7MN MAG8Qmk8f497A3wxuChK50Ebbz0Op9ba8GmtYUVP9mX7m+7ga72U+dBpMeRqVk6KvJ1z Lcrw== X-Gm-Message-State: APt69E3CBhpRDd2xaI7uV0Uwff7MP9Mqp12HhGgjBJLJuU5E/Yw7Ym9E RK2BjpAsqAxNIVeyQZn6W/JDwQ== X-Received: by 2002:a17:902:8f8b:: with SMTP id z11-v6mr5516405plo.203.1528445954765; Fri, 08 Jun 2018 01:19:14 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s4-v6sm72243947pgp.35.2018.06.08.01.19.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 01:19:13 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH 4/6] mmc: sdhci: add 32-bit block count support for v4 mode Date: Fri, 8 Jun 2018 16:18:11 +0800 Message-Id: <1528445893-14530-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> References: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When Host Version 4 is enabled, SDMA System Address register is re-defined as 32-bit Block Count, and SDMA uses ADMA System Address register (05Fh-058h) instead. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 5d3b0d8..b8ee124 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -943,7 +943,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + reg = host->v4_mode ? SDHCI_32BIT_BLK_CNT : SDHCI_BLOCK_COUNT; + sdhci_writew(host, data->blocks, reg); } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 820a863..1e84539 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) From patchwork Fri Jun 8 08:18:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 137940 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp585565lji; Fri, 8 Jun 2018 01:25:47 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLxvapZHImZ0WLUnXAJNiSsnnoYqDVQQYRh+NUOaJ9NNcPQACczKnqeh26MJSr5wHofXOv0 X-Received: by 2002:a17:902:26a:: with SMTP id 97-v6mr5628894plc.367.1528446347618; Fri, 08 Jun 2018 01:25:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528446347; cv=none; d=google.com; s=arc-20160816; b=IU0VmLiF7Dj6C/dyyDdE3Yf12wsXztRC5TfUk8zLzSlavNXLvFXhdZ+Cuy4xulg5vJ k23adPlt7r+gc6E3h+HcbmkKLHz2O6x+99Wp7/pI442q9e6e8A5P6YXJC00Egyf/VPda UgBJWU0JlTiaF5tRyUeUbLdcytl6bMwvFBcVPhw5TyhQCTeFclUI1UThOHZXLcP1rxUI 4z36dnP/H29IH5JFAJJ0lrqwZCh/gN88QKroT88yZ+jY3Wyc0yqayktwTgBF4MuswMGK 5rnTpXF97LEtLbwTzK8CoApi7rOhTvYn1DHxQm46n5HyWbm74Y7BSPTsY/n9wuK557IO 4ZLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Y2y/xY2dusr5GMTlLcs29f19Nju3/wuuxjplM+exAbo=; b=sqsj/9TFRsp8xnAmHMpa9884C9p+6Yui0EE430rakRYU2Z7farhQvtF2ZWRl0+DIKa yQLxawvLDMndC+IZuB7UbBEocLEJZTt1umWhTRaNl7WN/sOLo6qibFDTxehlzWffZ79e mTXDsYqWL4PnTmr2Ou1Wt/7OTSMBfHXjA3UIN3rOaIHHxqza0QkW8lJ8AAZ5dkgc5riY Sr9NKshSsZj/MxzedP/oEcD8gQN4HR0VtSIBULGANvkGOtTXhGK+TY7MRmM9y/GKoHTl AUxYj4sS9RDMTkZQMUxWFS2mQBjWALIldTvMDnPaKtHB8w9O2SYSesSMNgTTx3HRPZ/l mRzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FKieoiP+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e12-v6si10040218pgu.267.2018.06.08.01.25.47; Fri, 08 Jun 2018 01:25:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FKieoiP+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932362AbeFHIZn (ORCPT + 30 others); Fri, 8 Jun 2018 04:25:43 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:46057 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752910AbeFHITS (ORCPT ); Fri, 8 Jun 2018 04:19:18 -0400 Received: by mail-pg0-f68.google.com with SMTP id z1-v6so6030970pgv.12 for ; Fri, 08 Jun 2018 01:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y2y/xY2dusr5GMTlLcs29f19Nju3/wuuxjplM+exAbo=; b=FKieoiP+oTs39Jw8HxQ3lxOLeBs5f6t7CE83ff/85RIfHalbD8s+wfshp/M8iV4tbI I1r33vk+lPq7y6XD3ZVaO8Fh6nIg6wFXcDFUNOrKdsTKnDpXZsMJyl9eo8ZphQ+Z5LFb J6x6a2dFhQjM7Y1pZdermG1QvPPODua+nlxqs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y2y/xY2dusr5GMTlLcs29f19Nju3/wuuxjplM+exAbo=; b=nECMdiFDmNyI1wCI+iPx0WbTZ8QsW2Hp2DMZ7GXQRJMaLiHbzFyBdm/DVfYY642C98 vdZJ88kdmtCW0Cyyfr0X9YCBJRPmutuDl+6H9UstiJjR6EZDixHAxIE8F964+FH5YFFa OnUuZqIOrzX324BT0Etzk+4Fm+YnvrNzdA1NI3x24FrkQP28RrOcfBYZ9u/+3hRZbyrr FHQoCXPLHVLKX4TEwMdX03z9SUxQABJE4qh8/uKyBi18nd/5EtxJ+0cBk3KQxHjyZPkE +ZWhkuQyoAmCruQDHoGv2f8dmEXKJkkTOFZc7vEHXLpBOUkeZVP+3ZrRLICzCkdO90TQ jYow== X-Gm-Message-State: APt69E2c3QVJTPY/SastqmAYkIRwKuJvt1iEkT34lCQYzmXuigyD6tg6 wzjwttawQ2bSPCzmAbvk5oImTA== X-Received: by 2002:a62:e816:: with SMTP id c22-v6mr5006819pfi.124.1528445958137; Fri, 08 Jun 2018 01:19:18 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s4-v6sm72243947pgp.35.2018.06.08.01.19.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 01:19:17 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH 5/6] mmc: sdhci: add CMD23 support for v4 mode Date: Fri, 8 Jun 2018 16:18:12 +0800 Message-Id: <1528445893-14530-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> References: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Driver Version 4.10 adds a new bit in Host Control 2 Register for selecting Auto CMD23 or Auto CMD12 for ADMA3 data transfer. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 16 +++++++++++++++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 16 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index b8ee124..3b2af7e 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -954,6 +954,20 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host *host, !mrq->cap_cmd_during_tfr; } +static inline void sdhci_set_auto_cmd23(struct sdhci_host *host, + struct mmc_command *cmd) +{ + u16 ctrl2; + + if (host->v4_mode) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CMD23_ENABLE; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } else { + sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); + } +} + static void sdhci_set_transfer_mode(struct sdhci_host *host, struct mmc_command *cmd) { @@ -989,7 +1003,7 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, mode |= SDHCI_TRNS_AUTO_CMD12; else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { mode |= SDHCI_TRNS_AUTO_CMD23; - sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); + sdhci_set_auto_cmd23(host, cmd); } } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 1e84539..d5e1c10 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 From patchwork Fri Jun 8 08:18:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 137939 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp580387lji; Fri, 8 Jun 2018 01:19:33 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLgw1CFrNDGvzTlVwaNZnAB7esudVOL5lXf0+BFgDDY+FWL6CZX2BJilfenx/1LIKFRjLZE X-Received: by 2002:a17:902:b611:: with SMTP id b17-v6mr5518600pls.284.1528445973006; Fri, 08 Jun 2018 01:19:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528445973; cv=none; d=google.com; s=arc-20160816; b=UlBY7rpsKV2LWc2w7NsH5Cx9K1KPrNLpt6CQcCoHLIxAe9PyxeXr8zOl1S+ZqyxdcI uKAmulzAWJ6d7L23hYcQpop8tBIUZmo3h+1idZhdBfNqULUi1kek/AW3sblxDsaEmChK IlPOT2x24+dBSkrqF7CvTkARQzM61jH6nPYgP3a3aYLVDSALcS8ZpFOuJ3zhZr+iRElT QjX8IVlpU9Z0k4BEd0HYzHL7Rov707VwsqgEx9t8xKMZKp79D5B0d87YYhL1FjAsFVb5 nsrtjQzjZm/xmBchdr4xu9ZLji51z9VlBDOh6YL/zjNIstRCXEBnKuF34XHR0EAZ+oGr qC1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=OyYJFC/ULg+WaShQE42PX674Gh+T+hIOdh6V3P9Zpto=; b=v/20F49ONc8rBUcMJ2Ijs8zpfFDOIyF87hvAZMQuacExDT7bqb6sgiQ40dRU/58t4z Qd+KawbMSVbtLLW+Ecy4b/dLdMCwWZYHAiEJxwpEqQVlWJy7ExviPOg62ItsE4I3z0Hk dthXb8s0hLUxzI6EJiUpO3Mnw7kGJgyw6aM5rGp6uZ/WcJUQDgCEv+3JxyZd4c5+4P1T kjO6Lsas3MyfSjFXTiqhIK755AXUZvNLdaAWfUT8kTqCLc4klme03d9otZ3n/XsLr+IQ mbD4xX6jdKyIXeiWfxMGTCumbbRKfiNosirvIihaQQI06X+4L7n9JR5LzCvOQyh5InX+ FwGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jaEj11y6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r7-v6si56442506ple.585.2018.06.08.01.19.32; Fri, 08 Jun 2018 01:19:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jaEj11y6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932143AbeFHITa (ORCPT + 30 others); Fri, 8 Jun 2018 04:19:30 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:41674 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752952AbeFHITW (ORCPT ); Fri, 8 Jun 2018 04:19:22 -0400 Received: by mail-pf0-f193.google.com with SMTP id a11-v6so6256107pff.8 for ; Fri, 08 Jun 2018 01:19:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OyYJFC/ULg+WaShQE42PX674Gh+T+hIOdh6V3P9Zpto=; b=jaEj11y6u5WdwqbmDEk+6GiMoeZP2JBcneGCwomVUnfqid11cG/0gS1KG1GH7bCqj3 +R1wveFnmjKW7Ywf2GQ289H7vpOAQaYw3VxF/7ToMRHvb2eO6KNSqqypuVIqs7QYpxGy Pg8k5cZvXA1x8CVcDliAlb1sZ7k2XE3jzb4Rk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OyYJFC/ULg+WaShQE42PX674Gh+T+hIOdh6V3P9Zpto=; b=JoPLy4z+lNNfhNPECHKd4++Yzv41nS1RN/rlM6RE68sI0JQDrWxKlAf8g2FRE7ALKC WP6BZFdDKhnLe2BcaEC+dytB+k6Ij5L89oJ6EJmkxgNQPC/PHtJbVYyp1y/RUD0xSxyh qqu1WXkatu71PotpP15ADXueoZuYvaJC8SumXW36fKCLFTl0lhZvTmeskHUBRB1AoSdu ZHsatjHSofq+Rc+ZSd1oMKTIWb2he48XGPGM235S2p006YO9KGAOhUjlsnoJFZEEoVHY XRlGstZr/GmnMD9gXc7Ylaphc5zeE+nhgGpXO+q9epwNgkZpiTJNAr0wYpqopdgRDT6C RiXw== X-Gm-Message-State: APt69E0dgASHpKtqKTU55vH2GrG7nkS+Ylox6hcxTWYh4u56DrlHrCYc 2sNs/h7tGXu3JbHsYFER53rlzQ== X-Received: by 2002:a62:f551:: with SMTP id n78-v6mr5067968pfh.200.1528445961866; Fri, 08 Jun 2018 01:19:21 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id s4-v6sm72243947pgp.35.2018.06.08.01.19.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Jun 2018 01:19:20 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH 6/6] mmc: host: sdhci-sprd: added Spreadtrum's host controller R11 Date: Fri, 8 Jun 2018 16:18:13 +0800 Message-Id: <1528445893-14530-7-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> References: <1528445893-14530-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller - R11 found in some latest Spreadtrum chipsets. R11 is a variant based on SD v4.0 specification. With this driver, mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd-r11.c | 472 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 486 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd-r11.c -- 2.7.4 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 9589f9c..563baf5 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -584,6 +584,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD_R11 + tristate "Spreadtrum SDIO host Controller(IP version: R11P0)" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller(R11P0) in Spreadtrum + SoCs. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 6aead24..417394d 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o +obj-$(CONFIG_MMC_SDHCI_SPRD_R11) += sdhci-sprd-r11.o ifeq ($(CONFIG_CB710_DEBUG),y) CFLAGS-cb710-mmc += -DDEBUG diff --git a/drivers/mmc/host/sdhci-sprd-r11.c b/drivers/mmc/host/sdhci-sprd-r11.c new file mode 100644 index 0000000..fcd093a5 --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd-r11.c @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV (1 << 5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV (1 << 13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV (1 << 21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV (1 << 29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN (1 << 25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN (1 << 24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK (1 << 0) +#define SDHCI_SPRD_BIT_DLL_VAL (1 << 1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* SDHCI_SOFTWARE_RESET */ +#define SDHCI_HW_RESET_CARD 0x8 /* For Spreadtrum's design */ + +#define SDHCI_SPRD_MAX_CUR 1020 +#define SDHCI_SPRD_CLK_MAX_DIV 0x3FF + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_source; + struct clk *clk_enable; + u32 base_rate; +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static int sdhci_sprd_get_dt_resource(struct platform_device *pdev, + struct sdhci_sprd_host *sprd_host) +{ + int ret = 0; + struct clk *clk; + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_warn(&pdev->dev, "Failed to get sdio clock (%d)\n", ret); + goto out; + } + sprd_host->clk_sdio = clk; + + clk = devm_clk_get(&pdev->dev, "source"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_warn(&pdev->dev, "Failed to get source clock (%d)\n", ret); + goto out; + } + sprd_host->clk_source = clk; + + clk_set_parent(sprd_host->clk_sdio, sprd_host->clk_source); + sprd_host->base_rate = clk_get_rate(sprd_host->clk_source); + if (!sprd_host->base_rate) { + sprd_host->base_rate = 26000000; + dev_warn(&pdev->dev, "The source clock rate is 0\n"); + } + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_warn(&pdev->dev, "Failed to get gate clock (%d)\n", ret); + goto out; + } + sprd_host->clk_enable = clk; + +out: + return ret; +} + +static void sdhci_sprd_set_mmc_struct(struct platform_device *pdev, + struct mmc_host *mmc) +{ + struct device_node *np = pdev->dev.of_node; + struct sdhci_host *host = mmc_priv(mmc); + + mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + + mmc_of_parse(mmc); + mmc_of_parse_voltage(np, &host->ocr_mask); + + mmc->ocr_avail = 0x40000; + mmc->ocr_avail_sdio = mmc->ocr_avail; + mmc->ocr_avail_sd = mmc->ocr_avail; + mmc->ocr_avail_mmc = mmc->ocr_avail; + + mmc->max_current_330 = SDHCI_SPRD_MAX_CUR; + mmc->max_current_300 = SDHCI_SPRD_MAX_CUR; + mmc->max_current_180 = SDHCI_SPRD_MAX_CUR; + + host->dma_mask = DMA_BIT_MASK(64); + mmc_dev(host->mmc)->dma_mask = &host->dma_mask; +} + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set 64-bit addressing modes */ + val = sdhci_readw(host, SDHCI_HOST_CONTROL2); + val |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, val, SDHCI_HOST_CONTROL2); + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + return writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + return writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= (~SDHCI_CLOCK_CARD_EN); + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } + +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_reset(struct sdhci_host *host, u8 mask) +{ + sdhci_reset(host, mask); +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 = SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 = SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 = SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 = SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 = SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 = SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 = SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* Note: don't use sdhci_readb/writeb() API here */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + udelay(10); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + udelay(300); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_sprd_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + sprd_host = TO_SPRD_HOST(host); + + ret = sdhci_sprd_get_dt_resource(pdev, sprd_host); + if (ret) + goto pltfm_free; + + clk_prepare_enable(sprd_host->clk_sdio); + clk_prepare_enable(sprd_host->clk_enable); + + sdhci_sprd_init_config(host); + + sdhci_sprd_set_mmc_struct(pdev, host->mmc); + + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + ret = sdhci_add_host(host); + if (ret) { + dev_err(&pdev->dev, "failed to add mmc host: %d\n", ret); + goto pm_runtime_disable; + } + + return 0; + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhc-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + clk_prepare_enable(sprd_host->clk_enable); + clk_prepare_enable(sprd_host->clk_sdio); + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11");