From patchwork Thu Jun 14 18:08:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138592 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2438157lji; Thu, 14 Jun 2018 11:10:30 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKaObr+Q/c18ngZ8Cuu+tVIGL0BD9OKv1TXNd3/5TqLQPy8/Vr7JJwqbMj5IIxv9ZIPZcmf X-Received: by 2002:aa7:d0d2:: with SMTP id u18-v6mr3418393edo.205.1528999830223; Thu, 14 Jun 2018 11:10:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528999830; cv=none; d=google.com; s=arc-20160816; b=f22eknpSLJI8LT6iiIxQ3kSG8BwjbFewmSRDNIGp9BJw2yw6r11IOr5BOxEX85bGFb UX+VeW9BfU4G0Jad2XxhyTnQIaNkQ72LMtOoswf6ejdMmAjH7ISphGQZq/M6Qgf3bTeW QoddWi4MhHok8broW4Dot4+xvAzmPQjcDRgjJ2yJDFC9j/xUo0pyp8B6HTgrTJeJLKk6 X671HsI4MzeqiWcUQdE3tZLDC9tL3fltd0yl1IG+SfOWD4XsM1fDbMnqQDux6WodALoM EFMQpMLmYdkcyBQ4ywjg2/Mvhf5uu9RRYUKJbsbWHmv0GFOw0NTrERsRv/o4aVhMv6fd 1bAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=p20ssjTZFVZNGyfS0K7zgATXmd0UvtpfD992cZOXWvE=; b=F7zr4QnpUtaevFJZZ6JmiFt/LY7Q6x4agCZFJ5S/TDCYkhS5RZ7VAMpPVx1Jsg7ciz iOyEB7ECzvmGDfC+O8cPclbx+xc1YEpZ2JB80MITYI0foq2uQHdmQMnR5JMDQFjnoGBV csIn1SaaWXYVZVutmio9ilPJ9FqMzXaCL8UY9SWbB+BS4XBC+WbU0vx6BVwc0Z0DwnYn PWBcDqYYcCFOO9rTTjR7m2YcT+5QWgByN5nS8JniTi8RKmaitM5zDNHkA5IoWYeunYCP cE0hZp0fgbBNudfxV86jjCA+F3LDs8RvtusIOZKdCu66oBGybfCUVT03LClsD5iEn6b+ iyWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IsTl1pks; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id a8-v6si2498224edr.122.2018.06.14.11.10.29; Thu, 14 Jun 2018 11:10:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IsTl1pks; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id C4EEEC21DF9; Thu, 14 Jun 2018 18:09:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5D555C21DFD; Thu, 14 Jun 2018 18:09:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B230CC21BE5; Thu, 14 Jun 2018 18:09:12 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id 3F88DC21DFA for ; Thu, 14 Jun 2018 18:09:08 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id a7-v6so3968381plp.3 for ; Thu, 14 Jun 2018 11:09:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4fyFQj62kFNn5ITJ+FxO9GaKpsAguACKRt8+93yL6WY=; b=IsTl1pksKgUafcy2I6WzXpP9e8NYuqZrgCA5sQ/JwPaxngwsVZIV8Zvg10vsR5PZsF Ptj98iUnSo+j8Zj6FnUtOSxvslqJXOJNmXONfj4LdlElMDGYYsC3LISEebCecombKfM0 4aOLRft3DkiIoVNbj9Z4JG350P5b9VvusLQd4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4fyFQj62kFNn5ITJ+FxO9GaKpsAguACKRt8+93yL6WY=; b=tEq85trWt5Ma8L6ZR6vLoMI6V0/G5BAnzHIKwM01iymGuMh9IBr/9xa9pQDGcnemKI r4HRjIi7pWXBSQcF9dTzfyYVJE6/8fFVzDE5FS+wUvCk9a1JlOaOvJo8yosuwz7adYeq BWE7c8C0Rzf8rOejnB/BEH9sVyV784HJq1kobW0OvutHIIpO697ZsbJOT8haUSPcNm3o I15Dy/i1n1oG32TW2UDf5rw72HpuuTcWR7aukwH3KyW3XVEKva7vlphSjL2w+Wov/kJy MX9dVK7lkByVsSJ4qYX+vy2OL4w9s85LghIKUeP1NFEI32my1a7/Qpe7ftHtXvYDYx2L zPLQ== X-Gm-Message-State: APt69E2NREoHwXGt00Ft2EoSUnW21ncSJYmavfyyc0vpagCvHSD//a86 ta6N+TgFwU3o37UMaHfCCIn3 X-Received: by 2002:a17:902:4603:: with SMTP id o3-v6mr4015199pld.49.1528999746455; Thu, 14 Jun 2018 11:09:06 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.08.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:09:05 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:31 +0530 Message-Id: <20180614180839.8494-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 1/9] arm: Add support for Actions Semi OWL SoC family X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL SoC family support with S900 as the first target SoC. Signed-off-by: Manivannan Sadhasivam --- Changes in v3: * Moved the change log from cover letter Changes in v2: None arch/arm/Kconfig | 9 +++++++++ arch/arm/Makefile | 1 + arch/arm/dts/s900.dtsi | 23 +++++++++++++++++++++++ arch/arm/mach-owl/Kconfig | 6 ++++++ arch/arm/mach-owl/Makefile | 3 +++ arch/arm/mach-owl/sysmap-s900.c | 32 ++++++++++++++++++++++++++++++++ 6 files changed, 74 insertions(+) create mode 100644 arch/arm/dts/s900.dtsi create mode 100644 arch/arm/mach-owl/Kconfig create mode 100644 arch/arm/mach-owl/Makefile create mode 100644 arch/arm/mach-owl/sysmap-s900.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dde422bc5d..ec0bb5a42b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -699,6 +699,13 @@ config ARCH_MX5 select BOARD_EARLY_INIT_F imply MXC_GPIO +config ARCH_OWL + bool "Actions Semi OWL SoCs" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + config ARCH_QEMU bool "QEMU Virtual Platform" select DM @@ -1335,6 +1342,8 @@ source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig" source "arch/arm/mach-orion5x/Kconfig" +source "arch/arm/mach-owl/Kconfig" + source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 680c6e8516..f15b2287df 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -66,6 +66,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 +machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi new file mode 100644 index 0000000000..3bd14b82d4 --- /dev/null +++ b/arch/arm/dts/s900.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree Source for Actions Semi S900 SoC +// +// Copyright (C) 2015 Actions Semi Co., Ltd. +// Copyright (C) 2018 Manivannan Sadhasivam + +/dts-v1/; + +/ { + compatible = "actions,s900"; + #address-cells = <0x2>; + #size-cells = <0x2>; + + soc { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + }; +}; + diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig new file mode 100644 index 0000000000..f695c16d1e --- /dev/null +++ b/arch/arm/mach-owl/Kconfig @@ -0,0 +1,6 @@ +if ARCH_OWL + +config SYS_SOC + default "owl" + +endif diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile new file mode 100644 index 0000000000..1b43dc2921 --- /dev/null +++ b/arch/arm/mach-owl/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += sysmap-s900.o diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c new file mode 100644 index 0000000000..f78b639740 --- /dev/null +++ b/arch/arm/mach-owl/sysmap-s900.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi S900 Memory map + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include + +static struct mm_region s900_mem_map[] = { + { + .virt = 0x0UL, /* DDR */ + .phys = 0x0UL, /* DDR */ + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xE0000000UL, /* Peripheral block */ + .phys = 0xE0000000UL, /* Peripheral block */ + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = s900_mem_map; From patchwork Thu Jun 14 18:08:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138593 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2438521lji; Thu, 14 Jun 2018 11:10:50 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLH0RGkdR/WGAZ3U1UjazXwOowd4qQbc5IrJkkvjg+OJZkERml9VU+47gdnZzzzPeIoshqt X-Received: by 2002:a50:9090:: with SMTP id c16-v6mr3417411eda.310.1528999850516; Thu, 14 Jun 2018 11:10:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528999850; cv=none; d=google.com; s=arc-20160816; b=nM4nPuTNvE/CsVAaimbdZBA41479q1fse1rwXuUeCPYqk4vweU6C6h6leY3gzfDhr9 17PE2PYp/tTxbdhKaLz/XMbXDRAylccI5KKKTMwk73+e8jGMDr3lVJ5KvpXIPl/Ia67O eumO5YqrgvoVHXgcHAaZ1akTD0ikdiBADgQHKHOg7NCyLvpemdGP8P3wyCjAK41jdW0A eTrusL6HPRKATTRUNNetyQwulxPE9hld7nyRmRfEr9B953i0BBROvT/wRmzWLn847rSA TqUk8BnXS3jE414b4ZcV5xFvaKgETcnxQUh/9Xg6k8kYX99qCRpM1a3YJ7G4ZfFEjKrX lRsQ== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id l40-v6si3087502edc.143.2018.06.14.11.10.50; Thu, 14 Jun 2018 11:10:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HUnlvDtx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 01AC2C21E2B; Thu, 14 Jun 2018 18:09:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BDE22C21DF9; Thu, 14 Jun 2018 18:09:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E0133C21DD4; Thu, 14 Jun 2018 18:09:20 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id 094A3C21DDC for ; Thu, 14 Jun 2018 18:09:16 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id w12-v6so3273284pgc.6 for ; Thu, 14 Jun 2018 11:09:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9MtdjiCMhKPeacMvjaGSZrwKqucW+7mB9mpnMEOAlYA=; b=HUnlvDtx7ZmlTrYQGzbK990udrPOeSzkmb9/oZ5mZnGdxotQU4ccwKOIl3TjlCEqC0 6mR5S4w5oKd93yeHHyPjwWp4PEjToFBfkQ1KJyGqo8vSSHpFirloNp28bubwbrsj27oL 6qmnMKXoO3tkoVCwU+G9Or6M3R+UBAnL78zv4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9MtdjiCMhKPeacMvjaGSZrwKqucW+7mB9mpnMEOAlYA=; b=uUbKkfCyBjMB74P/FeMd+HWvpvXU8BeygDdOuWC4c138IwDMzaBsn3/olGWnvxI6r5 cYInMh9HMYpOGBz6MFz5s/SSciG8qxlXF2nehnW8tlYVGsaHlTUrr622KDjTRPsVickX Yp4y8ouI9W2PFYPTqJ1LhpuX9OENEMED+LNq/yEgIlUa663ljvIs4w6ZUQpAI8/5ZRvs g3u+1Othbwm9voJHCH2lADgLiOUzV5GLDclWJbo3F4RiDhmi7fuIaJgRQ+zPlTq+gIdp iXo1VOSubY6dEmYVX3PAwf8xcuEDBu74PlcUJ6kNSgqhSWU8/f21SK4vVwmcX2Sf0Am8 k/Bw== X-Gm-Message-State: APt69E1GIvlPAqT3/nvKooITY4+zURLkDoECkGAJbG1G4HhHZNVxZxoP jQy1q6Fl2oRK8YgPsbFWrxtf X-Received: by 2002:a62:494f:: with SMTP id w76-v6mr10493137pfa.152.1528999754526; Thu, 14 Jun 2018 11:09:14 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.09.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:09:13 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:32 +0530 Message-Id: <20180614180839.8494-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 2/9] board: Add uCRobotics Bubblegum-96 board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds uCRobotics Bubblegum-96 board support. This board is one of the 96Boards Consumer Edition platform based on Actions Semi S900 SoC. Features: - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU) - 2GiB RAM - 8GiB eMMC, uSD slot - WiFi, Bluetooth and GPS module - 2x Host, 1x Device USB port - HDMI - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons U-Boot will be loaded by ATF at EL2 execution level. Relevant driver support will be added in further commits. Signed-off-by: Manivannan Sadhasivam --- Changes in v3: * Moved the change log from cover letter Changes in v2: * Moved arch/arm/mach-owl/Kconfig changes from clk support patch arch/arm/Kconfig | 1 + arch/arm/dts/bubblegum_96.dts | 19 +++++++ arch/arm/mach-owl/Kconfig | 21 ++++++++ board/ucRobotics/bubblegum_96/Kconfig | 15 ++++++ board/ucRobotics/bubblegum_96/MAINTAINERS | 6 +++ board/ucRobotics/bubblegum_96/Makefile | 3 ++ board/ucRobotics/bubblegum_96/bubblegum_96.c | 56 ++++++++++++++++++++ configs/bubblegum_96_defconfig | 22 ++++++++ include/configs/bubblegum_96.h | 43 +++++++++++++++ 9 files changed, 186 insertions(+) create mode 100644 arch/arm/dts/bubblegum_96.dts create mode 100644 board/ucRobotics/bubblegum_96/Kconfig create mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS create mode 100644 board/ucRobotics/bubblegum_96/Makefile create mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c create mode 100644 configs/bubblegum_96_defconfig create mode 100644 include/configs/bubblegum_96.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ec0bb5a42b..6e203f96aa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1431,6 +1431,7 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" +source "board/ucRobotics/bubblegum_96/Kconfig" source "board/birdland/bav335x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" diff --git a/arch/arm/dts/bubblegum_96.dts b/arch/arm/dts/bubblegum_96.dts new file mode 100644 index 0000000000..4e34ebaa49 --- /dev/null +++ b/arch/arm/dts/bubblegum_96.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree Source for Bubblegum-96 +// +// Copyright (C) 2015 Actions Semi Co., Ltd. +// Copyright (C) 2018 Manivannan Sadhasivam + +/dts-v1/; +#include "s900.dtsi" + +/ { + model = "Bubblegum-96"; + compatible = "ucrobotics,bubblegum-96", "actions,s900"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index f695c16d1e..199e772988 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -3,4 +3,25 @@ if ARCH_OWL config SYS_SOC default "owl" +choice + prompt "Actions Semi OWL SoCs board select" + optional + +config TARGET_BUBBLEGUM_96 + bool "96Boards Bubblegum-96" + help + Support for 96Boards Bubblegum-96. This board complies with + 96Board Consumer Edition Specification. Features: + - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU) + - 2GiB RAM + - 8GiB eMMC, uSD slot + - WiFi, Bluetooth and GPS module + - 2x Host, 1x Device USB port + - HDMI + - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons + +endchoice + +source "board/ucRobotics/bubblegum_96/Kconfig" + endif diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig new file mode 100644 index 0000000000..2dd40d9b6a --- /dev/null +++ b/board/ucRobotics/bubblegum_96/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BUBBLEGUM_96 + +config SYS_BOARD + default "bubblegum_96" + +config SYS_VENDOR + default "ucRobotics" + +config SYS_SOC + default "s900" + +config SYS_CONFIG_NAME + default "bubblegum_96" + +endif diff --git a/board/ucRobotics/bubblegum_96/MAINTAINERS b/board/ucRobotics/bubblegum_96/MAINTAINERS new file mode 100644 index 0000000000..d0cb7278c6 --- /dev/null +++ b/board/ucRobotics/bubblegum_96/MAINTAINERS @@ -0,0 +1,6 @@ +BUBBLEGUM_96 BOARD +M: Manivannan Sadhasivam +S: Maintained +F: board/ucRobotics/bubblegum_96/ +F: include/configs/bubblegum_96.h +F: configs/bubblegum_96_defconfig diff --git a/board/ucRobotics/bubblegum_96/Makefile b/board/ucRobotics/bubblegum_96/Makefile new file mode 100644 index 0000000000..c4b524def2 --- /dev/null +++ b/board/ucRobotics/bubblegum_96/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := bubblegum_96.o diff --git a/board/ucRobotics/bubblegum_96/bubblegum_96.c b/board/ucRobotics/bubblegum_96/bubblegum_96.c new file mode 100644 index 0000000000..a4c202da19 --- /dev/null +++ b/board/ucRobotics/bubblegum_96/bubblegum_96.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Bubblegum-96 Boards Support + * + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * dram_init - sets uboots idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} + +/* This is called after dram_init() so use get_ram_size result */ +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +static void show_psci_version(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + + printf("PSCI: v%ld.%ld\n", + PSCI_VERSION_MAJOR(res.a0), + PSCI_VERSION_MINOR(res.a0)); +} + +int board_init(void) +{ + show_psci_version(); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig new file mode 100644 index 0000000000..a2bd7e80e2 --- /dev/null +++ b/configs/bubblegum_96_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_OWL=y +CONFIG_TARGET_BUBBLEGUM_96=y +CONFIG_SYS_TEXT_BASE=0x11000000 +CONFIG_IDENT_STRING="\nBubblegum-96" +CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_ARM_SMCCC=y +CONFIG_BOOTARGS="console=ttyOWL5,115200n8" +CONFIG_BOOTDELAY=5 +CONFIG_SYS_PROMPT="U-Boot => " +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CLK=y +CONFIG_CLK_OWL=y +CONFIG_CLK_S900=y +CONFIG_OWL_SERIAL=y diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h new file mode 100644 index 0000000000..a8f38a23f9 --- /dev/null +++ b/include/configs/bubblegum_96.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Bubblegum-96 + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _BUBBLEGUM_96_H_ +#define _BUGGLEGUM_96_H_ + +/* SDRAM Definitions */ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (24000000) /* 24MHz */ + +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0) + +/* + * This is the initial SP which is used only briefly for relocating the u-boot + * image to the top of SDRAM. After relocation u-boot moves the stack to the + * proper place. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) + +/* UART Definitions */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_SIZE 0x2000 + +/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif From patchwork Thu Jun 14 18:08:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138594 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2438683lji; Thu, 14 Jun 2018 11:11:00 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLHG0dYpIxTZ81H9tZ+11ko7RE3gDlGpJuitcFBVKXUk01a7YTuiUFG+fqF1rEOD/8XE2Lb X-Received: by 2002:a50:c90b:: with SMTP id o11-v6mr3483701edh.193.1528999860571; Thu, 14 Jun 2018 11:11:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528999860; cv=none; d=google.com; s=arc-20160816; b=AzEgFcY7ydmZ+pSdH9Yciancw49N48aBk7DY8qbAkWWg+jD5r6hnMOYgsKmk3zmFuv Jnlw8bQIl7Epi3AxcGC7fRa3Im6FmRE/LpP9ozDJDcGQNOz53vkyDq5whx5zP+HbrCAX //tLp2vgSnmo5aZ9be0TyzPMx9WvfuR225xYKYJOblUC1em34g832FJVGZOeLvPy80vs dYhuwlHyxeC+O0Sur7meYHU8Jj3YibF14VY8yWJYxI72cMSKZiNcFYK5jQdIJOZvRIQ0 gmOM7BRmNSHCTvVWQSXVEav52KsEW1rNwKFx52icvYixLsmjNAiONqG6RPCyrWKM0GEi liPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=TjFIpACw9bZpFpm4VJseGr/vsZtNgktrC07JOUXzZG4=; b=wX6YEModmQI2MU0n+nQs8Ye+Sh6KJ8Gs+hQm7WaLJlnHxyr6lPqWWPiKr3OEGLBrSh asI26BwpOk1e2fJ6f1E0dH301+6JoRA56CWglKR6j1uIdTORVOH7c7CicXLMlpdZizDO BziQ6U4qayR1iXw6w6VzV7j/ngYMGpVtepsn1YgZZRpDF4WeZW7AzRthdlvPfDW66xPe xdWCpOohCxAl9J6qjs8tiD/9hw48XbwFK9BtyHRVR+Cm+eTpY2oES1S3fMLFftIr7MXc O6whr63PFtsESyVzTF7/RKjFTm9bD/6DGGyy+6cT8c1QZ9nWucWo2LOkKzsHbXzaa64j lQEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dDF44QcB; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c53-v6si2593590edc.322.2018.06.14.11.11.00; Thu, 14 Jun 2018 11:11:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dDF44QcB; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 27652C21DA6; Thu, 14 Jun 2018 18:10:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1FA0AC21DF8; Thu, 14 Jun 2018 18:10:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7B31AC21DF9; Thu, 14 Jun 2018 18:09:27 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id 0A73BC21E13 for ; Thu, 14 Jun 2018 18:09:22 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id b14-v6so3956821pls.5 for ; Thu, 14 Jun 2018 11:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oSdzijfLpJu1Y9H6Kkufgi8cq/UCThTiUFJcVTXSPgc=; b=dDF44QcBhQSx5RXAFWJn1HP5gY0PwA5+pabZg3DPOTy8yUrpmSzImsf4JE964/BGXR RzS9jPBAgGJ6iBx+K39SmOBSkg7G3bsAkRt+NqwW+TO0c6E9nwFL2OT8OdhVvBeTMB56 az/1dpA7rnzRV4lzKXxS+K5LGtY3bfSDMSSD4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oSdzijfLpJu1Y9H6Kkufgi8cq/UCThTiUFJcVTXSPgc=; b=Rw8u0wg2ID7ugrxbSAyR252fQSX7WOcq9fhaNsalG9EedPYuhD744Y/oL7yfHEEmNl qReOR5lVOKQlEeYPxafkb/RBsQUz2yhndr91TG8OsGWUfMzTo5hfXXx8F5oLwsdNT49d mbGVshvrXIpgJlhIOUC7P/3QIy4iu+OVd9CfEriHBkRj0ME4RDW/T2UXRs6w/qlMEHGU 6ReqY0g+H3UFJSTtLQd/+7AYVf0yQu6+LxkOSFuUt4W3FjpmiFGAGmureilZpN2eEwOa rlFOQHIi0FxSRVI4zFSQv6Ebnh3wIXndnAl5luMzoJom6W8RqPVkZzw4sdKZ4VHaU4Ik bgrA== X-Gm-Message-State: APt69E28tVg0zxlWfd/CggU2Pohvg2B2S1FX1kjhsMOyJG+dBKl+hyOq XFS9JDc2kqvFPAQP4DybwiI+ X-Received: by 2002:a17:902:2864:: with SMTP id e91-v6mr4070218plb.240.1528999761566; Thu, 14 Jun 2018 11:09:21 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.09.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:09:20 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:33 +0530 Message-Id: <20180614180839.8494-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 3/9] dt-bindings: clock: Add S900 CMU register definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi S900 CMU register definitions to clock bindings. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Simon Glass --- Changes in v3: * Moved the change log from cover letter Changes in v2: * Added missing Signed-off-by tag include/dt-bindings/clock/s900_cmu.h | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 include/dt-bindings/clock/s900_cmu.h diff --git a/include/dt-bindings/clock/s900_cmu.h b/include/dt-bindings/clock/s900_cmu.h new file mode 100644 index 0000000000..2685a6df4a --- /dev/null +++ b/include/dt-bindings/clock/s900_cmu.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_ +#define _DT_BINDINGS_CLOCK_S900_CMU_H_ + +/* Module Clock ID */ +#define CLOCK_DDRCH1 0 +#define CLOCK_DMAC 1 +#define CLOCK_DDRCH0 2 +#define CLOCK_BROM 3 +#define CLOCK_NANDC0 4 +#define CLOCK_SD0 5 +#define CLOCK_SD1 6 +#define CLOCK_SD2 7 +#define CLOCK_DE 8 +#define CLOCK_LVDS 9 +#define CLOCK_EDP 10 +#define CLOCK_NANDC1 11 +#define CLOCK_DSI 12 +#define CLOCK_CSI0 13 +#define CLOCK_BISP 14 +#define CLOCK_CSI1 15 +#define CLOCK_SD3 16 +#define CLOCK_I2C4 17 +#define CLOCK_GPIO 18 +#define CLOCK_DMM 19 +#define CLOCK_I2STX 20 +#define CLOCK_I2SRX 21 +#define CLOCK_HDMIA 22 +#define CLOCK_SPDIF 23 +#define CLOCK_PCM0 24 +#define CLOCK_VDE 25 +#define CLOCK_VCE 26 +#define CLOCK_HDE 27 +#define CLOCK_SHARESRAM 28 +#define CLOCK_CMU_DDR1 29 +#define CLOCK_GPU3D 30 +#define CLOCK_CMUDDR0 31 +#define CLOCK_SPEED 32 +#define CLOCK_I2C5 33 +#define CLOCK_THERMAL 34 +#define CLOCK_HDMI 35 +#define CLOCK_PWM4 36 +#define CLOCK_PWM5 37 +#define CLOCK_UART0 38 +#define CLOCK_UART1 39 +#define CLOCK_UART2 40 +#define CLOCK_IRC 41 +#define CLOCK_SPI0 42 +#define CLOCK_SPI1 43 +#define CLOCK_SPI2 44 +#define CLOCK_SPI3 45 +#define CLOCK_I2C0 46 +#define CLOCK_I2C1 47 +#define CLOCK_PCM1 48 +#define CLOCK_IMX 49 +#define CLOCK_UART6 50 +#define CLOCK_UART3 51 +#define CLOCK_UART4 52 +#define CLOCK_UART5 53 +#define CLOCK_ETHERNET 54 +#define CLOCK_PWM0 55 +#define CLOCK_PWM1 56 +#define CLOCK_PWM2 57 +#define CLOCK_PWM3 58 +#define CLOCK_TIMER 59 +#define CLOCK_SE 60 +#define CLOCK_HDCP2TX 61 +#define CLOCK_I2C2 62 +#define CLOCK_I2C3 63 + +#endif From patchwork Thu Jun 14 18:08:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138595 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2438871lji; Thu, 14 Jun 2018 11:11:10 -0700 (PDT) X-Google-Smtp-Source: ADUXVKL2HLndiH03KDSj807yY2ZEbgoDzLkUItev2RczwCKAVvTF1Q/+fWkaeQPULtYq6mMATGwR X-Received: by 2002:a50:f5d7:: with SMTP id x23-v6mr3409659edm.132.1528999870106; Thu, 14 Jun 2018 11:11:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528999870; cv=none; d=google.com; s=arc-20160816; b=Sfg96gMcnz+QvguOZHxVMX66zI4oTBVEPzReQ6FppStNUAs0XRo8XMAyRW/mCbRuPf BeO6YJ5NtR3UOSBja2fXs/ELJXHUABbuDY+OCudegEZ5ord6oyvXOrYkBPGxSdO5IJup RTK8i/btYmG6zZMI6X5giS4/3EN9drlR6f0PvdC7Kk55TdcctL2AuZjwo6BjEDpPGF0I 6f8KOPijf+S98nlwLabRWdWMKV0l7BEho0ORxgtvkhHI7msz1YuU5J+oy+/bMaXL66gd zu2QfDwVaaSq8MYtbbpNm+5LZAgKUzmkH7qHk/htufBVBWJFeUC0Uh0NMAXeR8eZE+FR dQXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=KLIraOv+83x+BxK3IdYP3w89NxnNc8sDArhBTTip6+Y=; b=vZVviPetE5rgK6+5im+SEEa9QLX8ZDcXBZLALLlV5i6szUs/nkanDLEoJBg5Y8KJ7o XKD99KL2FJTSfJ9dBk4RKTNvgTrWouooYBQBgbrs/pNA+18AARveiUhuz+9uZhdDkQ44 WsTc9keI3QQI15TGKzd8I/iK1ljD+m5zN6DjfjuPeBBe7PRFENjINO83Rm+kGzyUca4q piIW9qIMlItInuMlNbp794GlYVkwx71FD6LPV7zwpZ18VYte5/0o3G7RMRZXgv+V3sB5 1o5PciySd/amaxA2zO4ArKdlCIpCWin6g8af6B1QPXAE8K6nQZ5KJAgMLHlD0CSZm0lc OSBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="J/b4uJwx"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id w30-v6si829804edd.212.2018.06.14.11.11.09; Thu, 14 Jun 2018 11:11:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="J/b4uJwx"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 93F3CC21D8E; Thu, 14 Jun 2018 18:10:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F335AC21E26; Thu, 14 Jun 2018 18:10:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AEED2C21E1E; Thu, 14 Jun 2018 18:09:34 +0000 (UTC) Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by lists.denx.de (Postfix) with ESMTPS id 390D3C21DFD for ; Thu, 14 Jun 2018 18:09:30 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id q1-v6so3615224pff.13 for ; Thu, 14 Jun 2018 11:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LJ6QglBZDhq3YVBLUbF1JN6u/lfmNmSuIAAgO52dImE=; b=J/b4uJwxplQnrOAMaqnzI25SQ+zGoJ8Hbq68khk7tijGY64MnulrMQauQJcgGaau2P oHYIOkZUwV500tkHa19hvgidt1didzhL48jWc/EkC3aGZspotanlEIDBcvxinsQ+G/Pk cP/T/Vx8ysnuyzvVTIR0KFkXV33pm/NZakvCg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LJ6QglBZDhq3YVBLUbF1JN6u/lfmNmSuIAAgO52dImE=; b=i2F9c/lzWx1qYN4cBOhQ2DtZe//dKLJPXb+J0BLkv0vMYslfFVzNCwWWtcid5Itu8k eyPtSDDcj3Bt0AdlzwipUwK8jgF6TGSKwPdSsaS1gW7ZtC9CxAtrKETerjsKG/1QW8C7 jF4Z6bb1YCbv9XGvXLGgJ2efs9Sxyojr46wkvhsFZOdJ07MkvBryfKaMUglx1sjgTwQc ErLmW6SxLcFrD6r1oDQ75B2bytQZ/NePZiVNWZtdYarWgopyaCkfmpS8dnCyPAhnPlBm NVcMlYD7xbKRtNoRTtEr58qBLhbES+Hqbc3mtUbBcWDAGuAesZqZW+JmesWAfIS8P/Yv eIMg== X-Gm-Message-State: APt69E3g0qiU/oxhey52s6j2UJOQUYBBOxpeKEVhQtMjZNedlwTcB4f0 CB2aPCg2QoTlYL2llkBgGOuj X-Received: by 2002:a62:9513:: with SMTP id p19-v6mr10519932pfd.239.1528999768768; Thu, 14 Jun 2018 11:09:28 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.09.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:09:28 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:34 +0530 Message-Id: <20180614180839.8494-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 4/9] arm: dts: s900: Add Clock Management Unit (CMU) nodes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Clock Management Unit (CMU) nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- Changes in v3: * Moved the change log from cover letter Changes in v2: None arch/arm/dts/s900.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi index 3bd14b82d4..e9d47b1ff1 100644 --- a/arch/arm/dts/s900.dtsi +++ b/arch/arm/dts/s900.dtsi @@ -6,18 +6,40 @@ // Copyright (C) 2018 Manivannan Sadhasivam /dts-v1/; +#include / { compatible = "actions,s900"; #address-cells = <0x2>; #size-cells = <0x2>; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + diff24M: diff24M { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + soc { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; + + cmu: clock-controller@e0160000 { + u-boot,dm-pre-reloc; + compatible = "actions,s900-cmu"; + reg = <0x0 0xe0160000 0x0 0x1000>; + clocks = <&losc>, <&diff24M>; + clock-names = "losc", "diff24M"; + #clock-cells = <1>; + }; }; }; From patchwork Thu Jun 14 18:08:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138596 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2440629lji; Thu, 14 Jun 2018 11:12:45 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJw1X+NOOXcPVFsQmLN+HpYzmBc4d6Sh+0csz1KT23mKFT9c09vNsx5gvqln3MTIaSVENvb X-Received: by 2002:a50:b723:: with SMTP id g32-v6mr3448999ede.139.1528999965714; Thu, 14 Jun 2018 11:12:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528999965; cv=none; d=google.com; s=arc-20160816; b=GEdD2kvBlLBef2smfpVNDs97pCk08lvwFzuPNRGwjfq+P06CZ50BTnn9GBXqmrAVvH PByaPQZQvXvUE61TDWTFjOVOsp0hbjzXklqZqmzk7JD/K3UFdmE/KprPThnit3m28rT6 Mx0n/a/rdg63H5kk7AzIe/vkpM4/aNWYB7RNY55dPN8zysTgMsPuAELDytRjJKy8poh4 AMcbxWRLKYCdoFBHqqc1atz4m/+4LOWxqqM/NC6lM2Qyj5Y3yThNYdSPlQtu1f1BKGI+ 9YM9bzL6Kuqkc8mUk3xYEV1rx6PEciUJntFbr6re6DAdUoqwlOs5KCD7Su37/I3GCW6h KBTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=kmhJ4kGK2GFAG/VYviMUUU99ScWEapInIW8zEzUyi00=; b=qPeBChGwqrrV/uVFViCEwWTPutQQDIelu1HFV7ZBq6C3rWkRLzZBC71wMyMyIZQiFt cF0dct4zUxkWo+EaKe0w8IGklnZzDILvKXaHXnKnSDWM8KSZRiyxbLL6l0SufAzSDevG hJ52TAZ+ZgI+j+ltZIL6SZZxl6564LeqmgFxircX+Ke5eIA5OLrFklmI/NE89Uj39y+n K8cuOfZOJVhfrqdYVX0Uayug9m8iXz7Vnzoa+mf73mLCtZGx5Y9Vcm50ogHvANTZOhtz Z+JB7ya1Ou4aHzxSNnXp7V6tP/uJIJ8DHFKLRNkgNeEaVH/ELPNShzk7LtT+3Blr8HAg ka/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KkUen8QS; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l8-v6si592898edj.379.2018.06.14.11.12.45; Thu, 14 Jun 2018 11:12:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KkUen8QS; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 4DB21C21E0D; Thu, 14 Jun 2018 18:10:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6DCBCC21E30; Thu, 14 Jun 2018 18:10:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 78237C21E07; Thu, 14 Jun 2018 18:09:42 +0000 (UTC) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by lists.denx.de (Postfix) with ESMTPS id BC6D4C21DF3 for ; Thu, 14 Jun 2018 18:09:37 +0000 (UTC) Received: by mail-pl0-f68.google.com with SMTP id b14-v6so3957132pls.5 for ; Thu, 14 Jun 2018 11:09:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UQ0OytNX07LIarVS+bQgmeqFfOJTij0zUallyLQFT/M=; b=KkUen8QSg3iQi2goapYfqirKAJlWlPW2NzEhdxgTYf2fmCQTC7rJ3U5OhitwifQh+N ZIVzvUNCQw2HFshS8hsSHPqiaUM2ah76lr3PpHy6TqIANhhV3njIjFmrW8NCIQLny0Ir nlFdO7NAY8YwjvUEdvzBgaI1QFpW77EYWLf78= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UQ0OytNX07LIarVS+bQgmeqFfOJTij0zUallyLQFT/M=; b=kg7EI/u9qz+jT9byzEfWtVMBrCwEKmBPgHkZk23eUND8qSe5ONSiUPWBiaphai0cHI +nVbsNBooIcjy9zL+9wTROfJVMZ9YSOacTDPxcoSiP3GE9qKRmhX11RUvOQmZVpBMz2V fs069OZoatzRNyCjB+jZ+OeN2n2leOP1CsacQKW1Wk3q/2cluT+hI/MVDbMvKWGcYf53 Em7UyoF+I5NOUJR3Cu/f75vcIi+68ov9ij3R4YaBvEOZYVdStuarrjdklO855SS9e5hf rMNMhezZYPJv6d52ilXAQAE9hDVRwl+nNrBh2+CD5s0t2LB8MbJWLMtzSffQEBpCdBSO RzWg== X-Gm-Message-State: APt69E2hPap24SC1jc7z8bETV2Xb4OhF1ojGFTU6ATBPfJIfqgVTE5oj APmcKnSW25xRiA0kJevh7M/9 X-Received: by 2002:a17:902:224:: with SMTP id 33-v6mr4128572plc.309.1528999776287; Thu, 14 Jun 2018 11:09:36 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.09.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:09:35 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:35 +0530 Message-Id: <20180614180839.8494-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 5/9] clk: Add Actions Semi OWL clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Simon Glass --- Changes in v3: * Moved the change log from cover letter Changes in v2: * Removed clk_owl.c and moved all clk code to clk_s900.c as per Simon's review comments. * Moved arch/arm/mach-owl/Kconfig changes to board support patch. arch/arm/include/asm/arch-owl/clk_s900.h | 57 +++++++++ arch/arm/include/asm/arch-owl/regs_s900.h | 64 ++++++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/owl/Kconfig | 12 ++ drivers/clk/owl/Makefile | 3 + drivers/clk/owl/clk_s900.c | 138 ++++++++++++++++++++++ 7 files changed, 276 insertions(+) create mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s900.h create mode 100644 drivers/clk/owl/Kconfig create mode 100644 drivers/clk/owl/Makefile create mode 100644 drivers/clk/owl/clk_s900.c diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h new file mode 100644 index 0000000000..88e88f77f8 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/clk_s900.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Actions Semi S900 Clock Definitions + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _OWL_CLK_S900_H_ +#define _OWL_CLK_S900_H_ + +#include + +struct owl_clk_priv { + phys_addr_t base; +}; + +/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0) + +/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24) + +/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6) + +/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16) + +/* DEVCLKEN1 register definitions */ +#define CMU_DEVCLKEN1_UART5 BIT(21) + +#define PLL_STABILITY_WAIT_US 50 + +#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s900.h b/arch/arm/include/asm/arch-owl/regs_s900.h new file mode 100644 index 0000000000..9e9106ddaa --- /dev/null +++ b/arch/arm/include/asm/arch-owl/regs_s900.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Actions Semi S900 Register Definitions + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _OWL_REGS_S900_H_ +#define _OWL_REGS_S900_H_ + +/* CMU registers */ +#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSICLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_BISPCLK (0x0034) +#define CMU_IMXCLK (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_PWM0CLK (0x0070) +#define CMU_PWM1CLK (0x0074) +#define CMU_PWM2CLK (0x0078) +#define CMU_PWM3CLK (0x007C) +#define CMU_USBPLL (0x0080) +#define CMU_ASSISTPLL (0x0084) +#define CMU_EDPCLK (0x0088) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_UART3CLK (0x00B0) +#define CMU_UART4CLK (0x00B4) +#define CMU_UART5CLK (0x00B8) +#define CMU_UART6CLK (0x00BC) +#define CMU_TLSCLK (0x00C0) +#define CMU_SD3CLK (0x00C4) +#define CMU_PWM4CLK (0x00C8) +#define CMU_PWM5CLK (0x00CC) +#define CMU_ANALOGDEBUG (0x00D4) +#define CMU_TVOUTPLLDEBUG0 (0x00EC) +#define CMU_TVOUTPLLDEBUG1 (0x00FC) + +#endif diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index edb4ca58ea..18bf8a6d28 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -89,6 +89,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/mvebu/Kconfig" +source "drivers/clk/owl/Kconfig" config ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 58139b13a8..078f8d7ae1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o +obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig new file mode 100644 index 0000000000..661f1981b9 --- /dev/null +++ b/drivers/clk/owl/Kconfig @@ -0,0 +1,12 @@ +config CLK_OWL + bool "Actions Semi OWL clock drivers" + depends on CLK && ARCH_OWL + help + Enable support for clock managemet unit present in Actions Semi + OWL SoCs. + +config CLK_S900 + bool "Actions Semi S900 clock driver" + depends on CLK_OWL && ARM64 + help + Enable support for the clocks in Actions Semi S900 SoC. diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile new file mode 100644 index 0000000000..9132dcc175 --- /dev/null +++ b/drivers/clk/owl/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_CLK_S900) += clk_s900.o diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c new file mode 100644 index 0000000000..2b39bb99af --- /dev/null +++ b/drivers/clk/owl/clk_s900.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi S900 clock driver + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include + +#include + +void owl_clk_init(struct owl_clk_priv *priv) +{ + u32 bus_clk = 0, core_pll, dev_pll; + + /* Enable ASSIST_PLL */ + setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0)); + + udelay(PLL_STABILITY_WAIT_US); + + /* Source HOSC to DEV_CLK */ + clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); + + /* Configure BUS_CLK */ + bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV | + CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV | + CMU_NOCCLK_SRC | CMU_CORECLK_HOSC); + writel(bus_clk, priv->base + CMU_BUSCLK); + + udelay(PLL_STABILITY_WAIT_US); + + /* Configure CORE_PLL */ + core_pll = readl(priv->base + CMU_COREPLL); + core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT); + writel(core_pll, priv->base + CMU_COREPLL); + + udelay(PLL_STABILITY_WAIT_US); + + /* Configure DEV_PLL */ + dev_pll = readl(priv->base + CMU_DEVPLL); + dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT); + writel(dev_pll, priv->base + CMU_DEVPLL); + + udelay(PLL_STABILITY_WAIT_US); + + /* Source CORE_PLL for CORE_CLK */ + clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK, + CMU_CORECLK_CPLL); + + /* Source DEV_PLL for DEV_CLK */ + setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); + + udelay(PLL_STABILITY_WAIT_US); +} + +void owl_uart_clk_enable(struct owl_clk_priv *priv) +{ + /* Source HOSC for UART5 interface */ + clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL); + + /* Enable UART5 interface clock */ + setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); +} + +void owl_uart_clk_disable(struct owl_clk_priv *priv) +{ + /* Disable UART5 interface clock */ + clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); +} + +int owl_clk_enable(struct clk *clk) +{ + struct owl_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case CLOCK_UART5: + owl_uart_clk_enable(priv); + break; + default: + return 0; + } + + return 0; +} + +int owl_clk_disable(struct clk *clk) +{ + struct owl_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case CLOCK_UART5: + owl_uart_clk_disable(priv); + break; + default: + return 0; + } + + return 0; +} + +static int owl_clk_probe(struct udevice *dev) +{ + struct owl_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + /* setup necessary clocks */ + owl_clk_init(priv); + + return 0; +} + +static struct clk_ops owl_clk_ops = { + .enable = owl_clk_enable, + .disable = owl_clk_disable, +}; + +static const struct udevice_id owl_clk_ids[] = { + { .compatible = "actions,s900-cmu" }, + { } +}; + +U_BOOT_DRIVER(clk_owl) = { + .name = "clk_s900", + .id = UCLASS_CLK, + .of_match = owl_clk_ids, + .ops = &owl_clk_ops, + .priv_auto_alloc_size = sizeof(struct owl_clk_priv), + .probe = owl_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Thu Jun 14 18:08:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138599 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2442462lji; Thu, 14 Jun 2018 11:14:33 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIomjHE98nUiZ5yaGlAlX2W+HTx9Wwcee6i2DWe2xiygT3UFMI5NcPfknnU5dEmLssL4DC6 X-Received: by 2002:a50:9fab:: with SMTP id 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[81.169.180.215]) by mx.google.com with ESMTP id g27-v6si5153318edb.317.2018.06.14.11.14.32; Thu, 14 Jun 2018 11:14:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=g0cXCQBe; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id C43A9C21E07; Thu, 14 Jun 2018 18:11:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 90F67C21E1A; Thu, 14 Jun 2018 18:10:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B560EC21E36; Thu, 14 Jun 2018 18:09:50 +0000 (UTC) Received: from mail-pg0-f43.google.com (mail-pg0-f43.google.com [74.125.83.43]) by lists.denx.de (Postfix) with ESMTPS id 9AFC0C21DED for ; Thu, 14 Jun 2018 18:09:45 +0000 (UTC) Received: by mail-pg0-f43.google.com with SMTP id q4-v6so3280309pgr.1 for ; Thu, 14 Jun 2018 11:09:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8j9XpwIzrznPGHBHpztpildBvAWxZca2WhKCaDycllU=; b=g0cXCQBeltuVMMf47qRQ4IMBBmPoq+RKY7yDOaczLobKQussK+ktaZz9XLt60BT9Wv 2X4V9q6Kbx4TDlUU+93mNJrIBLaGndQ2aHY8C8OPMF/GiL5K7l9EUq8tebxLL1LEmAUs OGQxOJfpmiTnFYLsOKTCuHPcI/yhOe0uR9JfQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8j9XpwIzrznPGHBHpztpildBvAWxZca2WhKCaDycllU=; b=rNWhV8JjkIbm60/s/rg24Qnh9lF0C2Ea6dF2hxD3VjRSDXom91kDyOLyHEMSvhJ9qG hr+UGetfxltSoCCY5szskDDr6asA7wWyi8PxvDnApdZM1MovRc8r81K0PXu3agryMOMd uqhD4mpVzYDVsEVZOSDTFpAW8IgCKzapYH2l4tnBoWOeTHEuSo6EJOerMAWY/rm9k/eI NQeZb5dDG/DAFMQXf2IWTZOrK2fKYSdB1ov7MZLXCWx179JSWSJ2ul73TDxuwUebA6Rv ugD3RQssFZVsAGT1rP6Kb4wO+WRr/n4u2K/ks3qL6TxUnegU8jVEgtsy0iyxSgdHiBTQ 8dew== X-Gm-Message-State: APt69E2SQtyhBFZkVlnss/NWAKxiWozQhOVG2+xTWrZiVIBnse/jEyzw B8CCYLGQ3h7sxIIiqqCxn95H X-Received: by 2002:a63:8f19:: with SMTP id n25-v6mr3274623pgd.344.1528999784204; Thu, 14 Jun 2018 11:09:44 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.09.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:09:43 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:36 +0530 Message-Id: <20180614180839.8494-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 6/9] arm: dts: s900: Add UART node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds UART node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- Changes in v3: * Moved the change log from cover letter Changes in v2: None arch/arm/dts/s900.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi index e9d47b1ff1..2bbb30a5a8 100644 --- a/arch/arm/dts/s900.dtsi +++ b/arch/arm/dts/s900.dtsi @@ -32,6 +32,14 @@ #size-cells = <0x2>; ranges; + uart5: serial@e012a000 { + u-boot,dm-pre-reloc; + compatible = "actions,s900-serial"; + reg = <0x0 0xe012a000 0x0 0x1000>; + clocks = <&cmu CLOCK_UART5>; + status = "disabled"; + }; + cmu: clock-controller@e0160000 { u-boot,dm-pre-reloc; compatible = "actions,s900-cmu"; From patchwork Thu Jun 14 18:08:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138598 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2441650lji; Thu, 14 Jun 2018 11:13:45 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIKOvqwd7It2qbzXJ1e7AgWuvvQVntLRcVylAs57PK8DO3Ic5MYYe+VFQezQik7vbL11RKd X-Received: by 2002:a50:f310:: with SMTP id p16-v6mr3479889edm.183.1529000024982; Thu, 14 Jun 2018 11:13:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529000024; cv=none; d=google.com; s=arc-20160816; b=PDq+elDkAeMGlRdC4T5fRPKe2JT4+qnMBjVhvLx0BSB3cuRag8N+BUu+RSjBduD3Ry jhuupieL7lxdAxXpXqKHT4+N0G/Z7l3DiXmMC3dU7XrddvEIxOYMdJ+fUUqkMdiTTk4D cMvlYzzqjSG9oV6b2k6vPQuZC7vqTnWWZwHP/Cs6hJTbKHsA6Sw3rPVpqzW2WTxiDnhd HP7QRjc7uKUilsdHmKvzHAkIMFj6mYZybX0GthGtS6aXeJja7Q3ke8hfoJ/5rVwjb+1G MTQo0nxVs7yk9+Dr1EzXKSHPUEVyHypUiEYGctpvxuktBVY0bSsMMkhdTbfPt0huQIBA 4TTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=7i39ekUh33n0ozGG7nygDqFY3+isfk/GCrz+neVAYSo=; b=Wz2dhr7Tmc3W0eqo2p1dJd0mlQzJQ6qhkvjZbWPWMNtS7WGUvHUU1A5YdFY0yb9Kdu dSE8Wa9BTeVM7VzIEjEIJlr8qESE2T6j0QbgsVzeJ677wMiaPlh3fp4Z0t0vQiAOd6yB 7U2iH9w1NVuYguMkZ3CCD+zXmKaQdX04LaNCFzTkQEowwtJY9qMAXjD1UA6tWfglTxbi dKaiy2T8QqURqSq8YCPTgTQoPS7d5FpBr9kXnL0FokCszV2aviPnLSlBdo0fFmd/jYnR zAb6ua3JR08ZR9Pf8ypsBKsgkd1wy52ntxxVhhwUjgyrAo4rQJNtjRT0KH3Wc44FGrIE p74Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=CJWFpqCN; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id q10-v6si4540846edh.327.2018.06.14.11.13.44; Thu, 14 Jun 2018 11:13:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=CJWFpqCN; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 8023FC21E1A; Thu, 14 Jun 2018 18:12:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1DBD4C21E26; Thu, 14 Jun 2018 18:12:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 95DC5C21CB6; Thu, 14 Jun 2018 18:10:00 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id 05E51C21DF3 for ; Thu, 14 Jun 2018 18:09:54 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id 6-v6so3421946plb.0 for ; Thu, 14 Jun 2018 11:09:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0LilUp6U/mRdDHRhND7MUg6BOBN8chLJ8uzDZQ5WikU=; b=CJWFpqCN67t0Qd2Z3tgzP/H05+fuM0w7NU4lC6GJpt3Th0QuaJbf/YU8hTIbIaNeZJ OZcGay9k9uS6Wo/4RTL9jTKnY6ujsczQvHRJnWajMBuePiPHMWrHVTtMRZWVShfw/pRY RDqlY1sXh3/SZdICItJVrtVZPUKga0/2+QZMk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0LilUp6U/mRdDHRhND7MUg6BOBN8chLJ8uzDZQ5WikU=; b=tst86xcE1IKjXhiHkLSO/G6maUsQPIuESD3h5Up/Kq1h8yGExpmTtbnAjkFjEMZhok BuKXg68DEG42UaLpPkPiXB8KsYkhwZ5OsMT/SA8Adc4gyaKyV0slxw9iI6n5MmWHJNyi 2jNDpvVeOhLV6NUee5bfotWQ/Wyq8oPXhUc8rek1wDONANR/Dn+0Y1ZfzO096jM9pS+c CrVXmjyzJBXSNGs5zfV40JMxREZqltgpuTlg8H7rsryAyWoAVoaQ2CLS7zRw2NENZeA7 z1koS6y+ljig+1+z8qf6kiEPGucQxxyuAj5yPUkM0hi6tstvp1OuErTWiglbshDgds90 VHXg== X-Gm-Message-State: APt69E2nT36QbcsSVT+wxx3AFXMKi4XcVDpriPlEbp/GLsv5m9tWeGFH sAFiayjW8TXYq4ScG6HO7uMy X-Received: by 2002:a17:902:a610:: with SMTP id u16-v6mr4115089plq.195.1528999792620; Thu, 14 Jun 2018 11:09:52 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.09.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:09:51 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:37 +0530 Message-Id: <20180614180839.8494-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 7/9] arm: dts: bubblegum_96: Enable UART5 for serial console X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit enables UART5 found in S900 SoC for serial console support. Signed-off-by: Manivannan Sadhasivam --- Changes in v3: * Moved the change log from cover letter Changes in v2: None arch/arm/dts/bubblegum_96.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/bubblegum_96.dts b/arch/arm/dts/bubblegum_96.dts index 4e34ebaa49..5b58d15594 100644 --- a/arch/arm/dts/bubblegum_96.dts +++ b/arch/arm/dts/bubblegum_96.dts @@ -12,8 +12,20 @@ model = "Bubblegum-96"; compatible = "ucrobotics,bubblegum-96", "actions,s900"; + aliases { + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial5:115200n8"; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; + +&uart5 { + status = "okay"; +}; From patchwork Thu Jun 14 18:08:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138597 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp2441294lji; Thu, 14 Jun 2018 11:13:26 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLigEhg/XWBKKD0SUTQj+lllLcXgwD2MTgO10LOTvCvoBZEWw4JjHcyZ4ROH2KfYZSjpGH4 X-Received: by 2002:a50:9734:: with SMTP id c49-v6mr3421257edb.267.1529000006009; Thu, 14 Jun 2018 11:13:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529000006; cv=none; d=google.com; s=arc-20160816; b=t192k70lk9FicaG1yEwHgyUBsFEZbWC1EAMsMKf3x9pwrP98tKYMRONSzbwDk512r8 kLX3c91xDhl0LOUTW1G1waW7lY2MkR1fEXVOyCEvCdMFaTHVnnxhZvnwUTYaiRbRNG0D nQYC7QF6zJY+iW5XChQ/xoQEoS+DrzIUg5muajk6afg/aY3hldqN86vLEAXxpaagpv+T hNPgpH0sX12EcVYPkn3qwt7/NKrKT86OswofQ6lF1YbXqAXCesbbp9+AZM+OWCetfd/p cifUzq3cmCdAgOsOXuIFKxrzoakyb62qg3MehuSst95YnBtfrBhr9p4JjtvDo7SqD5xT qduQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=092/ZgNokfTEeHR5/81wjmUVdQF8Qa69vXw+EXYg5Q4=; b=LCskp6doOuq9Ulu3t3Qp5RqRGLd8uUYMLDLTWdjaMEsErh3B+IbHyL1Qyt/cQkJkZb 9R/rsgNWu/M9aTSp+iLAx1SCRO0bAUWJjEsLOfe9ro+xo0LgxqCm36h8xK3iUJjj+X8I 9D4rV4S7CkRBvBOPSlmpxnBEyQnAj/7dcyUCz3AkCVg5U2NYmFZLQpjgIDPHefAYg0BL OdvQttIjq5YYIFhn/g9mPAXshushIFtrooyRRdKSF4LhTrz3y53i9JwZrfeCuzBDYBFp X2DSKYlHzKhKLiSOPbRsUQ7rMwoRgM+9WJ7oBH4hgSTbAMIzQtMbP2oHdpv7lpapiOO4 g79Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PL1NNoRM; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id k32-v6si1337663edc.340.2018.06.14.11.13.25; Thu, 14 Jun 2018 11:13:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PL1NNoRM; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 873EBC21DA2; Thu, 14 Jun 2018 18:11:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 883B2C21E29; Thu, 14 Jun 2018 18:11:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8EAC5C21DF9; Thu, 14 Jun 2018 18:10:07 +0000 (UTC) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by lists.denx.de (Postfix) with ESMTPS id 29D19C21DF3 for ; Thu, 14 Jun 2018 18:10:02 +0000 (UTC) Received: by mail-pf0-f193.google.com with SMTP id h12-v6so3615348pfk.11 for ; Thu, 14 Jun 2018 11:10:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QOVUceVI/lVdpSmneUw53RbFcoBouOKah2KyfR6RS/c=; b=PL1NNoRMaIcBXehIhYT/GVg0Jq7mdipzv7OtrXt9Xg/CpAr1cvRoS5lNIU91o1xJVI ZEZBiJWlFopLGpLx+n/rzSQZOl1i1QiqsxjOwk7d4sOjctXnLuh+aqgALJyC/X7NFEgR IiAGp1+tYqhKHwK7vXW2/NJEz1i9PNkB48IfU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QOVUceVI/lVdpSmneUw53RbFcoBouOKah2KyfR6RS/c=; b=EaRUo7a+nFfJVAriT5lzSwirbShiJVPWfQJckQFfmlS+JCH30+vspDj+TbZmnOpvqo VuFcU6jNfEqrTk/GHIPfEq1eB9M0gmjkKhWlhXdKOcu6rk7yzxgFMxCknFk07lR2SMGg wrN+GQrDrsqCjGYaf7JMIXukpSRF6uQu7HCdWnNSMyU6gKFctCJBzTmlU3+PdPDj6yBR MpmtT8NyHcDONBOwkTjV55zqgdLzZZc9UgLjPC5kTTB7yf/Wwuh2WhH2yvXq11XVkX3x eSeV2+kuZydoy4RhTMbusAzmVG3ya2FTzKnRqzXwBJg89rNQ8bqt85xAoYyH/CIk5DY9 bU8g== X-Gm-Message-State: APt69E2ZFIKHUnaWStoQLlJAXDPKJqViVHqEjIFQTCeOBPvYK9OI5Tvv Z04QjWj3vm8YkfUM6/GZqod2 X-Received: by 2002:a62:3c15:: with SMTP id j21-v6mr10573202pfa.7.1528999800641; Thu, 14 Jun 2018 11:10:00 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.09.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:10:00 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:38 +0530 Message-Id: <20180614180839.8494-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 8/9] serial: Add Actions Semi OWL UART support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL family UART support. This driver relies on baudrate configured by primary bootloaders. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Simon Glass --- Changes in v3: * Moved the change log from cover letter Changes in v2: None drivers/serial/Kconfig | 8 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_owl.c | 136 ++++++++++++++++++++++++++++++++++++ 3 files changed, 145 insertions(+) create mode 100644 drivers/serial/serial_owl.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 2940bd05dc..766e5ced03 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -625,6 +625,14 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config OWL_SERIAL + bool "Actions Semi OWL UART" + depends on DM_SERIAL && ARCH_OWL + help + If you have a Actions Semi OWL based board and want to use the on-chip + serial port, say Y to this option. If unsure, say N. + Single baudrate is supported in current implementation (115200). + config PXA_SERIAL bool "PXA serial port support" help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index e66899489e..9fa81d855d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o +obj-$(CONFIG_OWL_SERIAL) += serial_owl.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c new file mode 100644 index 0000000000..6fd97e2502 --- /dev/null +++ b/drivers/serial/serial_owl.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi OWL SoCs UART driver + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* UART Registers */ +#define OWL_UART_CTL (0x0000) +#define OWL_UART_RXDAT (0x0004) +#define OWL_UART_TXDAT (0x0008) +#define OWL_UART_STAT (0x000C) + +/* UART_CTL Register Definitions */ +#define OWL_UART_CTL_PRS_NONE GENMASK(6, 4) +#define OWL_UART_CTL_STPS BIT(2) +#define OWL_UART_CTL_DWLS 3 + +/* UART_STAT Register Definitions */ +#define OWL_UART_STAT_TFES BIT(10) /* TX FIFO Empty Status */ +#define OWL_UART_STAT_RFFS BIT(9) /* RX FIFO full Status */ +#define OWL_UART_STAT_TFFU BIT(6) /* TX FIFO full Status */ +#define OWL_UART_STAT_RFEM BIT(5) /* RX FIFO Empty Status */ + +struct owl_serial_priv { + phys_addr_t base; +}; + +int owl_serial_setbrg(struct udevice *dev, int baudrate) +{ + /* Driver supports only fixed baudrate */ + return 0; +} + +static int owl_serial_getc(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_RFEM) + return -EAGAIN; + + return (int)(readl(priv->base + OWL_UART_RXDAT)); +} + +static int owl_serial_putc(struct udevice *dev, const char ch) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_TFFU) + return -EAGAIN; + + writel(ch, priv->base + OWL_UART_TXDAT); + + return 0; +} + +static int owl_serial_pending(struct udevice *dev, bool input) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + unsigned int stat = readl(priv->base + OWL_UART_STAT); + + if (input) + return !(stat & OWL_UART_STAT_RFEM); + else + return !(stat & OWL_UART_STAT_TFES); +} + +static int owl_serial_probe(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + struct clk clk; + u32 uart_ctl; + int ret; + + /* Set data, parity and stop bits */ + uart_ctl = readl(priv->base + OWL_UART_CTL); + uart_ctl &= ~(OWL_UART_CTL_PRS_NONE); + uart_ctl &= ~(OWL_UART_CTL_STPS); + uart_ctl |= OWL_UART_CTL_DWLS; + writel(uart_ctl, priv->base + OWL_UART_CTL); + + /* Enable UART clock */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + return 0; +} + +static int owl_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct dm_serial_ops owl_serial_ops = { + .putc = owl_serial_putc, + .pending = owl_serial_pending, + .getc = owl_serial_getc, + .setbrg = owl_serial_setbrg, +}; + +static const struct udevice_id owl_serial_ids[] = { + { .compatible = "actions,s900-serial" }, + { } +}; + +U_BOOT_DRIVER(serial_owl) = { + .name = "serial_owl", + .id = UCLASS_SERIAL, + .of_match = owl_serial_ids, + .ofdata_to_platdata = owl_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct owl_serial_priv), + .probe = owl_serial_probe, + .ops = &owl_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; 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[81.169.180.215]) by mx.google.com with ESMTP id g10-v6si3142167edf.328.2018.06.14.11.15.23; Thu, 14 Jun 2018 11:15:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="j/de9VR4"; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id B99D0C21DA2; Thu, 14 Jun 2018 18:13:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 38EAEC21DAF; Thu, 14 Jun 2018 18:12:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1897AC21E12; Thu, 14 Jun 2018 18:10:10 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 62192C21D8E for ; Thu, 14 Jun 2018 18:10:09 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id a11-v6so3612824pff.8 for ; Thu, 14 Jun 2018 11:10:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e72pvf3nxKFgVSLZsoq4R2wewamUAD2fVQZxgLopK7I=; b=j/de9VR4iUj8plxDO9YyBKlWRQ/LgQbQREI0XiyCGP+JP3fTJ7wMB1U0l4OVc0R05t FVXe0vjQT8Er5mxb0lqalEewYdICoIBZX39mTkSGUXOR9+HTSydSE5XzxphbfdG5TFSd NdOBuMyQVLVG59HxG1NuXMZCMJn5DWdZb3kZQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e72pvf3nxKFgVSLZsoq4R2wewamUAD2fVQZxgLopK7I=; b=DEY6GC8P5YxQ5QR8M5AKcQma1quC3Ss/MRqec9oycq6G4safVZDG31Zt8rf6PWP8o6 U8c3MTkSU869VYKuash5fmRPO+g2e3zNUviL/iAkqkxn1EgNZNk3Tl0G5f5Y9p+O483N kB1/BwQ0+Y9uC35VbpSF5FwuDh8jRmg5Japf4tXOzUev1Ed1d4INWyndzjwolzgAmrHW muMsoJeHE2bAg7svEbctu0alBq1/55+xFtbjNEioLDlh5aDwE0xNbVWEIqyZSi/4AMbA xYT5h2qRsvInsgxU0kpQ+TNVuodT/0k19hOydf9DLcXeocXpP8rUIrYKgZF47EIxXTuk zPDA== X-Gm-Message-State: APt69E3HI7F5wGtG/xgQ8+1V6fqUr64iu0LaDyznYCxY2QZ9fGNxp+9b WBQwBrIYi00b7x4XU9gu95A5aHH33Q== X-Received: by 2002:a63:2682:: with SMTP id m124-v6mr3221154pgm.56.1528999807999; Thu, 14 Jun 2018 11:10:07 -0700 (PDT) Received: from localhost.localdomain ([2405:204:70c2:bb29:293b:24bf:4980:3a19]) by smtp.gmail.com with ESMTPSA id c74-v6sm11923363pfd.19.2018.06.14.11.10.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Jun 2018 11:10:07 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Thu, 14 Jun 2018 23:38:39 +0530 Message-Id: <20180614180839.8494-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> References: <20180614180839.8494-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, Manivannan Sadhasivam , thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [PATCH v3 9/9] MAINTAINERS: Add entries for Actions Semi OWL family X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add myself as the Maintainer for Actions Semi OWL family and its relevant board, drivers. Signed-off-by: Manivannan Sadhasivam --- Changes in v3: * Moved the change log from cover letter Changes in v2: None MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 642c448093..0f70cb04fe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -145,6 +145,15 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM OWL +M: Manivannan Sadhasivam +S: Maintained +F: arch/arm/include/asm/arch-owl/ +F: arch/arm/mach-owl/ +F: board/ucRobotics/ +F: drivers/clk/owl/ +F: drivers/serial/serial_owl.c + ARM RENESAS RMOBILE/R-CAR M: Nobuhiro Iwamatsu M: Marek Vasut