From patchwork Tue Apr 20 13:26:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 425430 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4BA8C433B4 for ; Tue, 20 Apr 2021 13:26:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A86CB6044F for ; Tue, 20 Apr 2021 13:26:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232494AbhDTN1I (ORCPT ); Tue, 20 Apr 2021 09:27:08 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:14547 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232456AbhDTN1G (ORCPT ); Tue, 20 Apr 2021 09:27:06 -0400 X-UUID: 14eedb80464c4e94a60d4d3755ee0d11-20210420 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=QRFvcRSzDacuRP/Rwmj28XFP20juDpAYqgUzkpxAhQw=; b=bVPoYDlJnu4V6bKP6mbt71gvkbw9VveTWYMGoBFZHtYGWdWc55etAOqNdyujddf+9RvEZ8fUvIV1nr+v/36HMFZCOYDH0ZoaP/CRx+KbwoX9uFIc9RBzU+c/QzyZLSUKo4lQ6TW9pa8Ds8Jm0nsKEYRXlBg3Aba8RpoWYNWDNy0=; X-UUID: 14eedb80464c4e94a60d4d3755ee0d11-20210420 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1991307290; Tue, 20 Apr 2021 21:26:27 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Apr 2021 21:26:17 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Apr 2021 21:26:16 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH 1/4] drm/panel: seperate panel power control from panel prepare/unprepare Date: Tue, 20 Apr 2021 21:26:10 +0800 Message-ID: <20210420132614.150242-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: 16A2BD5518165BF9873764FF788E4A99C5B0F7B7B0771DF8C7B7BBDDAE541BAA2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some dsi panels require the dsi lanes keeping low before panel power on. So seperate the panel power control and the communication with panel. And put the power control in drm_panel_prepare_power and drm_panel_unprepare_power. Put the communication with panel in drm_panel_prepare and drm_panel_unprepare. Signed-off-by: Jitao Shi --- drivers/gpu/drm/bridge/panel.c | 17 +++++++++++++++ drivers/gpu/drm/drm_panel.c | 38 ++++++++++++++++++++++++++++++++++ include/drm/drm_bridge.h | 2 ++ include/drm/drm_panel.h | 17 +++++++++++++++ 4 files changed, 74 insertions(+) -- 2.25.1 diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c index 0ddc37551194..a19c96e710fc 100644 --- a/drivers/gpu/drm/bridge/panel.c +++ b/drivers/gpu/drm/bridge/panel.c @@ -125,6 +125,23 @@ static int panel_bridge_get_modes(struct drm_bridge *bridge, return drm_panel_get_modes(panel_bridge->panel, connector); } +int panel_bridge_prepare_power(struct drm_bridge *bridge) +{ + struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge); + + return drm_panel_prepare_power(panel_bridge->panel); +} +EXPORT_SYMBOL(panel_bridge_prepare_power); + +int panel_bridge_unprepare_power(struct drm_bridge *bridge) +{ + struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge); + + return drm_panel_unprepare_power(panel_bridge->panel); +} +EXPORT_SYMBOL(panel_bridge_unprepare_power); + + static const struct drm_bridge_funcs panel_bridge_bridge_funcs = { .attach = panel_bridge_attach, .detach = panel_bridge_detach, diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c index f634371c717a..7bb5185db17d 100644 --- a/drivers/gpu/drm/drm_panel.c +++ b/drivers/gpu/drm/drm_panel.c @@ -115,6 +115,24 @@ int drm_panel_prepare(struct drm_panel *panel) } EXPORT_SYMBOL(drm_panel_prepare); +/** + * drm_panel_prepare_power - power on a panel's power + * @panel: DRM panel + * + * Calling this function will enable power and deassert any reset signals to + * the panel. + * + * Return: 0 on success or a negative error code on failure. + */ +int drm_panel_prepare_power(struct drm_panel *panel) +{ + if (panel && panel->funcs && panel->funcs->prepare_power) + return panel->funcs->prepare_power(panel); + + return panel ? -ENOSYS : -EINVAL; +} +EXPORT_SYMBOL(drm_panel_prepare_power); + /** * drm_panel_unprepare - power off a panel * @panel: DRM panel @@ -138,6 +156,26 @@ int drm_panel_unprepare(struct drm_panel *panel) } EXPORT_SYMBOL(drm_panel_unprepare); +/** + * drm_panel_unprepare_power - power off a panel + * @panel: DRM panel + * + * Calling this function will completely power off a panel (assert the panel's + * reset, turn off power supplies, ...). After this function has completed, it + * is usually no longer possible to communicate with the panel until another + * call to drm_panel_prepare_power and drm_panel_prepare(). + * + * Return: 0 on success or a negative error code on failure. + */ +int drm_panel_unprepare_power(struct drm_panel *panel) +{ + if (panel && panel->funcs && panel->funcs->unprepare_power) + return panel->funcs->unprepare_power(panel); + + return panel ? -ENOSYS : -EINVAL; +} +EXPORT_SYMBOL(drm_panel_unprepare_power); + /** * drm_panel_enable - enable a panel * @panel: DRM panel diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h index 2195daa289d2..cc94c9da47d8 100644 --- a/include/drm/drm_bridge.h +++ b/include/drm/drm_bridge.h @@ -892,6 +892,8 @@ struct drm_bridge *devm_drm_panel_bridge_add_typed(struct device *dev, struct drm_panel *panel, u32 connector_type); struct drm_connector *drm_panel_bridge_connector(struct drm_bridge *bridge); +int panel_bridge_prepare_power(struct drm_bridge *bridge); +int panel_bridge_unprepare_power(struct drm_bridge *bridge); #endif #endif diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h index 33605c3f0eba..48e83712ad44 100644 --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h @@ -68,6 +68,13 @@ enum drm_panel_orientation; * functionality to enable/disable backlight. */ struct drm_panel_funcs { + /** + * @prepare_power: + * + * Turn on panel power. + */ + int (*prepare_power)(struct drm_panel *panel); + /** * @prepare: * @@ -115,6 +122,13 @@ struct drm_panel_funcs { int (*get_modes)(struct drm_panel *panel, struct drm_connector *connector); + /** + * @unprepare_power: + * + * Turn off panel_power. + */ + int (*unprepare_power)(struct drm_panel *panel); + /** * @get_timings: * @@ -180,6 +194,9 @@ void drm_panel_init(struct drm_panel *panel, struct device *dev, void drm_panel_add(struct drm_panel *panel); void drm_panel_remove(struct drm_panel *panel); +int drm_panel_prepare_power(struct drm_panel *panel); +int drm_panel_unprepare_power(struct drm_panel *panel); + int drm_panel_prepare(struct drm_panel *panel); int drm_panel_unprepare(struct drm_panel *panel); From patchwork Tue Apr 20 13:26:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 424695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CB78C433ED for ; Tue, 20 Apr 2021 13:26:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25F5E61003 for ; Tue, 20 Apr 2021 13:26:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232498AbhDTN1I (ORCPT ); Tue, 20 Apr 2021 09:27:08 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:46817 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232453AbhDTN1H (ORCPT ); Tue, 20 Apr 2021 09:27:07 -0400 X-UUID: caceb05b186b46009969db505458c8e8-20210420 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Q1Yw7il2MClM4mQcrsnzuY1x1dqtCZCR9HbDGp8SKAI=; b=f3Fo92J5a+C5ZrVaQ8lZ0Awr10s3MGFx96ETF+J0WbxEwWHtaxh43fLLmHQb0Uads9bOEdVa3+FCcHwYMnjpz/6GZ5cLnL74HB/goT7MrSOypS1Rm1/VCWu/A57KktXy/4I3hYJ2mpeHJ8Vr+J8rBcwPnBYpB0CVDK/G4xYcEnU=; X-UUID: caceb05b186b46009969db505458c8e8-20210420 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1876854650; Tue, 20 Apr 2021 21:26:27 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Apr 2021 21:26:18 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Apr 2021 21:26:17 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH 2/4] drm/panel: boe-tv101wum-n16 seperate the panel power control Date: Tue, 20 Apr 2021 21:26:11 +0800 Message-ID: <20210420132614.150242-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210420132614.150242-1-jitao.shi@mediatek.com> References: <20210420132614.150242-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 45751ACB09465B252BD553B0B387AFEC38F4F85E73F60BF298E6246B4BC675732000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Seperate the panel power control from prepare/unprepare. Signed-off-by: Jitao Shi --- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 72 +++++++++++++------ 1 file changed, 50 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index db9d0b86d542..dc49079a74d1 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -50,6 +50,7 @@ struct boe_panel { struct regulator *avdd; struct gpio_desc *enable_gpio; + bool prepared_power; bool prepared; }; @@ -488,22 +489,13 @@ static int boe_panel_enter_sleep_mode(struct boe_panel *boe) return 0; } -static int boe_panel_unprepare(struct drm_panel *panel) +static int boe_panel_unprepare_power(struct drm_panel *panel) { struct boe_panel *boe = to_boe_panel(panel); - int ret; - if (!boe->prepared) + if (!boe->prepared_power) return 0; - ret = boe_panel_enter_sleep_mode(boe); - if (ret < 0) { - dev_err(panel->dev, "failed to set panel off: %d\n", ret); - return ret; - } - - msleep(150); - if (boe->desc->discharge_on_disable) { regulator_disable(boe->avee); regulator_disable(boe->avdd); @@ -512,6 +504,7 @@ static int boe_panel_unprepare(struct drm_panel *panel) usleep_range(5000, 7000); regulator_disable(boe->pp1800); } else { + msleep(150); gpiod_set_value(boe->enable_gpio, 0); usleep_range(500, 1000); regulator_disable(boe->avee); @@ -520,17 +513,39 @@ static int boe_panel_unprepare(struct drm_panel *panel) regulator_disable(boe->pp1800); } + boe->prepared_power = false; + + return 0; +} + +static int boe_panel_unprepare(struct drm_panel *panel) +{ + struct boe_panel *boe = to_boe_panel(panel); + int ret; + + if (!boe->prepared) + return 0; + + if (!boe->desc->discharge_on_disable) { + ret = boe_panel_enter_sleep_mode(boe); + if (ret < 0) { + dev_err(panel->dev, "failed to set panel off: %d\n", + ret); + return ret; + } + } + boe->prepared = false; return 0; } -static int boe_panel_prepare(struct drm_panel *panel) +static int boe_panel_prepare_power(struct drm_panel *panel) { struct boe_panel *boe = to_boe_panel(panel); int ret; - if (boe->prepared) + if (boe->prepared_power) return 0; gpiod_set_value(boe->enable_gpio, 0); @@ -558,18 +573,10 @@ static int boe_panel_prepare(struct drm_panel *panel) gpiod_set_value(boe->enable_gpio, 1); usleep_range(6000, 10000); - ret = boe_panel_init_dcs_cmd(boe); - if (ret < 0) { - dev_err(panel->dev, "failed to init panel: %d\n", ret); - goto poweroff; - } - - boe->prepared = true; + boe->prepared_power = true; return 0; -poweroff: - regulator_disable(boe->avee); poweroffavdd: regulator_disable(boe->avdd); poweroff1v8: @@ -580,6 +587,25 @@ static int boe_panel_prepare(struct drm_panel *panel) return ret; } +static int boe_panel_prepare(struct drm_panel *panel) +{ + struct boe_panel *boe = to_boe_panel(panel); + int ret; + + if (boe->prepared) + return 0; + + ret = boe_panel_init_dcs_cmd(boe); + if (ret < 0) { + dev_err(panel->dev, "failed to init panel: %d\n", ret); + return ret; + } + + boe->prepared = true; + + return 0; +} + static int boe_panel_enable(struct drm_panel *panel) { msleep(130); @@ -749,7 +775,9 @@ static int boe_panel_get_modes(struct drm_panel *panel, static const struct drm_panel_funcs boe_panel_funcs = { .unprepare = boe_panel_unprepare, + .unprepare_power = boe_panel_unprepare_power, .prepare = boe_panel_prepare, + .prepare_power = boe_panel_prepare_power, .enable = boe_panel_enable, .get_modes = boe_panel_get_modes, }; From patchwork Tue Apr 20 13:26:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 425429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9C93C43460 for ; Tue, 20 Apr 2021 13:26:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85DE2610A1 for ; Tue, 20 Apr 2021 13:26:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232544AbhDTN1Q (ORCPT ); Tue, 20 Apr 2021 09:27:16 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:13776 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232524AbhDTN1N (ORCPT ); Tue, 20 Apr 2021 09:27:13 -0400 X-UUID: 959f53c016c34ab6838cafa57f8b35a2-20210420 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=x4PC10VWjynceWQKGlyruq1xHVfMHe0q+ks95eUDcMM=; b=h4Amvf4zV4EtMkX2uOL4XqdQaDatxwvRwb5ngk9VPSOOCnHO5ReevrLdvhAn5RpAgTGbB5wpolNxmbFt+WEr/9H2fsGIk2bu9IoBdpwuMGd208bbXNW7Etcr83p6wkRXEVwqERMWhDQH5gSKCjU6igqkGVGEemsietuXaU9M0dQ=; X-UUID: 959f53c016c34ab6838cafa57f8b35a2-20210420 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1691856229; Tue, 20 Apr 2021 21:26:37 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Apr 2021 21:26:20 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Apr 2021 21:26:18 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH 3/4] drm/mediatek: fine tune the dsi panel's power sequence Date: Tue, 20 Apr 2021 21:26:12 +0800 Message-ID: <20210420132614.150242-3-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210420132614.150242-1-jitao.shi@mediatek.com> References: <20210420132614.150242-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: DE26EABE28240C1980E352A0A7E176B5B54C70B4B01E7B5C108E2A0C6A821C082000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the drm_panel_prepare_power and drm_panel_unprepare_power control. Turn on panel power(drm_panel_prepare_power) and control before dsi enable. And then dsi enable, send dcs cmd in drm_panel_prepare, last turn on backlight. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a1ff152ef468..455fe582c6b5 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -615,10 +615,13 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel, dsi->lanes); + if (panel_bridge_prepare_power(dsi->next_bridge)) + DRM_INFO("can't prepare power the panel\n"); + ret = clk_set_rate(dsi->hs_clk, dsi->data_rate); if (ret < 0) { dev_err(dev, "Failed to set data rate: %d\n", ret); - goto err_refcount; + goto err_prepare_power; } phy_power_on(dsi->phy); @@ -661,7 +664,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) clk_disable_unprepare(dsi->engine_clk); err_phy_power_off: phy_power_off(dsi->phy); -err_refcount: +err_prepare_power: + if (panel_bridge_unprepare_power(dsi->next_bridge)) + DRM_INFO("Can't unprepare power the panel\n"); dsi->refcount--; return ret; } @@ -694,6 +699,9 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) clk_disable_unprepare(dsi->digital_clk); phy_power_off(dsi->phy); + + if (panel_bridge_unprepare_power(dsi->next_bridge)) + DRM_INFO("Can't unprepare power the panel\n"); } static void mtk_output_dsi_enable(struct mtk_dsi *dsi) From patchwork Tue Apr 20 13:26:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 424696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92C8BC43462 for ; Tue, 20 Apr 2021 13:26:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 611EC6044F for ; Tue, 20 Apr 2021 13:26:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232492AbhDTN1H (ORCPT ); Tue, 20 Apr 2021 09:27:07 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:41349 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232448AbhDTN1G (ORCPT ); Tue, 20 Apr 2021 09:27:06 -0400 X-UUID: 67b4741ee606471bb1f9e905ed906884-20210420 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=F/Ns6WIK2Dy0aPedbYy3llJMXtmG+SMNazBAvgRMihY=; b=o0UFIGtF7B5l+zpZ/eonUMjp4IyVrBz4SJ+o6C1z6gZde/pSxgrVv04K313rlg+ePenX7Dlg1KHOp9jf8PVjKNBIJJJ8KWRe84pjKGf9dWuDqGTJ++lgzPRMwQmg56W91edZA3uBAjqgKD0bLYzKZwpxs8qbs4Zbps07DkEuBCk=; X-UUID: 67b4741ee606471bb1f9e905ed906884-20210420 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 369354208; Tue, 20 Apr 2021 21:26:29 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Apr 2021 21:26:21 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Apr 2021 21:26:20 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , , , , Jitao Shi Subject: [PATCH 4/4] drm/mediatek: add dsi module reset driver Date: Tue, 20 Apr 2021 21:26:13 +0800 Message-ID: <20210420132614.150242-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210420132614.150242-1-jitao.shi@mediatek.com> References: <20210420132614.150242-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: CDD0EDBC07D217E939DC5558E2076778B137CA9F9ABA7EDE162356D70FBDF6E02000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Reset dsi HW to default when power on. Prevent the setting differet between bootloader and kernel. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 36 +++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 455fe582c6b5..113438ddd4cc 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -7,10 +7,12 @@ #include #include #include +#include #include #include #include #include +#include #include