From patchwork Fri Apr 23 01:47:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 426434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECE00C43460 for ; Fri, 23 Apr 2021 01:48:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C60E561176 for ; Fri, 23 Apr 2021 01:48:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240190AbhDWBsf (ORCPT ); Thu, 22 Apr 2021 21:48:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240094AbhDWBsb (ORCPT ); Thu, 22 Apr 2021 21:48:31 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 048D8C061574; Thu, 22 Apr 2021 18:47:56 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id bx20so54579636edb.12; Thu, 22 Apr 2021 18:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pvbtV9z9Nr84yi5HQm0Sl3OJ0RmRKTgXaB8Aibs1Fi8=; b=EfRbrmuBOsfwwNIQNwN5GJp3OecEYddJmdaOR6JSbMsoY6lBC76RhjCTvceB0TPBd2 77S72/SYUO+z6E9y6A8iuGSV4h7Q27S0GqdEuhMp1KazW0IJpqyjiScuPSGO0SFRrSAz WnoTOh+LU0E5vUxZO59H1jFFN2CtOiIMRaiUMUZMLw0pucHTvFQc6y64awrM8uR9VXyC bR/dNgD0OPiU9usH0Yfk5ggv9J0E8twIM/Z/oV4dhKml8R43Z4UilpG2gQprQV0Ls0id /uVPlVqt+Oar8hY7GB+milL4VAr8MWSp8tjbxfSvaDpZh79aQvZi/cGsiKKdglcSskyl f1tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pvbtV9z9Nr84yi5HQm0Sl3OJ0RmRKTgXaB8Aibs1Fi8=; b=EUXRBRtv9uTqKjBc+Br08W77oJmjBSAmCDOZf6s8+Zfy2Q9y9r6BtC6sY5yQY6eaQN zTdy7Hof6aYBB0KnI2HqltLOICZct0VSi9im1M/oC6cZmEn2HwL/cuhv/yzcAMS78hkO A36Nb0Cg69wSlKZIEVkd9z8jN9cB648OdszlQWmQWANxtPe0LofRPyismBQOE1WZfgVj CHPXT8afef6xMd/5gj3E2ZDyxljaZUkbW4GvOD5dyI0MKTYS2Yqzrd5Xx+mlNjC0wH58 J3MJkbs45hlv30QiU4AXqoc9UGJJ6SQqiHWNVJWhHTElV1RULuLrQa9hb5qAu937QcAH ZEnQ== X-Gm-Message-State: AOAM5334cXKuHFxvYZWmf48OsJrlkXWuvBdwND10f9WIdN9oexwLAbK9 UmXdUqxNgGOGua+zX6EM2Jw= X-Google-Smtp-Source: ABdhPJxyUWMKaSFu4paSngAiB+5r6Rkz9pq5QLh3DwWoyDCpPTxn6OBbJPJGdeBTBeVqYp6gwZLQKw== X-Received: by 2002:aa7:c78a:: with SMTP id n10mr1527723eds.239.1619142474723; Thu, 22 Apr 2021 18:47:54 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:47:54 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] drivers: net: dsa: qca8k: tweak internal delay to oem spec Date: Fri, 23 Apr 2021 03:47:28 +0200 Message-Id: <20210423014741.11858-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The original code had the internal dalay set to 1 for tx and 2 for rx. Apply the oem internal dalay to fix some switch communication error. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 6 ++++-- drivers/net/dsa/qca8k.h | 9 ++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index a6d35b825c0e..b8bfc7acf6f4 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -849,8 +849,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, */ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); + QCA8K_PORT_PAD_RGMII_TX_DELAY(1) | + QCA8K_PORT_PAD_RGMII_RX_DELAY(2) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); break; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 7ca4b93e0bb5..e0b679133880 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -32,12 +32,11 @@ #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ - ((0x8 + (x & 0x3)) << 22) -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ - ((0x10 + (x & 0x3)) << 20) -#define QCA8K_MAX_DELAY 3 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) +#define QCA8K_MAX_DELAY 3 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) #define QCA8K_REG_PWS 0x010 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) From patchwork Fri Apr 23 01:47:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 426433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53CFFC433ED for ; Fri, 23 Apr 2021 01:48:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2537B61459 for ; Fri, 23 Apr 2021 01:48:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240301AbhDWBsp (ORCPT ); Thu, 22 Apr 2021 21:48:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240188AbhDWBsf (ORCPT ); Thu, 22 Apr 2021 21:48:35 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FC83C06138C; Thu, 22 Apr 2021 18:47:59 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id s15so55735953edd.4; Thu, 22 Apr 2021 18:47:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wfLXpnhGJBdDME0GgFox4THhUlvgNKI4GtU1C1FAZTE=; b=cEDhlBGdPUJnj5pvq+u72MgXY0g6OKTlixluwNLiPM7SpD87EBvaJmOzZjv1UNLuLI iOkAvgVWZ5Lx/QH7JHMXStrE+UWgC65MkYYUqjjWfCsXXBkyvI/SbaL1k46enyPbg0bd aaR20YX9/J+2n96zwzUtIMlKoOrDV86EoTeJhwlebv3BtUX+OCCve28vkwVd6f5XLNmr 9zAbfnwumIbPpxVeHJgOCtUCcDd6Kbf2+ebLSVMMdCvz7VKyP2qnV6tiYWe8i/6hok5O V/RvffW2GzDFenjbGTmLWmO9JrffeuFkMCcOa2YbYZ2Fs/QfTk1JhVdxv8KHlsuqfEut S5VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wfLXpnhGJBdDME0GgFox4THhUlvgNKI4GtU1C1FAZTE=; b=Lf0Sgb6o8H0Q7gooM3UZBMCzPW3x7odjQqmruKrxuB+MgEB5WkJhHfCSdtSsdYhMfh EDCob+R5WOXgyLjejpvmx+3mJSSFsO79d7q7oFqpPjLcV+xxP+WiRE9VMipIL7Yujm1W s/uR4cFhEjHPzyl7C1S0Oyr21iKJIIk4hBCDM/BhpLbLe27L45x5Dga+NdmufMoPcWUU KoH/6wUSU5u5x6HroRgfzWKb0okRDzga8yN27fOCbf+a/osjPDyMqUAzYfzMTC8EXnE9 h8b+Hygals/sOBFAe6KVZNZIS+0Yfqld1pPZnWXPv4DKQIBBJXABeCrhXMaah8kOeF9Z nooA== X-Gm-Message-State: AOAM532GNFxUdSQpZKHoFdBFH19qfhf9R+yS6iAW2Psmc5j8Jm6mKHBa rxQ5BnCjGo2icRS1cjn8ZfE5eiKOyhdsPw== X-Google-Smtp-Source: ABdhPJyv1e6gF3pgDMi6cudMISRbJFClxk8YgiRHQc6rSSJLZPkkyIi7DEXj0EHQ2ZqJR6dbUrR8PQ== X-Received: by 2002:aa7:de8b:: with SMTP id j11mr1544562edv.363.1619142477882; Thu, 22 Apr 2021 18:47:57 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:47:57 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] drivers: net: dsa: qca8k: apply suggested packet priority Date: Fri, 23 Apr 2021 03:47:30 +0200 Message-Id: <20210423014741.11858-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The port 5 of the ar8337 have some problem in flood condition. The original legacy driver had some specific buffer and priority settings for the different port suggested by the QCA switch team. Add this missing settings to improve switch stability under load condition. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 42 +++++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 24 +++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index b8bfc7acf6f4..7408cbee05c2 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -701,6 +701,7 @@ qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int ret, i; + u32 mask; /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { @@ -785,6 +786,47 @@ qca8k_setup(struct dsa_switch *ds) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); + /* The port 5 of the switch ar8337 have some problem in flood condition. + * To fix this the original code has some specific priority values + * suggested by the QCA switch team. + */ + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + switch (i) { + /* The 2 CPU port and port 5 requires some different + * priority than any other ports. + */ + case 0: + case 5: + case 6: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); + break; + default: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + } + qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); + + mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN; + qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), + QCA8K_PORT_HOL_CTRL1_ING_BUF | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN, + mask); + } + /* Flush the FDB table */ qca8k_fdb_flush(priv); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index e0b679133880..0ff7abbd40dc 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -163,6 +163,30 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) + +#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) +#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) +#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) +#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) + /* Pkt edit registers */ #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) From patchwork Fri Apr 23 01:47:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 426432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 701E4C433B4 for ; Fri, 23 Apr 2021 01:48:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5514661459 for ; Fri, 23 Apr 2021 01:48:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240291AbhDWBtB (ORCPT ); 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:02 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/14] drivers: net: dsa: qca8k: limit priority tweak to qca8337 switch Date: Fri, 23 Apr 2021 03:47:33 +0200 Message-Id: <20210423014741.11858-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The packet priority tweak and the rx delay is specific to qca8337. Limit this changes to qca8337 as now we also support 8327 switch. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 84 +++++++++++++++++++++++------------------ 1 file changed, 48 insertions(+), 36 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index ca12394c2ff7..19bb3754d9ec 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -700,9 +700,13 @@ static int qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + const struct qca8k_match_data *data; int ret, i; u32 mask; + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { pr_err("port 0 is not the CPU port\n"); @@ -790,41 +794,43 @@ qca8k_setup(struct dsa_switch *ds) * To fix this the original code has some specific priority values * suggested by the QCA switch team. */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - switch (i) { - /* The 2 CPU port and port 5 requires some different - * priority than any other ports. - */ - case 0: - case 5: - case 6: - mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | - QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | - QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | - QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); - break; - default: - mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | - QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | - QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | - QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + if (data->id == QCA8K_ID_QCA8337) { + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + switch (i) { + /* The 2 CPU port and port 5 requires some different + * priority than any other ports. + */ + case 0: + case 5: + case 6: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); + break; + default: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + } + qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); + + mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN; + qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), + QCA8K_PORT_HOL_CTRL1_ING_BUF | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN, + mask); } - qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); - - mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | - QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | - QCA8K_PORT_HOL_CTRL1_WRED_EN; - qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), - QCA8K_PORT_HOL_CTRL1_ING_BUF | - QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | - QCA8K_PORT_HOL_CTRL1_WRED_EN, - mask); } /* Flush the FDB table */ @@ -840,9 +846,13 @@ static void qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { + const struct qca8k_match_data *data; struct qca8k_priv *priv = ds->priv; u32 reg, val; + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + switch (port) { case 0: /* 1st CPU port */ if (state->interface != PHY_INTERFACE_MODE_RGMII && @@ -895,8 +905,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, QCA8K_PORT_PAD_RGMII_RX_DELAY(2) | QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); - qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); + /* QCA8337 requires to set rgmii rx delay */ + if (data->id == QCA8K_ID_QCA8337) + qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: From patchwork Fri Apr 23 01:47:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 426431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A82B6C433ED for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:05 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] drivers: net: dsa: qca8k: add support for switch rev Date: Fri, 23 Apr 2021 03:47:35 +0200 Message-Id: <20210423014741.11858-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org qca8k switch require some special debug value to be set based on the switch revision. Rework the switch id read function to also read the chip revision and make it accessible to the switch data. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 17 ++++++++++++----- drivers/net/dsa/qca8k.h | 7 +++++-- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index d469620e9344..20b507a35191 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1459,12 +1459,22 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_link_up = qca8k_phylink_mac_link_up, }; +static u8 qca8k_read_switch_id(struct qca8k_priv *priv) +{ + u32 val; + + val = qca8k_read(priv, QCA8K_REG_MASK_CTRL); + + priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); + + return QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); +} + static int qca8k_sw_probe(struct mdio_device *mdiodev) { const struct qca8k_match_data *data; struct qca8k_priv *priv; - u32 id; /* allocate the private data struct so that we can probe the switches * ID register @@ -1496,10 +1506,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev) return -ENODEV; /* read the switches ID register */ - id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); - id >>= QCA8K_MASK_CTRL_ID_S; - id &= QCA8K_MASK_CTRL_ID_M; - if (id != data->id) + if (qca8k_read_switch_id(priv) != data->id) return -ENODEV; priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 308d8410fdb6..dbd54d870a30 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -28,8 +28,10 @@ /* Global control registers */ #define QCA8K_REG_MASK_CTRL 0x000 -#define QCA8K_MASK_CTRL_ID_M 0xff -#define QCA8K_MASK_CTRL_ID_S 8 +#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) +#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) +#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) +#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c @@ -247,6 +249,7 @@ struct qca8k_match_data { }; struct qca8k_priv { + u8 switch_revision; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Fri Apr 23 01:47:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 426428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6809C43460 for ; Fri, 23 Apr 2021 01:49:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 89BD761477 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:06 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] drivers: net: dsa: qca8k: add support for specific QCA access function Date: Fri, 23 Apr 2021 03:47:36 +0200 Message-Id: <20210423014741.11858-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some qca8k switch revision require some special dbg value to be set based on the revision number. Add required function to write and read in these specific registers. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 51 +++++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 2 ++ 2 files changed, 53 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 20b507a35191..193c269d8ed3 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -69,6 +69,57 @@ static const struct qca8k_mib_desc ar8327_mib[] = { MIB_DESC(1, 0xa4, "TxLateCol"), }; +/* QCA specific MII registers access function */ +void qca8k_phy_dbg_read(struct qca8k_priv *priv, int phy_addr, u16 dbg_addr, u16 *dbg_data) +{ + struct mii_bus *bus = priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA); + mutex_unlock(&bus->mdio_lock); +} + +void qca8k_phy_dbg_write(struct qca8k_priv *priv, int phy_addr, u16 dbg_addr, u16 dbg_data) +{ + struct mii_bus *bus = priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data); + mutex_unlock(&bus->mdio_lock); +} + +static inline void qca8k_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg) +{ + bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr); + bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg); + bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000); +} + +void qca8k_phy_mmd_write(struct qca8k_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data) +{ + struct mii_bus *bus = priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + qca8k_phy_mmd_prep(bus, phy_addr, addr, reg); + bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data); + mutex_unlock(&bus->mdio_lock); +} + +u16 qca8k_phy_mmd_read(struct qca8k_priv *priv, int phy_addr, u16 addr, u16 reg) +{ + struct mii_bus *bus = priv->bus; + u16 data; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + qca8k_phy_mmd_prep(bus, phy_addr, addr, reg); + data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA); + mutex_unlock(&bus->mdio_lock); + + return data; +} + /* The 32bit switch registers are accessed indirectly. To achieve this we need * to set the page of the register. Track the last page that was set to reduce * mdio writes diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index dbd54d870a30..de00aa74868b 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -215,6 +215,8 @@ /* QCA specific MII registers */ #define MII_ATH_MMD_ADDR 0x0d #define MII_ATH_MMD_DATA 0x0e +#define MII_ATH_DBG_ADDR 0x1d +#define MII_ATH_DBG_DATA 0x1e enum { QCA8K_PORT_SPEED_10M = 0, From patchwork Fri Apr 23 01:47:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 426429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42793C433ED for ; Fri, 23 Apr 2021 01:49:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 18589613D1 for ; Fri, 23 Apr 2021 01:49:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236126AbhDWBtd (ORCPT ); Thu, 22 Apr 2021 21:49:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240403AbhDWBtA (ORCPT ); Thu, 22 Apr 2021 21:49:00 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07B66C06138C; Thu, 22 Apr 2021 18:48:10 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id n2so71582816ejy.7; Thu, 22 Apr 2021 18:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=56PL0a5zXu4rcg3HLsKZZ+epvuKuacuxdJ5tVhsmylI=; b=BqZZKKo1hpCxnIbzNFdSp+JpbJurHmDiX2ajEiy5gHkbeTWqo3Au0CAvO/YtkZ+Olw Icw7O0rBzbPPOAEJUGsg2bQmhngSLEwDqLQ3kcBTKMGMmP0/OB3tu4ss35N+wXsubJFl NwNbKhb3dr/+GDSg497I35s3PYRIBi/D1FsXeZgTBfGbiobrrg6/NVs7kCCYmknVnrnX O0cp627DUc6S+PAj2uuQzgFWkc/p5cjTi6iT0wNRsMndA5o6F/Pd/sr5Kni5Jn9wsisP P3qLda360N8KO76Jaf8PtutaUKLsreVGqmdXgBj2I1nGNYUwIlEaIFwMmy95mWUaBxka 9Iog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=56PL0a5zXu4rcg3HLsKZZ+epvuKuacuxdJ5tVhsmylI=; b=f0MWA46c+is9g5PjacWYKl5M6Kr+5q+maca42LsrcOBvbLVYVGWos9sb8bSwYz9+W/ +BeqHm+bmz3f9Rmf9nAhlH0pY9CPZM4YrwSySzCK6rwyzKB9JXbZRjiK0RonIhMzmki5 gLse7dnPfiiEl/BU1+mTnvlb3F4rPa0e0p1tC5KbhwlO7CkGMA38Jybit1jMtEPWgxKh rO5WkEa5zVA7UW3dOU/d2cJFC39XA1QIq5uK09RC7c25UYcDdvHf+jrJQb6Ccn/t8jwg O4syyQxHUwN/n/zjoBpZ3VHlR0ggLSsvMHuNfKm/TvDjeKIXReT6JzxKvonVqGewsawS A/PQ== X-Gm-Message-State: AOAM5336UBLLggSh1uV+lFrGHy7ICTKYIIy09D2siktCM7KQEnwdoRuk QhFZpI/4H/Rq46viV4d1TxY= X-Google-Smtp-Source: ABdhPJzfZqD/Zxc+bJLESHf2GJLG7qiUI1wsupPLBD/+ZmEgQudFNmr6VMSwrpRKt4NkNX23CKd4Qw== X-Received: by 2002:a17:907:3f22:: with SMTP id hq34mr1525547ejc.535.1619142488732; Thu, 22 Apr 2021 18:48:08 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:08 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] drivers: net: dsa: qca8k: apply switch revision fix Date: Fri, 23 Apr 2021 03:47:37 +0200 Message-Id: <20210423014741.11858-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org qca8k require special debug value based on the switch revision. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 193c269d8ed3..12d2c97d1417 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -909,7 +909,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, { const struct qca8k_match_data *data; struct qca8k_priv *priv = ds->priv; - u32 reg, val; + u32 phy, reg, val; /* get the switches ID from the compatible */ data = of_device_get_match_data(priv->dev); @@ -928,7 +928,26 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case 3: case 4: case 5: - /* Internal PHY, nothing to do */ + /* Internal PHY, apply revision fixup */ + phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; + switch (priv->switch_revision) { + case 1: + /* For 100M waveform */ + qca8k_phy_dbg_write(priv, phy, 0, 0x02ea); + /* Turn on Gigabit clock */ + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x68a0); + break; + + case 2: + qca8k_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0); + fallthrough; + case 4: + qca8k_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f); + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x6860); + qca8k_phy_dbg_write(priv, phy, 0x5, 0x2c46); + qca8k_phy_dbg_write(priv, phy, 0x3c, 0x6000); + break; + } return; case 6: /* 2nd CPU port / external PHY */ if (state->interface != PHY_INTERFACE_MODE_RGMII && From patchwork Fri Apr 23 01:47:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 426430 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C157FC433B4 for ; Fri, 23 Apr 2021 01:48:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9C923613D1 for ; Fri, 23 Apr 2021 01:48:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240636AbhDWBt3 (ORCPT ); Thu, 22 Apr 2021 21:49:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236126AbhDWBsy (ORCPT ); Thu, 22 Apr 2021 21:48:54 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1FE9C06174A; Thu, 22 Apr 2021 18:48:11 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id r12so71623086ejr.5; Thu, 22 Apr 2021 18:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Nf/+Y+13GJ3s0+R51l6M7NWLkrdPSWKqvmk7zfK1es=; b=GevxPR1q+4lC30fPIiTwR5droZivdeq5304ubvydRjKv+AGkBLB4Paxl1G/JMrDy7U VIV/f1ARCZxFsIE36tIX3do7Vm4KTumfD3ATnkfxGkYxhbsmNh7Z4QrfKopti6eLVLNO kJs8sjpGTNkvm3L4vdUKBlIJ/IZ6gPc+ixGJe1K0LGG7I8ErBaMGWQDAwTp0iRZKWD43 XktvUkt2dt5EYrs6zOqN18XvWdL8E8UMAYrTd1OrFWvfvP+b7pnv2NIV+UQKKkVOPzwK XbHf25SOQwaNf0MRlqoECC0l36hTkALmTYg1oZoyqu9QdAHiPZhU5cS1mG7W9m/Hztov 4t4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Nf/+Y+13GJ3s0+R51l6M7NWLkrdPSWKqvmk7zfK1es=; b=BAZ0CAuFNBSihsx2GI/zKPLb/EWiFjYv59i199lE90U1d/hzDSMQXSgjv+vdQhTPeH f84kTsjCknazu3GJ/snEBi9ABtZgSeZhJVbi/MO5b4QHFo5mmXdIBeRDq28JMb3TgrJK Gp/OgHO7X7kakNvxWgrG/feTr7TlbIwHUfc+iccOTG8ZRUX0Z4hB8EzkXltdJb6ObSGJ lgzHg3/RVW1cF/w0dkP1/hMoIwMLpE1QOKqqCyBN2DQXynCyupS9KKkygqkqLvWxRGTf IizG2+PmNj49zSz+qIRKBU81mZ+TkBTo2E5raTrVSP0IQmC5Bn1slWngwXXZ0IUjasgu F94g== X-Gm-Message-State: AOAM5323rGEotqURfXKisRZkI4Dz9191mq6kgBCO6K4C5gMfJaZ2vzQG z8nEPkmdHLbsqHkU64WueJo= X-Google-Smtp-Source: ABdhPJwIdyi0HpMxWThh4NHtG+R0F8nQpv0P1MvvoKE/G5pRR/UZpm4tT0l3Z2hwLn+kcEKpQIqSNg== X-Received: by 2002:a17:906:7d82:: with SMTP id v2mr1625907ejo.524.1619142490267; Thu, 22 Apr 2021 18:48:10 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:09 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/14] drivers: net: dsa: qca8k: clear MASTER_EN after phy read/write Date: Fri, 23 Apr 2021 03:47:38 +0200 Message-Id: <20210423014741.11858-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write operation. The MDIO_MASTER_EN bit is not reset after read/write operation and the next operation can be wrongly interpreted by the switch as a mdio operation. This cause a production of wrong/garbage data from the switch and underfined bheavior. (random port drop, unplugged port flagged with link up, wrong port speed) Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 12d2c97d1417..88a0234f1a7b 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -613,6 +613,7 @@ static int qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) { u32 phy, val; + int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; @@ -628,8 +629,13 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); - return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + + return ret; } static int @@ -657,6 +663,9 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & QCA8K_MDIO_MASTER_DATA_MASK); + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + return val; }