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Begin using f-strings on changed lines. Signed-off-by: Richard Henderson --- scripts/decodetree.py | 66 +++++++++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 28 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 4637b633e7..0861e5d503 100644 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -102,6 +102,21 @@ def str_fields(fields): return r[1:] +def whex(val): + """Return a hex string for val padded for insnwidth""" + global insnwidth + return f'0x{val:0{insnwidth // 4}x}' + + +def whexC(val): + """Return a hex string for val padded for insnwidth, + and with the proper suffix for a C constant.""" + suffix = '' + if val >= 0x80000000: + suffix = 'u' + return whex(val) + suffix + + def str_match_bits(bits, mask): """Return a string pretty-printing BITS/MASK""" global insnwidth @@ -477,11 +492,8 @@ def output_code(self, i, extracted, outerbits, outermask): if outermask != p.fixedmask: innermask = p.fixedmask & ~outermask innerbits = p.fixedbits & ~outermask - output(ind, 'if ((insn & ', - '0x{0:08x}) == 0x{1:08x}'.format(innermask, innerbits), - ') {\n') - output(ind, ' /* ', - str_match_bits(p.fixedbits, p.fixedmask), ' */\n') + output(ind, f'if ((insn & {whexC(innermask)}) == {whexC(innerbits)}) {{\n') + output(ind, f' /* {str_match_bits(p.fixedbits, p.fixedmask)} */\n') p.output_code(i + 4, extracted, p.fixedbits, p.fixedmask) output(ind, '}\n') else: @@ -500,12 +512,12 @@ def __init__(self, fm, tm): def str1(self, i): ind = str_indent(i) - r = '{0}{1:08x}'.format(ind, self.fixedmask) + r = ind + whex(self.fixedmask) if self.format: r += ' ' + self.format.name r += ' [\n' for (b, s) in self.subs: - r += '{0} {1:08x}:\n'.format(ind, b) + r += ind + f' {whex(b)}:\n' r += s.str1(i + 4) + '\n' r += ind + ']' return r @@ -529,16 +541,16 @@ def output_code(self, i, extracted, outerbits, outermask): if sh > 0: # Propagate SH down into the local functions. def str_switch(b, sh=sh): - return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh) + return f'(insn >> {sh}) & {b >> sh:#x}' def str_case(b, sh=sh): - return '0x{0:x}'.format(b >> sh) + return hex(b >> sh) else: def str_switch(b): - return 'insn & 0x{0:08x}'.format(b) + return f'insn & {whexC(b)}' def str_case(b): - return '0x{0:08x}'.format(b) + return whexC(b) output(ind, 'switch (', str_switch(self.thismask), ') {\n') for b, s in sorted(self.subs): @@ -962,19 +974,19 @@ def parse_generic(lineno, parent_pat, name, toks): # Validate the masks that we have assembled. if fieldmask & fixedmask: - error(lineno, 'fieldmask overlaps fixedmask (0x{0:08x} & 0x{1:08x})' - .format(fieldmask, fixedmask)) + error(lineno, 'fieldmask overlaps fixedmask ', + f'({whex(fieldmask)} & {whex(fixedmask)})') if fieldmask & undefmask: - error(lineno, 'fieldmask overlaps undefmask (0x{0:08x} & 0x{1:08x})' - .format(fieldmask, undefmask)) + error(lineno, 'fieldmask overlaps undefmask ', + f'({whex(fieldmask)} & {whex(undefmask)})') if fixedmask & undefmask: - error(lineno, 'fixedmask overlaps undefmask (0x{0:08x} & 0x{1:08x})' - .format(fixedmask, undefmask)) + error(lineno, 'fixedmask overlaps undefmask ', + f'({whex(fixedmask)} & {whex(undefmask)})') if not is_format: allbits = fieldmask | fixedmask | undefmask if allbits != insnmask: - error(lineno, 'bits left unspecified (0x{0:08x})' - .format(allbits ^ insnmask)) + error(lineno, 'bits left unspecified ', + f'({whex(allbits ^ insnmask)})') # end parse_general @@ -1104,10 +1116,9 @@ def __init__(self, m, w): def str1(self, i): ind = str_indent(i) - r = '{0}{1:08x}'.format(ind, self.mask) - r += ' [\n' + r = ind + whex(self.mask) + ' [\n' for (b, s) in self.subs: - r += '{0} {1:08x}:\n'.format(ind, b) + r += ind + f' {whex(b)}:\n' r += s.str1(i + 4) + '\n' r += ind + ']' return r @@ -1131,16 +1142,16 @@ def output_code(self, i, extracted, outerbits, outermask): if sh > 0: # Propagate SH down into the local functions. def str_switch(b, sh=sh): - return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh) + return f'(insn >> {sh}) & {b >> sh:#x}' def str_case(b, sh=sh): - return '0x{0:x}'.format(b >> sh) + return hex(b >> sh) else: def str_switch(b): - return 'insn & 0x{0:08x}'.format(b) + return f'insn & {whexC(b)}' def str_case(b): - return '0x{0:08x}'.format(b) + return whexC(b) output(ind, 'switch (', str_switch(self.mask), ') {\n') for b, s in sorted(self.subs): @@ -1162,8 +1173,7 @@ def __init__(self, m, w): self.width = w def str1(self, i): - ind = str_indent(i) - return '{0}{1:08x}'.format(ind, self.mask) + return str_indent(i) + whex(self.mask) def __str__(self): return self.str1(0) From patchwork Fri Apr 30 01:15:15 2021 Content-Type: text/plain; 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Thu, 29 Apr 2021 18:15:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/30] decodetree: More use of f-strings Date: Thu, 29 Apr 2021 18:15:15 -0700 Message-Id: <20210430011543.1017113-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- scripts/decodetree.py | 50 ++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 27 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires Reviewed-by: Philippe Mathieu-Daudé diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 0861e5d503..d5da101167 100644 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -59,9 +59,9 @@ def error_with_file(file, lineno, *args): prefix = '' if file: - prefix += '{0}:'.format(file) + prefix += f'{file}:' if lineno: - prefix += '{0}:'.format(lineno) + prefix += f'{lineno}:' if prefix: prefix += ' ' print(prefix, end='error: ', file=sys.stderr) @@ -203,7 +203,7 @@ def str_extract(self): extr = 'sextract32' else: extr = 'extract32' - return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len) + return f'{extr}(insn, {self.pos}, {self.len})' def __eq__(self, other): return self.sign == other.sign and self.mask == other.mask @@ -227,11 +227,11 @@ def str_extract(self): ret = '0' pos = 0 for f in reversed(self.subs): + ext = f.str_extract() if pos == 0: - ret = f.str_extract() + ret = ext else: - ret = 'deposit32({0}, {1}, {2}, {3})' \ - .format(ret, pos, 32 - pos, f.str_extract()) + ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})' pos += f.len return ret @@ -675,11 +675,11 @@ def parse_field(lineno, name, toks): subtoks = t.split(':') sign = False else: - error(lineno, 'invalid field token "{0}"'.format(t)) + error(lineno, f'invalid field token "{t}"') po = int(subtoks[0]) le = int(subtoks[1]) if po + le > insnwidth: - error(lineno, 'field {0} too large'.format(t)) + error(lineno, f'field {t} too large') f = Field(sign, po, le) subs.append(f) width += le @@ -724,9 +724,9 @@ def parse_arguments(lineno, name, toks): anyextern = True continue if not re.fullmatch(re_C_ident, t): - error(lineno, 'invalid argument set token "{0}"'.format(t)) + error(lineno, f'invalid argument set token "{t}"') if t in flds: - error(lineno, 'duplicate argument "{0}"'.format(t)) + error(lineno, f'duplicate argument "{t}"') flds.append(t) if name in arguments: @@ -895,14 +895,14 @@ def parse_generic(lineno, parent_pat, name, toks): flen = flen[1:] shift = int(flen, 10) if shift + width > insnwidth: - error(lineno, 'field {0} exceeds insnwidth'.format(fname)) + error(lineno, f'field {fname} exceeds insnwidth') f = Field(sign, insnwidth - width - shift, shift) flds = add_field(lineno, flds, fname, f) fixedbits <<= shift fixedmask <<= shift undefmask <<= shift else: - error(lineno, 'invalid token "{0}"'.format(t)) + error(lineno, f'invalid token "{t}"') width += shift if variablewidth and width < insnwidth and width % 8 == 0: @@ -914,7 +914,7 @@ def parse_generic(lineno, parent_pat, name, toks): # We should have filled in all of the bits of the instruction. elif not (is_format and width == 0) and width != insnwidth: - error(lineno, 'definition has {0} bits'.format(width)) + error(lineno, f'definition has {width} bits') # Do not check for fields overlapping fields; one valid usage # is to be able to duplicate fields via import. @@ -932,8 +932,7 @@ def parse_generic(lineno, parent_pat, name, toks): if arg: for f in flds.keys(): if f not in arg.fields: - error(lineno, 'field {0} not in argument set {1}' - .format(f, arg.name)) + error(lineno, f'field {f} not in argument set {arg.name}') else: arg = infer_argument_set(flds) if name in formats: @@ -960,13 +959,12 @@ def parse_generic(lineno, parent_pat, name, toks): arg = fmt.base for f in flds.keys(): if f not in arg.fields: - error(lineno, 'field {0} not in argument set {1}' - .format(f, arg.name)) + error(lineno, f'field {f} not in argument set {arg.name}') if f in fmt.fields.keys(): - error(lineno, 'field {0} set by format and pattern'.format(f)) + error(lineno, f'field {f} set by format and pattern') for f in arg.fields: if f not in flds.keys() and f not in fmt.fields.keys(): - error(lineno, 'field {0} not initialized'.format(f)) + error(lineno, f'field {f} not initialized') pat = Pattern(name, lineno, fmt, fixedbits, fixedmask, undefmask, fieldmask, flds, width) parent_pat.pats.append(pat) @@ -1097,7 +1095,7 @@ def parse_file(f, parent_pat): elif re.fullmatch(re_pat_ident, name): parse_generic(start_lineno, parent_pat, name, toks) else: - error(lineno, 'invalid token "{0}"'.format(name)) + error(lineno, f'invalid token "{name}"') toks = [] if nesting != 0: @@ -1131,9 +1129,8 @@ def output_code(self, i, extracted, outerbits, outermask): # If we need to load more bytes to test, do so now. if extracted < self.width: - output(ind, 'insn = ', decode_function, - '_load_bytes(ctx, insn, {0}, {1});\n' - .format(extracted // 8, self.width // 8)); + output(ind, f'insn = {decode_function}_load_bytes', + f'(ctx, insn, {extracted // 8}, {self.width // 8});\n') extracted = self.width # Attempt to aid the compiler in producing compact switch statements. @@ -1184,9 +1181,8 @@ def output_code(self, i, extracted, outerbits, outermask): # If we need to load more bytes, do so now. if extracted < self.width: - output(ind, 'insn = ', decode_function, - '_load_bytes(ctx, insn, {0}, {1});\n' - .format(extracted // 8, self.width // 8)); + output(ind, f'insn = {decode_function}_load_bytes', + f'(ctx, insn, {extracted // 8}, {self.width // 8});\n') extracted = self.width output(ind, 'return insn;\n') # end SizeLeaf @@ -1220,7 +1216,7 @@ def build_size_tree(pats, width, outerbits, outermask): for p in pats: pnames.append(p.name + ':' + p.file + ':' + str(p.lineno)) error_with_file(pats[0].file, pats[0].lineno, - 'overlapping patterns size {0}:'.format(width), pnames) + f'overlapping patterns size {width}:', pnames) bins = {} for i in pats: From patchwork Fri Apr 30 01:15:16 2021 Content-Type: text/plain; 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This will be used to implement the new 64-bit Power ISA 3.1 instructions. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Luis Pires Message-Id: [rth: Drop the change to the field type; use bitop_width instead of separate variables for extract/deposit; use "ull" for 64-bit constants.] Signed-off-by: Richard Henderson --- scripts/decodetree.py | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/scripts/decodetree.py b/scripts/decodetree.py index d5da101167..f85da45ee3 100644 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -27,6 +27,7 @@ import getopt insnwidth = 32 +bitop_width = 32 insnmask = 0xffffffff variablewidth = False fields = {} @@ -112,7 +113,9 @@ def whexC(val): """Return a hex string for val padded for insnwidth, and with the proper suffix for a C constant.""" suffix = '' - if val >= 0x80000000: + if val >= 0x100000000: + suffix = 'ull' + elif val >= 0x80000000: suffix = 'u' return whex(val) + suffix @@ -199,11 +202,9 @@ def __str__(self): return str(self.pos) + ':' + s + str(self.len) def str_extract(self): - if self.sign: - extr = 'sextract32' - else: - extr = 'extract32' - return f'{extr}(insn, {self.pos}, {self.len})' + global bitop_width + s = 's' if self.sign else '' + return f'{s}extract{bitop_width}(insn, {self.pos}, {self.len})' def __eq__(self, other): return self.sign == other.sign and self.mask == other.mask @@ -224,6 +225,7 @@ def __str__(self): return str(self.subs) def str_extract(self): + global bitop_width ret = '0' pos = 0 for f in reversed(self.subs): @@ -231,7 +233,7 @@ def str_extract(self): if pos == 0: ret = ext else: - ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})' + ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - pos}, {ext})' pos += f.len return ret @@ -1270,6 +1272,7 @@ def main(): global insntype global insnmask global decode_function + global bitop_width global variablewidth global anyextern @@ -1299,6 +1302,10 @@ def main(): if insnwidth == 16: insntype = 'uint16_t' insnmask = 0xffff + elif insnwidth == 64: + insntype = 'uint64_t' + insnmask = 0xffffffffffffffff + bitop_width = 64 elif insnwidth != 32: error(0, 'cannot handle insns of width', insnwidth) else: From patchwork Fri Apr 30 01:15:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429726 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2104000jao; Thu, 29 Apr 2021 18:19:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx3bWHXMu/cBNbBdRxdlZe3m7NTbxu/zCBFWqHxgTsOt6EoyWZpJfc7Cdn+IXYyEyj4zBip X-Received: by 2002:a05:6638:3048:: with SMTP id u8mr2490549jak.91.1619745596555; Thu, 29 Apr 2021 18:19:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619745596; cv=none; d=google.com; s=arc-20160816; b=BQQLduDxLLGAvm29cyFFRf9VQyt6TMlMOk9KrqY3hNkFrpu1VQJnjPTikfYMkgZ4Et r5g+E816Ak0qvJAek3PlYJKRpB7cpfmoxcNtZyIwRUWrSy7tj6VUWqEwhqmKEeznR8wK npGuNj8HQbydk9OZh+URgFKD8xzTXv8bw8dw/5/CgW/dJ7JaeB7R/472kSJz6mQ2D1yi GdJ2emA+VaGnyDOsCrdT6V0iAq9NqyD+tWmxZls9dhJzcPKYzF3Ufz0iWd0BUJaFGQi6 5bZB0hztlYT7vwzbvQWA/vPsKKXilPTVocqGrruwqxF8ScEEWKAEVbVx78BCLu3O5ieN eX8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZTuVGlYcdxM3KgVRg58NcnxnAH+jbo2FXAOFg2CqtP8=; b=EroPHzjaokhcJR8yXqpPiVmp1h9iFH4CaftSCE5IIZrv/rkZYG/TJERZJ2a/rV5XxF BhjU7wvitYp6MjaeTjWVtCseBxzg4UphqCTOGF4xKv4bjjSGH0xQi2ayDsW4WZMmzAlX qXM8ijUtW4fRLs6uG5gEpflT88NEMw1EkT6IyGBNEmNDErOFDJ+pQT+1QIQHzLa71wuF F35jHQdOY4ISmClQKKpqwQO8SLYaAt/WwzWNxlq741W1aUFx3MsPPHq3wBMUVL7pX0Eq jNJ+FQW6xvuOuHIf+95GbEPtug6ECFBuiNFRa7p4ZX95KP/94d5xdDGJ3GrStapX7ba2 r6zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="uc9wU/hf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- docs/devel/decodetree.rst | 11 ++++--- tests/decode/succ_argset_type1.decode | 1 + scripts/decodetree.py | 45 +++++++++++++++++---------- 3 files changed, 36 insertions(+), 21 deletions(-) create mode 100644 tests/decode/succ_argset_type1.decode -- 2.25.1 Reviewed-by: Luis Pires diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst index 74f66bf46e..49ea50c2a7 100644 --- a/docs/devel/decodetree.rst +++ b/docs/devel/decodetree.rst @@ -40,9 +40,6 @@ and returns an integral value extracted from there. A field with no ``unnamed_fields`` and no ``!function`` is in error. -FIXME: the fields of the structure into which this result will be stored -is restricted to ``int``. Which means that we cannot expand 64-bit items. - Field examples: +---------------------------+---------------------------------------------+ @@ -66,9 +63,14 @@ Argument Sets Syntax:: args_def := '&' identifier ( args_elt )+ ( !extern )? - args_elt := identifier + args_elt := identifier (':' identifier)? Each *args_elt* defines an argument within the argument set. +If the form of the *args_elt* contains a colon, the first +identifier is the argument name and the second identifier is +the argument type. If the colon is missing, the argument +type will be ``int``. + Each argument set will be rendered as a C structure "arg_$name" with each of the fields being one of the member arguments. @@ -86,6 +88,7 @@ Argument set examples:: ®3 ra rb rc &loadstore reg base offset + &longldst reg base offset:int64_t Formats diff --git a/tests/decode/succ_argset_type1.decode b/tests/decode/succ_argset_type1.decode new file mode 100644 index 0000000000..ed946b420d --- /dev/null +++ b/tests/decode/succ_argset_type1.decode @@ -0,0 +1 @@ +&asdf b:bool c:uint64_t a diff --git a/scripts/decodetree.py b/scripts/decodetree.py index f85da45ee3..a03dc6b5e3 100644 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -165,11 +165,15 @@ def is_contiguous(bits): return -1 -def eq_fields_for_args(flds_a, flds_b): - if len(flds_a) != len(flds_b): +def eq_fields_for_args(flds_a, arg): + if len(flds_a) != len(arg.fields): return False + # Only allow inference on default types + for t in arg.types: + if t != 'int': + return False for k, a in flds_a.items(): - if k not in flds_b: + if k not in arg.fields: return False return True @@ -313,10 +317,11 @@ def __ne__(self, other): class Arguments: """Class representing the extracted fields of a format""" - def __init__(self, nm, flds, extern): + def __init__(self, nm, flds, types, extern): self.name = nm self.extern = extern - self.fields = sorted(flds) + self.fields = flds + self.types = types def __str__(self): return self.name + ' ' + str(self.fields) @@ -327,8 +332,8 @@ def struct_name(self): def output_def(self): if not self.extern: output('typedef struct {\n') - for n in self.fields: - output(' int ', n, ';\n') + for (n, t) in zip(self.fields, self.types): + output(f' {t} {n};\n') output('} ', self.struct_name(), ';\n\n') # end Arguments @@ -719,21 +724,27 @@ def parse_arguments(lineno, name, toks): global anyextern flds = [] + types = [] extern = False - for t in toks: - if re.fullmatch('!extern', t): + for n in toks: + if re.fullmatch('!extern', n): extern = True anyextern = True continue - if not re.fullmatch(re_C_ident, t): - error(lineno, f'invalid argument set token "{t}"') - if t in flds: - error(lineno, f'duplicate argument "{t}"') - flds.append(t) + if re.fullmatch(re_C_ident + ':' + re_C_ident, n): + (n, t) = n.split(':') + elif re.fullmatch(re_C_ident, n): + t = 'int' + else: + error(lineno, f'invalid argument set token "{n}"') + if n in flds: + error(lineno, f'duplicate argument "{n}"') + flds.append(n) + types.append(t) if name in arguments: error(lineno, 'duplicate argument set', name) - arguments[name] = Arguments(name, flds, extern) + arguments[name] = Arguments(name, flds, types, extern) # end parse_arguments @@ -760,11 +771,11 @@ def infer_argument_set(flds): global decode_function for arg in arguments.values(): - if eq_fields_for_args(flds, arg.fields): + if eq_fields_for_args(flds, arg): return arg name = decode_function + str(len(arguments)) - arg = Arguments(name, flds.keys(), False) + arg = Arguments(name, flds.keys(), ['int'] * len(flds), False) arguments[name] = arg return arg From patchwork Fri Apr 30 01:15:18 2021 Content-Type: text/plain; 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envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/ppc/translate.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Bruno Larsen (billionai) Reviewed-by: Luis Pires diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0984ce637b..ee25badba2 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -154,6 +154,7 @@ void ppc_translate_init(void) /* internal defines */ struct DisasContext { DisasContextBase base; + target_ulong cia; /* current instruction address */ uint32_t opcode; uint32_t exception; /* Routine used to access memory */ @@ -254,7 +255,7 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) * faulting instruction */ if (ctx->exception == POWERPC_EXCP_NONE) { - gen_update_nip(ctx, ctx->base.pc_next - 4); + gen_update_nip(ctx, ctx->cia); } t0 = tcg_const_i32(excp); t1 = tcg_const_i32(error); @@ -273,7 +274,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp) * faulting instruction */ if (ctx->exception == POWERPC_EXCP_NONE) { - gen_update_nip(ctx, ctx->base.pc_next - 4); + gen_update_nip(ctx, ctx->cia); } t0 = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); @@ -3113,7 +3114,7 @@ static void gen_eieio(DisasContext *ctx) */ if (!(ctx->insns_flags2 & PPC2_ISA300)) { qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" - TARGET_FMT_lx "\n", ctx->base.pc_next - 4); + TARGET_FMT_lx "\n", ctx->cia); } else { bar = TCG_MO_ST_LD; } @@ -3782,14 +3783,14 @@ static void gen_b(DisasContext *ctx) li = LI(ctx->opcode); li = (li ^ 0x02000000) - 0x02000000; if (likely(AA(ctx->opcode) == 0)) { - target = ctx->base.pc_next + li - 4; + target = ctx->cia + li; } else { target = li; } if (LK(ctx->opcode)) { gen_setlr(ctx, ctx->base.pc_next); } - gen_update_cfar(ctx, ctx->base.pc_next - 4); + gen_update_cfar(ctx, ctx->cia); gen_goto_tb(ctx, 0, target); } @@ -3888,11 +3889,11 @@ static void gen_bcond(DisasContext *ctx, int type) } tcg_temp_free_i32(temp); } - gen_update_cfar(ctx, ctx->base.pc_next - 4); + gen_update_cfar(ctx, ctx->cia); if (type == BCOND_IM) { target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); if (likely(AA(ctx->opcode) == 0)) { - gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); + gen_goto_tb(ctx, 0, ctx->cia + li); } else { gen_goto_tb(ctx, 0, li); } @@ -4008,7 +4009,7 @@ static void gen_rfi(DisasContext *ctx) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - gen_update_cfar(ctx, ctx->base.pc_next - 4); + gen_update_cfar(ctx, ctx->cia); gen_helper_rfi(cpu_env); gen_sync_exception(ctx); #endif @@ -4025,7 +4026,7 @@ static void gen_rfid(DisasContext *ctx) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - gen_update_cfar(ctx, ctx->base.pc_next - 4); + gen_update_cfar(ctx, ctx->cia); gen_helper_rfid(cpu_env); gen_sync_exception(ctx); #endif @@ -4042,7 +4043,7 @@ static void gen_rfscv(DisasContext *ctx) if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } - gen_update_cfar(ctx, ctx->base.pc_next - 4); + gen_update_cfar(ctx, ctx->cia); gen_helper_rfscv(cpu_env); gen_sync_exception(ctx); #endif @@ -4338,7 +4339,7 @@ static inline void gen_op_mfspr(DisasContext *ctx) if (sprn != SPR_PVR) { qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, - ctx->base.pc_next - 4); + ctx->cia); } gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); } @@ -4352,7 +4353,7 @@ static inline void gen_op_mfspr(DisasContext *ctx) /* Not defined */ qemu_log_mask(LOG_GUEST_ERROR, "Trying to read invalid spr %d (0x%03x) at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); /* * The behaviour depends on MSR:PR and SPR# bit 0x10, it can @@ -4516,7 +4517,7 @@ static void gen_mtspr(DisasContext *ctx) /* Privilege exception */ qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, - ctx->base.pc_next - 4); + ctx->cia); gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); } } else { @@ -4530,7 +4531,7 @@ static void gen_mtspr(DisasContext *ctx) /* Not defined */ qemu_log_mask(LOG_GUEST_ERROR, "Trying to write invalid spr %d (0x%03x) at " - TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4); + TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); /* @@ -8002,6 +8003,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); + ctx->cia = ctx->base.pc_next; ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); @@ -8031,7 +8033,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) TARGET_FMT_lx " %d\n", opc1(ctx->opcode), opc2(ctx->opcode), opc3(ctx->opcode), opc4(ctx->opcode), - ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); + ctx->opcode, ctx->cia, (int)msr_ir); } else { uint32_t inval; @@ -8048,7 +8050,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) TARGET_FMT_lx "\n", ctx->opcode & inval, opc1(ctx->opcode), opc2(ctx->opcode), opc3(ctx->opcode), opc4(ctx->opcode), - ctx->opcode, ctx->base.pc_next - 4); + ctx->opcode, ctx->cia); gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); ctx->base.is_jmp = DISAS_NORETURN; return; From patchwork Fri Apr 30 01:15:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429731 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2107397jao; Thu, 29 Apr 2021 18:24:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeNDgMkJ0sSjhRxHDfCOnilmL9BFOoRkWZXKWiNytAgzaN0mErLBygZ0t8BqZVd4yrgo4M X-Received: by 2002:a5e:940f:: with SMTP id q15mr1684971ioj.197.1619745899531; Thu, 29 Apr 2021 18:24:59 -0700 (PDT) ARC-Seal: i=1; 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envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/ppc/translate.c | 115 +++++++++++++++++++++++------------------ 1 file changed, 64 insertions(+), 51 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ee25badba2..ebe5afe7ae 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7876,6 +7876,62 @@ void ppc_cpu_dump_statistics(CPUState *cs, int flags) #endif } +static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) +{ + opc_handler_t **table, *handler; + uint32_t inval; + + ctx->opcode = insn; + + LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", + insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), + ctx->le_mode ? "little" : "big"); + + table = cpu->opcodes; + handler = table[opc1(insn)]; + if (is_indirect_opcode(handler)) { + table = ind_table(handler); + handler = table[opc2(insn)]; + if (is_indirect_opcode(handler)) { + table = ind_table(handler); + handler = table[opc3(insn)]; + if (is_indirect_opcode(handler)) { + table = ind_table(handler); + handler = table[opc4(insn)]; + } + } + } + + /* Is opcode *REALLY* valid ? */ + if (unlikely(handler->handler == &gen_invalid)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " + "%02x - %02x - %02x - %02x (%08x) " + TARGET_FMT_lx "\n", + opc1(insn), opc2(insn), opc3(insn), opc4(insn), + insn, ctx->cia); + return false; + } + + if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) + && Rc(insn))) { + inval = handler->inval2; + } else { + inval = handler->inval1; + } + + if (unlikely((insn & inval) != 0)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " + "%02x - %02x - %02x - %02x (%08x) " + TARGET_FMT_lx "\n", insn & inval, + opc1(insn), opc2(insn), opc3(insn), opc4(insn), + insn, ctx->cia); + return false; + } + + handler->handler(ctx); + return true; +} + static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); @@ -7997,66 +8053,23 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = cs->env_ptr; - opc_handler_t **table, *handler; + uint32_t insn; + bool ok; LOG_DISAS("----------------\n"); LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); ctx->cia = ctx->base.pc_next; - ctx->opcode = translator_ldl_swap(env, ctx->base.pc_next, - need_byteswap(ctx)); - - LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", - ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), - opc3(ctx->opcode), opc4(ctx->opcode), - ctx->le_mode ? "little" : "big"); + insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); ctx->base.pc_next += 4; - table = cpu->opcodes; - handler = table[opc1(ctx->opcode)]; - if (is_indirect_opcode(handler)) { - table = ind_table(handler); - handler = table[opc2(ctx->opcode)]; - if (is_indirect_opcode(handler)) { - table = ind_table(handler); - handler = table[opc3(ctx->opcode)]; - if (is_indirect_opcode(handler)) { - table = ind_table(handler); - handler = table[opc4(ctx->opcode)]; - } - } - } - /* Is opcode *REALLY* valid ? */ - if (unlikely(handler->handler == &gen_invalid)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " - "%02x - %02x - %02x - %02x (%08x) " - TARGET_FMT_lx " %d\n", - opc1(ctx->opcode), opc2(ctx->opcode), - opc3(ctx->opcode), opc4(ctx->opcode), - ctx->opcode, ctx->cia, (int)msr_ir); - } else { - uint32_t inval; - if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) - && Rc(ctx->opcode))) { - inval = handler->inval2; - } else { - inval = handler->inval1; - } - - if (unlikely((ctx->opcode & inval) != 0)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " - "%02x - %02x - %02x - %02x (%08x) " - TARGET_FMT_lx "\n", ctx->opcode & inval, - opc1(ctx->opcode), opc2(ctx->opcode), - opc3(ctx->opcode), opc4(ctx->opcode), - ctx->opcode, ctx->cia); - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - ctx->base.is_jmp = DISAS_NORETURN; - return; - } + ok = decode_legacy(cpu, ctx, insn); + if (!ok) { + gen_invalid(ctx); + ctx->base.is_jmp = DISAS_NORETURN; } - (*(handler->handler))(ctx); + #if defined(DO_PPC_STATISTICS) handler->count++; #endif From patchwork Fri Apr 30 01:15:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429735 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2109335jao; Thu, 29 Apr 2021 18:28:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTubMkkczin33nai4fy4eRXU/9HLzFmLGd9boP6wZiRzaouXjXDGBQs+hPt9XsOtdB0Ka9 X-Received: by 2002:aca:5c44:: with SMTP id q65mr2105606oib.12.1619746103892; Thu, 29 Apr 2021 18:28:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746103; cv=none; d=google.com; s=arc-20160816; b=FF8XrOda1KWu4CKTbD8vVaP1trmIg4Kdd8LFTACfOzsun+AZoNAEFcUeNXxj74wR5b nGMRjGpo6LazpXukChSKU7Y2SkmXoI9cP6zB7z65MGkeaQVrijMaC1336fxnpa57oQfz zHY7LYOZ3C6bUiKumOe3X+/YWjD72dGgqq5KDA0f179w3OrcOE+XR2qcLZQ9aaOYZgYB 67R7sWn+//ci4NqmCmj4UO1yBVDpJWRWPEMKajajPdVenv8VHMNJ4ciq+Qh2OL23iIwC c62551089DbXbdHMP8ScPoHYG8fMpS46UDuqHuebXD3uTZ0NaYpzp+1xWjlvOYuY2LlL aQxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jt6WDlTVZ95m5Svb67/E+vHr02oKATGFQUbtmFvmoVU=; b=rwZNkBOMc0ljy5EBet3CF5gHI0x9kV+2Z1MQ7Sf+MF0uwT7v4x07cE5/7YbIGUFzo5 8sbR8MOEtq4SDYBoiqgszd2KDkRQZASs75zR1SrD6oaKaEPPdS71n5Zfz97VgyWAlBds Uk3At1unoUtKyjuRK2PZBPGhqzI6/suLfgN2+p6ZlEB09bGppv5JdB+m/kFKJczJKr62 lAdl2F75XEsdTWFz4W3Svr340q358FgR4ErxcMMtTp6gQm/2AzbPrLQLzLGjgWGsWCzV lGOLBbl7V4nYmmtLQqnL5wGyrWfNcvzJCmT5Zab+kjog9bdnUaB5Vp/gWRqc4Ct2NDzZ R6ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NOVOgnWW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- v3: Retain an exit from translator loop for ctx->exception. Do not emit code for single-step or ppc_tr_tb_stop for NORETURN. --- target/ppc/translate.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/target/ppc/translate.c b/target/ppc/translate.c index ebe5afe7ae..3607cc12f3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -262,7 +262,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) gen_helper_raise_exception_err(cpu_env, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - ctx->exception = (excp); + ctx->exception = excp; + ctx->base.is_jmp = DISAS_NORETURN; } static void gen_exception(DisasContext *ctx, uint32_t excp) @@ -279,7 +280,8 @@ static void gen_exception(DisasContext *ctx, uint32_t excp) t0 = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); tcg_temp_free_i32(t0); - ctx->exception = (excp); + ctx->exception = excp; + ctx->base.is_jmp = DISAS_NORETURN; } static void gen_exception_nip(DisasContext *ctx, uint32_t excp, @@ -291,7 +293,8 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp, t0 = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); tcg_temp_free_i32(t0); - ctx->exception = (excp); + ctx->exception = excp; + ctx->base.is_jmp = DISAS_NORETURN; } /* @@ -337,6 +340,7 @@ static void gen_debug_exception(DisasContext *ctx) t0 = tcg_const_i32(EXCP_DEBUG); gen_helper_raise_exception(cpu_env, t0); tcg_temp_free_i32(t0); + ctx->base.is_jmp = DISAS_NORETURN; } static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) @@ -8037,7 +8041,6 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, DisasContext *ctx = container_of(dcbase, DisasContext, base); gen_debug_exception(ctx); - dcbase->is_jmp = DISAS_NORETURN; /* * The address covered by the breakpoint must be included in * [tb->pc, tb->pc + tb->size) in order to for it to be properly @@ -8067,18 +8070,19 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ok = decode_legacy(cpu, ctx, insn); if (!ok) { gen_invalid(ctx); - ctx->base.is_jmp = DISAS_NORETURN; } #if defined(DO_PPC_STATISTICS) handler->count++; #endif + /* Check trace mode exceptions */ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && ctx->exception != POWERPC_SYSCALL && ctx->exception != POWERPC_EXCP_TRAP && - ctx->exception != POWERPC_EXCP_BRANCH)) { + ctx->exception != POWERPC_EXCP_BRANCH && + ctx->base.is_jmp != DISAS_NORETURN)) { uint32_t excp = gen_prep_dbgex(ctx); gen_exception_nip(ctx, excp, ctx->base.pc_next); } @@ -8089,14 +8093,20 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); } - ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? - DISAS_NEXT : DISAS_NORETURN; + if (ctx->base.is_jmp == DISAS_NEXT + && ctx->exception != POWERPC_EXCP_NONE) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } } static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + if (ctx->base.is_jmp == DISAS_NORETURN) { + return; + } + if (ctx->exception == POWERPC_EXCP_NONE) { gen_goto_tb(ctx, 0, ctx->base.pc_next); } else if (ctx->exception != POWERPC_EXCP_BRANCH) { From patchwork Fri Apr 30 01:15:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429730 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2106887jao; Thu, 29 Apr 2021 18:24:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTpAqoyaU6AVepWUk95AqshxNBc7DyGb7V09kS4kgCAXR7ssKvAicCAwOPndkatsrRxbzM X-Received: by 2002:a6b:d10c:: with SMTP id l12mr1719374iob.179.1619745842919; Thu, 29 Apr 2021 18:24:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619745842; cv=none; d=google.com; s=arc-20160816; b=hvZhTcUxRvdnBAj4Sf3NUaHLaTWP5iim+VVK4K7Syefqn19vw+FSCqHQUKViXwDiru FGxW0+VrPo+E4RB1yiKw4P3zyL2NKz0CaeLacvGZDAcHkHfVvvd0yTUxR8VtxzDS5k1W LoxvS/tldOMw5306Dz4rwamJhU09A828FgGfJO3OQmiUpn7h6lbEph6iK07Fkj3lZ+2S 2JUXBEozjQurNMnyDs9iWMxTkQLQZPwp/a1CoZoA6PiIE0n9eVIGPfzqt6UD2TQKo0a1 O2wBnleLehDiv5952843VRRiVKP2LrQuISnmdHH37vBB1NFOfShyN+ey4Wegymqaq+ry 4qoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4VcD0HXsANNijrzBkXm424aZmwDpF4g6Adk9HJA2tSo=; b=YfQcKmnFYy6tIzP80ZeNQUac/RGf6teXtF2wj9YCM/ubR9f9/c5ONpQrB/KDtYMXjN aMQAHoF+3rjL389RyCSVHZThf+43iQJOOLbb8i7YKIij5HZYy1vF91DnGba/puX7VKAx Mf7V9igGC7jX1TJvOfR9MuDAHSQzbwlU7D3sGe906DAN9/rxRuCYeOMtjy/LDyPDjLLY dCH/M1mEl6WkPD1bm73s5zWlLyYgBvQuK3n5vUCNdMXAjpHTjwu+rfIxXROc4vkAfbem j0FSEPtBfYhLwDszlKJcxo6FMqifM43AyUi8Hzmq+3S9EZ3bAqfVW3ErmSnNjrFWMjUr 1Tvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ctn207bS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j4si426883jak.82.2021.04.29.18.24.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:24:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ctn207bS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51262 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcHsw-0002PM-AZ for patch@linaro.org; Thu, 29 Apr 2021 21:24:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlF-0002s4-Um for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:05 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:39702) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl2-0007WF-3N for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:05 -0400 Received: by mail-pl1-x631.google.com with SMTP id s15so7323302plg.6 for ; Thu, 29 Apr 2021 18:15:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4VcD0HXsANNijrzBkXm424aZmwDpF4g6Adk9HJA2tSo=; b=ctn207bSfrzmA32Jl+1chgNcjdlBWFq+WjDG6+LXzs8pEpYodfQvRlZUajmwqFitKn tBb3lx3jpzv4G59wb7Cmmo/KZ507CIHeSfTtIiRNROMv9ZRnUnAY01kKggQOF4SMzAK0 pcI7B+m87wnC3nrPltrLaYZL1m8+/PyBLCeYi3FuhiDCdalJYw2kRbX+rEaADmuVqIk5 3TMSA9C2Qnl3GwxFP1/ug4E4C9GmkzHmYp0ZueYt+ZM5vNlttXeBCXSpoDtX/9c8XHIj JwZx+fdGs6GtXxhhLMkT5MjOlSHub6Ya2KDpUwe7V2uqA8n1QnjvgQGb244Z6o2eBrGE sNjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4VcD0HXsANNijrzBkXm424aZmwDpF4g6Adk9HJA2tSo=; b=PmHPDGQfYFst1ISLw7HUP7SVTVxt0lYRwmLxGXlDSt+4yNvPC2nOD9F7qDjs4vCxED iQ8g8Jp7uscH1QUW2eql7404x3/BvGyewDwL1u1hqAe3GDALbgJBjLlKH4tFXvmEJDoS +pPzafo1ua68MwR8+7aKti39zmWVGxyh4ivtiDGjgFXE64/XKRxpwxeGKTGc4jb3ocOi rDz0lQjVGCcsuvSiPHA2tJaykto41XgZfx3XfXgtuC2zQi8uos+sTnL19RKrus6Y3zeg TOGmEWtQmCFw83o73U90FROWYd4QJ7hsMBGY4ATFZ9qoB9VQZkjZHB8f4jHNs23ZOpIr hZDQ== X-Gm-Message-State: AOAM531tCmp21fZCjSOPSQmNyBFNtD/+eD5KgO58foCxcSbjUEfu25+a drUk9gP5aT+TVR5VG0g1Iutp2cnNHSJijw== X-Received: by 2002:a17:90b:958:: with SMTP id dw24mr12001633pjb.185.1619745350172; Thu, 29 Apr 2021 18:15:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/30] target/ppc: Remove special case for POWERPC_SYSCALL Date: Thu, 29 Apr 2021 18:15:21 -0700 Message-Id: <20210430011543.1017113-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since POWERPC_SYSCALL is raised by gen_exception_err, we will have also set DISAS_NORETURN. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 1 - 1 file changed, 1 deletion(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3607cc12f3..b26b6964a7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8079,7 +8079,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Check trace mode exceptions */ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && - ctx->exception != POWERPC_SYSCALL && ctx->exception != POWERPC_EXCP_TRAP && ctx->exception != POWERPC_EXCP_BRANCH && ctx->base.is_jmp != DISAS_NORETURN)) { From patchwork Fri Apr 30 01:15:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429734 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2109151jao; Thu, 29 Apr 2021 18:28:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxMRF3raDLA6ka2hzbMs9Bt2tHTYnxMyzKD/NQ3vWrvknbbS1T7lZ6CLuX6htN1ywmmot8+ X-Received: by 2002:a05:6830:119:: with SMTP id i25mr1704754otp.39.1619746085844; Thu, 29 Apr 2021 18:28:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746085; cv=none; d=google.com; s=arc-20160816; b=z1pE6TqYLNMsBLVy7X3CvmVUtBHu2ldvsDPd/dk1NiBT67T1KwY5jbpjmT0fqZbdIM aCziC7xm9Fv7Uj9RIYOGLtvukfLASqzgV9HYH/iw8LTGyYrKFajeuH1x2Y5zZ1Ik8quH gC6dReSEW+ZSGq7kVElkiuBHCk+bkkonW1hpYT21bBFYtdoj8IxxG9Kfy+vVAq6o7YKa wmhAt7NhT86bWvPKqzEIq/7E6zhMLEagypzKds9GGCnsSEjPHu6g6aC4oACPbLDPhLyy i5JjrRjt3fYgF+7+SMIb1Jy6J59sVQ2BFkwQIhIlLa27kKR1hJvlpBZnykUxmDUQ6SSj NsWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YW6DwxqU5VNxXS27VotK2HOgdC1z8tUYOO4XDsjF6GM=; b=rvsI52URT1Lz9dOEv3p1DGyK3CKREoWmUqi/CYQgilknlU+DbYncbRdltW8MW1HqrQ cZy3k6tlJSxuWrteDiUfUZ3breKqf/Lm7vlPwqoEblpbL1v3Qk3DTiRA5SY3yTtTOOML SjuLT0dy3Vg9pJkgQ/5swAlIFhhK75jB4aSZ8DDHBZzMByxm98bAxgMaMbJpfFMnlpvY Tn8yX9sA9hQS8WwibJcKIBp7bBNxaqrBicZDlM5eOzP/87WMo4Gl7c4oPB2L6iBA09B2 b1Gs7SPF+IHcDDIt47jU44GdvBCaKviazNP6v1HzImOHGA5+WHOjsjb3i/ETNTeuwY0G DhuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=m+EFKGXt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c2si1478765oto.237.2021.04.29.18.28.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:28:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=m+EFKGXt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcHwr-0006Rz-99 for patch@linaro.org; Thu, 29 Apr 2021 21:28:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlI-0002yk-WE for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:09 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:42888) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl5-0007Wq-7I for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:08 -0400 Received: by mail-pf1-x42d.google.com with SMTP id n6so1574692pfv.9 for ; Thu, 29 Apr 2021 18:15:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YW6DwxqU5VNxXS27VotK2HOgdC1z8tUYOO4XDsjF6GM=; b=m+EFKGXtdfSaQsnwR1ioFH7mavQiNB3ojoFI5cTc78qG4g5uw/rHnp1YFBVCo7syLp hL+ITn2DsMEpnQFfrtOpWNyI8fDdN08COzH6lYHiwLA7BONNj9d3r+JXXW9Wnn/nE+z2 78D5W8KmljGBJEyk+7nTYlE7YjMQBzqJUGbTe0MFs811zQx8h4MXY5nSR4nIoROjV5tQ MfTgEgwOHjWsYHjtPb+Dg/NciglNoUCT2JVZ+YxzW8uuHtIFskJ0EinRmZtEJXdiL/Rd lSXk1gCGQGLYm2cupSIeWaICdsuhBlxRQ7+ZfB4Xqcefsk8/a65zMaBCCaoJOWB1RIYz GbVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YW6DwxqU5VNxXS27VotK2HOgdC1z8tUYOO4XDsjF6GM=; b=Bz/YrOMIHl6duMLPb+i6VjUKj+Z2ylzZB7VFujGKBtZU4/WJ9j6LaUt8CPBCNMk6t5 b2GpA70M4eKnkEasyIOhTkAYHPW65GPjRLcSyDSQFTF/0EH8BP8Y5iQPGpnEtHJrQuQM wMKPpkblnV7WdPYEGRtJMj2IaAgC15wnV1cKz5x04ayCLxjgGyiV9M6h6wn8E9XfapSO 9wy4+T+wCw6zG/jojlXaBqm8hVP8iD33LjWYqhfLVUs2rPogXBmNlKEHqqniHCV04HhM /0hG22y1JZ+8RVrf/AQf2hFFqxYIUp040CUhfNsb9d+dUHiDeRl5/VoDzn8ok5SmnVXk leLg== X-Gm-Message-State: AOAM532nT7Si3AaxTS0zxXDcBL1fizEAwxfY94u/Mv9+XhiVFBmoUIy8 xqvYvgr8OER6bBy8cPcRHIM61TUwo32vrw== X-Received: by 2002:a65:60d8:: with SMTP id r24mr2386645pgv.226.1619745350779; Thu, 29 Apr 2021 18:15:50 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/30] target/ppc: Remove special case for POWERPC_EXCP_TRAP Date: Thu, 29 Apr 2021 18:15:22 -0700 Message-Id: <20210430011543.1017113-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SUBJ_WIPE_DEBT=1.004 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since POWERPC_EXCP_TRAP is raised by gen_exception_err, we will have also set DISAS_NORETURN. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 1 - 1 file changed, 1 deletion(-) -- 2.25.1 Reviewed-by: Luis Pires diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b26b6964a7..5efa4d6566 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8079,7 +8079,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Check trace mode exceptions */ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && - ctx->exception != POWERPC_EXCP_TRAP && ctx->exception != POWERPC_EXCP_BRANCH && ctx->base.is_jmp != DISAS_NORETURN)) { uint32_t excp = gen_prep_dbgex(ctx); From patchwork Fri Apr 30 01:15:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429729 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2105101jao; Thu, 29 Apr 2021 18:21:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw18Nn6h/emn9v5hPAatzXTXkLfMkn4UzDaAZ8hQ+llo9/e7wrSopEg503RTCCc+AJUmyGl X-Received: by 2002:a92:c048:: with SMTP id o8mr2129141ilf.147.1619745684080; Thu, 29 Apr 2021 18:21:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619745684; cv=none; d=google.com; s=arc-20160816; b=NCmRwo4C3ct8S+BUlxj3HBR/qH0bk2H3B4eldZLBPn5xuYX5DaEpi51aMsLvRzn2LD aCEJrDHrwf/gb0I1A35B84jUYBImVc2ahcGe2R4nqiSLk4kvyfX3PWIGSALbYSM10rRx mXJtAf19topwjNGwyFCFGtArcARrEqaMpKRxhEkT4wrHizs+oF/eLhLo4AsUkYvxDOXL 8Srsopq8uCe+ELpmqN2VV5g2KpiJOaVLmzizxSuO8wryLDgmmyGmmZvUF7OnbpBohfgz joB5YqW2H8u+z72xlLgvCWl1ClhlJhcSWVl2CgxkJYdA3n5CSVt42r4A3LcQVcgC6dY+ TR5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TsKRE3i/n4/0bXPCvuEuwUe3xdoGP8klreSD2fnz1lk=; b=gv6MnFE+vr6JP0InoVXiHoeZDmPU2mrwwstOsIAggmrZX2ZT7glUqv680J/GTHhTfd /TsusR2x7kGgzWLHPQefX4gAQrTxaOiQEcY9fYIlDJ+7FK+lR68FswoQA+NhI8yN4G8x aFwgTrVlFIB8au6QYKCua+DUP/OJA2e5g5VCUfzYEwQVk7MoKNVzLUcxZ0IAzgHeRmdN trFWCac0GDyToSnroxP/KFgfjJpXss2IbE2Pz/H5trh0ZnzvHk82T64nzjSlRCBiI6R7 kLWv/LfzXa5Z2T0jMV6HTKwqGzdMuYrl7SkVQh4FHEft277SnkO1r7ggWJLiS6EquK5U v57g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="o6TyBAN/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g16si1572079iox.5.2021.04.29.18.21.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:21:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="o6TyBAN/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcHqN-0007mL-IM for patch@linaro.org; Thu, 29 Apr 2021 21:21:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlH-0002w1-Dl for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:07 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:42997) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl3-0007X1-Vi for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:06 -0400 Received: by mail-pj1-x1029.google.com with SMTP id j6-20020a17090adc86b02900cbfe6f2c96so890463pjv.1 for ; Thu, 29 Apr 2021 18:15:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TsKRE3i/n4/0bXPCvuEuwUe3xdoGP8klreSD2fnz1lk=; b=o6TyBAN/E3u/JOIDIxuaJDUBZSxd9EqQoPtO2LO0iFRp2gEOg18FY5GsKxtu+5aFeC Mu1ITWJHq9Xp9vfwO1/vCdrTECqGV7/Sqv6W9T3C1JBg/Ya9hG6+atsDdhgyNvRztdtx U5+RMzjENCu5PZc4AUXVnoinjB+OZlq8gfvXAAfic9LOOxV4R1XzNrAR337m1xUbyyiu Ql7xBN5tkMGKM1Jr9i2jE0XKj/xhxBiTehiGIlCDiXZe6kXKjqgBiZuFqSs5DPe0uTcN 6YYoSNoYEMiy6ELIBDNYOG6Su+7m+zxPVCM5DKQOm7M0ZATdo9nHnvYy8n7Ga/owIZZd qbIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TsKRE3i/n4/0bXPCvuEuwUe3xdoGP8klreSD2fnz1lk=; b=ETYBn9M5e9tBODz6//Fjib+zizNowYeOeg/EiJPGGOYCf0yqhB1Dj2putlHBsiycgw 6nfTk9UelSbWK54RKBge/siTzSlm6CSWt9TnF/lEIhQE16xRIDDuQL2l+pmgV0wZa0vL JUfPiEs13pjbJ6tJV431epkI1PSC3z8dzFm61neXg7HC4FA9HIOa2MbhF/FJt3JwwvVM xpJB+WROJFGrki1MzaBC7EUxvRhQW6qtjJJWp6ReI1iRz0n8r7VHr7Gbq0ZZzwE0FE+5 eMwSLKIXuxiZLfitEu4j/gy7Ku0ARV194R6ZeX50qwR5b3DRtiYHpGRIZesF6HEpeMmI KDuw== X-Gm-Message-State: AOAM5325TwSDvMQQ6hXlc3zpYhoVslPKtmwwj9EXHCYIt86GMBTWV1t2 WdHIr6pUwhtYdMUleIF5GcmUxv6iYXbAsw== X-Received: by 2002:a17:90a:9f44:: with SMTP id q4mr12274182pjv.233.1619745351368; Thu, 29 Apr 2021 18:15:51 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/30] target/ppc: Simplify gen_debug_exception Date: Thu, 29 Apr 2021 18:15:23 -0700 Message-Id: <20210430011543.1017113-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Two of the call sites that use gen_debug_exception have already updated NIP. Only ppc_tr_breakpoint_check requires the update. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5efa4d6566..b58e2ac8dc 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -327,19 +327,7 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx) static void gen_debug_exception(DisasContext *ctx) { - TCGv_i32 t0; - - /* - * These are all synchronous exceptions, we set the PC back to the - * faulting instruction - */ - if ((ctx->exception != POWERPC_EXCP_BRANCH) && - (ctx->exception != POWERPC_EXCP_SYNC)) { - gen_update_nip(ctx, ctx->base.pc_next); - } - t0 = tcg_const_i32(EXCP_DEBUG); - gen_helper_raise_exception(cpu_env, t0); - tcg_temp_free_i32(t0); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); ctx->base.is_jmp = DISAS_NORETURN; } @@ -8040,6 +8028,7 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, { DisasContext *ctx = container_of(dcbase, DisasContext, base); + gen_update_nip(ctx, ctx->base.pc_next); gen_debug_exception(ctx); /* * The address covered by the breakpoint must be included in From patchwork Fri Apr 30 01:15:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429727 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2104292jao; Thu, 29 Apr 2021 18:20:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzDAN7roSUCgoTuuoyoEU+0iwk62d9szWHwPtGrBl488uO3P/D7qT3uFVZlAugqOGnQQQ+ X-Received: by 2002:a02:b788:: with SMTP id f8mr2501816jam.113.1619745623194; Thu, 29 Apr 2021 18:20:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619745623; cv=none; d=google.com; s=arc-20160816; b=AYGr+NsSemS9x8H1RW71ceFUQ98hRng7EBB2BxkeBL67C5UO+LoOBUVxhlPIgY1x7x iKOahOYWDeds4ryOgeoeBdX/lIo2oC2SwsCKoR0rkr/qbKRd1mWBHsb3462aQ5cznaG1 6Ni/VuIx9XG0xc9X0kVHwZrVMUBs4jIcx0gLufcC2jwKa25JGCXaJz7oU4MLJLxbFap/ a5OKP8yxP+7Y17BuKb6BgMSUaEbDKvvl/m2NSSfQm3Uvy8NM2nOMVlLjN0JDyfQJxGV1 lLPgj/qY9AWlF8uxTYNKG1O1AGYd6viwtM9zI8wXTTm0uSXrzT0/Jcx/oYvWurGOfXLt U3HQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GtzxgNF32jBOW0rDu46zgnrIq+Tr4i7MyBybLCPP5F4=; b=0k47PM3pTvYX3yKOz3bQaX+n5qbZYT3y4ltT5w/bDKtmS9AznbNbHvUuANZwKJTbSr g85fOv/RrT3PFGGjdIye1jBOL3xpr5IGAfJNTnTgd1qEZIBMX4n/wslSov1tEb1phSNV Eq8q5EEPDmsrpLELbuP4RPv4oDL7gDhi7SAnhxlF+X4vMNh8l66o3I2xGJ7qrEMCKR0M w35s8D1C2XlB69pUH5fq08FaMgF7Yk6rhPuDBZAu29+xdmnpdlmRFv4qRfcRc88/8A+V Y0/ozcUYAXvYFh4YLBQ/jioHKZrR7DHNMJAovScefHE+HZVgHUfSezG2O91fIaXJXwdS T/gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pVeWUI2y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w25si458239jal.57.2021.04.29.18.20.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:20:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pVeWUI2y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcHpN-0007os-Mo for patch@linaro.org; Thu, 29 Apr 2021 21:20:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34016) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlL-00030o-SH for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:12 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:54844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl5-0007XD-8k for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:11 -0400 Received: by mail-pj1-x102a.google.com with SMTP id t13so9516082pji.4 for ; Thu, 29 Apr 2021 18:15:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GtzxgNF32jBOW0rDu46zgnrIq+Tr4i7MyBybLCPP5F4=; b=pVeWUI2yN7WtPNi2VOm/Oo874xvs4K82CUJ8V7aJbKlWDd2TzXcMSiY8p3iqseb5YB F4358xlolmbHkmEsNPjwRyqXU/OC+Yr5vZHYdYV0YYy1MGJt3MedY5KEuSTyCAxfegG2 MuYB7l55/yHnuWTxVEbzMfNgkclOHwilSLHb0+HfwgRo8LVo7W0L/jv56AhcaXPKpmcl 6okhB0SDfoMLgIit33Hhia/eKojCFKPWpX1cetzazSyYslHU2e2XYguFy9jaEYsBo8fc XS1ed64kH1wE0MK1LmqEqO5iCPWD71gz4EyCD3LuT92TrdEbxv4ai2od/Kqss6NVW0x1 zcKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GtzxgNF32jBOW0rDu46zgnrIq+Tr4i7MyBybLCPP5F4=; b=fv0GsxRGgVbAiYuFyRRp6//fNCsZM1LUZwa0LqQmguwJZn89Q4Zudb4D4tWys+3WTb 2LD8/DD6JRdeYPTYBwUSCxqdR6DxOBnE35ywYmdtZBxBcpt+1Tmba9BNeGn2VkcvWlgZ 9bb8G2MRJ2GH5ygTtGQaVPVqLqjZv/uE4G2v18EwMHKVDN7CG5brricmF2XJLFl1qAVj 8yI5R4QnYqfmOPhSU5rFaHNKIk028YNkVHDxsgc3IrzSRZiT/sE3SyQAFWrgxmLowtHR SATh2/bVlf6Ce1TpP7LxajgM5PApiHqhdPpx5qqAXUPH1by04N896R0TuZab5qIpJEba 0iqw== X-Gm-Message-State: AOAM533NDGesXBKrIuY8ABgSOdHLZbFcSPOoLMnZPHmy1Naal9SVWJL3 ybkzpXxeOJQnwrBLCH/ghdN7ButqmeRt9w== X-Received: by 2002:a17:90b:b05:: with SMTP id bf5mr2848277pjb.123.1619745351990; Thu, 29 Apr 2021 18:15:51 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/30] target/ppc: Introduce DISAS_{EXIT, CHAIN}{, _UPDATE} Date: Thu, 29 Apr 2021 18:15:24 -0700 Message-Id: <20210430011543.1017113-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rewrite ppc_tr_tb_stop to handle these new codes. Convert ctx->exception into these new codes at the end of ppc_tr_translate_insn, prior to pushing the change back throughout translate.c. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 75 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 65 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b58e2ac8dc..7dbdf3d047 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -183,6 +183,11 @@ struct DisasContext { uint64_t insns_flags2; }; +#define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ +#define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ +#define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ +#define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ + /* Return true iff byteswap is needed in a scalar memop */ static inline bool need_byteswap(const DisasContext *ctx) { @@ -8080,28 +8085,78 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); } - if (ctx->base.is_jmp == DISAS_NEXT - && ctx->exception != POWERPC_EXCP_NONE) { - ctx->base.is_jmp = DISAS_TOO_MANY; + if (ctx->base.is_jmp == DISAS_NEXT) { + switch (ctx->exception) { + case POWERPC_EXCP_NONE: + break; + case POWERPC_EXCP_BRANCH: + ctx->base.is_jmp = DISAS_NORETURN; + break; + case POWERPC_EXCP_SYNC: + case POWERPC_EXCP_STOP: + ctx->base.is_jmp = DISAS_EXIT; + break; + default: + /* Every other ctx->exception should have set NORETURN. */ + g_assert_not_reached(); + } } } static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + DisasJumpType is_jmp = ctx->base.is_jmp; + target_ulong nip = ctx->base.pc_next; - if (ctx->base.is_jmp == DISAS_NORETURN) { + if (is_jmp == DISAS_NORETURN) { + /* We have already exited the TB. */ return; } - if (ctx->exception == POWERPC_EXCP_NONE) { - gen_goto_tb(ctx, 0, ctx->base.pc_next); - } else if (ctx->exception != POWERPC_EXCP_BRANCH) { - if (unlikely(ctx->base.singlestep_enabled)) { - gen_debug_exception(ctx); + /* Honor single stepping. */ + if (unlikely(ctx->base.singlestep_enabled)) { + switch (is_jmp) { + case DISAS_TOO_MANY: + case DISAS_EXIT_UPDATE: + case DISAS_CHAIN_UPDATE: + gen_update_nip(ctx, nip); + break; + case DISAS_EXIT: + case DISAS_CHAIN: + break; + default: + g_assert_not_reached(); } - /* Generate the return instruction */ + gen_debug_exception(ctx); + return; + } + + switch (is_jmp) { + case DISAS_TOO_MANY: + if (use_goto_tb(ctx, nip)) { + tcg_gen_goto_tb(0); + gen_update_nip(ctx, nip); + tcg_gen_exit_tb(ctx->base.tb, 0); + break; + } + /* fall through */ + case DISAS_CHAIN_UPDATE: + gen_update_nip(ctx, nip); + /* fall through */ + case DISAS_CHAIN: + tcg_gen_lookup_and_goto_ptr(); + break; + + case DISAS_EXIT_UPDATE: + gen_update_nip(ctx, nip); + /* fall through */ + case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); + break; + + default: + g_assert_not_reached(); } } From patchwork Fri Apr 30 01:15:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429725 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2102938jao; Thu, 29 Apr 2021 18:18:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzWhY11mgR8BdA4zsB25LYjv3Hy159EmSjX+JUSAaFDIkuNP2YQIlqhXEW7nBpqL6yzghh5 X-Received: by 2002:a6b:d60e:: with SMTP id w14mr1691080ioa.187.1619745484636; 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Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 1 - target/ppc/translate.c | 27 +++++++++------------------ 2 files changed, 9 insertions(+), 19 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68..cf10117065 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -135,7 +135,6 @@ enum { POWERPC_EXCP_STOP = 0x200, /* stop translation */ POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ /* QEMU exceptions: special cases we want to stop translation */ - POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ }; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7dbdf3d047..d22d6e5b85 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -360,14 +360,6 @@ static inline void gen_stop_exception(DisasContext *ctx) ctx->exception = POWERPC_EXCP_STOP; } -#ifndef CONFIG_USER_ONLY -/* No need to update nip here, as execution flow will change */ -static inline void gen_sync_exception(DisasContext *ctx) -{ - ctx->exception = POWERPC_EXCP_SYNC; -} -#endif - #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) @@ -4008,7 +4000,7 @@ static void gen_rfi(DisasContext *ctx) } gen_update_cfar(ctx, ctx->cia); gen_helper_rfi(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif } @@ -4025,7 +4017,7 @@ static void gen_rfid(DisasContext *ctx) } gen_update_cfar(ctx, ctx->cia); gen_helper_rfid(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif } @@ -4042,7 +4034,7 @@ static void gen_rfscv(DisasContext *ctx) } gen_update_cfar(ctx, ctx->cia); gen_helper_rfscv(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif } #endif @@ -4055,7 +4047,7 @@ static void gen_hrfid(DisasContext *ctx) /* Restore CPU state */ CHK_HV; gen_helper_hrfid(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif } #endif @@ -5941,7 +5933,7 @@ static void gen_rfsvc(DisasContext *ctx) CHK_SV; gen_helper_rfsvc(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6321,7 +6313,7 @@ static void gen_rfci_40x(DisasContext *ctx) CHK_SV; /* Restore CPU state */ gen_helper_40x_rfci(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6333,7 +6325,7 @@ static void gen_rfci(DisasContext *ctx) CHK_SV; /* Restore CPU state */ gen_helper_rfci(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6348,7 +6340,7 @@ static void gen_rfdi(DisasContext *ctx) CHK_SV; /* Restore CPU state */ gen_helper_rfdi(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6361,7 +6353,7 @@ static void gen_rfmci(DisasContext *ctx) CHK_SV; /* Restore CPU state */ gen_helper_rfmci(cpu_env); - gen_sync_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -8092,7 +8084,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) case POWERPC_EXCP_BRANCH: ctx->base.is_jmp = DISAS_NORETURN; break; - case POWERPC_EXCP_SYNC: case POWERPC_EXCP_STOP: ctx->base.is_jmp = DISAS_EXIT; break; From patchwork Fri Apr 30 01:15:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429732 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2107422jao; Thu, 29 Apr 2021 18:25:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsA5HRhu5ZJ8TNPScizz6osqh38RCwcdD/h0ZIPHlGusUnJPhk0wTGbc/kyEkU/QgJFMD9 X-Received: by 2002:a92:ab01:: with SMTP id v1mr2206479ilh.190.1619745901561; Thu, 29 Apr 2021 18:25:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619745901; cv=none; d=google.com; s=arc-20160816; b=iuORE3Fk5UPHyWA0H5qmQb+XkgSGLbXD4d3pa3HVNJSY4Bc22Oh71vgl2Bn7vlVXKb Tvsuqj0y27FexUcQNaEznGQWvpGelDp9+A7c9LUXMpIHzMVirHZNw7lck2FyZfILz8F6 OEGZSuhi6V0Zoub3kuGfM1rh0a6OSeRHiXkIcd/Byf0VVKJbIWAh7vqgGbPcmZCcMfuM B9RnHJgy2vcoyrPti2KOHCFaryXMtaEL57sQ8cxWqrPbW/ZL8oYj/R7quUZVZG4ykuQk iM4Yx/PKveHmVHTFk07FQ8cr32nGNMjWYOWpY8zQxrXS3Hg5GWEgesIHEOTjBYQsyoy2 ntBg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id m6si546897jav.15.2021.04.29.18.25.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:25:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ddO2zIGS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcHtt-0002yn-0i for patch@linaro.org; Thu, 29 Apr 2021 21:25:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34018) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlM-00032F-IP for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:12 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:37810) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl5-0007Xx-Cy for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:12 -0400 Received: by mail-pl1-x62f.google.com with SMTP id h20so35744321plr.4 for ; Thu, 29 Apr 2021 18:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vI0Nppr/jR9QkJKg+7QUG9KyH4vg0w2u1KFcbBuivD8=; b=ddO2zIGSTDY2L38kz6bmQjJ8II9lUr0kvFNDZifC2aw0jUrXzQ/6Q780qJWR8QspF8 2yiQx7fOkLU+4dsFMzZYurJ3ijeamgHooBJZ9PZwm1Zpsxg6Z1YKM4LuPo/iXRkgi3vu PPATHWPGi8Gnwj7eo1BadznYkD+es6urumz2AEx1LQzoRAj3+//2+QqnqVlvO+on6Vsb gxPUsTU9Bqg+HAiMMZy4jYiO+TS2BO8VyXizXKZeT6YGPGWf4ZvgYO2JZZDsCOZPjaEy 1msLtDMTKxQmxwa2PNm5Gf1tcqpL+fI1O1tOx7uA0L6OM3vhBZvFarn7K5z4FHM0R6fw wPJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vI0Nppr/jR9QkJKg+7QUG9KyH4vg0w2u1KFcbBuivD8=; b=QapqwenRi0ulzDIQ8C5fkb9FX7+A8l6dm6Bfz82kFgyDCMJFKwXci+Z7FKQvgR1+NW ueXM1MBSoJv2IPAP3EoByOES6jQOm6HFboWbrSFET6O9Wg4G8wB9/46kVseNq9FKuVzD 7SUJzQwArZig0IXLz8/W5CfOXKFCexMccNYqgjyHVWZh/qinSIO7m4ulhLooRPjXKkl/ 7rgnre367RWCboM5tBLoWlYOZcVgb2O52lViEcloVSjtVNBS06D7YD3HZ/sSmy1fSwDj dQF2tU3s6dZL7TSmb6SfEUV2Tr4vDt3r+vP4YjHK171QzImdem+MNhxwtXQnv4GpATFC lTuw== X-Gm-Message-State: AOAM533MaVYq5x0CJsw6v2ctSlruW6kD0sNfaY3ep/tZZYOTC7tRSpas ijbjkVdkPCX/yMmH0A1pR/JfRPylXA5wKw== X-Received: by 2002:a17:90b:4b12:: with SMTP id lx18mr2662667pjb.45.1619745353251; Thu, 29 Apr 2021 18:15:53 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/30] target/ppc: Remove unnecessary gen_io_end calls Date: Thu, 29 Apr 2021 18:15:26 -0700 Message-Id: <20210430011543.1017113-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since ba3e7926691ed33, we switched the implementation of icount to always reset can_do_io at the start of the following TB. Most of them were removed in 9e9b10c64911, but some were missed. Signed-off-by: Richard Henderson --- target/ppc/translate_init.c.inc | 6 ------ 1 file changed, 6 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index c03a7c4f52..99e5f52925 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -213,7 +213,6 @@ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) } gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); gen_stop_exception(ctx); } } @@ -225,7 +224,6 @@ static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) } gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); gen_stop_exception(ctx); } } @@ -250,7 +248,6 @@ static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) } gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); gen_stop_exception(ctx); } } @@ -262,7 +259,6 @@ static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) } gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); gen_stop_exception(ctx); } } @@ -311,7 +307,6 @@ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) } gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); gen_stop_exception(ctx); } } @@ -323,7 +318,6 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) } gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); gen_stop_exception(ctx); } } From patchwork Fri Apr 30 01:15:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429739 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2111767jao; Thu, 29 Apr 2021 18:32:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJUTbrACGKjn3otq9xGKViZFc/vgxBOWBO6xahtfVt0bPhrXMrC6YyZ6ukHejP8+e5rKx+ X-Received: by 2002:a5d:9cd8:: with SMTP id w24mr1927417iow.78.1619746332233; Thu, 29 Apr 2021 18:32:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746332; cv=none; d=google.com; s=arc-20160816; b=t0f2n0tilWmBjUmjc5mhv+VL0W/D82SSTZA2JKG1Y5+8B1za/c53fnhDh9nHyYLwpy jeu61xNhyKKhubhqP06lMECphD5dY4H0EoHcoAJSPF33kDzeUP2HvKTTHt0SjjVJSwkh 5L+rMhPZMGgH12U6p9D9idG0RGHY8Ta0vTZS5EZSLN+OBazh1//2U4OqDu3UAjcO5qJn ShGHkC1hEZqMyXji2RoNHrGbqqSvP90dWCfb/dewaoHEWcTGPobSvSZTWcmmGQLs6lTZ tcWflOgIelly3d124IGTn2YY/I3+5kjjM3VmWMDwBEco83dZ1yZ8uuQxn5In7jcY/vcR y4ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0dtTAq0h6uZvJe2v8duAmpGVqYM3A3f710RFs1XYPxA=; b=vmQOlUgFnIIkXJiaoTk98UVdS7bRM1HTqMkC8ObDXo0vEDUUeD7n91/gPx4srMgTAq Dbo44Nmid2dOmlaagfr+nsQZP9KiGsMKrrK5yYTQ+/2eqP2CiA4iQ677E8XPSLe9moIO MtwQ5s+pjFw+BM8QByBKYa1MeV+Hf7tAG/mlDqdmpuKpWxEoO48eILXXHG8933FlzF5s qASihbzWHfu0X8VEZRwcYvTGKV598gt0OasEi+JWyao3VmvbweyrHDdByqVOv5LwomVu 4a52e7N03Pn4GD3b/nJEqrXl5mhszQtQK7Mfz8KZulRRtvg1XlERJ/JcCCifwGVFiFhH z0Lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cxkuCXsS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Force the exit from the tb via DISAS_TOO_MANY, which allows chaining to the next tb, where the code emitted for gen_tb_start() will determine if we must exit. We can thus remove any matching conditional call to gen_stop_exception. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 41 +++++----- target/ppc/translate_init.c.inc | 133 +++++--------------------------- 2 files changed, 39 insertions(+), 135 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d22d6e5b85..45cd3189c0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -302,6 +302,20 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp, ctx->base.is_jmp = DISAS_NORETURN; } +static void gen_icount_io_start(DisasContext *ctx) +{ + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + /* + * An I/O instruction must be last in the TB. + * Chain to the next TB, and let the code from gen_tb_start + * decide if we need to return to the main loop. + * Doing this first also allows this value to be overridden. + */ + ctx->base.is_jmp = DISAS_TOO_MANY; + } +} + /* * Tells the caller what is the appropriate exception to generate and prepares * SPR registers for this exception. @@ -1842,18 +1856,13 @@ static void gen_darn(DisasContext *ctx) if (l > 2) { tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); } else { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); if (l == 0) { gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); } else { /* Return 64-bit random for both CRN and RRN */ gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); } - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } } #endif @@ -3995,9 +4004,7 @@ static void gen_rfi(DisasContext *ctx) } /* Restore CPU state */ CHK_SV; - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_update_cfar(ctx, ctx->cia); gen_helper_rfi(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -4012,9 +4019,7 @@ static void gen_rfid(DisasContext *ctx) #else /* Restore CPU state */ CHK_SV; - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_update_cfar(ctx, ctx->cia); gen_helper_rfid(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -4029,9 +4034,7 @@ static void gen_rfscv(DisasContext *ctx) #else /* Restore CPU state */ CHK_SV; - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_update_cfar(ctx, ctx->cia); gen_helper_rfscv(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -4406,9 +4409,7 @@ static void gen_mtmsrd(DisasContext *ctx) CHK_SV; #if !defined(CONFIG_USER_ONLY) - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); if (ctx->opcode & 0x00010000) { /* L=1 form only updates EE and RI */ TCGv t0 = tcg_temp_new(); @@ -4443,9 +4444,7 @@ static void gen_mtmsr(DisasContext *ctx) CHK_SV; #if !defined(CONFIG_USER_ONLY) - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); if (ctx->opcode & 0x00010000) { /* L=1 form only updates EE and RI */ TCGv t0 = tcg_temp_new(); diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 99e5f52925..9af3fb2066 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -183,24 +183,14 @@ static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) #if !defined(CONFIG_USER_ONLY) static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_load_decr(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } #endif @@ -208,24 +198,14 @@ static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) /* Time base */ static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } ATTRIBUTE_UNUSED @@ -243,24 +223,14 @@ static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) #if !defined(CONFIG_USER_ONLY) static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } ATTRIBUTE_UNUSED @@ -279,80 +249,45 @@ static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) ATTRIBUTE_UNUSED static void spr_read_purr(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_load_purr(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_purr(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } /* HDECR */ static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } #endif @@ -560,71 +495,41 @@ static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) #if !defined(CONFIG_USER_ONLY) static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_store_spr(sprn, cpu_gpr[gprn]); gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); /* We must stop translation as we may have rebooted */ gen_stop_exception(ctx); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + gen_icount_io_start(ctx); gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_stop_exception(ctx); - } } #endif From patchwork Fri Apr 30 01:15:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429743 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2113675jao; 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Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 1 - linux-user/ppc/cpu_loop.c | 3 --- target/ppc/translate.c | 20 +++++--------------- target/ppc/translate_init.c.inc | 4 ++-- 4 files changed, 7 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cf10117065..9bb370abba 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -132,7 +132,6 @@ enum { /* EOL */ POWERPC_EXCP_NB = 103, /* QEMU exceptions: used internally during code translation */ - POWERPC_EXCP_STOP = 0x200, /* stop translation */ POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ /* QEMU exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index df71e15a25..4c308835bd 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env) cpu_abort(cs, "Maintenance exception while in user mode. " "Aborting\n"); break; - case POWERPC_EXCP_STOP: /* stop translation */ - /* We did invalidate the instruction cache. Go on */ - break; case POWERPC_EXCP_BRANCH: /* branch instruction: */ /* We just stopped because of a branch. Go on */ break; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 45cd3189c0..82fdf0bb77 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -367,13 +367,6 @@ static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); } -/* Stop translation */ -static inline void gen_stop_exception(DisasContext *ctx) -{ - gen_update_nip(ctx, ctx->base.pc_next); - ctx->exception = POWERPC_EXCP_STOP; -} - #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) @@ -3157,7 +3150,7 @@ static void gen_isync(DisasContext *ctx) gen_check_tlb_flush(ctx, false); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_stop_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) @@ -4434,7 +4427,7 @@ static void gen_mtmsrd(DisasContext *ctx) gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); } /* Must stop the translation as machine state (may have) changed */ - gen_stop_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; #endif /* !defined(CONFIG_USER_ONLY) */ } #endif /* defined(TARGET_PPC64) */ @@ -4477,7 +4470,7 @@ static void gen_mtmsr(DisasContext *ctx) tcg_temp_free(msr); } /* Must stop the translation as machine state (may have) changed */ - gen_stop_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; #endif } @@ -6614,7 +6607,7 @@ static void gen_wrtee(DisasContext *ctx) * Stop translation to have a chance to raise an exception if we * just set msr_ee to 1 */ - gen_stop_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -6628,7 +6621,7 @@ static void gen_wrteei(DisasContext *ctx) if (ctx->opcode & 0x00008000) { tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); /* Stop translation to have a chance to raise an exception */ - gen_stop_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } else { tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); } @@ -8083,9 +8076,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) case POWERPC_EXCP_BRANCH: ctx->base.is_jmp = DISAS_NORETURN; break; - case POWERPC_EXCP_STOP: - ctx->base.is_jmp = DISAS_EXIT; - break; default: /* Every other ctx->exception should have set NORETURN. */ g_assert_not_reached(); diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index 9af3fb2066..f3e79b8685 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -463,7 +463,7 @@ static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) { gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); /* Must stop the translation as endianness may have changed */ - gen_stop_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } #endif @@ -511,7 +511,7 @@ static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) gen_store_spr(sprn, cpu_gpr[gprn]); gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); /* We must stop translation as we may have rebooted */ - gen_stop_exception(ctx); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) From patchwork Fri Apr 30 01:15:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429740 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2111830jao; Thu, 29 Apr 2021 18:32:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtm4ghJZCCRXX7kDIw4TTJWLa7iG6mU7V6HXJX1j267oJVjonwp0vh19q9W+qz+yZOJnnx X-Received: by 2002:a05:6602:122a:: with SMTP id z10mr1941502iot.60.1619746337133; Thu, 29 Apr 2021 18:32:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746337; cv=none; d=google.com; s=arc-20160816; b=gAQk+ULyWNM9fQwlF/JCSEvZlumoe85wI7JP++gEfxb+LLg71JAx3hYy4WO/ka3IMn 2JO8HZCM7phyETDTtpn3jvvwQ3pKCDbi7SS6RlMf2iOfTaX0bv9EnMnYfxaK+Lhgy0/h jy2CJkPNdPSwxYNcZmS0gJqbMkiSOhAbAxmuYEsDGvPG04nfLBPUkOCLLUiC+Vu6usju PlMpGCJe7RvyH8rH+U+GXEJuZP3NAEV7UsmQr0FqLz7kPP5342oS4e8zsMPKnEQVJtj3 H5irBglxqrBcZDlchNSsfqI356DnatcgQ8MmY/0LaZX91vloA3IB+KdEcYdJJbPawCN8 ZPkw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id y15si464026ilv.72.2021.04.29.18.32.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:32:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=d4p4Wqjg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcI0u-00021B-GR for patch@linaro.org; Thu, 29 Apr 2021 21:32:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlT-0003BL-46 for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:19 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:41907) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl7-0007YV-3a for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:18 -0400 Received: by mail-pj1-x102a.google.com with SMTP id y22-20020a17090a8b16b0290150ae1a6d2bso912702pjn.0 for ; Thu, 29 Apr 2021 18:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=otPhcvbNJ17mxlPliTzuao80JoAxdfhn5Twl3YLl2dY=; b=d4p4Wqjgb26lk8uPtCQSMef/IKxLF+wPfemCHxHoNEqkLwwBRMoEslZHE1YJf1iDZI NJ2ypzKS4i6Xz/eDxIIusdfSJ11LXbRGkimaVTgtIbxHZl0E+cfPjKTb0xgdteWEHFDy w2UcBcuuUmQ/rb5xgH3VR8A5eFxA2gGJOUxuo0HezMk9detdJwRAO7qao+Ckd8NKT0ZS a+stD+jTzsV5WbF+e1CmjMAxR2x83rctMfnxnN62hsRVSP2jdaz540SroNuBTIi3c8SP Y5Tsx3TcQ791JKr/87vMYKAMfqotgX4vryJ3j8vHpOzh6/F6hLmVzy9Pt+hU2+9BYCBY Yx2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=otPhcvbNJ17mxlPliTzuao80JoAxdfhn5Twl3YLl2dY=; b=iiOqxwzLwfXzp365s/C7yOWWFCVbkBVnez9Q8KsKzaLO0DOVOQDlmkNTYQa0KNZTwg pKSpR3BBJ94U2m9qhTIEykfz0v+dmMF/nppRq4eiz5CS3O+DWo3lxmwguWRvk/Vxrpt2 VkLH7ixLRka4Mx6zIuIBdrSftuy+AbsMYOfaAHQSNulTL/R75LVjQUBeR5Iygf2iO/Kl acsatP0w9t2/QKtS0VuC1WmKFTFQb7apRCjdOEA038kaF2jJEh71jo93L8TiZ4D9XOBC 5GjUA6KonafN0bsYNHlYUcV+S8BKleh04HP1pxQCageyYLTuEpp/BK5rQY/N2i2HhcoF goUA== X-Gm-Message-State: AOAM532uJZnnSIhCv/eTOuHKUgnEGBH/aTaUDHzK3TVOoZlxNrqYFF5J NANCUneWXVPyk5ZFNOkKgsYQiAQRV4R/JA== X-Received: by 2002:a17:902:4d:b029:ec:94df:c9aa with SMTP id 71-20020a170902004db02900ec94dfc9aamr2779364pla.7.1619745355265; Thu, 29 Apr 2021 18:15:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/30] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN Date: Thu, 29 Apr 2021 18:15:29 -0700 Message-Id: <20210430011543.1017113-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The translation of branch instructions always results in exit from the TB. Remove the synthetic "exception" after no more uses. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 2 -- linux-user/ppc/cpu_loop.c | 3 --- target/ppc/translate.c | 8 ++------ 3 files changed, 2 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9bb370abba..5b22eb64dc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -131,8 +131,6 @@ enum { POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */ /* EOL */ POWERPC_EXCP_NB = 103, - /* QEMU exceptions: used internally during code translation */ - POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ /* QEMU exceptions: special cases we want to stop translation */ POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ }; diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 4c308835bd..adf5a8a4e6 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -423,9 +423,6 @@ void cpu_loop(CPUPPCState *env) cpu_abort(cs, "Maintenance exception while in user mode. " "Aborting\n"); break; - case POWERPC_EXCP_BRANCH: /* branch instruction: */ - /* We just stopped because of a branch. Go on */ - break; case POWERPC_EXCP_SYSCALL_USER: /* system call in user-mode emulation */ /* WARNING: diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 82fdf0bb77..276a4a2a79 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3769,7 +3769,6 @@ static void gen_b(DisasContext *ctx) { target_ulong li, target; - ctx->exception = POWERPC_EXCP_BRANCH; /* sign extend LI */ li = LI(ctx->opcode); li = (li ^ 0x02000000) - 0x02000000; @@ -3783,6 +3782,7 @@ static void gen_b(DisasContext *ctx) } gen_update_cfar(ctx, ctx->cia); gen_goto_tb(ctx, 0, target); + ctx->base.is_jmp = DISAS_NORETURN; } #define BCOND_IM 0 @@ -3795,7 +3795,6 @@ static void gen_bcond(DisasContext *ctx, int type) uint32_t bo = BO(ctx->opcode); TCGLabel *l1; TCGv target; - ctx->exception = POWERPC_EXCP_BRANCH; if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { target = tcg_temp_local_new(); @@ -3902,6 +3901,7 @@ static void gen_bcond(DisasContext *ctx, int type) gen_set_label(l1); gen_goto_tb(ctx, 1, ctx->base.pc_next); } + ctx->base.is_jmp = DISAS_NORETURN; } static void gen_bc(DisasContext *ctx) @@ -8057,7 +8057,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) /* Check trace mode exceptions */ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && - ctx->exception != POWERPC_EXCP_BRANCH && ctx->base.is_jmp != DISAS_NORETURN)) { uint32_t excp = gen_prep_dbgex(ctx); gen_exception_nip(ctx, excp, ctx->base.pc_next); @@ -8073,9 +8072,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) switch (ctx->exception) { case POWERPC_EXCP_NONE: break; - case POWERPC_EXCP_BRANCH: - ctx->base.is_jmp = DISAS_NORETURN; - break; default: /* Every other ctx->exception should have set NORETURN. */ g_assert_not_reached(); From patchwork Fri Apr 30 01:15:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429742 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2113409jao; Thu, 29 Apr 2021 18:34:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxBVz/fjYJhf3DFvpL9IJ5k03qn6XKC4R/zgyR8O9V6o4cT3fC5Wd7rmKwP4w8OkZDgPdk3 X-Received: by 2002:a92:d24f:: with SMTP id v15mr2105559ilg.248.1619746483428; Thu, 29 Apr 2021 18:34:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746483; cv=none; d=google.com; s=arc-20160816; b=y1LvCGQrp2ebR9wzt4wCzygwOBVwWzOAsQdPKtAewA2wzCvXWpU+GRGC9lkrQQRbmS MBguY9dNqsomym1lgnV37LqbcAPmzvTlgqHvJ4YeDXM346b71ub4DOrEL77ik7ryt8li qj0R+MzjKrTLptmjQoLwLgpafoabBcInZJgyFNMBYW0R4RpduuR+HBUBDpG4f855S9ju UA/nCt35zsCAjhUsVTJdPQ7aqMYlQiUmu7Qocy6/SDhp0hn1XyMHSkcsSBSxmmo5eDqw 7mMf3ParfCD48CJb7wf7t4yj0RXEV5RtwctsYkRhGYcozDyJAu00A+CPy6WTqa86537b xQYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lvFYTR21Ndabo3puJK2zdhaYlEZw9zSgHgo2egIRWs4=; b=c4bFqRdEKh0mLSMNfBhVhw9h9JMW+zgLyBsTzrcRjICn2nDGb16Quebc7yfFHxtjok 1s2b46j91lbMagQ5eqRKCwiXmpCyIHJjN533zra4+qXNWYOr3zCb21/aFzhOJ7nmOBu9 wVJ+7X0Jy2erDaNkHg2Hv58zfm8glJ0j1Nqpskj+cLSGckctSxRtIqGOgIfhQrQdXf8D csm4b6PH6hXXGFz1F12iPH8AFcnvAyHj3J1Rgk+fQcf7ms5oTjXYq2UdZmB0VT8Pz7lE Yipf7BthFPyJOZAbourOXrvgCDBPy0XXuIobESgWNK3bMZY6yvHZrTPuZXXN7kRR7wZ0 A7nA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a+bd3fVB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i26si1502313ioj.39.2021.04.29.18.34.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:34:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a+bd3fVB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcI3G-0005Xs-RY for patch@linaro.org; Thu, 29 Apr 2021 21:34:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlV-0003E3-Iq for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:21 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:44952) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl7-0007ZE-5B for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:21 -0400 Received: by mail-pl1-x62d.google.com with SMTP id y1so20090389plg.11 for ; Thu, 29 Apr 2021 18:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lvFYTR21Ndabo3puJK2zdhaYlEZw9zSgHgo2egIRWs4=; b=a+bd3fVBebYnYMekKuIPsNqYpbCviq35aTyaqOhXO69rx3ZAvZ7ugZod2rC0b56AXj saqninyBAR7vAwZcGD30uvDMD+Gw5PWD6lgoDliMHdZuLvQUCN34ovCh9heKTjc1TBwS E+HTyxIPk/guHB4v/1CRcIYJqei8DPR6IDSI/gQgdmPtFuI2kQZFcc1z7IPchcwqec3/ wYL/YDOhMKOyY4Z5QH5bHlZstUiNsi5V43SGv9h3AP2UkGkfJmxG7h3qRmK6RFA8N//N LQIb1TVNdyQ592hDcGC9GZsmEbiTPCl/82wiAxSqBeTVV+aZIZ4CeSQO+9wExNnVB5zW VkPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lvFYTR21Ndabo3puJK2zdhaYlEZw9zSgHgo2egIRWs4=; b=qosJiEbm1dQVhTfKCnVPtb5o+Rff9ZEo+5AeX91xry5XGjm7fW+CwcrfMY9Ci1ekYG iqb0c/u6v1yEQfRzkOfmSbEkHCo6UchckLl/thBkjZQxAgFgzbFFVunMaq+/fom+p4H7 yTikJuntNf1DzzH7sp+Fz540Hwts8r/yX5owgowbuM8MtJhbSpndguPd3Zg0z/rgPlXs VSIw4vS5Wi6L/s3Mpvr+gcsFxV7E6/945DTSZdR/c35QmEw8TyG6g2DJ6TGakuowfTCP tMHjHFbkbFaqnKIk+Vl6bzc25YRszJpoFKLTH8ZtcVHrDj0qiGnMxRo6xfVdE2iOpIJA DWqQ== X-Gm-Message-State: AOAM533U/KtBk8N45+6qmLCPhcdn0sKUgkfkSc5AqCWZHjcKLTjS8ZiM AaeBfJbua2vFTD+nE8i3gbHCfbJ/p38boA== X-Received: by 2002:a17:90b:4b11:: with SMTP id lx17mr8922216pjb.130.1619745355895; Thu, 29 Apr 2021 18:15:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/30] target/ppc: Remove DisasContext.exception Date: Thu, 29 Apr 2021 18:15:30 -0700 Message-Id: <20210430011543.1017113-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that we have removed all of the fake exceptions, and all real exceptions exit via DISAS_NORETURN, we can remove this field. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 276a4a2a79..d78071a4a4 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -259,15 +259,12 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) * These are all synchronous exceptions, we set the PC back to the * faulting instruction */ - if (ctx->exception == POWERPC_EXCP_NONE) { - gen_update_nip(ctx, ctx->cia); - } + gen_update_nip(ctx, ctx->cia); t0 = tcg_const_i32(excp); t1 = tcg_const_i32(error); gen_helper_raise_exception_err(cpu_env, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); - ctx->exception = excp; ctx->base.is_jmp = DISAS_NORETURN; } @@ -279,13 +276,10 @@ static void gen_exception(DisasContext *ctx, uint32_t excp) * These are all synchronous exceptions, we set the PC back to the * faulting instruction */ - if (ctx->exception == POWERPC_EXCP_NONE) { - gen_update_nip(ctx, ctx->cia); - } + gen_update_nip(ctx, ctx->cia); t0 = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); tcg_temp_free_i32(t0); - ctx->exception = excp; ctx->base.is_jmp = DISAS_NORETURN; } @@ -298,7 +292,6 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp, t0 = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); tcg_temp_free_i32(t0); - ctx->exception = excp; ctx->base.is_jmp = DISAS_NORETURN; } @@ -7919,7 +7912,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) CPUPPCState *env = cs->env_ptr; int bound; - ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; ctx->pr = msr_pr; ctx->mem_idx = env->dmmu_idx; @@ -8067,16 +8059,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); } - - if (ctx->base.is_jmp == DISAS_NEXT) { - switch (ctx->exception) { - case POWERPC_EXCP_NONE: - break; - default: - /* Every other ctx->exception should have set NORETURN. */ - g_assert_not_reached(); - } - } } static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) From patchwork Fri Apr 30 01:15:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429737 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2110978jao; Thu, 29 Apr 2021 18:31:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwPfOBsZ9Pm+5CXf/yGcKiXeZ0IBIjso/XuAXBrvyER3ruerJBMuirje7yMHNAPBpTOrAyc X-Received: by 2002:a6b:cdc6:: with SMTP id d189mr1819137iog.46.1619746264736; Thu, 29 Apr 2021 18:31:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746264; cv=none; d=google.com; s=arc-20160816; b=B0Wc8+TNUX1pM4jgwg26uiBcw3Rvsicg7GQ8Kej1YW3uSrqQ20ojs+NxjQCUqsD453 Vj4GpLRfTMQ+nFxPMA4ydL1LxqSeVYjQ2oxPbQVarFQL3afkm5rMwt8cmC+KTPDGBCYu PGuV64dMbZvjFsXsh810JRaW8d+xu+hiGVV4ytGtciC9SUAdQkLqpriOeXPXv6XWx1GQ YoV/rlFvb6ydDN8J1iuJR/D5MilVpq93iN/3lwgO6B5CbN00lgu0fAkmCS0WmDAX7GdX 2kNTMm+84OlHfFAStnUgPtZqSB3IOYyqOD43OrZwVqI612CLV0eA+iD+Uxx00dmNKZGI 375A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FG8lZNLGBFMSNwAJ87zP7K0VIxx2bT3pD9iURDdrTvs=; b=JbTmfpUnRHmv45dY90lav7fIH4j7QSgXZ4Oj2Z5JfWiXCo2emkWSFJerzpjrVuiRPI 5LaJwPwSPCN9BOoOomkKIpwAds5Lq3iubhqZ6HHH63BjD1ualVFDn5xFiPdEPmVKAzcV HI0+3xo+HjdNKBO78Saz+u0QijWzxRaqZTSSP9fZrV2s2v8eoTmTRWKVa29NlQSq1BGt JRkHdke2QQKM0pIYIU6zg0TXNgCZKJhWv780I3H5u6w/0g/mPlIukvVQL9E+xnoJsa5L FgW7vyExg3wyvPK1pA9ExU0bzgMvnqg7uQdKD3knOujkGKDf+QLaad3guwSE7nFbjX94 hJXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aA6d4RcC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z7si418611jal.122.2021.04.29.18.31.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 29 Apr 2021 18:31:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aA6d4RcC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37336 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lcHzk-0008U0-11 for patch@linaro.org; Thu, 29 Apr 2021 21:31:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lcHlU-0003C8-H2 for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:20 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:39674) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lcHl9-0007ZQ-3k for qemu-devel@nongnu.org; Thu, 29 Apr 2021 21:16:20 -0400 Received: by mail-pf1-x429.google.com with SMTP id c17so12744271pfn.6 for ; Thu, 29 Apr 2021 18:15:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FG8lZNLGBFMSNwAJ87zP7K0VIxx2bT3pD9iURDdrTvs=; b=aA6d4RcCrK1Mw/SsO8LfVyMJcYm/BwMsyZ6QjnaGfNyQlFtb5hZOc5+T3KsgOEGCxF OPmyJeZTQezvngq6zYozd2ZUoUa6dummK22iJs3uqqJSzyPWfs0SK7NP/xmNBl014XwX 5JM6h8/5GR967M3BGphi1M8rfrpR3m5012q3bhTzM7QqZwZyZIEui8SDTsIeW2Sqyy74 VOByVSdBzqrL6x5d4y4//uS6Qejnk6YH3bvxO67110EKCu5crLSSNZNFb9JUmW0Pp3qn ddwKomMdVM/l/LE0r5NSdcVVgsYpYFVZ6WtLv/lHOHKmNAutRJZ9tTjYYlbnQFB4hjGj fe1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FG8lZNLGBFMSNwAJ87zP7K0VIxx2bT3pD9iURDdrTvs=; b=QCgaDGDnuYwMTUZFSoNy0qqielhL58qiHNLrGyiXRxufYUrGM9hEsl/guRjpkEi/5x KdhwGb3e6WFn3jWT/UOmf7O8Iu4w6JbFZVGS/q3EkzunTaJ88Vd2RXmaKjUt8pdERLuU eJ/NKSkbq8tTr4Tu5g3PwPD9AshAQsJUoEv6t5EfNOGKJJudd7mP4G2nkiMqgvJLagGK 4imfUX9TMfd2R9c0fyfh6eq2hNPKX3mxJ9vIY9eLK59akia4lC11Xya12tqG4dY7DdeU BmTuR9sZDBldLfl/Zpx/ZzDvm2dB6hyJBjYWXbeUUzNk1YcaqG/Fpq6chDr1jg2qtWk0 t4ug== X-Gm-Message-State: AOAM532ihi9r23dZPpoGIhQoqUkcRv5JaFiy6aEOaopGC2AD4oh9MYNh G7Ky2f05mT//pluPV3AdYqmye+P7YKMMUQ== X-Received: by 2002:a62:6202:0:b029:208:f11c:2143 with SMTP id w2-20020a6262020000b0290208f11c2143mr2788727pfb.32.1619745356543; Thu, 29 Apr 2021 18:15:56 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 1sm161277pjx.46.2021.04.29.18.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Apr 2021 18:15:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/30] target/ppc: Move single-step check to ppc_tr_tb_stop Date: Thu, 29 Apr 2021 18:15:31 -0700 Message-Id: <20210430011543.1017113-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When single-stepping, force max_insns to 1 in init_disas so that we exit the translation loop immediately. Combine the single-step checks in tb_stop, and give the gdb exception priority over the cpu exception, just as we already do in gen_lookup_and_goto_ptr. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d78071a4a4..c018960ce9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7910,7 +7910,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUPPCState *env = cs->env_ptr; - int bound; ctx->spr_cb = env->spr_cb; ctx->pr = msr_pr; @@ -7986,13 +7985,13 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } -#if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr_se = 1; -#endif - bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - ctx->base.max_insns = MIN(ctx->base.max_insns, bound); + if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { + ctx->base.max_insns = 1; + } else { + int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; + ctx->base.max_insns = MIN(ctx->base.max_insns, bound); + } } static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) @@ -8046,14 +8045,6 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) handler->count++; #endif - /* Check trace mode exceptions */ - if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && - (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && - ctx->base.is_jmp != DISAS_NORETURN)) { - uint32_t excp = gen_prep_dbgex(ctx); - gen_exception_nip(ctx, excp, ctx->base.pc_next); - } - if (tcg_check_temp_count()) { qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), @@ -8066,6 +8057,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasJumpType is_jmp = ctx->base.is_jmp; target_ulong nip = ctx->base.pc_next; + int sse; if (is_jmp == DISAS_NORETURN) { /* We have already exited the TB. */ @@ -8073,7 +8065,8 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) } /* Honor single stepping. */ - if (unlikely(ctx->base.singlestep_enabled)) { + sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP); + if (unlikely(sse)) { switch (is_jmp) { case DISAS_TOO_MANY: case DISAS_EXIT_UPDATE: @@ -8086,8 +8079,16 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) default: g_assert_not_reached(); } - gen_debug_exception(ctx); - return; + + if (sse & GDBSTUB_SINGLE_STEP) { + gen_debug_exception(ctx); + return; + } + /* else CPU_SINGLE_STEP... */ + if (nip <= 0x100 || nip > 0xf00) { + gen_exception(ctx, gen_prep_dbgex(ctx)); + return; + } } switch (is_jmp) { From patchwork Fri Apr 30 01:15:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429741 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2113259jao; Thu, 29 Apr 2021 18:34:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyEd+6vsh29/lIb0oMg0BAyXqC4v7E/tvqY4uZPig9eqBj9W/GF15WSUWJiEBKiUdOv4/xU X-Received: by 2002:a6b:b404:: with SMTP id d4mr1936538iof.56.1619746468542; Thu, 29 Apr 2021 18:34:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746468; cv=none; d=google.com; s=arc-20160816; b=jp+YSTp1GQffnlh1asfmpGmZ4QFucLLV9M+9zNw3r5cD3PGm1sK+UKiFmIw1WfqvOs VU712EbGNZE6lrs0OQHQG9psPnzJHbc8WQH2KaeKI878diQrCLUS65qlrzeFXahoPkXm L+95A4BVBglUMQ5CoxCLgJ7Cx9ZrP60+Ka49xWfF7g2GFl7xN0Bt+MEwpxcFM3fb5Uwd i8BXz6jK8RE86HIV/8kNYFhE3vdzBmCKOV710T4k2kTWQUDgWxjp6OUDcGi1nj6xLp8S XH3wQcBmfEEMtyj4s/U/pvsIZGwC/u1OAoI8BW/9Gdb4xFdHFvYjzm0AZexmfLOpehhG lN1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WLwfFICyGCDMWMxJirWXS2mvwpYV2dRQ+KP9fVeeh6c=; b=El3iIJIj2+KZmnBN76ya6/gzQKv4DKQWa6d216e6eyXbGe7M92BHGU0ZkFnD3gwtvT 87fSwWcGPfcGiZQbSQVUTVrzL55W75r5S9p1p5qQeG7jLn5jK0pKVe5JqnUUFNw0MWDG A1zoaKoNKLr80frkfZLvRnvzWahisTO2cb5xKqwxXeerL6S1cdIZNRQuPrmxLEWt4ZQw ynb50z831DGplfOGvuw2WE/lDq38OuzKYoC+W38V32q+b/CCendX6GZ/qhyieCr0W5E/ Ag28vVujM62/eRRQSgOBrsZdaaw0bFAEZ7SbOGpIcIHuXfDPfJ80QmeXX90KOhkttf+g tQrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ld8+sUbu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c018960ce9..fe3982e289 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3726,8 +3726,9 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx) } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { uint32_t excp = gen_prep_dbgex(ctx); gen_exception(ctx, excp); + } else { + tcg_gen_exit_tb(NULL, 0); } - tcg_gen_exit_tb(NULL, 0); } else { tcg_gen_lookup_and_goto_ptr(); } From patchwork Fri Apr 30 01:15:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429745 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2114943jao; Thu, 29 Apr 2021 18:37:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsJAkuPxysHSiBiIbcQtIulZ24nSBAv5ZUmh+B3x2JUKs72LKk4EQBVMmzJd2wlWVY1of6 X-Received: by 2002:a92:1805:: with SMTP id 5mr2174067ily.82.1619746652059; Thu, 29 Apr 2021 18:37:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746652; cv=none; d=google.com; s=arc-20160816; b=QTA/TmRs46eB+rViUsemGbVv8I57XPukOa2SVxuwFZGIfhx63gznxx7dVGc+S+93nY bRbfx/6bg4BaNAfVzSpNL6s2m48m6/cdf8YlOysMgzcr1o268L1u6jAL+WjMpT25GryW 6yaHLfkH8HIAFZxgl8Iw31UI90u3LnEzI5LR3p38pnTUKPeFr9TtfNJM6Opfi4LtA2Px lsro9u2a5GSDt5I8uQwqoJadMxOF+BCqZLJAgp3OL+OtgHpKJUtXsTbzrTAjZ3W5+X/B Sdqj9rFefBOQRbEob64VhNMECl0g79RRIZr3fDKhnE8Ef6bT8If//nPn7hxNTTwHaMbk rLgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SMBeb0vvlSxkj9D6NrOhypGO0r00xMqrewSjQLWfP30=; b=PeHJ9559hy50CwwL1F8xhnXFnvYx4Vs+crcI872xVD1WqLja4FMv04Xs510fhkp1aR W6uDvFs3/vmVL4C8Lz6J++kR3Xf0gG9yBkA6pg/gPEj1ri1dDbLUswZ8VamShwU2ifAx f66kRdVv6N1iBDX3gSITMNF8dDRJzmCuGs8xazFoO+9+q8+Qtyj8K1Xa42WO1fMcjlq1 Yk9O/R6l//UVi5p0ppRIF0WJk3qknmCMf9iGN5cHcz+3buSVhscEFL5fZrCndU1SpgRG nDEdeOlMhg/VdKrRL5b0IW4e+IUtNAZgmWLd8i/ofJnoIgeOJYJOUUZxRF/Vh8QR52dI piWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hM4Skwkz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 29 Apr 2021 18:15:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 20/30] target/ppc: Mark helper_raise_exception* as noreturn Date: Thu, 29 Apr 2021 18:15:33 -0700 Message-Id: <20210430011543.1017113-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..af5b3586d1 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -1,5 +1,5 @@ -DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, void, env, i32, i32) -DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_3(raise_exception_err, TCG_CALL_NO_WG, noreturn, env, i32, i32) +DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) DEF_HELPER_FLAGS_4(tw, TCG_CALL_NO_WG, void, env, tl, tl, i32) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_4(td, TCG_CALL_NO_WG, void, env, tl, tl, i32) From patchwork Fri Apr 30 01:15:34 2021 Content-Type: text/plain; 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It will have been done immediately before in the log file. Signed-off-by: Richard Henderson --- target/ppc/translate.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index fe3982e289..112afd02d5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8046,11 +8046,7 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) handler->count++; #endif - if (tcg_check_temp_count()) { - qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " - "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), - opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); - } + translator_loop_temp_check(&ctx->base); } static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) From patchwork Fri Apr 30 01:15:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429736 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2110078jao; Thu, 29 Apr 2021 18:29:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUt9TQ1rZslpPXOJPcohxmMTMyRYKJijeg0Ddz7fSTGBeEaYnG5jDoZwcXFY06FVBtjXRo X-Received: by 2002:a02:6d53:: with SMTP id e19mr2554787jaf.128.1619746183375; Thu, 29 Apr 2021 18:29:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746183; cv=none; d=google.com; s=arc-20160816; b=uBuTuG3nxSF5L4dxjq/+6peI9nmHPgwf9NX1xyfVnUs25CgP44MNAMlQhwrbf7qHnY s+2oRR+ePt3PpG5bWz+kh+8W2q9ieY/Y6kKvcy5ppaR0sqLc60ab2v8dwdB4vIN+oL6u lOR1RkU1HLwbxcuGi7m7yOI+b4DW5RhPmiaELJpcM/n0bAQW48uyOlleCoQjIyh5sOIV GI5zcCtGSZ17r5AlIwt2GMk5VZn7Lzuf9GTshmHth8+fQ8a6GGxngYfHcm0X6jQ49cSH /v4Qh04hgy6TN+/Ou7iOzB9mpdGzFw4uDWt8kTnJ2seP7FkrKMBQbLL7/d82UdmxtaiM ISew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+unikDpz5k4psDt6Hvdrjf1plcZuWIxFIQ3ND5/kQ/Y=; b=lttR1merW+I7aw/tqYm4AgMPn3luVypV0hcsjOaKbdgsawG29Dz7EcwuasK98e0b8u u+K//XRsrQcdBx9sKc5/7vPrAEQ6pL0U2HmIv+kf11s3K4DK4XQRr/FIqvJ7BB3TtK3p lYcdxYD+wuQXk4LuQOKdKFRF4+qeQq3OGUxFJH6ti0lNpWIa3L12oGlGx3cgTmHA3L3E zRLbgUzJ/Mx/mFftiu0cTLb6w+Re8df4r9VHUNY5YocrChrEuBNlPsG8Rg+G0uQTiWVe b/fWt/RkNfcrgA0jpALv9Aql/0EsmRY8yIOHXyuhS5SCY2Ubo2Ry6iwJxoTRD8Qtv8Kd AKpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=p56Bjonr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/translate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 112afd02d5..cde12e9d38 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6876,6 +6876,32 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } +/* + * Helpers for trans_* functions to check for specific insns flags. + * Use token pasting to ensure that we use the proper flag with the + * proper variable. + */ +#define REQUIRE_INSNS_FLAGS(CTX, NAME) \ + do { \ + if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ + return false; \ + } \ + } while (0) + +#define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ + do { \ + if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ + return false; \ + } \ + } while (0) + +/* Then special-case the check for 64-bit so that we elide code for ppc32. */ +#if TARGET_LONG_BITS == 32 +# define REQUIRE_64BIT(CTX) return false +#else +# define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) +#endif + #include "translate/fp-impl.c.inc" #include "translate/vmx-impl.c.inc" From patchwork Fri Apr 30 01:15:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429746 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2115046jao; Thu, 29 Apr 2021 18:37:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9RwyKd+BZBVbciIVHmSrBsZaJyy0gNnlmG84nuOKd+2p2iTJjADZbikxOGWCWgsF3+jR+ X-Received: by 2002:a05:6602:140c:: with SMTP id t12mr1655434iov.169.1619746660379; Thu, 29 Apr 2021 18:37:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746660; cv=none; d=google.com; s=arc-20160816; b=fNONZ9Xg7c9Fi6MeAMhahbWCkZ3boZpE7/w/zyr1cL5JNT9pIDqaUY5I/8kVwA0YnW /wSrFGvxeLs/oyTcoYyjF4RyHsT9tL2FYNtPN2NWJYmyOPscxfiv8t1KKmJkt9f0rBHP iWNOjYaZVzG0xzZuPTAbC3CiN+mlQmGEChK4snnuCllW+ckmd/Ek+T0v3jnywrIHHtod L+wHVNwVgRu46cm4khaI+2OtVgyw2E+cMhtYHXqy3q8NLIWqWYQJN42OTKbXa7Z7ii1a V4wWpqmqsn5ZP8EeiISwVXpHBoS50ZkrwHi/FwoPdgAANXeFytu8KepgwesdakPAmo6K U+Hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Z0G20m3/HQxhX+4xgzOfpR38gUGqllNoyp55v0Hp1U0=; b=pN5r7l4IaZmH+OSLoXDyhd3pTjxehqKKbI/DjGI+S7Pi68kx43zfEWJe7LbOfplagr 9L+rwm7Bh7U+LqKQjiltc1Q7Au3PTB9RGuGGIZTMYaTrDr0vy8YdnDTt5Av98szuvsnm CI/ZI7iPBXPTWNIkN+6Vn7xixo+Od5EGVYezw2b6KeBEqBiuRC1TlUOunxBfd2Ex3nEU 5Smwq+Oc+nBZZ2ypmLrbbKJXXKDeZ3Wy9gW2K2M+FJIWoQwbi0a7/PPOypeGa3lknqqG v1+ybrSIlDMx6fSUo2LB9lufj+rCOyS7C6TobPaY4J8cFWH0JTIgpxSQmZv7Khu+3G4o g3BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ndXqGUNR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Luis Pires Signed-off-by: Richard Henderson --- v3: Move page crossing check to its own patch, fold in ISA310 check to is_prefix_insn --- target/ppc/cpu.h | 1 + target/ppc/insn32.decode | 18 ++++++++++++ target/ppc/insn64.decode | 18 ++++++++++++ target/ppc/translate.c | 34 +++++++++++++++++++--- target/ppc/translate/fixedpoint-impl.c.inc | 18 ++++++++++++ target/ppc/meson.build | 9 ++++++ 6 files changed, 94 insertions(+), 4 deletions(-) create mode 100644 target/ppc/insn32.decode create mode 100644 target/ppc/insn64.decode create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc -- 2.25.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5b22eb64dc..82a2bf1e58 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -144,6 +144,7 @@ enum { POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ + POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */ /* Exception subtypes for POWERPC_EXCP_PROGRAM */ /* FP exceptions */ POWERPC_EXCP_FP = 0x10, diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode new file mode 100644 index 0000000000..b175441209 --- /dev/null +++ b/target/ppc/insn32.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 32-bit insns (opcode space 0) +# +# Copyright (c) 2021 Luis Pires +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode new file mode 100644 index 0000000000..9fc45d0614 --- /dev/null +++ b/target/ppc/insn64.decode @@ -0,0 +1,18 @@ +# +# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1) +# +# Copyright (c) 2021 Luis Pires +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# diff --git a/target/ppc/translate.c b/target/ppc/translate.c index cde12e9d38..65848463ea 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6902,6 +6902,10 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif +#include "decode-insn32.c.inc" +#include "decode-insn64.c.inc" +#include "translate/fixedpoint-impl.c.inc" + #include "translate/fp-impl.c.inc" #include "translate/vmx-impl.c.inc" @@ -8047,11 +8051,18 @@ static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, return true; } +static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + return opc1(insn) == 1; +} + static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = cs->env_ptr; + target_ulong pc; uint32_t insn; bool ok; @@ -8059,11 +8070,26 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); - ctx->cia = ctx->base.pc_next; - insn = translator_ldl_swap(env, ctx->base.pc_next, need_byteswap(ctx)); - ctx->base.pc_next += 4; + ctx->cia = pc = ctx->base.pc_next; + insn = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; - ok = decode_legacy(cpu, ctx, insn); + if (!is_prefix_insn(ctx, insn)) { + ok = (decode_insn32(ctx, insn) || + decode_legacy(cpu, ctx, insn)); + } else if ((pc & 63) == 0) { + /* + * Power v3.1, section 1.9 Exceptions: + * attempt to execute a prefixed instruction that crosses a + * 64-byte address boundary (system alignment error). + */ + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); + ok = true; + } else { + uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx)); + ctx->base.pc_next = pc += 4; + ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); + } if (!ok) { gen_invalid(ctx); } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc new file mode 100644 index 0000000000..b740083605 --- /dev/null +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -0,0 +1,18 @@ +/* + * Power ISA decode for Fixed-Point Facility instructions + * + * Copyright (c) 2021 Luis Pires + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ diff --git a/target/ppc/meson.build b/target/ppc/meson.build index bbfef90e08..e604e56c6a 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -15,6 +15,15 @@ ppc_ss.add(files( ppc_ss.add(libdecnumber) +gen = [ + decodetree.process('insn32.decode', + extra_args: '--static-decode=decode_insn32'), + decodetree.process('insn64.decode', + extra_args: ['--static-decode=decode_insn64', + '--insnwidth=64']), +] +ppc_ss.add(gen) + ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) From patchwork Fri Apr 30 01:15:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429747 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2115633jao; Thu, 29 Apr 2021 18:38:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzKFaUV3+aHBegWB4W9gWpCjupgNndUSFksJwmqAZi8Bsosy4CYQfEVyg68DVAPi4i0jZ9z X-Received: by 2002:a9d:1b63:: with SMTP id l90mr1709770otl.306.1619746723082; Thu, 29 Apr 2021 18:38:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746723; cv=none; d=google.com; s=arc-20160816; b=VhM+XiDrc8ZQHlqIeoxivi0XlpGTcXoXb4aNuH7AccHglNo/VH2T2iA2qbSHzh6H8C wlBhlRHnO4ZRG8BR2DbhMbAR+DwDPCJgh+rZSW7fRDxLQLQiuiVLvQkwJQPAsidjxj93 xUywpZFeXTGad8tsCRfZ9efIwXfwdV361iWczc+nEtZkVNErzhEJzOWyc4bNWYM/ns8i a7dLG0gYMEH4rdsv/zCQ/rQEkCqE+SIhEe19IzegyGBe4jCaHFENLxYsyd9Bo3AzIIFt m/5SPP3zc92heVBOKVlwPbS/zSawd4GrGJ+OT+0AznsrQftT/QVGz9teVK8/ZoxKHZ4s R+EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YcK4JXJlH4dCJ4S4ufZcFbDwhd9ORD+at0xFGfdapcw=; b=iYVxwafM5ULF5v33EKCE6Gf57H40xQ8r09oqQwBWOkfRJr+ritaIz5gix4njxWSawQ /HD52jEhQJOtRvBsQjwtmyUK0S18/YdhWdzTYgb84e52sJqdK9crqtsR183x/nhE8IGi CK+d6l2xjl6QbB6zWNQEvXeJRGk3R6bm/b8TsTG3aLfVoKFQjCxB2UPWVVsHONWHFCyA bF/RjEqNOz9zcCkHnkJmLNwTU2g6bZBmRFpI7oqy92svym7Kek+gWYmmUURntDK9UiCq bQAkBz4aK36U22A/Jxc3KNSWkmgq0M3nf8q5/vq0aoMw8Crzxrxqk7yk5e4cm7aPl3TM UK+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tSESPIG2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/ppc/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 65848463ea..d782a13d27 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8019,9 +8019,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { ctx->base.max_insns = 1; - } else { - int bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; - ctx->base.max_insns = MIN(ctx->base.max_insns, bound); } } @@ -8098,6 +8095,11 @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) handler->count++; #endif + /* End the TB when crossing a page boundary. */ + if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } + translator_loop_temp_check(&ctx->base); } From patchwork Fri Apr 30 01:15:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429751 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2117712jao; Thu, 29 Apr 2021 18:42:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhaOsRNew5IBA2hulVTfX6Zp/y7F9B1Tusi85X0X5+yInemE5vYR9HpKX89OaW4utuX9Mb X-Received: by 2002:a92:d444:: with SMTP id r4mr2111810ilm.278.1619746939010; Thu, 29 Apr 2021 18:42:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746939; cv=none; d=google.com; s=arc-20160816; b=Lpscsigbg+sgd48qZikTz8MK4hpwWM7CcpZfyGcVK0BE/8NyD5tHx4FG9ymAMmRyTS 7Ow040Q9N/LR1s4Cz9DN/rlKkN6L3rOKRfVomQ3hCXiPetNpQw7NdW/i41y1VXbVMy64 4NBA28grzpeg9XT9GFYjCy5mSTZSVHIDXmYf/63uZKzS2TBPEl9zfz1oG0MT7yrmjKKD 3keRGK9UFbBPEpXg4CUEdwKOkDqNH0+7DH9rAt+FLZYcrk/Pc7I9RWb0oIbZWOb++oIb 2cWDBF3a2el0HRng2y9g3JD8GQ3Yl1/w5m2mh3X2L9oBVddapxgDDdSorAUo1E8RqChl L15g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZA4bSMjar5L7uXmkw0P7MvAki5DM6E2paFogrNIkUC8=; b=IcvQYJgmyAItoAgpsuaCEvrShfo6owrulSNXh8et6Ok6uvVdUTvqw1k3KxbH/t1FaM NxLceXt9n1Ohrp1nQc9vYqXHdukiEbMLLUAijxYSJHmd4Y3o6kLwT7EJhWbY/TKfxLBq mhap6rClInsKhFvcOPCaVV/Jwv8sVg3dkdi97AZBtZ7ME5nWFPdZHYNCLOEhCM2ql3F/ JSKVBIEVY7l/WfHa5w/Nw+dHWci3zU1PoyENgwQGPEzkd+SMSkysCEJGaVOx0CiUtJez 6F+k1bE1CzafjfzdVyipB0QamKa4glqS7ZPIdtAM8rLkM4YkDVHJ6fsgrVq4h/UWX4Np oeDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ahqxc2v3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Thu, 29 Apr 2021 18:16:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 25/30] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI Date: Thu, 29 Apr 2021 18:15:38 -0700 Message-Id: <20210430011543.1017113-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/ppc/insn32.decode | 12 +++++++ target/ppc/insn64.decode | 15 +++++++++ target/ppc/translate.c | 29 ---------------- target/ppc/translate/fixedpoint-impl.c.inc | 39 ++++++++++++++++++++++ 4 files changed, 66 insertions(+), 29 deletions(-) -- 2.25.1 diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index b175441209..52d9b355d4 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -16,3 +16,15 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +&D rt ra si +@D ...... rt:5 ra:5 si:s16 &D + +# If a prefix is allowed, decode with default values. +&PLS_D rt ra si:int64_t r:bool +@PLS_D ...... rt:5 ra:5 si:s16 &PLS_D r=0 + +### Fixed-Point Arithmetic Instructions + +ADDI 001110 ..... ..... ................ @PLS_D +ADDIS 001111 ..... ..... ................ @D diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 9fc45d0614..f4272df724 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -16,3 +16,18 @@ # You should have received a copy of the GNU Lesser General Public # License along with this library; if not, see . # + +# Many all of these instruction names would be prefixed by "P", +# but we share code with the non-prefixed instruction. + +# Format MLS:D and 8LS:D +&PLS_D rt ra si:int64_t r:bool !extern +%pls_si 32:s18 0:16 +@PLS_D ...... .. ... r:1 .. .................. \ + ...... rt:5 ra:5 ................ \ + &PLS_D si=%pls_si + +### Fixed-Point Arithmetic Instructions + +ADDI 000001 10 0--.-- .................. \ + 001110 ..... ..... ................ @PLS_D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d782a13d27..5a8a3c39c3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -924,19 +924,6 @@ GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); /* addze addze. addzeo addzeo.*/ GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) -/* addi */ -static void gen_addi(DisasContext *ctx) -{ - target_long simm = SIMM(ctx->opcode); - - if (rA(ctx->opcode) == 0) { - /* li case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm); - } -} /* addic addic.*/ static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) { @@ -956,20 +943,6 @@ static void gen_addic_(DisasContext *ctx) gen_op_addic(ctx, 1); } -/* addis */ -static void gen_addis(DisasContext *ctx) -{ - target_long simm = SIMM(ctx->opcode); - - if (rA(ctx->opcode) == 0) { - /* lis case */ - tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); - } else { - tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rA(ctx->opcode)], simm << 16); - } -} - /* addpcis */ static void gen_addpcis(DisasContext *ctx) { @@ -7029,10 +7002,8 @@ GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), -GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), -GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index b740083605..7af1b3bcf5 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -16,3 +16,42 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ + +/* + * Incorporate CIA into the constant when R=1. + * Validate that when R=1, RA=0. + */ +static bool resolve_PLS_D(DisasContext *ctx, arg_PLS_D *a) +{ + if (a->r) { + if (unlikely(a->ra != 0)) { + gen_invalid(ctx); + return false; + } + a->si += ctx->cia; + } + return true; +} + +static bool trans_ADDI(DisasContext *ctx, arg_PLS_D *a) +{ + if (resolve_PLS_D(ctx, a)) { + if (a->ra) { + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], a->si); + } else { + tcg_gen_movi_tl(cpu_gpr[a->rt], a->si); + } + } + return true; +} + +static bool trans_ADDIS(DisasContext *ctx, arg_D *a) +{ + int si = a->si << 16; + if (a->ra) { + tcg_gen_addi_tl(cpu_gpr[a->rt], cpu_gpr[a->ra], si); + } else { + tcg_gen_movi_tl(cpu_gpr[a->rt], si); + } + return true; +} From patchwork Fri Apr 30 01:15:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429738 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2111438jao; 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envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/ppc/insn32.decode | 2 ++ target/ppc/insn64.decode | 11 +++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 5 +++++ 3 files changed, 18 insertions(+) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 52d9b355d4..2ed25c7e67 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -17,6 +17,8 @@ # License along with this library; if not, see . # +&empty + &D rt ra si @D ...... rt:5 ra:5 si:s16 &D diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index f4272df724..5a82ce375e 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -20,6 +20,8 @@ # Many all of these instruction names would be prefixed by "P", # but we share code with the non-prefixed instruction. +&empty !extern + # Format MLS:D and 8LS:D &PLS_D rt ra si:int64_t r:bool !extern %pls_si 32:s18 0:16 @@ -31,3 +33,12 @@ ADDI 000001 10 0--.-- .................. \ 001110 ..... ..... ................ @PLS_D + +### Prefixed No-operation Instruction + +# TODO: diagnose the set of patterns that are illegal: +# branches, rfebb, sync other than isync, or a service processor attention. +# The Engineering Note allows us to either diagnose these as illegal, +# or treat them all as no-op. +NOP 000001 11 0000-- 000000000000000000 \ + -------------------------------- diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 7af1b3bcf5..96b8c38f60 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -55,3 +55,8 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a) } return true; } + +static bool trans_NOP(DisasContext *ctx, arg_NOP *a) +{ + return true; +} From patchwork Fri Apr 30 01:15:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 429749 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2116068jao; Thu, 29 Apr 2021 18:39:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJymwYtrwVrbAshxkkIQWLrmFWA7pRDUoNiSUqlRWu9KZ0trXRMGSomRGG3UTeawLNU52BMU X-Received: by 2002:a05:6e02:12ce:: with SMTP id i14mr2199225ilm.252.1619746764074; Thu, 29 Apr 2021 18:39:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1619746764; cv=none; d=google.com; s=arc-20160816; b=c3i+CQW/r/TuitDLyBNDg2IQ0TDDTseXpYeBxd6Dtyw9OESXgwNxnaFggVgnxZi4Oj mKDupgl8LaQCUrcOTgD+Ysttj19IBFgXCHRfEfOIKiqlEctIOUQK7Ht0Iz0+2D2Akx12 FtiNtQJnxCY9M5gIbwAazMxnz37ABdxBWfUrKWoDrsvmU5wsu9ZESsvfk6rYaBhMQlos etU5o8gokqkH6nCk9g4mOfflMeOeA1rFZm0VakgGdX+q2S5Vz0MPiSEI9l119lIKbvkr uNAr6AhBzw6zKrHFzp/y5O6pxDpTCDbQLQ3vCFVluExrWCBnxrEKlSh3Hdyzfb+3z0q6 0ZhQ== ARC-Message-Signature: i=1; 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Decode the D and DS forms into the PLS_D argument set so that prefixed insns can share code. Signed-off-by: Richard Henderson --- target/ppc/insn32.decode | 37 ++++++ target/ppc/translate.c | 145 ++++----------------- target/ppc/translate/fixedpoint-impl.c.inc | 114 ++++++++++++++++ 3 files changed, 174 insertions(+), 122 deletions(-) -- 2.25.1 diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 2ed25c7e67..1c1b4620fc 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -26,6 +26,43 @@ &PLS_D rt ra si:int64_t r:bool @PLS_D ...... rt:5 ra:5 si:s16 &PLS_D r=0 +%ds_si 2:s14 !function=times_4 +@PLS_DS ...... rt:5 ra:5 .............. .. &PLS_D si=%ds_si r=0 + +&X rt ra rb +@X ...... rt:5 ra:5 rb:5 .......... . &X + +### Fixed-Point Load Instructions + +LBZ 100010 ..... ..... ................ @PLS_D +LBZU 100011 ..... ..... ................ @PLS_D +LBZX 011111 ..... ..... ..... 0001010111 - @X +LBZUX 011111 ..... ..... ..... 0001110111 - @X + +LHZ 101000 ..... ..... ................ @PLS_D +LHZU 101001 ..... ..... ................ @PLS_D +LHZX 011111 ..... ..... ..... 0100010111 - @X +LHZUX 011111 ..... ..... ..... 0100110111 - @X + +LHA 101010 ..... ..... ................ @PLS_D +LHAU 101011 ..... ..... ................ @PLS_D +LHAX 011111 ..... ..... ..... 0101010111 - @X +LHAXU 011111 ..... ..... ..... 0101110111 - @X + +LWZ 100000 ..... ..... ................ @PLS_D +LWZU 100001 ..... ..... ................ @PLS_D +LWZX 011111 ..... ..... ..... 0000010111 - @X +LWZUX 011111 ..... ..... ..... 0000110111 - @X + +LWA 111010 ..... ..... ..............10 @PLS_DS +LWAX 011111 ..... ..... ..... 0101010101 - @X +LWAUX 011111 ..... ..... ..... 0101110101 - @X + +LD 111010 ..... ..... ..............00 @PLS_DS +LDU 111010 ..... ..... ..............01 @PLS_DS +LDX 011111 ..... ..... ..... 0000010101 - @X +LDUX 011111 ..... ..... ..... 0000110101 - @X + ### Fixed-Point Arithmetic Instructions ADDI 001110 ..... ..... ................ @PLS_D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5a8a3c39c3..1fdb501ee9 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2487,54 +2487,6 @@ GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) #endif -#define GEN_LD(name, ldop, opc, type) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_LDU(name, ldop, opc, type) \ -static void glue(gen_, name##u)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0 || \ - rA(ctx->opcode) == rD(ctx->opcode))) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - if (type == PPC_64B) \ - gen_addr_imm_index(ctx, EA, 0x03); \ - else \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_LDUX(name, ldop, opc2, opc3, type) \ -static void glue(gen_, name##ux)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0 || \ - rA(ctx->opcode) == rD(ctx->opcode))) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ static void glue(gen_, name##x)(DisasContext *ctx) \ { \ @@ -2553,21 +2505,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) -#define GEN_LDS(name, ldop, op, type) \ -GEN_LD(name, ldop, op | 0x20, type); \ -GEN_LDU(name, ldop, op | 0x21, type); \ -GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ -GEN_LDX(name, ldop, 0x17, op | 0x00, type) - -/* lbz lbzu lbzux lbzx */ -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); -/* lha lhau lhaux lhax */ -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); -/* lhz lhzu lhzux lhzx */ -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); -/* lwz lwzu lwzux lwzx */ -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); - #define GEN_LDEPX(name, ldop, opc2, opc3) \ static void glue(gen_, name##epx)(DisasContext *ctx) \ { \ @@ -2588,47 +2525,12 @@ GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) #endif #if defined(TARGET_PPC64) -/* lwaux */ -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); -/* lwax */ -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); -/* ldux */ -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); -/* ldx */ -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); - /* CI load/store variants */ GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) -static void gen_ld(DisasContext *ctx) -{ - TCGv EA; - if (Rc(ctx->opcode)) { - if (unlikely(rA(ctx->opcode) == 0 || - rA(ctx->opcode) == rD(ctx->opcode))) { - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - return; - } - } - gen_set_access_type(ctx, ACCESS_INT); - EA = tcg_temp_new(); - gen_addr_imm_index(ctx, EA, 0x03); - if (ctx->opcode & 0x02) { - /* lwa (lwau is undefined) */ - gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); - } else { - /* ld - ldu */ - gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); - } - if (Rc(ctx->opcode)) { - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); - } - tcg_temp_free(EA); -} - /* lq */ static void gen_lq(DisasContext *ctx) { @@ -6849,6 +6751,14 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } +/* + * Helpers for decodetree used by !function for decoding arguments. + */ +static int times_4(DisasContext *ctx, int x) +{ + return x * 4; +} + /* * Helpers for trans_* functions to check for specific insns flags. * Use token pasting to ensure that we use the proper flag with the @@ -6875,6 +6785,21 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) #endif +/* + * Helpers for implementing sets of trans_* functions. + * Defer the implementation of NAME to FUNC, with optional extra arguments. + */ +#define TRANS(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { return FUNC(ctx, a, __VA_ARGS__); } + +#define TRANS64(NAME, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ + { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } + +/* TODO: More TRANS* helpers for extra insn_flags checks. */ + + #include "decode-insn32.c.inc" #include "decode-insn64.c.inc" #include "translate/fixedpoint-impl.c.inc" @@ -7059,7 +6984,6 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, PPC_NONE, PPC2_ISA300), #endif #if defined(TARGET_PPC64) -GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), #endif @@ -7425,34 +7349,11 @@ GEN_PPC64_R2(rldcr, 0x1E, 0x09), GEN_PPC64_R4(rldimi, 0x1E, 0x06), #endif -#undef GEN_LD -#undef GEN_LDU -#undef GEN_LDUX #undef GEN_LDX_E -#undef GEN_LDS -#define GEN_LD(name, ldop, opc, type) \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDU(name, ldop, opc, type) \ -GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_LDUX(name, ldop, opc2, opc3, type) \ -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), -#define GEN_LDS(name, ldop, op, type) \ -GEN_LD(name, ldop, op | 0x20, type) \ -GEN_LDU(name, ldop, op | 0x21, type) \ -GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ -GEN_LDX(name, ldop, 0x17, op | 0x00, type) -GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) -GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) -GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) -GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) #if defined(TARGET_PPC64) -GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) -GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) -GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) -GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) /* HV/P7 and later only */ diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 96b8c38f60..cb3219c996 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -33,6 +33,120 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_PLS_D *a) return true; } +/* + * Fixed-Point Load/Store Instructions + */ + +static bool do_ldst_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool update, + bool store, MemOp mop) +{ + TCGv ea; + + if (!resolve_PLS_D(ctx, a)) { + return true; + } + if (update && (a->ra == 0 || (!store && a->ra == a->rt))) { + gen_invalid(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + + ea = tcg_temp_new(); + if (a->ra) { + tcg_gen_addi_tl(ea, cpu_gpr[a->ra], a->si); + } else { + tcg_gen_movi_tl(ea, a->si); + } + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(ea, ea); + } + mop ^= ctx->default_tcg_memop_mask; + if (store) { + tcg_gen_qemu_st_tl(cpu_gpr[a->rt], ea, ctx->mem_idx, mop); + } else { + tcg_gen_qemu_ld_tl(cpu_gpr[a->rt], ea, ctx->mem_idx, mop); + } + if (update) { + tcg_gen_mov_tl(cpu_gpr[a->ra], ea); + } + tcg_temp_free(ea); + + return true; +} + +static bool do_ldst_X(DisasContext *ctx, arg_X *a, bool update, + bool store, MemOp mop) +{ + TCGv ea; + + if (update && (a->ra == 0 || (!store && a->ra == a->rt))) { + gen_invalid(ctx); + return true; + } + gen_set_access_type(ctx, ACCESS_INT); + + ea = tcg_temp_new(); + if (a->ra) { + tcg_gen_add_tl(ea, cpu_gpr[a->ra], cpu_gpr[a->rb]); + } else { + tcg_gen_mov_tl(ea, cpu_gpr[a->rb]); + } + if (NARROW_MODE(ctx)) { + tcg_gen_ext32u_tl(ea, ea); + } + mop ^= ctx->default_tcg_memop_mask; + if (store) { + tcg_gen_qemu_st_tl(cpu_gpr[a->rt], ea, ctx->mem_idx, mop); + } else { + tcg_gen_qemu_ld_tl(cpu_gpr[a->rt], ea, ctx->mem_idx, mop); + } + if (update) { + tcg_gen_mov_tl(cpu_gpr[a->ra], ea); + } + tcg_temp_free(ea); + + return true; +} + +/* Load Byte and Zero */ +TRANS(LBZ, do_ldst_PLS_D, false, false, MO_UB) +TRANS(LBZX, do_ldst_X, false, false, MO_UB) +TRANS(LBZU, do_ldst_PLS_D, true, false, MO_UB) +TRANS(LBZUX, do_ldst_X, true, false, MO_UB) + +/* Load Halfword and Zero */ +TRANS(LHZ, do_ldst_PLS_D, false, false, MO_UW) +TRANS(LHZX, do_ldst_X, false, false, MO_UW) +TRANS(LHZU, do_ldst_PLS_D, true, false, MO_UW) +TRANS(LHZUX, do_ldst_X, true, false, MO_UW) + +/* Load Halfword Algebraic */ +TRANS(LHA, do_ldst_PLS_D, false, false, MO_SW) +TRANS(LHAX, do_ldst_X, false, false, MO_SW) +TRANS(LHAU, do_ldst_PLS_D, true, false, MO_SW) +TRANS(LHAXU, do_ldst_X, true, false, MO_SW) + +/* Load Word and Zero */ +TRANS(LWZ, do_ldst_PLS_D, false, false, MO_UL) +TRANS(LWZX, do_ldst_X, false, false, MO_UL) +TRANS(LWZU, do_ldst_PLS_D, true, false, MO_UL) +TRANS(LWZUX, do_ldst_X, true, false, MO_UL) + +/* Load Word Algebraic */ +TRANS64(LWA, do_ldst_PLS_D, false, false, MO_SL) +TRANS64(LWAX, do_ldst_X, false, false, MO_SL) +TRANS64(LWAUX, do_ldst_X, true, false, MO_SL) + +/* Load Doubleword */ +TRANS64(LD, do_ldst_PLS_D, false, false, MO_Q) +TRANS64(LDX, do_ldst_X, false, false, MO_Q) +TRANS64(LDU, do_ldst_PLS_D, true, false, MO_Q) +TRANS64(LDUX, do_ldst_X, true, false, MO_Q) + +/* + * Fixed-Point Arithmetic Instructions + */ + static bool trans_ADDI(DisasContext *ctx, arg_PLS_D *a) { if (resolve_PLS_D(ctx, a)) { From patchwork Fri Apr 30 01:15:41 2021 Content-Type: text/plain; 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Thu, 29 Apr 2021 18:16:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 28/30] target/ppc: Implement prefixed integer load instructions Date: Thu, 29 Apr 2021 18:15:41 -0700 Message-Id: <20210430011543.1017113-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430011543.1017113-1-richard.henderson@linaro.org> References: <20210430011543.1017113-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/ppc/insn64.decode | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.25.1 diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 5a82ce375e..4198e5c8f3 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -29,6 +29,21 @@ ...... rt:5 ra:5 ................ \ &PLS_D si=%pls_si +### Fixed-Point Load Instructions + +LBZ 000001 10 0--.-- .................. \ + 100010 ..... ..... ................ @PLS_D +LHZ 000001 10 0--.-- .................. \ + 101000 ..... ..... ................ @PLS_D +LHA 000001 10 0--.-- .................. \ + 101010 ..... ..... ................ @PLS_D +LWZ 000001 10 0--.-- .................. \ + 100000 ..... ..... ................ @PLS_D +LWA 000001 00 0--.-- .................. \ + 101001 ..... ..... ................ @PLS_D +LD 000001 00 0--.-- .................. \ + 111001 ..... ..... ................ @PLS_D + ### Fixed-Point Arithmetic Instructions ADDI 000001 10 0--.-- .................. \ From patchwork Fri Apr 30 01:15:42 2021 Content-Type: text/plain; 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Signed-off-by: Richard Henderson --- target/ppc/insn32.decode | 22 ++++++ target/ppc/translate.c | 83 +--------------------- target/ppc/translate/fixedpoint-impl.c.inc | 24 +++++++ 3 files changed, 48 insertions(+), 81 deletions(-) -- 2.25.1 diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 1c1b4620fc..7d35f61e45 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -63,6 +63,28 @@ LDU 111010 ..... ..... ..............01 @PLS_DS LDX 011111 ..... ..... ..... 0000010101 - @X LDUX 011111 ..... ..... ..... 0000110101 - @X +### Fixed-Point Store Instructions + +STB 100110 ..... ..... ................ @PLS_D +STBU 100111 ..... ..... ................ @PLS_D +STBX 011111 ..... ..... ..... 0011010111 - @X +STBUX 011111 ..... ..... ..... 0011110111 - @X + +STH 101100 ..... ..... ................ @PLS_D +STHU 101101 ..... ..... ................ @PLS_D +STHX 011111 ..... ..... ..... 0110010111 - @X +STHUX 011111 ..... ..... ..... 0110110111 - @X + +STW 100100 ..... ..... ................ @PLS_D +STWU 100101 ..... ..... ................ @PLS_D +STWX 011111 ..... ..... ..... 0010010111 - @X +STWUX 011111 ..... ..... ..... 0010110111 - @X + +STD 111110 ..... ..... ..............00 @PLS_DS +STDU 111110 ..... ..... ..............01 @PLS_DS +STDX 011111 ..... ..... ..... 0010010101 - @X +STDUX 011111 ..... ..... ..... 0010110101 - @X + ### Fixed-Point Arithmetic Instructions ADDI 001110 ..... ..... ................ @PLS_D diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1fdb501ee9..ad32fcc740 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -2463,7 +2463,9 @@ static void glue(gen_qemu_, stop)(DisasContext *ctx, \ tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ } +#if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) +#endif GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) @@ -2596,52 +2598,6 @@ static void gen_lq(DisasContext *ctx) #endif /*** Integer store ***/ -#define GEN_ST(name, stop, opc, type) \ -static void glue(gen_, name)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_STU(name, stop, opc, type) \ -static void glue(gen_, stop##u)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - if (type == PPC_64B) \ - gen_addr_imm_index(ctx, EA, 0x03); \ - else \ - gen_addr_imm_index(ctx, EA, 0); \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - -#define GEN_STUX(name, stop, opc2, opc3, type) \ -static void glue(gen_, name##ux)(DisasContext *ctx) \ -{ \ - TCGv EA; \ - if (unlikely(rA(ctx->opcode) == 0)) { \ - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ - return; \ - } \ - gen_set_access_type(ctx, ACCESS_INT); \ - EA = tcg_temp_new(); \ - gen_addr_reg_index(ctx, EA); \ - gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ - tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ - tcg_temp_free(EA); \ -} - #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ static void glue(gen_, name##x)(DisasContext *ctx) \ { \ @@ -2659,19 +2615,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) -#define GEN_STS(name, stop, op, type) \ -GEN_ST(name, stop, op | 0x20, type); \ -GEN_STU(name, stop, op | 0x21, type); \ -GEN_STUX(name, stop, 0x17, op | 0x01, type); \ -GEN_STX(name, stop, 0x17, op | 0x00, type) - -/* stb stbu stbux stbx */ -GEN_STS(stb, st8, 0x06, PPC_INTEGER); -/* sth sthu sthux sthx */ -GEN_STS(sth, st16, 0x0C, PPC_INTEGER); -/* stw stwu stwux stwx */ -GEN_STS(stw, st32, 0x04, PPC_INTEGER); - #define GEN_STEPX(name, stop, opc2, opc3) \ static void glue(gen_, name##epx)(DisasContext *ctx) \ { \ @@ -2693,8 +2636,6 @@ GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) #endif #if defined(TARGET_PPC64) -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) @@ -7378,31 +7319,11 @@ GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) #endif -#undef GEN_ST -#undef GEN_STU -#undef GEN_STUX #undef GEN_STX_E -#undef GEN_STS -#define GEN_ST(name, stop, opc, type) \ -GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STU(name, stop, opc, type) \ -GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), -#define GEN_STUX(name, stop, opc2, opc3, type) \ -GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), -#define GEN_STS(name, stop, op, type) \ -GEN_ST(name, stop, op | 0x20, type) \ -GEN_STU(name, stop, op | 0x21, type) \ -GEN_STUX(name, stop, 0x17, op | 0x01, type) \ -GEN_STX(name, stop, 0x17, op | 0x00, type) -GEN_STS(stb, st8, 0x06, PPC_INTEGER) -GEN_STS(sth, st16, 0x0C, PPC_INTEGER) -GEN_STS(stw, st32, 0x04, PPC_INTEGER) #if defined(TARGET_PPC64) -GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) -GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index cb3219c996..6d57f0038b 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -143,6 +143,30 @@ TRANS64(LDX, do_ldst_X, false, false, MO_Q) TRANS64(LDU, do_ldst_PLS_D, true, false, MO_Q) TRANS64(LDUX, do_ldst_X, true, false, MO_Q) +/* Store Byte */ +TRANS(STB, do_ldst_PLS_D, false, true, MO_UB) +TRANS(STBX, do_ldst_X, false, true, MO_UB) +TRANS(STBU, do_ldst_PLS_D, true, true, MO_UB) +TRANS(STBUX, do_ldst_X, true, true, MO_UB) + +/* Store Halfword */ +TRANS(STH, do_ldst_PLS_D, false, true, MO_UW) +TRANS(STHX, do_ldst_X, false, true, MO_UW) +TRANS(STHU, do_ldst_PLS_D, true, true, MO_UW) +TRANS(STHUX, do_ldst_X, true, true, MO_UW) + +/* Store Word */ +TRANS(STW, do_ldst_PLS_D, false, true, MO_UL) +TRANS(STWX, do_ldst_X, false, true, MO_UL) +TRANS(STWU, do_ldst_PLS_D, true, true, MO_UL) +TRANS(STWUX, do_ldst_X, true, true, MO_UL) + +/* Store Doubleword */ +TRANS64(STD, do_ldst_PLS_D, false, true, MO_Q) +TRANS64(STDX, do_ldst_X, false, true, MO_Q) +TRANS64(STDU, do_ldst_PLS_D, true, true, MO_Q) +TRANS64(STDUX, do_ldst_X, true, true, MO_Q) + /* * Fixed-Point Arithmetic Instructions */ From patchwork Fri Apr 30 01:15:43 2021 Content-Type: text/plain; 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envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, luis.pires@eldorado.org.br, qemu-ppc@nongnu.org, lagarcia@br.ibm.com, bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/ppc/insn64.decode | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.25.1 diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index 4198e5c8f3..7a71a7a3bb 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -44,6 +44,18 @@ LWA 000001 00 0--.-- .................. \ LD 000001 00 0--.-- .................. \ 111001 ..... ..... ................ @PLS_D +### Fixed-Point Store Instructions + +STW 000001 10 0--.-- .................. \ + 100100 ..... ..... ................ @PLS_D +STB 000001 10 0--.-- .................. \ + 100110 ..... ..... ................ @PLS_D +STH 000001 10 0--.-- .................. \ + 101100 ..... ..... ................ @PLS_D + +STD 000001 00 0--.-- .................. \ + 111101 ..... ..... ................ @PLS_D + ### Fixed-Point Arithmetic Instructions ADDI 000001 10 0--.-- .................. \