From patchwork Thu Jun 21 08:13:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 139507 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1761860lji; Thu, 21 Jun 2018 01:13:23 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLlflakv0Ttj1JJy0u8YXLa6TF8EuB1ThGB5Y8S4ZbGt18xQSXV0dp7kg8GjkTKJH/cyy5p X-Received: by 2002:a65:47cc:: with SMTP id f12-v6mr21660242pgs.173.1529568803213; Thu, 21 Jun 2018 01:13:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529568803; cv=none; d=google.com; s=arc-20160816; b=XVssT/k3/3INpQNqikrOCKyN/I3V5ONcSGUCaFQwGOQzFohDyVky95cAcORTLPc0SB Ed90pcSNfL4yR54msR3CPEJReZV6JmilcDlKbeqvvsX0tS8obd9Rv8X+OX1Jm2pjnrnK w5fejqOy7f9YUUEuwjUQa8N1+kjAPVw4WvZbQ7qw65zPoZtZHItwoKXLiHSkwmrpQBOT HCtR12dNnzQ1JJNicLgCCn3f5ea30akkbi+ZW6JzlONtfv8YXOJEF3HOc+0CyWHdFnKe 8pon5zxzTwsXU932t1RT4PLdAGR4VNQiEnfmxq62N9D8S5hirQPCakM3RT4p6l6Vqu1/ 7LIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=dBcaUq9R5qvjwAdTJD3gCrcJ1ZCsA5MQe4Mj+34sDnY=; b=GB6W8xUzy76yrETeFxyIe14Ha/MEPNLj4/Fly6ZoetXDViEy8ZMRLFKB5Mf0y/sIpc eS9hHPqAEyKZoViSwxGgZ/qqw+QTV38NxvUsVqdbE5PrGqPmTRor1AlFz1tSNUeiyDws MLu2pqtdj6TDnoAZzoLNcLbjt1i0gQaTrrRdWy685gTlToQJkG18naDsfMDS7laAT/79 ZJqfVoAbxMEgKeR73x1A/B/NVn9Us4ZfSVB3tgiqjHCNIvBgbM7KLCFYzokYmajnbLrF qH/4LxnTCNYPLpoqHqGKyhp3QnjhwpAa+VOJWhb0cMoT9XvQx7zhAvfKNwfebJX+H5GN qAPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kwCvtReE; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id f12-v6si3447488pgn.459.2018.06.21.01.13.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kwCvtReE; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CA6BA211DB43F; Thu, 21 Jun 2018 01:13:22 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D3EF8211C8302 for ; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id f16-v6so2162696wrm.3 for ; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R+Lo6Atv3Y/KMTl59+QeCsQFql15WuO17UHq1O9S9gw=; b=kwCvtReEylkLl5OyguPSlUeLkPTT7iJDDXiJhlHBSOfWsPX9dHY+m1KEbrYLh2CM2O jRUb5tae374DdHAElchMJaEOGllJFYSQfS6VEs5qGC90hH+A+LJUjYUdGVy/4cSeGlQJ 6t6PX0yp5JoFXwNxri6/GP2PznPDWmPLzPZIc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R+Lo6Atv3Y/KMTl59+QeCsQFql15WuO17UHq1O9S9gw=; b=Wzwv7TC/9SRzjPYQ1ugrFPq6iuf4yBtk4Moo365cSViUjq3MsOiCuGGLjHN1QVPlKY 9kuDQpwE9nmbJ8MmHy4TXAZzSH2rO7PhpdQqDYLhNYPxWoyEB+EPz78Ld05ciOMl1f9G KT2eCJYau+rgFVoq6ykehyB6kXdO7v1tYkO54YrAQ5vy5nqO8C49AZBCuVPlvVYIGMgX upjPeF0yzPrnTV6Doxi6bY2llp+r85XnF2kGHZFG83XeIsa3jrccDlF5pzuGfjTlWkbR d/+vETOt65y8iFyO7xcr9C+M0SrfqCODlpXwXwrM+M0t7Die1FLiC1z5h36qfxVc3tSy ws6Q== X-Gm-Message-State: APt69E0luzOCoVMG6iPsWOLyFgYEXB6ePvrxczgIlvk0ZECU82sb5but OPCdHalEt1i42xEMBugF4EmOpK6UXWI= X-Received: by 2002:a5d:4306:: with SMTP id h6-v6mr21206260wrq.58.1529568800166; Thu, 21 Jun 2018 01:13:20 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:104b:ef1a:8c01:a5bb]) by smtp.gmail.com with ESMTPSA id q17-v6sm4803152wro.30.2018.06.21.01.13.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:18 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 21 Jun 2018 10:13:14 +0200 Message-Id: <20180621081315.16228-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621081315.16228-1-ard.biesheuvel@linaro.org> References: <20180621081315.16228-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 1/2] ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contents X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Peculiarly enough, the current page table manipulation code takes it upon itself to write back and invalidate the memory contents covered by section mappings when their memory attributes change. It is not generally the case that data must be written back when such a change occurs, even when switching from cacheable to non-cacheable attributes, and in some cases, it is actually causing problems. (The cache maintenance is also performed on the PCIe MMIO regions as they get mapped by the PCI bus driver, and under virtualization, each cache maintenance operation on an emulated MMIO region triggers a round trip to the host and back) So let's just drop this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 12 ------------ 1 file changed, 12 deletions(-) -- 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index 9bf4ba03fd5b..9c2578979e44 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -597,12 +597,6 @@ UpdatePageEntries ( if (CurrentPageTableEntry != PageTableEntry) { Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); - // Clean/invalidate the cache for this page, but only - // if we are modifying the memory type attributes - if (((CurrentPageTableEntry ^ PageTableEntry) & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) != 0) { - WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE); - } - // Only need to update if we are changing the entry PageTable[PageTableIndex] = PageTableEntry; ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva); @@ -718,12 +712,6 @@ UpdateSectionEntries ( if (CurrentDescriptor != Descriptor) { Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT); - // Clean/invalidate the cache for this section, but only - // if we are modifying the memory type attributes - if (((CurrentDescriptor ^ Descriptor) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) != 0) { - WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB); - } - // Only need to update if we are changing the descriptor FirstLevelTable[FirstLevelIdx + i] = Descriptor; ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva); From patchwork Thu Jun 21 08:13:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 139508 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp1761914lji; Thu, 21 Jun 2018 01:13:26 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLZbuaYmUKhbrgBDM2cfuXHNc629Lk4nAYG/SYc31yOM3RhT5jrjkka6eESPz+Bpd/TViBZ X-Received: by 2002:a63:aa4c:: with SMTP id x12-v6mr21068246pgo.387.1529568806014; Thu, 21 Jun 2018 01:13:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529568806; cv=none; d=google.com; s=arc-20160816; b=iRvdDWujplhLZMBeJJXRlycwiRq006S/+H4QGLEPFrkH3KpdFhGNBg3lPUBMAts0hv FDGmxLyMEyhy1uIIP1QNUdVJ5VNRsMPOzIYDjDjbOS0Cc59bmmRrufKuiyJLUPJSMkls ylsfwRqrOCv8vbGa2XFHKpiL5m/ms5BJsvmuWNwgeZOSOVyfbNst7wLb+eXfXV7Sw1XW l42NMXxVhV+DJ4bm1fGeV2eEb2Nv+VPsjOqi0diEZMiO2MKMg9I2SM//yfuwm2JL3qO+ D/pQuKqjgpVlK8HJUyW4oJktQ9IwzqtVcytK55QteVLcxdWI0lLX/Ubv7NC5yIP3sNrL EkSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=skcoZYHABGnspugWJOl6ZKUpKhNnYCwFgpwQOCYYSjw=; b=Xz/u1BwGVjuJ2On4uzYD1cCdvLaoiXC0D/2zUQNQPugkb8yTx8UQjtehA1RrPzR0L6 qJy5uzEBUkUQ9XFk4HLw3b9RlocICfOpUrXL8/zZrW4AXzm7seTfQghXcCJKLC9T1d4e h3jq3MVhKWceHvZ5fSEhiUJG50vHnCsG0RqkcU+yT/sVJ0mXXeE0Jl4Xoi2wYkhdJWRn OHrDCMnWiWfmyFMqGslnghMaNzWr8+PoyLKbbsQIxl3CCoAyKHYNayToLD5gJoKBGDcE YJQNgVDDZinBfxL/i15McA6m6Fb2/gWWp1W8C5YW48RuzOd93riKc8fn7pE0auGPULVj 0Vtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=A2EMMckZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id 97-v6si4555932pld.345.2018.06.21.01.13.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=A2EMMckZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 06E9D211DBE04; Thu, 21 Jun 2018 01:13:25 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3082A211C8302 for ; Thu, 21 Jun 2018 01:13:23 -0700 (PDT) Received: by mail-wr0-x242.google.com with SMTP id k16-v6so2163616wro.0 for ; Thu, 21 Jun 2018 01:13:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xQ8MhwOxfAim2qnrZ0l4y2It3bLdPmUEOfX6l3rj+lk=; b=A2EMMckZgJnDBSSpi1sT0tN8k+Tt5sPpUqv3RPRwqbL+E3rnGfvoqb4+yEE3pWjewa a1EHkv9eP+5xa4usrwwxWP0v0oxVAL3TtEOUxDUNv2BFWm4sr9JsK7qloW3Ssy39oORI O+P5JKSTXUKvuz38oBfixI6JtjJ/M8q2lDLXY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xQ8MhwOxfAim2qnrZ0l4y2It3bLdPmUEOfX6l3rj+lk=; b=NoW+IHpGX+pNictyDf6vASKCnboTu3xFVwUfs/dm5I+cyeL/5WJMdok+EHgCGSVgVl v1GPBfE/6tI91GNroF7I4GIpa8Eka7cxlHlJPBEhZwqqvTeluZrwqFpcvHGJW1+y3aLH jHCM3aO8OflCUyYaGeJ7KrecVvcEqj1WyCVle6zQaeQHLTG6rtFS2SLkHcrhDPpObRzt BuNit2X7cXr4T3uhiQRUGzCDtkLeRMBzWhyBciqX+Y4WgaVCSuuiX3pHMSZu/412+DVC 4erICECIlF8ab3cDuP+PTbvUwdo3g88yXU2DD1DBUBzDP9anCXCyJnigrdvUnxuOx5lU cPuw== X-Gm-Message-State: APt69E0Bnh4qhmbnpQx+y7oHM8naRhbQWDwf/ycODPLRan7ZDJ2/USAA ZM4yIQaoClCBodAQiWvncRCF63rTNpA= X-Received: by 2002:adf:bd89:: with SMTP id l9-v6mr20970050wrh.266.1529568801489; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:104b:ef1a:8c01:a5bb]) by smtp.gmail.com with ESMTPSA id q17-v6sm4803152wro.30.2018.06.21.01.13.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:20 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 21 Jun 2018 10:13:15 +0200 Message-Id: <20180621081315.16228-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621081315.16228-1-ard.biesheuvel@linaro.org> References: <20180621081315.16228-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 2/2] ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 2 -- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 14 +++----------- 2 files changed, 3 insertions(+), 13 deletions(-) -- 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S index 149b57e059ee..f2a517671f0a 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress) // IN VOID *MVA // R1 // ); ASM_FUNC(ArmUpdateTranslationTableEntry) - mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA - dsb mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp dsb diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index 9c2578979e44..3037b642d40c 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -343,17 +343,12 @@ ArmConfigureMmu ( } // Translate the Memory Attributes into Translation Table Register Attributes - if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) { - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || + if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) { - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH; } else { - ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to. + // Page tables must reside in memory mapped as writeback cacheable + ASSERT (0); return RETURN_UNSUPPORTED; } @@ -461,9 +456,6 @@ ConvertSectionToPages ( PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor; } - // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks - WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE_SIZE); - // Formulate page table entry, Domain=0, NS=0 PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;