From patchwork Tue May 4 05:52:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430808 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3492405jao; Mon, 3 May 2021 23:03:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyw9u9r6KuPhqtI6QjZ3f4KUlcbvBknD4MMlld4/aGEtnkt10XeKBeCVXEiXDJvh2tFPI4h X-Received: by 2002:a05:6122:72b:: with SMTP id 43mr10171761vki.11.1620108206006; Mon, 03 May 2021 23:03:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108206; cv=none; d=google.com; s=arc-20160816; b=yyZI2DCBpseOorCHhCFZGzR35Z4pnK6RvzwmKSQ+yk9sQctqwaAIUC4z6qUxwLw4r3 myUdGEHt3Oweev+wue4TfZKc4Y/TglZHa4scoz63abDgTl1ZBircYuVC0I05Qbelz4sr NENax22qNgJeO2X2mkNNz+5/ZtNik85I6diOi3Qx3x8s0HstFl2x9xNiEBoXw7BahtiN K4VJxfZHCiHiy1PiBiwJFpEWYI4FJbSsFdWGxTtoZXYq0mRRPfb2vIFxaNKm/LoXET7X 3zFOSN3c1IzK7hvXAwvBW3BP2K/r8Coy/VPRkhXVavxROmS6PmSmd/sNVPTB81iH1lwd zhJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZAjEDdAs3zwk1abv5CCShEO46AT+5r0TGXYo+kRjfg4=; b=fGWM67OlqM9VkIwGvC+qdMMUXNn/kDQP7DhPIUPq5SfnhXmo05PqBAuX9RhxU0lCln d5fxP4pRJ1DUQXGT6dLUWyGketTu9VtT5bYuM0/i1Vwd1jyJtVL44/oo2RtY6Fom1Rk/ RmWKLmRidOSzDUT0Mt3+aptsb2YORyPbkumyfDnogrHrSnkM6S6BE5P+fF6ntfdk0NQM sh3Zovz9NG1I7ExRqTDcP32mxO8QMdkXSmZ25PglU4dUevrVZV1g6dV9UPmdXYERodXc yWpAPwhoOInMNd7NTtPyj8R9zIyGZ4y1Iaf3g8xJG+Y9jPYKt3awcNakPi7dj+mQyog6 8xBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=LyAZ7IzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s129si6116944vsc.283.2021.05.03.23.03.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:03:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=LyAZ7IzZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:35902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo9V-0004vC-BL for patch@linaro.org; Tue, 04 May 2021 02:03:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60368) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzr-00058k-F5; Tue, 04 May 2021 01:53:27 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:47715) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzn-0004a1-Ja; Tue, 04 May 2021 01:53:27 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CJ6ZtNz9sW8; Tue, 4 May 2021 15:53:16 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107596; bh=oiyPiLUSEfVDN6Hic2i2vSkbwYSlKuLN7VQdHYLVgoY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LyAZ7IzZz10+CT9EWyh/J3F7XAiZUWobA2q3TDeu2JzbfPdYRMpBYcGPm0lO4ArX4 fXwvJ8RPC+M/Pg3+oPLdbfseHTHP8LfM6npDVn32OBvp/wDhJf/JB9n1xvhK3usvnn CzKa0aserH9BDDmI1BnpjDzCY1UP+EyRfw+UcK/Y= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 02/46] target/ppc: Move helper_regs.h functions out-of-line Date: Tue, 4 May 2021 15:52:28 +1000 Message-Id: <20210504055312.306823-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Move the functions to a new file, helper_regs.c. Note int_helper.c was relying on helper_regs.h to indirectly include qemu/log.h. Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-2-richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/helper_regs.c | 197 +++++++++++++++++++++++++++++++++++++++ target/ppc/helper_regs.h | 184 ++---------------------------------- target/ppc/int_helper.c | 1 + target/ppc/meson.build | 1 + 4 files changed, 207 insertions(+), 176 deletions(-) create mode 100644 target/ppc/helper_regs.c -- 2.31.1 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c new file mode 100644 index 0000000000..5e18232b84 --- /dev/null +++ b/target/ppc/helper_regs.c @@ -0,0 +1,197 @@ +/* + * PowerPC emulation special registers manipulation helpers for qemu. + * + * Copyright (c) 2003-2007 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "sysemu/kvm.h" +#include "helper_regs.h" + +/* Swap temporary saved registers with GPRs */ +void hreg_swap_gpr_tgpr(CPUPPCState *env) +{ + target_ulong tmp; + + tmp = env->gpr[0]; + env->gpr[0] = env->tgpr[0]; + env->tgpr[0] = tmp; + tmp = env->gpr[1]; + env->gpr[1] = env->tgpr[1]; + env->tgpr[1] = tmp; + tmp = env->gpr[2]; + env->gpr[2] = env->tgpr[2]; + env->tgpr[2] = tmp; + tmp = env->gpr[3]; + env->gpr[3] = env->tgpr[3]; + env->tgpr[3] = tmp; +} + +void hreg_compute_mem_idx(CPUPPCState *env) +{ + /* + * This is our encoding for server processors. The architecture + * specifies that there is no such thing as userspace with + * translation off, however it appears that MacOS does it and some + * 32-bit CPUs support it. Weird... + * + * 0 = Guest User space virtual mode + * 1 = Guest Kernel space virtual mode + * 2 = Guest User space real mode + * 3 = Guest Kernel space real mode + * 4 = HV User space virtual mode + * 5 = HV Kernel space virtual mode + * 6 = HV User space real mode + * 7 = HV Kernel space real mode + * + * For BookE, we need 8 MMU modes as follow: + * + * 0 = AS 0 HV User space + * 1 = AS 0 HV Kernel space + * 2 = AS 1 HV User space + * 3 = AS 1 HV Kernel space + * 4 = AS 0 Guest User space + * 5 = AS 0 Guest Kernel space + * 6 = AS 1 Guest User space + * 7 = AS 1 Guest Kernel space + */ + if (env->mmu_model & POWERPC_MMU_BOOKE) { + env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; + env->immu_idx += msr_is ? 2 : 0; + env->dmmu_idx += msr_ds ? 2 : 0; + env->immu_idx += msr_gs ? 4 : 0; + env->dmmu_idx += msr_gs ? 4 : 0; + } else { + env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; + env->immu_idx += msr_ir ? 0 : 2; + env->dmmu_idx += msr_dr ? 0 : 2; + env->immu_idx += msr_hv ? 4 : 0; + env->dmmu_idx += msr_hv ? 4 : 0; + } +} + +void hreg_compute_hflags(CPUPPCState *env) +{ + target_ulong hflags_mask; + + /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ + hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | + (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | + (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); + hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; + hreg_compute_mem_idx(env); + env->hflags = env->msr & hflags_mask; + /* Merge with hflags coming from other registers */ + env->hflags |= env->hflags_nmsr; +} + +void cpu_interrupt_exittb(CPUState *cs) +{ + if (!kvm_enabled()) { + return; + } + + if (!qemu_mutex_iothread_locked()) { + qemu_mutex_lock_iothread(); + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + qemu_mutex_unlock_iothread(); + } else { + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); + } +} + +int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) +{ + int excp; +#if !defined(CONFIG_USER_ONLY) + CPUState *cs = env_cpu(env); +#endif + + excp = 0; + value &= env->msr_mask; +#if !defined(CONFIG_USER_ONLY) + /* Neither mtmsr nor guest state can alter HV */ + if (!alter_hv || !(env->msr & MSR_HVB)) { + value &= ~MSR_HVB; + value |= env->msr & MSR_HVB; + } + if (((value >> MSR_IR) & 1) != msr_ir || + ((value >> MSR_DR) & 1) != msr_dr) { + cpu_interrupt_exittb(cs); + } + if ((env->mmu_model & POWERPC_MMU_BOOKE) && + ((value >> MSR_GS) & 1) != msr_gs) { + cpu_interrupt_exittb(cs); + } + if (unlikely((env->flags & POWERPC_FLAG_TGPR) && + ((value ^ env->msr) & (1 << MSR_TGPR)))) { + /* Swap temporary saved registers with GPRs */ + hreg_swap_gpr_tgpr(env); + } + if (unlikely((value >> MSR_EP) & 1) != msr_ep) { + /* Change the exception prefix on PowerPC 601 */ + env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; + } + /* + * If PR=1 then EE, IR and DR must be 1 + * + * Note: We only enforce this on 64-bit server processors. + * It appears that: + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS + * exploits it. + * - 64-bit embedded implementations do not need any operation to be + * performed when PR is set. + */ + if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { + value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); + } +#endif + env->msr = value; + hreg_compute_hflags(env); +#if !defined(CONFIG_USER_ONLY) + if (unlikely(msr_pow == 1)) { + if (!env->pending_interrupts && (*env->check_pow)(env)) { + cs->halted = 1; + excp = EXCP_HALTED; + } + } +#endif + + return excp; +} + +#ifndef CONFIG_USER_ONLY +void check_tlb_flush(CPUPPCState *env, bool global) +{ + CPUState *cs = env_cpu(env); + + /* Handle global flushes first */ + if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { + env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; + env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; + tlb_flush_all_cpus_synced(cs); + return; + } + + /* Then handle local ones */ + if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { + env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; + tlb_flush(cs); + } +} +#endif diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index efcc903427..4148a442b3 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -20,184 +20,16 @@ #ifndef HELPER_REGS_H #define HELPER_REGS_H -#include "qemu/main-loop.h" -#include "exec/exec-all.h" -#include "sysemu/kvm.h" +void hreg_swap_gpr_tgpr(CPUPPCState *env); +void hreg_compute_mem_idx(CPUPPCState *env); +void hreg_compute_hflags(CPUPPCState *env); +void cpu_interrupt_exittb(CPUState *cs); +int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); -/* Swap temporary saved registers with GPRs */ -static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) -{ - target_ulong tmp; - - tmp = env->gpr[0]; - env->gpr[0] = env->tgpr[0]; - env->tgpr[0] = tmp; - tmp = env->gpr[1]; - env->gpr[1] = env->tgpr[1]; - env->tgpr[1] = tmp; - tmp = env->gpr[2]; - env->gpr[2] = env->tgpr[2]; - env->tgpr[2] = tmp; - tmp = env->gpr[3]; - env->gpr[3] = env->tgpr[3]; - env->tgpr[3] = tmp; -} - -static inline void hreg_compute_mem_idx(CPUPPCState *env) -{ - /* - * This is our encoding for server processors. The architecture - * specifies that there is no such thing as userspace with - * translation off, however it appears that MacOS does it and some - * 32-bit CPUs support it. Weird... - * - * 0 = Guest User space virtual mode - * 1 = Guest Kernel space virtual mode - * 2 = Guest User space real mode - * 3 = Guest Kernel space real mode - * 4 = HV User space virtual mode - * 5 = HV Kernel space virtual mode - * 6 = HV User space real mode - * 7 = HV Kernel space real mode - * - * For BookE, we need 8 MMU modes as follow: - * - * 0 = AS 0 HV User space - * 1 = AS 0 HV Kernel space - * 2 = AS 1 HV User space - * 3 = AS 1 HV Kernel space - * 4 = AS 0 Guest User space - * 5 = AS 0 Guest Kernel space - * 6 = AS 1 Guest User space - * 7 = AS 1 Guest Kernel space - */ - if (env->mmu_model & POWERPC_MMU_BOOKE) { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_is ? 2 : 0; - env->dmmu_idx += msr_ds ? 2 : 0; - env->immu_idx += msr_gs ? 4 : 0; - env->dmmu_idx += msr_gs ? 4 : 0; - } else { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_ir ? 0 : 2; - env->dmmu_idx += msr_dr ? 0 : 2; - env->immu_idx += msr_hv ? 4 : 0; - env->dmmu_idx += msr_hv ? 4 : 0; - } -} - -static inline void hreg_compute_hflags(CPUPPCState *env) -{ - target_ulong hflags_mask; - - /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ - hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | - (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); - hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; - hreg_compute_mem_idx(env); - env->hflags = env->msr & hflags_mask; - /* Merge with hflags coming from other registers */ - env->hflags |= env->hflags_nmsr; -} - -static inline void cpu_interrupt_exittb(CPUState *cs) -{ - if (!kvm_enabled()) { - return; - } - - if (!qemu_mutex_iothread_locked()) { - qemu_mutex_lock_iothread(); - cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); - qemu_mutex_unlock_iothread(); - } else { - cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); - } -} - -static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, - int alter_hv) -{ - int excp; -#if !defined(CONFIG_USER_ONLY) - CPUState *cs = env_cpu(env); -#endif - - excp = 0; - value &= env->msr_mask; -#if !defined(CONFIG_USER_ONLY) - /* Neither mtmsr nor guest state can alter HV */ - if (!alter_hv || !(env->msr & MSR_HVB)) { - value &= ~MSR_HVB; - value |= env->msr & MSR_HVB; - } - if (((value >> MSR_IR) & 1) != msr_ir || - ((value >> MSR_DR) & 1) != msr_dr) { - cpu_interrupt_exittb(cs); - } - if ((env->mmu_model & POWERPC_MMU_BOOKE) && - ((value >> MSR_GS) & 1) != msr_gs) { - cpu_interrupt_exittb(cs); - } - if (unlikely((env->flags & POWERPC_FLAG_TGPR) && - ((value ^ env->msr) & (1 << MSR_TGPR)))) { - /* Swap temporary saved registers with GPRs */ - hreg_swap_gpr_tgpr(env); - } - if (unlikely((value >> MSR_EP) & 1) != msr_ep) { - /* Change the exception prefix on PowerPC 601 */ - env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; - } - /* - * If PR=1 then EE, IR and DR must be 1 - * - * Note: We only enforce this on 64-bit server processors. - * It appears that: - * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS - * exploits it. - * - 64-bit embedded implementations do not need any operation to be - * performed when PR is set. - */ - if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { - value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); - } -#endif - env->msr = value; - hreg_compute_hflags(env); -#if !defined(CONFIG_USER_ONLY) - if (unlikely(msr_pow == 1)) { - if (!env->pending_interrupts && (*env->check_pow)(env)) { - cs->halted = 1; - excp = EXCP_HALTED; - } - } -#endif - - return excp; -} - -#if !defined(CONFIG_USER_ONLY) -static inline void check_tlb_flush(CPUPPCState *env, bool global) -{ - CPUState *cs = env_cpu(env); - - /* Handle global flushes first */ - if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { - env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; - env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; - tlb_flush_all_cpus_synced(cs); - return; - } - - /* Then handle local ones */ - if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { - env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; - tlb_flush(cs); - } -} -#else +#ifdef CONFIG_USER_ONLY static inline void check_tlb_flush(CPUPPCState *env, bool global) { } +#else +void check_tlb_flush(CPUPPCState *env, bool global); #endif #endif /* HELPER_REGS_H */ diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 429de28494..a44c2d90ea 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" +#include "qemu/log.h" #include "exec/helper-proto.h" #include "crypto/aes.h" #include "fpu/softfloat.h" diff --git a/target/ppc/meson.build b/target/ppc/meson.build index bbfef90e08..4079d01ee3 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -6,6 +6,7 @@ ppc_ss.add(files( 'excp_helper.c', 'fpu_helper.c', 'gdbstub.c', + 'helper_regs.c', 'int_helper.c', 'mem_helper.c', 'misc_helper.c', From patchwork Tue May 4 05:52:29 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id m12si1561280qtx.246.2021.05.03.22.53.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 22:53:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=Wey+sXsW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:46244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo0M-00059r-L9 for patch@linaro.org; Tue, 04 May 2021 01:53:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzp-00057k-EN; Tue, 04 May 2021 01:53:25 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:38887 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzn-0004a2-J6; Tue, 04 May 2021 01:53:25 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK01nQz9sW1; Tue, 4 May 2021 15:53:16 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=Twg3ixSosYubY2S6kfpWfV4IThjGfpdxnG0ofrjJl5o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wey+sXsWMpXtdyngiL5nCJRjXigGzkg59MtvR79TfxhMUiYwngHSPunLEMkLBc9RY 477Q+iSWgE7KZuDOU/XPjtlKvmI4YvdfGM6+/d4UOQqI9M1VcbTbKzHYHM6LFzg+H5 W173M41ZUFjqCgD3iJPgsoxg6LdNsKjMnYFQLLAo= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 03/46] target/ppc: Move 601 hflags adjustment to hreg_compute_hflags Date: Tue, 4 May 2021 15:52:29 +1000 Message-Id: <20210504055312.306823-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Keep all hflags computation in one place, as this will be especially important later. Introduce a new POWERPC_FLAG_HID0_LE bit to indicate when LE should be taken from HID0. This appears to be set if and only if POWERPC_FLAG_RTC_CLK is set, but we're not short of bits and having both names will avoid confusion. Note that this was the only user of hflags_nmsr, so we can perform a straight assignment rather than mask and set. Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-3-richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/cpu.h | 2 ++ target/ppc/helper_regs.c | 13 +++++++++++-- target/ppc/misc_helper.c | 8 +++----- target/ppc/translate_init.c.inc | 4 ++-- 4 files changed, 18 insertions(+), 9 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68..061d2eed1b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -581,6 +581,8 @@ enum { POWERPC_FLAG_TM = 0x00100000, /* Has SCV (ISA 3.00) */ POWERPC_FLAG_SCV = 0x00200000, + /* Has HID0 for LE bit (601) */ + POWERPC_FLAG_HID0_LE = 0x00400000, }; /*****************************************************************************/ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 5e18232b84..95b9aca61f 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -96,8 +96,17 @@ void hreg_compute_hflags(CPUPPCState *env) hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; hreg_compute_mem_idx(env); env->hflags = env->msr & hflags_mask; - /* Merge with hflags coming from other registers */ - env->hflags |= env->hflags_nmsr; + + if (env->flags & POWERPC_FLAG_HID0_LE) { + /* + * Note that MSR_LE is not set in env->msr_mask for this cpu, + * and so will never be set in msr or hflags at this point. + */ + uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); + env->hflags |= le << MSR_LE; + /* Retain for backward compatibility with migration. */ + env->hflags_nmsr = le << MSR_LE; + } } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 5d6e0de396..63e3147eb4 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -194,16 +194,14 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) target_ulong hid0; hid0 = env->spr[SPR_HID0]; + env->spr[SPR_HID0] = (uint32_t)val; + if ((val ^ hid0) & 0x00000008) { /* Change current endianness */ - env->hflags &= ~(1 << MSR_LE); - env->hflags_nmsr &= ~(1 << MSR_LE); - env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); - env->hflags |= env->hflags_nmsr; + hreg_compute_hflags(env); qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, val & 0x8 ? 'l' : 'b', env->hflags); } - env->spr[SPR_HID0] = (uint32_t)val; } void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index c03a7c4f52..049d76cfd1 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -5441,7 +5441,7 @@ POWERPC_FAMILY(601)(ObjectClass *oc, void *data) pcc->excp_model = POWERPC_EXCP_601; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; } #define POWERPC_MSRR_601v (0x0000000000001040ULL) @@ -5485,7 +5485,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) #endif pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; - pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; + pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; } static void init_proc_602(CPUPPCState *env) From patchwork Tue May 4 05:52:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430802 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3487191jao; Mon, 3 May 2021 22:54:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxDvdDej2aBNEI6oiaCd/ZMKGbG6fxUSJ7l0VWgrX6XKjpwV9jZWZXTe0MAvPmMeWpKjLMp X-Received: by 2002:a37:40d5:: with SMTP id n204mr22680822qka.79.1620107651532; Mon, 03 May 2021 22:54:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620107651; cv=none; d=google.com; s=arc-20160816; b=y16VJ3VQgxFA5/EklMBz3xHZDcnD//S9wBiWuZv3igY9aLQ/zx9RlcS+OU/tApsK6A zqE0tqtcD1y/uPzkTmcsJlxB13xrirwvmTqIE9kG2OQBocXR2IEDTt/xvKBAWjeRZgbb TQBSdb7NSK5G92FtIxjvAP+c793o6AD7vBGHeYKcRyha2EcXJm/mUDUu6t7WpUf4XXiJ 0WT71GMoawXKTLQkeVAUO/xuojVUUVWcYX8XWyyH0dAQUQpwwyqIC5UBhSNvcBuM/pWA +YSDVRBdQd9YUPfz37zQVIz/bmKQ26x7l3f6NuEdrunjfSIRnCvE7EH9LGELbq00ct7W VPpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=raCF2vn88sF8rQ0ooL9VF7est1Xp53bPcSMgYctwGKg=; b=A7Jg5MDzIhowtizIcxIffsyBFBMiTVYB/5QzDLacMBqabE9RVdrnIRyksgcUpH4fzQ ud50T2HiU4pWAdGYQiUfT4fwZgGuXyCIjlvbkBVqmwKh3uQ0cbFuC+PrX0F5SVSMAdX3 KY2vA7L6WKUKmqGurPBZt6Sk8HHhpeOgzZr/JVcruLmdmY/o2KHCUsO3qSQz49WY4Vhs qBIrFT0l//21qyFkLGQrz72oJE0E0CZWXZ5s6gsXuKnlHbWtkiGQkQJwk0e1P6azZI4G SlpmfuOzsqnPuRwdtzJTnhy+sdsSlfWvta+eEZ7EZ9EqCnTY15Q4Q6o0/UTVdb63Ew5A Z5fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=gWvivPjD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c19si1445393qtd.294.2021.05.03.22.54.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 22:54:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=gWvivPjD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:47168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo0Y-0005hL-Tv for patch@linaro.org; Tue, 04 May 2021 01:54:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzq-00057z-Jw; Tue, 04 May 2021 01:53:26 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:49311 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzn-0004a3-Jh; Tue, 04 May 2021 01:53:26 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK0MzZz9sWB; Tue, 4 May 2021 15:53:16 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=vah07RKjf90sFxm6WFtEddSHyy3538FGdU5PnH34764=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gWvivPjDv4vcoNWkNG9bunqtf75/jkyu56D4FZ95GKQol7cKzrVjZVwfpz301Uhda GEs4QPmvEq49yfBbPB3uFlhKdAcmKINiKA+wJJenm+dvkLJICSZdiTkGCA6DgwzMos NtHEsbM6Svoy5E4OqGWbqkuJioBCc8w5LLVfvntE= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 04/46] target/ppc: Properly sync cpu state with new msr in cpu_load_old Date: Tue, 4 May 2021 15:52:30 +1000 Message-Id: <20210504055312.306823-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Match cpu_post_load in using ppc_store_msr to set all of the cpu state implied by the value of msr. Do not restore hflags or hflags_nmsr, as we recompute them in ppc_store_msr. Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-4-richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/machine.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 283db1d28a..87d7bffb86 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -21,6 +21,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) int32_t slb_nr; #endif target_ulong xer; + target_ulong msr; for (i = 0; i < 32; i++) { qemu_get_betls(f, &env->gpr[i]); @@ -111,11 +112,19 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_betls(f, &env->ivpr_mask); qemu_get_betls(f, &env->hreset_vector); qemu_get_betls(f, &env->nip); - qemu_get_betls(f, &env->hflags); - qemu_get_betls(f, &env->hflags_nmsr); + qemu_get_sbetl(f); /* Discard unused hflags */ + qemu_get_sbetl(f); /* Discard unused hflags_nmsr */ qemu_get_sbe32(f); /* Discard unused mmu_idx */ qemu_get_sbe32(f); /* Discard unused power_mode */ + /* + * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB + * before restoring. Note that this recomputes hflags and mem_idx. + */ + msr = env->msr; + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); + ppc_store_msr(env, msr); + /* Recompute mmu indices */ hreg_compute_mem_idx(env); From patchwork Tue May 4 05:52:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430815 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3494755jao; Mon, 3 May 2021 23:07:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBe/FM/pOExzWNhdlzlVQl4r2hJWfMPPRxIMB2Y2IcT0QPZq0HZFhbFxfZiUKtSANWwIQi X-Received: by 2002:ab0:12a:: with SMTP id 39mr18454849uak.19.1620108434760; Mon, 03 May 2021 23:07:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108434; cv=none; d=google.com; s=arc-20160816; b=pGeSkXw4F8aEnlJjDfBaZ1iu/+oFBLNUDJdaXGMjizJdYmtR4dB6dw6Z26ITPpPKgH 5OpnHCYihLdXAM6TYKjsQeXSK4G9xv9oSA4l1CwIMaSVsFB58knXzEdjo0WOPRzwnt2q xm+8bO60U8ExkKp7HQ7SrUV2NEX525GmToymMKkX87zLeyuTx80nUKLKpOBz/ejjuTOM 5VENiA5OcsLr1ba60bcPZDEzZgrYCloCiLtZh/q21UnYD3lFD26oGt/JM8OtPI9aajvb WQU0LATTk1ax5m2XWKD2XjSHO+05Tm5jDBFRp+QjZa6UcyD18KzmLWQM7WC9bLOBwhxt LJFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qjt0/C/HKHsPupxveZh+Pau68rtfK+FtSqHagX4Ele8=; b=frJBoyAMXe4odRsBtPlILPh18lwDHYBAZ3oZdNIhBL2sVvuJSi+hi9gjiP0dhUJxSn ptN/JaAKFryi9TLCzsw3p1oynYez7+LyMdB17nL6fbHc/yNo5qr802v3EzL96hbAFw0A XD3En44gn5MJtYRTjmiJKNPPTZZxOUXH7t7UJvHBaevOkDtS48fkxpspDuw2RddFHvS1 r49kYiCA/NKtpKPs0TABRZMRagQQakfMEF4cQqORBsM477RS/Y+tGPRKD/txdDhy0ICA LAF0EzIxbSVsz7/ZitEvfKbaQAPvXNr4A1yagWBo5++KyImKn/aAFnEHCjgagQfZ5FQv A9rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=R3Ifb37U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o2si1257466uat.235.2021.05.03.23.07.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:07:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=R3Ifb37U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:44612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoDB-0000LH-G9 for patch@linaro.org; Tue, 04 May 2021 02:07:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzu-0005Az-Jq; Tue, 04 May 2021 01:53:30 -0400 Received: from ozlabs.org ([203.11.71.1]:43605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzr-0004fR-Sg; Tue, 04 May 2021 01:53:29 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK1C7zz9sWM; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=f78B5YbYtAyXCQJDJDaRmnQ7EsORe8dS0KxqvyuLBfg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R3Ifb37U8NK2cclA6WdrEjotocnKgNAKpykhY8qla+Gf47AQfzZZrpjHDTDAuijtK kvx2aKZcENs49C8oUJKKNh5Va35UXEpiki2O20ywnDnBULPZEwIkrE5Wc3jpHmO/xA navL+yZGTu1zhbOQQFjkUG2nlowxXDaX2mfftOUs= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 05/46] target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr Date: Tue, 4 May 2021 15:52:31 +1000 Message-Id: <20210504055312.306823-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson In ppc_store_msr we call hreg_compute_hflags, which itself calls hreg_compute_mem_idx. Rely on ppc_store_msr to update everything required by the msr update. Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-5-richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/machine.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.31.1 diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 87d7bffb86..f6eeda9642 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -125,9 +125,6 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - /* Recompute mmu indices */ - hreg_compute_mem_idx(env); - return 0; } @@ -418,14 +415,12 @@ static int cpu_post_load(void *opaque, int version_id) /* * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring + * before restoring. Note that this recomputes hflags and mem_idx. */ msr = env->msr; env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - hreg_compute_mem_idx(env); - return 0; } From patchwork Tue May 4 05:52:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430805 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3489407jao; Mon, 3 May 2021 22:58:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxd+koJdnO6SeibgO3HzeMj/Ffc14pUSUnOX7iZtGbSA8MzZap1btcfRPofyJ5wjuncYFFG X-Received: by 2002:ac8:6954:: with SMTP id n20mr21605390qtr.314.1620107928100; Mon, 03 May 2021 22:58:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620107928; cv=none; d=google.com; s=arc-20160816; b=vnHH1eaTL77y59guK0FPnW5vJhO1klDxrU+qHtx1p0zoPolaj4J0CbfwsC2TMBkPGC xiHEseC7mU8KBBlL5839gwgWbOnOlE/DKq35tMc0lf5UmYtWJJwyB5e/zIe0vz+eBArl OBJIre63WZUxqMdJeWg1oe1hXyjQKkkluvSstv0NYGRXvAv3cGFKtcdGeZbBG4blcKax h3zr7c4yH+Q0Ewjy2aus0wC9H4tuEcaTFZKWqbdWrHR7WcSWm/Z4PK7cLb2rTC8LXgGs lYsP6wzj3fVC0/xIHGFLa4aIok6b+6UMkBDfuMCCLF/FlqyyR4HS9vePawLul/d0ho/i 0fzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dYxoT5SVSOt+HvhFKBqdZWZt9SLOcJdVViDaZ1ciOj8=; b=uWEq5MpF/P+PANFTyY1UF+bIJLZoTkHMVbkbuxmxlo8HM0qKcO76JQzRuPJ1J2FIuf NHMeO9lYSaPp1SVmCeb0lAkD6q7uXY44Zaqi1izVCsklTWlNEcXG/TCPOVEgme5uJ8uX hfZXBtf5OnJEbl2JDh/a0HAkVVFWbZR/juCnPHlI0p21rznbTjLHQ5hhT39/aAKazEvp 8Lkph2W/11tBGrV34r6TOrnYG3QkRHrWRfq/I5vyT/ZSk01OtMyIPxKx9v8xIeU67Q4t 10oVVcYHJZKereOUfniHvQ2BDg4TNGUeNd1Ymj+8eaECXz6v/nDam5/EsR3/VKTyKqKd IRew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=I7leRdoP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t17si5206172qkm.316.2021.05.03.22.58.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 22:58:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=I7leRdoP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo51-0001Y2-Hj for patch@linaro.org; Tue, 04 May 2021 01:58:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzu-0005B7-LC; Tue, 04 May 2021 01:53:32 -0400 Received: from ozlabs.org ([203.11.71.1]:51761) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzs-0004fS-0V; Tue, 04 May 2021 01:53:29 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK0rvwz9sWC; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=QN9OGBLE2HmT8V/0wRszHECV89IjJIxItnBzN/dvEDo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I7leRdoPnCOG4Zb4KWK9sKd64s3IYRQklnOsX8pvnvyReir5IXHLmrGva9kRiVduk JLV40zniKYAI5iE2NsSgHaTSvVZKj3NWdjczPcfDgD8oKzRFpxVST5VTmqgby/XRrs 3kMo+tTLJgRwwS2illfeOfiPt2Rmw3UmrpQV1+D8= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 06/46] target/ppc: Retain hflags_nmsr only for migration Date: Tue, 4 May 2021 15:52:32 +1000 Message-Id: <20210504055312.306823-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We have eliminated all normal uses of hflags_nmsr. We need not even compute it except when we want to migrate. Rename the field to emphasize this. Remove the fixme comment for migrating access_type. This value is only ever used with the current executing instruction, and is never live when the cpu is halted for migration. Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-6-richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 ++-- target/ppc/helper_regs.c | 2 -- target/ppc/machine.c | 9 ++++++--- 3 files changed, 8 insertions(+), 7 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 061d2eed1b..79c4033a42 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1105,8 +1105,8 @@ struct CPUPPCState { #endif /* These resources are used only in QEMU core */ - target_ulong hflags; /* hflags is MSR & HFLAGS_MASK */ - target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ + target_ulong hflags; + target_ulong hflags_compat_nmsr; /* for migration compatibility */ int immu_idx; /* precomputed MMU index to speed up insn accesses */ int dmmu_idx; /* precomputed MMU index to speed up data accesses */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 95b9aca61f..a87e354ca2 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -104,8 +104,6 @@ void hreg_compute_hflags(CPUPPCState *env) */ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); env->hflags |= le << MSR_LE; - /* Retain for backward compatibility with migration. */ - env->hflags_nmsr = le << MSR_LE; } } diff --git a/target/ppc/machine.c b/target/ppc/machine.c index f6eeda9642..1f7a353c78 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -310,6 +310,10 @@ static int cpu_pre_save(void *opaque) } } + /* Retain migration compatibility for pre 6.0 for 601 machines. */ + env->hflags_compat_nmsr = (env->flags & POWERPC_FLAG_HID0_LE + ? env->hflags & MSR_LE : 0); + return 0; } @@ -829,9 +833,8 @@ const VMStateDescription vmstate_ppc_cpu = { /* Supervisor mode architected state */ VMSTATE_UINTTL(env.msr, PowerPCCPU), - /* Internal state */ - VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU), - /* FIXME: access_type? */ + /* Backward compatible internal state */ + VMSTATE_UINTTL(env.hflags_compat_nmsr, PowerPCCPU), /* Sanity checking */ VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration), From patchwork Tue May 4 05:52:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430803 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3488536jao; Mon, 3 May 2021 22:57:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz8H2fhP/yXl5vxxE0HI0sKiLFzDa84mgRq6qmfMOrmPedxBWtmvImZG61oWfbdfEoRxpuZ X-Received: by 2002:a37:8bc1:: with SMTP id n184mr23714647qkd.268.1620107826328; Mon, 03 May 2021 22:57:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620107826; cv=none; d=google.com; s=arc-20160816; b=pWySEhvu5ZMhSi2QGc3EV+day8xGC2SO+QF1zPgAhkFy09mp4MrIQ9t6fibeLGRlzZ jw9rGqgu9aWDJzgW7J4iEzyewTln0tG8QWQf308rQLD25CM8MAh0VEu6T5hUIAw77Vua ZtNJjPAtl6GPTBrCUb+t2oCD57QU2+BjQgeHH7efD7J5CqB+UlpIGEFy4DASi1u/AcSd H4MmECEuma3SdLRwUAnnH/4nlzs/ofIz0nRHcSQgupRgkFRNtGTQ0V5InD8NufBcHJnc XG9b9T9tgEW/yFQvcnAQUg/qnKA9bSSzykokQbcDUJbVacSFoSzlW+YQQC+PJolHkRap 7RWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aTS0JBfDPncws2Dl9KEHpGgbcg1akBbUxtVua/t/DY0=; b=auL0QSRzuBp3Czf7BCTwK7+3LrQa20mw2rPHAsPb2ybff/NUe2d0JM0iczvHzwl8LP ZJRwrmSqKmYMc+guFIKg4jlwHOjIDQKrwmUn1N/GoCj+Bu4mjTGv0cjpOxKZg/5MJfUT 0TnU9V8DkrZH7of+C5E9Ry3l+zcS/LjqqK7xzkMGqDXbcTana7ygUCKr9PM5m4aY5pQX qFb03WVsoT3ByyycLePWmCVjNKByWL/YPtKx0I0i4Mv7fGSLD7EnFMsm4p9DPWRZvB10 q/Jkb+McGkne3Hx/CrC2NoC0dDJ/xczX++rTsBHUaxddohweFCjn9D/1O4FO3EcZC0HC TRVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=He+sCNp9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v7si9421103qvi.216.2021.05.03.22.57.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 22:57:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=He+sCNp9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:51104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo3N-0007Z1-PO for patch@linaro.org; Tue, 04 May 2021 01:57:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60426) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzw-0005DO-RV; Tue, 04 May 2021 01:53:34 -0400 Received: from ozlabs.org ([203.11.71.1]:46053) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzs-0004fV-4L; Tue, 04 May 2021 01:53:30 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK1xKvz9sWW; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=O6avjl1hbr3lZtelooLHSiYSY2uVa/zlg2sxWvyezxM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=He+sCNp9Hl2ol6wKSm+dt/YzhwrYaEQANl4sp9wt0kPVIa2zoCAVLW/K/+CUiyCs7 fsetEw5M+B0Ewk2ypVFZ1qc4jjiR1LWwYj4VKpFdvHeJ3XS0Ty6orUlB7ISFSQ3TZo KHm08wSDDe83MVnoRczgsw7+Cgea5Lgh1iECDXzs= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 07/46] target/ppc: Fix comment for MSR_FE{0,1} Date: Tue, 4 May 2021 15:52:33 +1000 Message-Id: <20210504055312.306823-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson As per hreg_compute_hflags: We 'forget' FE0 & FE1: we'll never generate imprecise exceptions remove the hflags marker from the respective comments. Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-7-richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 79c4033a42..fd13489dce 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -322,13 +322,13 @@ typedef struct ppc_v3_pate_t { #define MSR_PR 14 /* Problem state hflags */ #define MSR_FP 13 /* Floating point available hflags */ #define MSR_ME 12 /* Machine check interrupt enable */ -#define MSR_FE0 11 /* Floating point exception mode 0 hflags */ +#define MSR_FE0 11 /* Floating point exception mode 0 */ #define MSR_SE 10 /* Single-step trace enable x hflags */ #define MSR_DWE 10 /* Debug wait enable on 405 x */ #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ #define MSR_BE 9 /* Branch trace enable x hflags */ #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ -#define MSR_FE1 8 /* Floating point exception mode 1 hflags */ +#define MSR_FE1 8 /* Floating point exception mode 1 */ #define MSR_AL 7 /* AL bit on POWER */ #define MSR_EP 6 /* Exception prefix on 601 */ #define MSR_IR 5 /* Instruction relocate */ From patchwork Tue May 4 05:52:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430804 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3489369jao; Mon, 3 May 2021 22:58:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwlZuRMUvjPqcNwkcLfvJgUi7MN/vgj6Nq5heABQD8rlusouyCh8eP/Prv4P3vKg1Xdqxq+ X-Received: by 2002:a37:a051:: with SMTP id j78mr6527472qke.216.1620107923191; Mon, 03 May 2021 22:58:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620107923; cv=none; d=google.com; s=arc-20160816; b=FUOtmyuO9qTF/PW6+5aJQtZ89W+dwWBzHUwRYryzWU8PpP0AqMbwc1ryMePX2BJjH6 2wd0an42OIX6BWmaVHXgfXGd7noXivivQkSlYnhzRNGYFzk7FmnWsGQwA6mXplAlQJYz lXoZiNDWzZQK23TgfS3Xyxfm3uepLyMD340NVk6fkVVPu7prItM9r7l0/+OKpRK/pZQk 9PkGCj35AZ9Kb+0S/LCl6A7m5oUbMnVxSFmTPKPSuLkzHLHU6+JMrd919Qbbqwb3BDe+ 7WzVRWWgsdg0fgQ9glaeMRiA78e4LL7fuKMyno/nxetHBj1pf/GM8oum8LtcQmAWsHJd t/5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mFpWojEzaS2JiCOjIkqLAB/iismou+0tsGsK2WI4HR4=; b=v+b80d4ozf6Fg5aWzHeQP9W+x5kFwCOiLjuaZgxwUEhf7hiGgzDAKf2tKTar8AYCEw yHSg3EsbQ/d+5xyAOpde6G2+hUs/5RfXA3QS/67P7VpTGRRm+Af3+i/m1KJx/yImORJM yWytN1q/DAwxR6umyiOZ3ufCADS4Co/uCh5YxigFbnG4dHC/ECcLcITuknY5iRaQXEln HTNeMHUfj6uQsDh0WUf+VyUePwmJ+GV1iKBZ8C0JX+tVUTwZciLxUhtxiuwugkiwN+wX D2ULFadGhWKEyJ8Vvv1dbun4ByO/ITrXseMaShYofe4TqIuWURWSZb1Yn9dzkdiV6WpW qDkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=jS+Y1Xgt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j20si4246392qko.293.2021.05.03.22.58.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 22:58:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=jS+Y1Xgt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo4w-0001Jf-I5 for patch@linaro.org; Tue, 04 May 2021 01:58:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzw-0005DQ-Rj; Tue, 04 May 2021 01:53:34 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:51991) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzs-0004fX-R4; Tue, 04 May 2021 01:53:31 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK1YrWz9sWH; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=O5zitTu+nloRXDlrgGA5ooBE2GZ6ePUNtmsAOMIModU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jS+Y1XgtrUo/X4LKu+GcN0TgNn3KEXeWvz981JCyJDnYCXOAy7FdJP2I5J3dfkB/g nwuW/2wg/XpicofvtV8MzYDnaCnJv7AWGT+GVic34OgRrMSeV2QZcPSzvJL2Ir+KnU Hz61gcwsf/uw3yKujxeD40U1z6NYq5zRoQPk7gR4= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 08/46] hw/ppc/pnv_core: Update hflags after setting msr Date: Tue, 4 May 2021 15:52:34 +1000 Message-Id: <20210504055312.306823-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-15-richard.henderson@linaro.org> Signed-off-by: David Gibson --- hw/ppc/pnv_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.31.1 diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index bd2bf2e044..8c2a15a0fb 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -29,6 +29,7 @@ #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" +#include "helper_regs.h" static const char *pnv_core_cpu_typename(PnvCore *pc) { @@ -55,8 +56,8 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) env->gpr[3] = PNV_FDT_ADDR; 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Tue, 04 May 2021 01:53:36 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:48167) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzu-0004gH-Lj; Tue, 04 May 2021 01:53:33 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK2mzGz9sWl; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=EaUDafy/8AJuydSXL0bhyrdgLP0aiUNh84eXCOph83Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o/ETwZDh4AmO7IMxZqN8i0QaMbHqt+DtMsK+fsYLRU3AhIeclTVNhHgSBUR23JDn+ ebpO/iCjsEQGvccAicEv2hWnXbvnNKBx5+uilUgm8F9CoO5IXd2FJFR4HT/Fg09H6t A4wuEF/9jy6ToTTIzWPKxi5UXWpREAFaMH7jFbpQ= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 09/46] hw/ppc/spapr_rtas: Update hflags after setting msr Date: Tue, 4 May 2021 15:52:35 +1000 Message-Id: <20210504055312.306823-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Message-Id: <20210315184615.1985590-16-richard.henderson@linaro.org> Signed-off-by: David Gibson --- hw/ppc/spapr_rtas.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.31.1 diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 8a79f9c628..6ec3e71757 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -51,6 +51,7 @@ #include "target/ppc/mmu-hash64.h" #include "target/ppc/mmu-book3s-v3.h" #include "migration/blocker.h" +#include "helper_regs.h" static void rtas_display_character(PowerPCCPU *cpu, SpaprMachineState *spapr, uint32_t token, uint32_t nargs, @@ -163,6 +164,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr, cpu_synchronize_state(CPU(newcpu)); env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME); + hreg_compute_hflags(env); /* Enable Power-saving mode Exit Cause exceptions for the new CPU */ lpcr = env->spr[SPR_LPCR]; From patchwork Tue May 4 05:52:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430807 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3491993jao; Mon, 3 May 2021 23:02:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjocjNwKhl1+3U055MUaiFANpV/OYEGT0gwH2fuACPKy3nCGdPnYyKl36gvMUOqC+M21hM X-Received: by 2002:a1f:9f52:: with SMTP id i79mr3406015vke.4.1620108165686; Mon, 03 May 2021 23:02:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108165; cv=none; d=google.com; s=arc-20160816; b=o0PkhiPN63DwzrSFwTjsC5aljt/zW7TmISxClSapeFq6gbUeIzZCV6Wy2yLNvFBUqM G4rY4aEfuyOKN1h30G9UBimuNMskwhaMvSR2l1xFJSbHujLp89RRHlwfghctuei3/WcS x+P9AJ8nby+lwSRqRPSUPX+371PuEXqUV9EUm7mumyhmIfSUHQiliugoREo97JYEwrw9 a8JkE5XOm0vdjVsu/O01lUB98EDkDGppN9wJp1L5xw8qAo/K7nZoePFqVbO68wvQclj+ nJbh5JKVk5SfJz7fQMrZ66jQU3dr9v7+EBXIziHlrJZS8hZy3hHEZnYB7dV6DB2IrAYT wk7w== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id t6si1219512ual.185.2021.05.03.23.02.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:02:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=QazuReSh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo8r-0005UC-28 for patch@linaro.org; Tue, 04 May 2021 02:02:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzy-0005ER-RK; Tue, 04 May 2021 01:53:36 -0400 Received: from ozlabs.org ([203.11.71.1]:60029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzu-0004fy-L1; Tue, 04 May 2021 01:53:33 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK2HFbz9sWP; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=oW4gZLOC55a8GtLu9aFZEjL0E+dLRASXBtOs5tL/xpw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QazuReShYv9d9YYcApIrSml4UbUWrVzhLV+hxfZe5Ow0OOi4S7XBexXu/ne0Qp9ES aehyZPoD+h0GLBkgd2pkXSfRLDqFs1IcspLlZAZLKUu7npRVLvHNspKzqdpTYcdbKL Tz+lDt6nglU6KxlFyT9hE6EwZ+UTzYD7e0vcyaSQ= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 10/46] target/ppc: Extract post_load_update_msr Date: Tue, 4 May 2021 15:52:36 +1000 Message-Id: <20210504055312.306823-11-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Extract post_load_update_msr to share between cpu_load_old and cpu_post_load in updating the msr. Suggested-by: Cédric Le Goater Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-2-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/machine.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) -- 2.31.1 diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 1f7a353c78..09c5765a87 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -10,6 +10,18 @@ #include "kvm_ppc.h" #include "exec/helper-proto.h" +static void post_load_update_msr(CPUPPCState *env) +{ + target_ulong msr = env->msr; + + /* + * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB + * before restoring. Note that this recomputes hflags and mem_idx. + */ + env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); + ppc_store_msr(env, msr); +} + static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) { PowerPCCPU *cpu = opaque; @@ -21,7 +33,6 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) int32_t slb_nr; #endif target_ulong xer; - target_ulong msr; for (i = 0; i < 32; i++) { qemu_get_betls(f, &env->gpr[i]); @@ -117,13 +128,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_sbe32(f); /* Discard unused mmu_idx */ qemu_get_sbe32(f); /* Discard unused power_mode */ - /* - * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring. Note that this recomputes hflags and mem_idx. - */ - msr = env->msr; - env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); - ppc_store_msr(env, msr); + post_load_update_msr(env); return 0; } @@ -343,7 +348,6 @@ static int cpu_post_load(void *opaque, int version_id) PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; int i; - target_ulong msr; /* * If we're operating in compat mode, we should be ok as long as @@ -417,13 +421,7 @@ static int cpu_post_load(void *opaque, int version_id) ppc_store_sdr1(env, env->spr[SPR_SDR1]); } - /* - * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring. Note that this recomputes hflags and mem_idx. - */ - msr = env->msr; - env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); - ppc_store_msr(env, msr); + post_load_update_msr(env); return 0; } From patchwork Tue May 4 05:52:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430817 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3496115jao; Mon, 3 May 2021 23:09:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRZIOuZEigze8e1OBJRKo4Yxe2vw4YmK0IxXANR4BdPC51iLsevHhpuYXHm1Avfr0cI9/k X-Received: by 2002:a1f:5583:: with SMTP id j125mr15086292vkb.18.1620108577025; Mon, 03 May 2021 23:09:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108577; cv=none; d=google.com; s=arc-20160816; b=m7umwTGvJt7kmTYn4L7f0clAWkVQJT4GeAlMdqKfwFIV8qsboKw2JcBOdt2QsqF79f zRmaTsut+TGUqMr9GaBCAI1CPIYCj9doWTfFAuZce4Ts5O0lyKauDLq+jWiyVJpa9Qy9 A2lBcPUqhyxMppCisChgpxlnqlRxD/SW1LXld4S7UTS98nociqXCPFRUvd9JXVn1smk6 Zd0xx3HwHV2Wm51sjJniGrSX5dhbRaDUP0NQSNjkhkfQzaQs6gGNScJwwc5PMUUrTVG7 dqyCEuUA67NNgVN5zemyjiDpkGeehxWI4CvfhF2CwcWWmdohrvlqprcdrqPbfSyviHhW Uzrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ksczQh2dqjOmns5xlj952xcq5rK2uQDKmObkWS8dnSE=; b=V900MthK/IY2Mmxbunjna9E6mzX4P1bzOkBsqSNkm6cgYe4GBylyYRVg+3uv1MJbSt 7YFkL+TVe4LZATKDySK+4aRQ5Bj1mWcXMoibcPXIFOVQk7WcBasPUAqMcLpHeP7thQFI fiHk7SwB1rUk7q4jYBpNpdMnVaCOw6XVXtoFwvFJpMXtLWLQBhg1HMkCfst8HxgiCZmq 2elXqHk385r2+ty1DmumxX4B5M+phcrxa/AK9CzFwbEwqdOku7Hi5edDnv282fFvRgBq nShQYzzWLd0XWE/c84485piABLkIjHWNay0JyHJFREQnfylWsoLLrVIhVX7Ca5vxVebn +ppQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=SmfC7LkV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m9si3821534vsj.66.2021.05.03.23.09.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:09:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=SmfC7LkV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:45660 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoFU-0000ok-Cp for patch@linaro.org; Tue, 04 May 2021 02:09:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo00-0005Fj-Rx; Tue, 04 May 2021 01:53:36 -0400 Received: from ozlabs.org ([203.11.71.1]:40259) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzu-0004gR-M1; Tue, 04 May 2021 01:53:35 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK37VCz9sWc; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=krNKTKKeBY1/6yuZmLDI7IFkkJRwL6rpd5wRKD5l5NE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SmfC7LkVbNhZrP8aWpOKAPsL0TpFJHL+UDtT6k3mx63ZXIpG53d3wbQmlQBtYRE6K 2YnoR1ZRUv7mrmYiWYQONF0JHOfU9cFviGen7ZRGHGFIV88py4Z2nElnEICwZ3Rhqa bU1vLc9kEOcxQDW+OmaENd1OlOeXiz7vJyPMIl7s= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 11/46] target/ppc: Disconnect hflags from MSR Date: Tue, 4 May 2021 15:52:37 +1000 Message-Id: <20210504055312.306823-12-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ivan Warren , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Copying flags directly from msr has drawbacks: (1) msr bits mean different things per cpu, (2) msr has 64 bits on 64 cpus while tb->flags has only 32 bits. Create a enum to define these bits. Document the origin of each bit and validate those bits that must match MSR. This fixes the truncation of env->hflags to tb->flags, because we no longer have hflags bits set above bit 31. Most of the code in ppc_tr_init_disas_context is moved over to hreg_compute_hflags. Some of it is simple extractions from msr, some requires examining other cpu flags. Anything that is moved becomes a simple extract from hflags in ppc_tr_init_disas_context. Several existing bugs are left in ppc_tr_init_disas_context, where additional changes are required -- to be addressed in future patches. Remove a broken #if 0 block. Reported-by: Ivan Warren Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-3-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 25 ++++++++++++++++ target/ppc/helper_regs.c | 65 +++++++++++++++++++++++++++++++++------- target/ppc/translate.c | 55 ++++++++++------------------------ 3 files changed, 95 insertions(+), 50 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fd13489dce..fe6c3f815d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -585,6 +585,31 @@ enum { POWERPC_FLAG_HID0_LE = 0x00400000, }; +/* + * Bits for env->hflags. + * + * Most of these bits overlap with corresponding bits in MSR, + * but some come from other sources. Those that do come from + * the MSR are validated in hreg_compute_hflags. + */ +enum { + HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */ + HFLAGS_HV = 1, /* computed from MSR_HV and other state */ + HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ + HFLAGS_DR = 4, /* MSR_DR */ + HFLAGS_IR = 5, /* MSR_IR */ + HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ + HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ + HFLAGS_TM = 8, /* computed from MSR_TM */ + HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ + HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ + HFLAGS_FP = 13, /* MSR_FP */ + HFLAGS_PR = 14, /* MSR_PR */ + HFLAGS_SA = 22, /* MSR_SA */ + HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ +}; + /*****************************************************************************/ /* Floating point status and control register */ #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index a87e354ca2..df9673b90f 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" +#include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" @@ -87,24 +88,66 @@ void hreg_compute_mem_idx(CPUPPCState *env) void hreg_compute_hflags(CPUPPCState *env) { - target_ulong hflags_mask; + target_ulong msr = env->msr; + uint32_t ppc_flags = env->flags; + uint32_t hflags = 0; + uint32_t msr_mask; - /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ - hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | - (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); - hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; - hreg_compute_mem_idx(env); - env->hflags = env->msr & hflags_mask; + /* Some bits come straight across from MSR. */ + QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); + QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); + QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); + QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR); + QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); + QEMU_BUILD_BUG_ON(MSR_SA != HFLAGS_SA); + QEMU_BUILD_BUG_ON(MSR_AP != HFLAGS_AP); + msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | + (1 << MSR_DR) | (1 << MSR_IR) | + (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); - if (env->flags & POWERPC_FLAG_HID0_LE) { + if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* * Note that MSR_LE is not set in env->msr_mask for this cpu, - * and so will never be set in msr or hflags at this point. + * and so will never be set in msr. */ uint32_t le = extract32(env->spr[SPR_HID0], 3, 1); - env->hflags |= le << MSR_LE; + hflags |= le << MSR_LE; + } + + if (ppc_flags & POWERPC_FLAG_BE) { + QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); + msr_mask |= 1 << MSR_SE; + } + + if (msr_is_64bit(env, msr)) { + hflags |= 1 << HFLAGS_64; + } + if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { + hflags |= 1 << HFLAGS_SPE; + } + if (ppc_flags & POWERPC_FLAG_VRE) { + QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); + msr_mask |= 1 << MSR_VR; } + if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { + hflags |= 1 << HFLAGS_VSX; + } + if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { + hflags |= 1 << HFLAGS_TM; + } + +#ifndef CONFIG_USER_ONLY + if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { + hflags |= 1 << HFLAGS_HV; + } +#endif + + env->hflags = hflags | (msr & msr_mask); + hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0984ce637b..a9325a12e5 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7879,67 +7879,48 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUPPCState *env = cs->env_ptr; + uint32_t hflags = ctx->base.tb->flags; int bound; ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; - ctx->pr = msr_pr; + ctx->pr = (hflags >> HFLAGS_PR) & 1; ctx->mem_idx = env->dmmu_idx; - ctx->dr = msr_dr; -#if !defined(CONFIG_USER_ONLY) - ctx->hv = msr_hv || !env->has_hv_mode; -#endif + ctx->dr = (hflags >> HFLAGS_DR) & 1; + ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; ctx->insns_flags2 = env->insns_flags2; ctx->access_type = -1; ctx->need_access_type = !mmu_is_64bit(env->mmu_model); - ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); + ctx->le_mode = (hflags >> HFLAGS_LE) & 1; ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; ctx->flags = env->flags; #if defined(TARGET_PPC64) - ctx->sf_mode = msr_is_64bit(env, env->msr); + ctx->sf_mode = (hflags >> HFLAGS_64) & 1; ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); #endif ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B || env->mmu_model == POWERPC_MMU_601 || env->mmu_model & POWERPC_MMU_64; - ctx->fpu_enabled = !!msr_fp; - if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { - ctx->spe_enabled = !!msr_spe; - } else { - ctx->spe_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { - ctx->altivec_enabled = !!msr_vr; - } else { - ctx->altivec_enabled = false; - } - if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { - ctx->vsx_enabled = !!msr_vsx; - } else { - ctx->vsx_enabled = false; - } + ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; + ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; + ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; + ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; if ((env->flags & POWERPC_FLAG_SCV) && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { ctx->scv_enabled = true; } else { ctx->scv_enabled = false; } -#if defined(TARGET_PPC64) - if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { - ctx->tm_enabled = !!msr_tm; - } else { - ctx->tm_enabled = false; - } -#endif + ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); - if ((env->flags & POWERPC_FLAG_SE) && msr_se) { - ctx->singlestep_enabled = CPU_SINGLE_STEP; - } else { - ctx->singlestep_enabled = 0; + + ctx->singlestep_enabled = 0; + if ((hflags >> HFLAGS_SE) & 1) { + ctx->singlestep_enabled |= CPU_SINGLE_STEP; } - if ((env->flags & POWERPC_FLAG_BE) && msr_be) { + if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } if ((env->flags & POWERPC_FLAG_DE) && msr_de) { @@ -7956,10 +7937,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } -#if defined(DO_SINGLE_STEP) && 0 - /* Single step trace mode */ - msr_se = 1; -#endif bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns = MIN(ctx->base.max_insns, bound); From patchwork Tue May 4 05:52:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430816 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3495391jao; Mon, 3 May 2021 23:08:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdsdsLpsbX/xfDYv/5tWiTPy8TUkIy0WEpn2wzYnJ57p89/umcUMvgsWsoEqX7jICIS02T X-Received: by 2002:a1f:aecf:: with SMTP id x198mr18802407vke.6.1620108498443; Mon, 03 May 2021 23:08:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108498; cv=none; d=google.com; s=arc-20160816; b=0reAY7mERgEQS5r1oQVagDu18iT2/buNiVDcOnBHUQqWsYPITor/R+qXIEV04RRvPR kITAFETcXhSRZsgBkCAXPYgtAJsqOyMDUXpBkFwqV2T/ES0n/m+xzyy6eT/bRSySMp/2 azdiFTLIofD0Gylb0q/mEMTQ2BmhNnDcVCX5e/F2bGO2eek2+GhvBReLJ9JZH8K4VGmi MdQURsJWC6za2j+Llv4ae0DfhTAiGdpE2SP+7nCEtGWjLSnbkTu+3feS/i7WluImJTDT pYIZryElJo2PZ3Sat0j0EyXJ1cwaRRryrVMbgG+etj+o28cSAi/F2M8YDUrjfMa+cLsZ 5QJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7+0Zdz8aDWQUYaiGKm0jzmmEl4d8buVqy3MK1NHhVZA=; b=gjXN2Rz1cSHbpHZ9jNY2qvcKTHlN+1uS/VQ6x5aJYWEqHm0YbyCnd3ujUMG5uOkQUo Uv7GUEPMsc6j6f/h+lkV7VuyxcS9JLZSomZRRxcgxDpQKnVF6W6/p2viZRi+zRdPaN3O iA5g+YyYXgehAuqRa8YdWBVdtSugHP2Nr/Bhowzc29mDLcNQwMLN+5sfLD2vG11oE00L jC2sync1Irwy3OasOSMLYtLhWL2SFUJJBfYlPLg91YtS1VzmrNUHjm220gVA553AIJuB gBaioSY3cqg/Ny6XYTCQbN6Ki5O65ZyDY85j+KkP831KzInfHO7tQRVdNTwu5gepFXqj gzig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=EHtLWjbj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d8si401028vsj.247.2021.05.03.23.08.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:08:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=EHtLWjbj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:46340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoED-00016t-Nh for patch@linaro.org; Tue, 04 May 2021 02:08:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo00-0005Fn-RV; Tue, 04 May 2021 01:53:36 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:45969 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzu-0004h3-PK; Tue, 04 May 2021 01:53:34 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK3TXjz9sWp; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=9Q0vDRcy2WGfG9TN8BUHQg8bYCUSstmE97i7Vbf7JZ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EHtLWjbjww+dIgUQ9FjO/CFpUljMUlGIvKr4XZAVP0wpKd4J6Kz2P4HpO4+jmG88k dr2ZcGxJi9xSf51zEzKyBpp4hB9BSJqMbaLIRno3vAMgILqJrq1IzldCkRkhYq52Cr lLkeyGkcTaizVVXUshIld/2opdfOx+T0stLCsglI= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 12/46] target/ppc: Reduce env->hflags to uint32_t Date: Tue, 4 May 2021 15:52:38 +1000 Message-Id: <20210504055312.306823-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson It will be stored in tb->flags, which is also uint32_t, so let's use the correct size. Reviewed-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-4-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 ++-- target/ppc/misc_helper.c | 2 +- target/ppc/translate.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index fe6c3f815d..d5f362506a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1129,8 +1129,8 @@ struct CPUPPCState { bool resume_as_sreset; #endif - /* These resources are used only in QEMU core */ - target_ulong hflags; + /* These resources are used only in TCG */ + uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ int immu_idx; /* precomputed MMU index to speed up insn accesses */ int dmmu_idx; /* precomputed MMU index to speed up data accesses */ diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 63e3147eb4..b04b4d7c6e 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -199,7 +199,7 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) if ((val ^ hid0) & 0x00000008) { /* Change current endianness */ hreg_compute_hflags(env); - qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, + qemu_log("%s: set endianness to %c => %08x\n", __func__, val & 0x8 ? 'l' : 'b', env->hflags); } } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a9325a12e5..a85b890bb0 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7657,7 +7657,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) env->nip, env->lr, env->ctr, cpu_read_xer(env), cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " - TARGET_FMT_lx " iidx %d didx %d\n", + "%08x iidx %d didx %d\n", env->msr, env->spr[SPR_HID0], env->hflags, env->immu_idx, env->dmmu_idx); #if !defined(NO_TIMER_DUMP) From patchwork Tue May 4 05:52:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430814 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3494489jao; Mon, 3 May 2021 23:06:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsGhzJjw8Yj6op+tPhfUTkc4LMt1QrPw9VxI/0jNPrvsd/jEh1zHFSeiQA8u6WVaLpYxbd X-Received: by 2002:ab0:6031:: with SMTP id n17mr18634810ual.128.1620108405761; Mon, 03 May 2021 23:06:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108405; cv=none; d=google.com; s=arc-20160816; b=OQODTVPtNZj6K+Acms6KgGK1gklZtSVfANMeRx99x17Ef3Bp8dy2UbC0PgxItMRRE6 4esM/PY7uea+6eLignyvxioXEH5Zc7vsUnPmqJuA+jUkrWfKwbfCKtN6ztdP18Ba89/U 96aKPPNfGTfFVxyU3j4ME/YRsHv7CnRsjgDq7MGMG8TWLyzB5yTg8zLeuFo4rYX8xSvq DwITaxnak9UdMZhqMd6P3n8KVcgh97jcQ5HaDmRqlia7Lzh86Xc1+pzvNZQ69frFh2Xv +yeXwuLPm/XLoIHyJ7S5bVA3xWBliUsAz9WEwsy4r/hex4NnCabQtf7CTZdbZOeStjil e0XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vsKXNQHEN/ClCvwk35VaRNDFhlIVq9m/oiLEG9b2sCY=; b=qPzNN/llvlGb4C/ZUWViZg818xpa4JG9tTLZLHOg8Y2ljgtHXu8+InKw7hxN/WTlzj A3nVNErtei1ATAjBOuRrSv0brhBtRAj8t20+g6KkK/fjuM2OE0mpLcFPpUhruKJT5c5L ld1EJoXOaqtdGkm7OvIMJcyb1n0R4kWSo7h2vKbv+zhqF3CLmscnjmc/qEJsXilFZdcc a2indi8UHvA3OLO9optnyfsb7Zldgdgw8UxxS7EbNG7LDrwpEI4xUY15rbfcaUxTgzuE mpzvpwBM0atPwajSsIxQsRHeOC4rGI7uvSnZNR1m6jfYmq5EenaRt9Z7Jg4TN8QjLKwy g9Fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="CG/zmRBj"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r18si6941900vsj.440.2021.05.03.23.06.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:06:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="CG/zmRBj"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:41742 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoCj-0007P5-4t for patch@linaro.org; Tue, 04 May 2021 02:06:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo04-0005IN-FP; Tue, 04 May 2021 01:53:42 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:49839) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzy-0004ie-Uv; Tue, 04 May 2021 01:53:39 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK4BjVz9sX5; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=AE/4n5PGUFoays6zdARQ1IYd5KqZTCtHN4fMxuKqurw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CG/zmRBj11BgKHf0CMIk3b+0a/IQ3qoo7/funvWg9rGiqlypcfw4yItCqMdaSLEII dd/XWbcASUARDs4Hj/5xlSBdCmtovbYdh58aaIodPA6ZcmTO/v3bHjPqTudMVxn8Jp 6vwWsW2239DGCFiGNX/9AzO4CKfhgufVnDyWfYDo= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 13/46] target/ppc: Put dbcr0 single-step bits into hflags Date: Tue, 4 May 2021 15:52:39 +1000 Message-Id: <20210504055312.306823-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Because these bits were not in hflags, the code generated for single-stepping on BookE was essentially random. Recompute hflags when storing to dbcr0. Reviewed-by: David Gibson Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-5-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/helper_regs.c | 24 +++++++++++++++++------- target/ppc/misc_helper.c | 3 +++ target/ppc/translate.c | 11 ----------- 3 files changed, 20 insertions(+), 18 deletions(-) -- 2.31.1 diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index df9673b90f..e345966b6b 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -114,13 +114,23 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= le << MSR_LE; } - if (ppc_flags & POWERPC_FLAG_BE) { - QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); - msr_mask |= 1 << MSR_BE; - } - if (ppc_flags & POWERPC_FLAG_SE) { - QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); - msr_mask |= 1 << MSR_SE; + if (ppc_flags & POWERPC_FLAG_DE) { + target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; + if (dbcr0 & DBCR0_ICMP) { + hflags |= 1 << HFLAGS_SE; + } + if (dbcr0 & DBCR0_BRT) { + hflags |= 1 << HFLAGS_BE; + } + } else { + if (ppc_flags & POWERPC_FLAG_BE) { + QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); + msr_mask |= 1 << MSR_BE; + } + if (ppc_flags & POWERPC_FLAG_SE) { + QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); + msr_mask |= 1 << MSR_SE; + } } if (msr_is_64bit(env, msr)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index b04b4d7c6e..002958be26 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -215,6 +215,9 @@ void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) { + /* Bits 26 & 27 affect single-stepping. */ + hreg_compute_hflags(env); + /* Bits 28 & 29 affect reset or shutdown. */ store_40x_dbcr0(env, val); } diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a85b890bb0..7912495f28 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7923,17 +7923,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) if ((hflags >> HFLAGS_BE) & 1) { ctx->singlestep_enabled |= CPU_BRANCH_STEP; } - if ((env->flags & POWERPC_FLAG_DE) && msr_de) { - ctx->singlestep_enabled = 0; - target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; - if (dbcr0 & DBCR0_ICMP) { - ctx->singlestep_enabled |= CPU_SINGLE_STEP; - } - if (dbcr0 & DBCR0_BRT) { - ctx->singlestep_enabled |= CPU_BRANCH_STEP; - } - - } if (unlikely(ctx->base.singlestep_enabled)) { ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; } From patchwork Tue May 4 05:52:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430809 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3492952jao; Mon, 3 May 2021 23:04:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwvrMiq8MTIoUsCStv8Ad/9SjIh7aftJK59/xT7YCyeRkdOFsdsuuW9oBLRbsA2zhJeKt6m X-Received: by 2002:a9f:2c04:: with SMTP id r4mr18963542uaj.123.1620108257110; Mon, 03 May 2021 23:04:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108257; cv=none; d=google.com; s=arc-20160816; b=FJy4HHFrgc7/ZzmPHgcEJlmXEWm19nepqD3EUPwOyTIjnklr7tGfRCx6B2Dq6rhXuf C+v2VLv1rbzTezzyLjfEoZEgPyVSBM3z+U0CJEzAU78r+i7M7YETKq6GuhI50movyPvD Bt5idoinE5plGKFs8Ts+fohwl88bm53MmmElSoifsRORW6EDaxBNzHyQ10fJrcMUBrxU EFkAJ2W7NkqoRPO1Ua5FBcOEu2TPoSRcBj4LtU/H5/QTade4Q6idWJFKZaI/D6sne41M 4TVvgnW4zyYsLyNOvDkP6J26Ud5fmKz1SKeARVEgBSjGqBWvYXLz5B8sAeToMc8zlCoK h9PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DSrOVqqvsuDx4ZGTKch5p1+QDSPmVAqK0JF9JnO3tNw=; b=vuoM+n1r4kKicUKNbHq63pa1eUU+6SIaJfEovCmy1nrYCnYKnr3CSFZLjQosK/lkcw Mb87ZlcVU6MOl8ffjbLRHq4qq3UfUnbMiR/Js93fXAIw7L7f9zK5vCaoBLeAuEL3skq9 5FMI8qc+7HGFpZGHQ//N4tB6Uah/an5x9wUyI/SXx1FTJL/rD/vtCJmp1mpJK71ZzXEt WIAH5X8o+dekSujI9rsh2IDeRVRZTzJrNq16+BGzMBl0E2nuj5nG8w6r3aeRTxqAP5+P W7tIUOCFM8+h0yeTBPvQizcrcuUqPgLsfZPsRD4/y7doajblp/hUqJlSoZDhmjxTkgfM z1Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="SS2Zb5K/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e12si7128078vsj.54.2021.05.03.23.04.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:04:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="SS2Zb5K/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:37828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoAK-0005hs-FC for patch@linaro.org; Tue, 04 May 2021 02:04:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60480) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo00-0005Fk-Rr; Tue, 04 May 2021 01:53:36 -0400 Received: from ozlabs.org ([203.11.71.1]:35751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzx-0004iX-Ds; Tue, 04 May 2021 01:53:35 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK3r9Gz9sWq; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=x/kaaARkUFgaoRSSOlm3/nAAxu0ti8r5riiog6MzMng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SS2Zb5K/3uP1HmLgP5f7Kc0o6l6jaXc1h2Ey54o4xWjRVQ2UNf37tLM5WEe50CGgC jjKENZ2oGHnNGs3raVfzXB08AJoEh6qWZDSB6SzHTgjD+veeYAM/BS/82oWMPjCt0l VERgCXZiBWjaLaCxMTTLpXSsAI6Md8OKq+MiYnqY= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 14/46] target/ppc: Create helper_scv Date: Tue, 4 May 2021 15:52:40 +1000 Message-Id: <20210504055312.306823-15-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Perform the test against FSCR_SCV at runtime, in the helper. This means we can remove the incorrect set against SCV in ppc_tr_init_disas_context and do not need to add an HFLAGS bit. Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-6-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/excp_helper.c | 9 +++++++++ target/ppc/helper.h | 1 + target/ppc/translate.c | 20 +++++++------------- 3 files changed, 17 insertions(+), 13 deletions(-) -- 2.31.1 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 85de7e6c90..5c95e0c103 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1130,6 +1130,15 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) } #if defined(TARGET_PPC64) +void helper_scv(CPUPPCState *env, uint32_t lev) +{ + if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { + raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); + } else { + raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); + } +} + void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) { CPUState *cs; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 6a4dccf70c..513066d54d 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -13,6 +13,7 @@ DEF_HELPER_1(rfci, void, env) DEF_HELPER_1(rfdi, void, env) DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) +DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7912495f28..d48c554290 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -173,7 +173,6 @@ struct DisasContext { bool vsx_enabled; bool spe_enabled; bool tm_enabled; - bool scv_enabled; bool gtse; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; @@ -4081,15 +4080,16 @@ static void gen_sc(DisasContext *ctx) #if !defined(CONFIG_USER_ONLY) static void gen_scv(DisasContext *ctx) { - uint32_t lev; + uint32_t lev = (ctx->opcode >> 5) & 0x7F; - if (unlikely(!ctx->scv_enabled)) { - gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_SCV); - return; + /* Set the PC back to the faulting instruction. */ + if (ctx->exception == POWERPC_EXCP_NONE) { + gen_update_nip(ctx, ctx->base.pc_next - 4); } + gen_helper_scv(cpu_env, tcg_constant_i32(lev)); - lev = (ctx->opcode >> 5) & 0x7F; - gen_exception_err(ctx, POWERPC_SYSCALL_VECTORED, lev); + /* This need not be exact, just not POWERPC_EXCP_NONE */ + ctx->exception = POWERPC_SYSCALL_VECTORED; } #endif #endif @@ -7907,12 +7907,6 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; - if ((env->flags & POWERPC_FLAG_SCV) - && (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) { - ctx->scv_enabled = true; - } else { - ctx->scv_enabled = false; - } ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); From patchwork Tue May 4 05:52:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430806 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3491798jao; Mon, 3 May 2021 23:02:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhWSLCQH5mb5yY7xNjkb/f4haJSSrMToU6MJNSm9GeuF+D6Fr0XhfqUvfNK9D6OLrlXf83 X-Received: by 2002:ab0:4757:: with SMTP id i23mr18945631uac.87.1620108147777; Mon, 03 May 2021 23:02:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108147; cv=none; d=google.com; s=arc-20160816; b=eCJdhpUExaxShHxL9dX8TNHbXXLavNe0+Zf+zjUw56iYbbWwYycv3jImNae1lDZwN/ x2D0BfKmnQ6CEjY35ciOWSeJ0bZtXVJXUUFOCkCWE/IvMUbRgIfq9tpEHQ25K6DLygZw B9TVHlRKx3M17c+enzix1be65B6BUgmVd6pORqtbOZjQGT766Aqk6afLWB2nYFfM2Isp PM6USM+SytpYRuRU8MW+3dWsIzJx4Qu6p/kqdPhqd7ohTa1KBmZBYezD2In8pNcC0n6S W8lQ/rhEeEZCZ6zBKs8YTwSOuMyvd4XOhO/B8vD9C/miootDGoHt0cbiUnL4jCYdp7Mg X/dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=g56ZJv2rLl0TdfoNa2Rr4NI9ATwJQTuugbn8uua26ps=; b=YojzH8D23xyMlMxrO34yGiQkZQE1LYdZJnNj9nnaBhb2mr7mPO04dT7XWlLFCz72R1 5BzWVBkKwBp7eb12hQy7O2+SMCESxktEKl5/rac6WgQrvMNNgOvjlpap6/CDCUJkCEeE ahl4xkvxyPBMhS45J8pL4O4PXLTtNL25MhYaMLKscFDTXFGsqpIDoXLfuHCm2m9HtyTy bp0Ftky73IQhBBOFUBIsXs9hhAm/gkvLSeBEU4PM2hhLIrYpUkKvKvuqmXsurMmZBgfh pmT4m5af215Wb3NiLdPN7GaCqMjo41wlPP59jPzJuimtDX9cLuwYGXQi1f0vn4Db9oc9 z09w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=AnXHInv5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u3si6357730vse.90.2021.05.03.23.02.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:02:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=AnXHInv5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:33306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldo8X-0003dU-0Z for patch@linaro.org; Tue, 04 May 2021 02:02:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo02-0005Hc-IK; Tue, 04 May 2021 01:53:39 -0400 Received: from ozlabs.org ([203.11.71.1]:39851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldnzz-0004kR-Cw; Tue, 04 May 2021 01:53:37 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK4VJQz9sX3; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=EOPu6ADeRLGhAyKKyY2SdVCCjqq706WI0Er+aWaZJ8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AnXHInv5jo+304cUKO5rozSV2twH5FZNjMPDqQ4PAZRhJgM4jHLFwt1z0eNg/9RT2 fNu0Oj2NiodXUeoBknFdWAjIyrrOF7DHnKcQLiJTxC3KkWJX3jk1k/uIxZ6QVfD+V6 aPgE1SI5CLnU+ej1HgXGKMmtGt8a+TsF1/h3Uz78= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 15/46] target/ppc: Put LPCR[GTSE] in hflags Date: Tue, 4 May 2021 15:52:41 +1000 Message-Id: <20210504055312.306823-16-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Because this bit was not in hflags, the privilege check for tlb instructions was essentially random. Recompute hflags when storing to LPCR. Reviewed-by: David Gibson Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-7-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 1 + target/ppc/helper_regs.c | 3 +++ target/ppc/mmu-hash64.c | 3 +++ target/ppc/translate.c | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d5f362506a..3c28ddb331 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -596,6 +596,7 @@ enum { HFLAGS_LE = 0, /* MSR_LE -- comes from elsewhere on 601 */ HFLAGS_HV = 1, /* computed from MSR_HV and other state */ HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ + HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */ HFLAGS_DR = 4, /* MSR_DR */ HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index e345966b6b..f85bb14d1d 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -149,6 +149,9 @@ void hreg_compute_hflags(CPUPPCState *env) if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; } + if (env->spr[SPR_LPCR] & LPCR_GTSE) { + hflags |= 1 << HFLAGS_GTSE; + } #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0fabc10302..d517a99832 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "hw/hw.h" #include "mmu-book3s-v3.h" +#include "helper_regs.h" /* #define DEBUG_SLB */ @@ -1125,6 +1126,8 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env = &cpu->env; env->spr[SPR_LPCR] = val & pcc->lpcr_mask; + /* The gtse bit affects hflags */ + hreg_compute_hflags(env); } void helper_store_lpcr(CPUPPCState *env, target_ulong val) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d48c554290..5e629291d3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7908,7 +7908,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; - ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); + ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) { From patchwork Tue May 4 05:52:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430822 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3501687jao; Mon, 3 May 2021 23:19:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxaKIo/Bdp/Fyf5vsXWAVFPoyF2k5BlWuzFqDMx2rRfwE6BOy/dV59TFPqFhXao0EipJvlT X-Received: by 2002:ab0:3a6:: with SMTP id 35mr18766476uau.29.1620109180238; Mon, 03 May 2021 23:19:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620109180; cv=none; d=google.com; s=arc-20160816; b=T8fZii3eDV7d2NZ5UEdIiTpu9KJbocdUb9e/PU7w/sgpwTpawfwlxf931BgBZApFBg zmxquJ0w9GKJCnlBD2l/YrL/TkmNpUrNaHBKud9rXUqMRMY+xZlrbcgXpUvnWsIyQHeV iEdZhtyhY0lU0RiEkS8BHErBya+gV4Ye0YZFYVuy3CIl1Vs0N1u2h9XkijXIklrlodBj nKdlWsgBbf3N1aH1fbchE5lCFEc4fscM/9ijmKBH6Uc4tVBpa2KmppfJOFLsvO7ZwBYA CPtTryliUuQAWu7r3n831wwZiZAlf2qp+YKzp94C5UH8Cz0HcCSOASOXlcVsWgsjuGCr yImQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pZNpWidWt5EUj1W7OhnVyZqGsMHC6/xIeJNs62nx1R8=; b=eQT2h0IkyHn1ouU4sJzkb9rWPc6XUKNp7Bs/tKzQb6LGuYBorrLmJDYy5qCGUbhNQ2 C9uJ2C9cVKMUq6ajmVYC1dWO+p4xpso2atRkCtCAEj/YlGdrNG1Ah6FX7KqRycRXsHJe YNMGVV2XCjTcMxFXn4oLUNA3bEWSxreMKAsRm5U/wnpi7nI3Cxs/h7E62X5VeeoNVvtV 4ZPfALmaaFmUGsjkGl0iB5mnzVyhu0k6dGKSBQI+Sf0MPWCI1gTvVvLB7dWWnt/shbJX P5GzfceVvkv8q+ifnmwAgDKxaX+1XXXXdHY0YsrqNASeHg5kvm/eDpX51s2erx5NEjwF yDBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="azv2z9J/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t4si3280948vsj.142.2021.05.03.23.19.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:19:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="azv2z9J/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:35086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoP6-0000SK-GO for patch@linaro.org; Tue, 04 May 2021 02:19:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo04-0005IM-FK; Tue, 04 May 2021 01:53:42 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:51127 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo00-0004kV-Pa; Tue, 04 May 2021 01:53:39 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK4xscz9sXH; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=Xk1wYOuZSpZWxh2ux/tBAmxZ1jpImU1ImlZmhp9mW8o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=azv2z9J/mErL83AOAoT9QXVFaLY4N1WtUEUecMWWwpubJbocbTTUdU+3M5FDyHf97 CzJDjWPDrPrJQlvptPRrFjXujgYi9ujgJyh1y9iM0yDmyVatnNOPqSjetDOBZ6/U2a 4CKRHOVczwG/GLggkGyJfrlOIqX6OrG2nJ4rjyKY= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 16/46] target/ppc: Remove MSR_SA and MSR_AP from hflags Date: Tue, 4 May 2021 15:52:42 +1000 Message-Id: <20210504055312.306823-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Nothing within the translator -- or anywhere else for that matter -- checks MSR_SA or MSR_AP on the 602. This may be a mistake. However, for the moment, we need not record these bits in hflags. This allows us to simplify HFLAGS_VSX computation by moving it to overlap with MSR_VSX. Reviewed-by: David Gibson Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-8-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 4 +--- target/ppc/helper_regs.c | 10 ++++------ 2 files changed, 5 insertions(+), 9 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3c28ddb331..2f72f83ee3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -600,14 +600,12 @@ enum { HFLAGS_DR = 4, /* MSR_DR */ HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ - HFLAGS_VSX = 7, /* from MSR_VSX if cpu has VSX; avoid overlap w/ MSR_AP */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */ HFLAGS_FP = 13, /* MSR_FP */ HFLAGS_PR = 14, /* MSR_PR */ - HFLAGS_SA = 22, /* MSR_SA */ - HFLAGS_AP = 23, /* MSR_AP */ + HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ }; diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index f85bb14d1d..dd3cd770a3 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -99,11 +99,8 @@ void hreg_compute_hflags(CPUPPCState *env) QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR); QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); - QEMU_BUILD_BUG_ON(MSR_SA != HFLAGS_SA); - QEMU_BUILD_BUG_ON(MSR_AP != HFLAGS_AP); msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | - (1 << MSR_FP) | (1 << MSR_SA) | (1 << MSR_AP)); + (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -143,8 +140,9 @@ void hreg_compute_hflags(CPUPPCState *env) QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); msr_mask |= 1 << MSR_VR; } - if ((ppc_flags & POWERPC_FLAG_VSX) && (msr & (1 << MSR_VSX))) { - hflags |= 1 << HFLAGS_VSX; + if (ppc_flags & POWERPC_FLAG_VSX) { + QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX); + msr_mask |= 1 << MSR_VSX; } if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { hflags |= 1 << HFLAGS_TM; From patchwork Tue May 4 05:52:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430821 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3499898jao; Mon, 3 May 2021 23:16:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHeUiRxgQ4sqarRuGyD6c3t1hXn9lojc6r/jSaJflTEGxXYUI8wnHuGlcC4dKTtO5J9hjY X-Received: by 2002:a67:3310:: with SMTP id z16mr10717233vsz.25.1620108969109; Mon, 03 May 2021 23:16:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108969; cv=none; d=google.com; s=arc-20160816; b=BXIregGktHXFgwozjlBSP+jH/mmwwpCG73HhIk2xit0IC3la1nlp14eBMokeP7HR5F QMhj7QthaF6EEjsx4HZTB8nY7R3ODqXMBwyUSKmLjh/8T9NPdiiZK976OirQv9kO7SZ2 Lh0b//mqbzZwehUjXKombnz0wg/TehFMNwyE4gzYH6T4txHHTpZenN03v7iVdni6kpAE sTiUBAFqhVHtBPAtZys+lL7a/GQicyw/RGIvlLJ1tCtXhlrgQ/lpxxGhzp8Ojy25hC4b QvFE8AdhnJJMDqcqZHNyfvdI3LZZb0nqR1FGcApLOaQjABzln3wC9HYubpw3OYu6JX/K 4ywQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BNYTwbEHdNQRHjp+K02XFh5gtx8O9h7N4nvIVbaFMkU=; b=0A7fqCRiHbLTj32OYzv6uA2D1PxIutOAVEPWPilwgq3wlAwq5kTzVjdYGuKZq5oqb8 1tK5KEE3wFMRuw3C0tzAPEislZPbTc/cpUTA3yMQbHc1r1fviDZ1AN8E5v/enRYhRhyw rxD8Wgg7zxnnZCXn6zL71j1oBAx6rgJTR9TsFdgW30wIp1vkWQOZYcWkm5sC6qPA3ubh BTfGyJA3ROTmjMrhi+WSMzZAsKKV42LaDr7SzRjnnXaJ4HSd68Pd6SK4o4boHloAccIp R6TRZvLMoYG32+2PbRksbUOwFcYoHeucdlZApt/vL7l82Lv7+6q7p/RzSPb2TCiwCEzi 1pjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=YICwhH+P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s189si5968805vka.16.2021.05.03.23.16.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:16:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=YICwhH+P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoLo-0005nB-Fw for patch@linaro.org; Tue, 04 May 2021 02:16:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo06-0005JT-DP; Tue, 04 May 2021 01:53:43 -0400 Received: from ozlabs.org ([203.11.71.1]:44901) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo02-0004mZ-QF; Tue, 04 May 2021 01:53:41 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK5GgVz9sXM; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=PqIL/NNdjNzqldj5TBgHl3AG7TfjMwpEseQKUgN7u/c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YICwhH+PdEqi2j1lr/vqi1jyfu3DOdxQgkwywDqD4GY2n5jhTi3ue5qb6PS5a//Ww Hi6MKrlK2U4z+fzDLSc3r197bqkWwPB1cwlH6fIsb/7p7nh8Kg1ukQ8DKW3qHw9AaK wFFmyF15MW3Me3vuD8aRttgWx3hBF1mLXnbbBVhg= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 17/46] target/ppc: Remove env->immu_idx and env->dmmu_idx Date: Tue, 4 May 2021 15:52:43 +1000 Message-Id: <20210504055312.306823-18-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We weren't recording MSR_GS in hflags, which means that BookE memory accesses were essentially random vs Guest State. Instead of adding this bit directly, record the completed mmu indexes instead. This makes it obvious that we are recording exactly the information that we need. This also means that we can stop directly recording MSR_IR. Reviewed-by: David Gibson Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-9-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 12 ++++-- target/ppc/helper_regs.c | 89 +++++++++++++++++++--------------------- target/ppc/helper_regs.h | 1 - target/ppc/machine.c | 2 +- target/ppc/mem_helper.c | 2 +- target/ppc/translate.c | 6 +-- 6 files changed, 56 insertions(+), 56 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2f72f83ee3..3d021f61f3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -598,7 +598,6 @@ enum { HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */ HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */ HFLAGS_DR = 4, /* MSR_DR */ - HFLAGS_IR = 5, /* MSR_IR */ HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */ HFLAGS_TM = 8, /* computed from MSR_TM */ HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */ @@ -607,6 +606,9 @@ enum { HFLAGS_PR = 14, /* MSR_PR */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ + + HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */ + HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */ }; /*****************************************************************************/ @@ -1131,8 +1133,6 @@ struct CPUPPCState { /* These resources are used only in TCG */ uint32_t hflags; target_ulong hflags_compat_nmsr; /* for migration compatibility */ - int immu_idx; /* precomputed MMU index to speed up insn accesses */ - int dmmu_idx; /* precomputed MMU index to speed up data accesses */ /* Power management */ int (*check_pow)(CPUPPCState *env); @@ -1368,7 +1368,11 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define MMU_USER_IDX 0 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) { - return ifetch ? env->immu_idx : env->dmmu_idx; +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; +#endif } /* Compatibility modes */ diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index dd3cd770a3..5411a67e9a 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,49 +43,6 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_mem_idx(CPUPPCState *env) -{ - /* - * This is our encoding for server processors. The architecture - * specifies that there is no such thing as userspace with - * translation off, however it appears that MacOS does it and some - * 32-bit CPUs support it. Weird... - * - * 0 = Guest User space virtual mode - * 1 = Guest Kernel space virtual mode - * 2 = Guest User space real mode - * 3 = Guest Kernel space real mode - * 4 = HV User space virtual mode - * 5 = HV Kernel space virtual mode - * 6 = HV User space real mode - * 7 = HV Kernel space real mode - * - * For BookE, we need 8 MMU modes as follow: - * - * 0 = AS 0 HV User space - * 1 = AS 0 HV Kernel space - * 2 = AS 1 HV User space - * 3 = AS 1 HV Kernel space - * 4 = AS 0 Guest User space - * 5 = AS 0 Guest Kernel space - * 6 = AS 1 Guest User space - * 7 = AS 1 Guest Kernel space - */ - if (env->mmu_model & POWERPC_MMU_BOOKE) { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_is ? 2 : 0; - env->dmmu_idx += msr_ds ? 2 : 0; - env->immu_idx += msr_gs ? 4 : 0; - env->dmmu_idx += msr_gs ? 4 : 0; - } else { - env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; - env->immu_idx += msr_ir ? 0 : 2; - env->dmmu_idx += msr_dr ? 0 : 2; - env->immu_idx += msr_hv ? 4 : 0; - env->dmmu_idx += msr_hv ? 4 : 0; - } -} - void hreg_compute_hflags(CPUPPCState *env) { target_ulong msr = env->msr; @@ -97,10 +54,9 @@ void hreg_compute_hflags(CPUPPCState *env) QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); - QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR); QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | - (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP)); + (1 << MSR_DR) | (1 << MSR_FP)); if (ppc_flags & POWERPC_FLAG_HID0_LE) { /* @@ -155,10 +111,51 @@ void hreg_compute_hflags(CPUPPCState *env) if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { hflags |= 1 << HFLAGS_HV; } + + /* + * This is our encoding for server processors. The architecture + * specifies that there is no such thing as userspace with + * translation off, however it appears that MacOS does it and some + * 32-bit CPUs support it. Weird... + * + * 0 = Guest User space virtual mode + * 1 = Guest Kernel space virtual mode + * 2 = Guest User space real mode + * 3 = Guest Kernel space real mode + * 4 = HV User space virtual mode + * 5 = HV Kernel space virtual mode + * 6 = HV User space real mode + * 7 = HV Kernel space real mode + * + * For BookE, we need 8 MMU modes as follow: + * + * 0 = AS 0 HV User space + * 1 = AS 0 HV Kernel space + * 2 = AS 1 HV User space + * 3 = AS 1 HV Kernel space + * 4 = AS 0 Guest User space + * 5 = AS 0 Guest Kernel space + * 6 = AS 1 Guest User space + * 7 = AS 1 Guest Kernel space + */ + unsigned immu_idx, dmmu_idx; + dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; + if (env->mmu_model & POWERPC_MMU_BOOKE) { + dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; + dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; + } else { + dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; + immu_idx = dmmu_idx; + immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; + dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; + } + hflags |= immu_idx << HFLAGS_IMMU_IDX; + hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif env->hflags = hflags | (msr & msr_mask); - hreg_compute_mem_idx(env); } void cpu_interrupt_exittb(CPUState *cs) diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 4148a442b3..42f26870b9 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -21,7 +21,6 @@ #define HELPER_REGS_H void hreg_swap_gpr_tgpr(CPUPPCState *env); -void hreg_compute_mem_idx(CPUPPCState *env); void hreg_compute_hflags(CPUPPCState *env); void cpu_interrupt_exittb(CPUState *cs); int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv); diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 09c5765a87..e5bffbe365 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -16,7 +16,7 @@ static void post_load_update_msr(CPUPPCState *env) /* * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB - * before restoring. Note that this recomputes hflags and mem_idx. + * before restoring. Note that this recomputes hflags. */ env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index f4f7e730de..444b2a30ef 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -278,7 +278,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr, target_ulong mask, dcbz_size = env->dcache_line_size; uint32_t i; void *haddr; - int mmu_idx = epid ? PPC_TLB_EPID_STORE : env->dmmu_idx; + int mmu_idx = epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); #if defined(TARGET_PPC64) /* Check for dcbz vs dcbzl on 970 */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5e629291d3..a53463b9b8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7658,8 +7658,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) cs->cpu_index); qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " "%08x iidx %d didx %d\n", - env->msr, env->spr[SPR_HID0], - env->hflags, env->immu_idx, env->dmmu_idx); + env->msr, env->spr[SPR_HID0], env->hflags, + cpu_mmu_index(env, true), cpu_mmu_index(env, false)); #if !defined(NO_TIMER_DUMP) qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 #if !defined(CONFIG_USER_ONLY) @@ -7885,7 +7885,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->exception = POWERPC_EXCP_NONE; ctx->spr_cb = env->spr_cb; ctx->pr = (hflags >> HFLAGS_PR) & 1; - ctx->mem_idx = env->dmmu_idx; + ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; ctx->dr = (hflags >> HFLAGS_DR) & 1; ctx->hv = (hflags >> HFLAGS_HV) & 1; ctx->insns_flags = env->insns_flags; From patchwork Tue May 4 05:52:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430820 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3499324jao; Mon, 3 May 2021 23:15:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzZ/pZhSewyxA4D+r7wrANHNANQ74MQtp0zhMah5QSY9t+SslJ60XDMXV08rPiCzzpLENm+ X-Received: by 2002:ab0:6309:: with SMTP id a9mr4887431uap.75.1620108903250; Mon, 03 May 2021 23:15:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108903; cv=none; d=google.com; s=arc-20160816; b=rBov4O/pQwPUUUYJmt75uAI2cFkyGiM51raG22XpXOmbQcDcG4MFO2z73kgODlbahb 3BQNnewQNGI4rA5ExfJ/c210iUdRpbXF6KULC7IgIo3gtzxH4au1XWsndoQJAMrKUgla qnU0bls84a/Wq/JT2UtWntrJR9FkxWsTLPnXB6wMvtA27qjy7rYRvvHg7FWGxxnYTLzl IWtqyIiwpvHuMLvKIzH0VKKtkwpaXbxnuYOEPBeA+bt0QpYfOZSRM3ER5q21d1EyfAAj 54bb3KsTYClbIQHN+V9a/ujMkxCfxpRFeE6jSLcs0BM08iTjZ9LJ/9zPFj7ytsuvOr5H Otcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=piwRJO5T5plEKoOiXYNnWwY6c3qD1aXFAuJpnWSJQDc=; b=zoi2d7KSbOFdh1KRN1AIcGOEDZq4MK3R2D7pWgWkr6JXBkhjC1RwKUPasIV/bpAYbT oYYAjVyrp8EuXKkXzw6Om960Qc3r8lvT7jB0l3q1DREpUg7OHJIdVHe+QiTokCOwXuIO vH6oNtfK9HXB5h8tsh0/qodnFFCsirHu+0191GosCDFCcYZGsvdNpy/6LDfnoNkKT3Jw P/klqg4GEVze3G6zkF9uN5FuMtGhN/T1ST1GMpDohP3WKyVVpwMiBqR/Z7UklVeGmPKj AMh1pXN7EObtiGMvvtP2N/wbEH2V2aBIyGGkQl4DhI0xuzN2aGqs3s86ms7FfofD9KFh e1SQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=kdtkbdHD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e25si6368303vsl.332.2021.05.03.23.15.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:15:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=kdtkbdHD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoKk-0005cw-Ka for patch@linaro.org; Tue, 04 May 2021 02:15:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo06-0005JS-DV; Tue, 04 May 2021 01:53:43 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:34629) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo02-0004mm-M7; Tue, 04 May 2021 01:53:40 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK6LJLz9sXN; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=6Z6jyo3bzAclzYab342gMCr7M/a/GiGYHd806MpvsQw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kdtkbdHDsnqI4XUrnOnqBteRDvuttHL3b14s3mSU/7UfgOPrGjoCs2YI7HzkodiS9 8N7Io1PFS+i5uZQ60d8HaQ6Pu2+0aDNkm7vpRncRQN/pn4e312bhR1UhRgjZ6viYT/ fEKzeAboAzneRalwUmgzHNEYm0W1cvt7/RjUDqiY= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 18/46] linux-user/ppc: Fix msr updates for signal handling Date: Tue, 4 May 2021 15:52:44 +1000 Message-Id: <20210504055312.306823-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson In save_user_regs, there are two bugs where we OR in a bit number instead of the bit, clobbering the low bits of MSR. However: The MSR_VR and MSR_SPE bits control the availability of the insns. If the bits were not already set in MSR, then any attempt to access those registers would result in SIGILL. For linux-user, we always initialize MSR to the capabilities of the cpu. We *could* add checks vs MSR where we currently check insn_flags and insn_flags2, but we know they match. Also, there's a stray cut-and-paste comment in restore. Then, do not force little-endian binaries into big-endian mode. Finally, use ppc_store_msr for the update to affect hflags. Which is the reason none of these bugs were previously noticed. Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-10-richard.henderson@linaro.org> Signed-off-by: David Gibson --- linux-user/ppc/cpu_loop.c | 5 +++-- linux-user/ppc/signal.c | 23 +++++++++++------------ 2 files changed, 14 insertions(+), 14 deletions(-) -- 2.31.1 diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index df71e15a25..4a0f6c8dc2 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -492,11 +492,12 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) #if defined(TARGET_PPC64) int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF; #if defined(TARGET_ABI32) - env->msr &= ~((target_ulong)1 << flag); + ppc_store_msr(env, env->msr & ~((target_ulong)1 << flag)); #else - env->msr |= (target_ulong)1 << flag; + ppc_store_msr(env, env->msr | (target_ulong)1 << flag); #endif #endif + env->nip = regs->nip; for(i = 0; i < 32; i++) { env->gpr[i] = regs->gpr[i]; diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index b78613f7c8..bad38f8ed9 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -261,9 +261,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VR in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_VR; #if defined(TARGET_PPC64) vrsave = (uint32_t *)&frame->mc_vregs.altivec[33]; /* 64-bit needs to put a pointer to the vectors in the frame */ @@ -300,9 +297,6 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); } - /* Set MSR_SPE in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ - msr |= MSR_SPE; __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); } #endif @@ -354,8 +348,10 @@ static void restore_user_regs(CPUPPCState *env, __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); /* If doing signal return, restore the previous little-endian mode. */ - if (sig) - env->msr = (env->msr & ~(1ull << MSR_LE)) | (msr & (1ull << MSR_LE)); + if (sig) { + ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) | + (msr & (1ull << MSR_LE)))); + } /* Restore Altivec registers if necessary. */ if (env->insns_flags & PPC_ALTIVEC) { @@ -376,8 +372,6 @@ static void restore_user_regs(CPUPPCState *env, __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]); __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]); } - /* Set MSR_VEC in the saved MSR value to indicate that - frame->mc_vregs contains valid data. */ #if defined(TARGET_PPC64) vrsave = (uint32_t *)&v_regs[33]; #else @@ -468,7 +462,7 @@ void setup_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); unlock_user_struct(frame, frame_addr, 1); return; @@ -563,8 +557,13 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, env->nip = (target_ulong) ka->_sa_handler; #endif +#ifdef TARGET_WORDS_BIGENDIAN /* Signal handlers are entered in big-endian mode. */ - env->msr &= ~(1ull << MSR_LE); + ppc_store_msr(env, env->msr & ~(1ull << MSR_LE)); +#else + /* Signal handlers are entered in little-endian mode. */ + ppc_store_msr(env, env->msr | (1ull << MSR_LE)); +#endif unlock_user_struct(rt_sf, rt_sf_addr, 1); return; From patchwork Tue May 4 05:52:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430818 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3497959jao; Mon, 3 May 2021 23:12:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzVMS9m8juSZkAx/5pFwM2/h3Ikk1FlOh47nLPgVDD9oCF8By3IUJMsWU7Pq9M5ALN2OOZS X-Received: by 2002:a05:622a:1309:: with SMTP id v9mr20726514qtk.133.1620108761132; Mon, 03 May 2021 23:12:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620108761; cv=none; d=google.com; s=arc-20160816; b=nxTLXgyNYnf8yHft5vT3iRktDSVxug4VWqpUy+x9gaQ1XX+ScO9P/D+vH1mHzIH9Bw HyYzV21L+8Hp0m+Og2ebdH4VoM5K1ufjJWMvEojiy5TLITHiQ9063tIASy/CUx5H5pTZ EUD+QfFrUdX0u3RJbgxffi8jzGzhXsv2ZOCC9EYfbOl4Bwp+bU/hVPSuvf0VwvgDlWeM jhVdGcc9PGKPqQGLej6MMnbcCwOsgQVqeUSBhMBI6AYrq9nWeACIto3DyXHFUmvVZ7qU wjycfpav7OBMWirTzF1Eex0cPgLHaNjXF0a2fa81rN1KBs9VWWnnd/euBP2tAcl5lzio U84w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=woEJAS8b5msPl7RpTC3T/RC+M3NXFRr1ABPp/0eVKNQ=; b=BLuRqyA8GA3UGArgTCvQFwKhNOThtfjccXgWu6SjhwAQgBFUhMHsB8cWcL2jRBzRZL fBmvjc0PnguLXSqajdByMTzODTQHL7vPceorT9daDTbZ+q5MWuY4uI+WpL8BhuS8q88y xusi7mTa7fr3hTFnoMqfrnq8lMtHHqYFjCuIch6IVCSuNzHcKge04NBJjPaUYNNoQ6gZ eSykvM2AdlX2uWnCMULY5XciQAO90PcGFf3J0JFLHLYYrv39copuv1VMAeqtyFXsNEP/ bNpew059dC/q0rp8OunUFDC21nLSVkP5tYRnEDuAuokQJQ8de6tHpu1/3wH7ibu8tMve i8rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=GWWgbX9N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c6si1120265qtd.256.2021.05.03.23.12.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:12:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=GWWgbX9N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:51938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoIS-0003jb-G8 for patch@linaro.org; Tue, 04 May 2021 02:12:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo08-0005KM-HP; Tue, 04 May 2021 01:53:44 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:39689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo04-0004o5-K3; Tue, 04 May 2021 01:53:43 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CK6f1gz9sXS; Tue, 4 May 2021 15:53:17 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107597; bh=sCuff11fEliXRuJdwQKxzTDCAkDLJs5IHy1UGt0Z4sk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GWWgbX9NvZERlsoa7sLo19BqB0OCR7TupQZfWJJVJZ8V662dD4eV8bCrG/v2GViXG ZUytIdDmkKbADSwhNDjfRaDzHMNivUYYBhdAcA4irFo6lUUZt5lXoLSbZ+SoQoW+op RpIkhdpqrP4vmAE7MDMvroObBAvb1eIkCNcqK1UQ= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 19/46] target/ppc: Validate hflags with CONFIG_DEBUG_TCG Date: Tue, 4 May 2021 15:52:45 +1000 Message-Id: <20210504055312.306823-20-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Verify that hflags was updated correctly whenever we change cpu state that is used by hflags. Signed-off-by: Richard Henderson Message-Id: <20210323184340.619757-11-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 5 +++++ target/ppc/helper_regs.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3d021f61f3..69fc9a2831 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2425,6 +2425,10 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags); +#else static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { @@ -2432,6 +2436,7 @@ static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, *cs_base = 0; *flags = env->hflags; } +#endif void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 5411a67e9a..3723872aa6 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -43,7 +43,7 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] = tmp; } -void hreg_compute_hflags(CPUPPCState *env) +static uint32_t hreg_compute_hflags_value(CPUPPCState *env) { target_ulong msr = env->msr; uint32_t ppc_flags = env->flags; @@ -155,8 +155,33 @@ void hreg_compute_hflags(CPUPPCState *env) hflags |= dmmu_idx << HFLAGS_DMMU_IDX; #endif - env->hflags = hflags | (msr & msr_mask); + return hflags | (msr & msr_mask); +} + +void hreg_compute_hflags(CPUPPCState *env) +{ + env->hflags = hreg_compute_hflags_value(env); +} + +#ifdef CONFIG_DEBUG_TCG +void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + uint32_t hflags_current = env->hflags; + uint32_t hflags_rebuilt; + + *pc = env->nip; + *cs_base = 0; + *flags = hflags_current; + + hflags_rebuilt = hreg_compute_hflags_value(env); + if (unlikely(hflags_current != hflags_rebuilt)) { + cpu_abort(env_cpu(env), + "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", + hflags_current, hflags_rebuilt); + } } +#endif void cpu_interrupt_exittb(CPUState *cs) { From patchwork Tue May 4 05:53:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430827 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3518993jao; Mon, 3 May 2021 23:52:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyF0bhlfZ6RaQz9TmA3g12nCIkSAn0qGVGjv2CUuJHTFx40Yn5T9k2BxnmbM/VtLnG+RM18 X-Received: by 2002:a5d:8b01:: with SMTP id k1mr17028948ion.127.1620111170075; Mon, 03 May 2021 23:52:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620111170; cv=none; d=google.com; s=arc-20160816; b=MJBrI2PqrnMaNJcuC9f96Sj44pKkarU7BwTwQ4EqkZsyYGBvQMVRzQNtVSv/8cLcV0 SLtym0t39iNnTWog8yJSy7mEVXQ25zzHS6sTVIiZ8aTjl4akF+yy4c/vn9IXZ4xWu4KF CzkfsyuV7GlYeyCpP7y2mxJAxjJUSsi5p4Y1nJ3Xa9L2hAm4ndVomLCN86nvWAzZ08Wr TDLY3YIYHD3kLZ2fKXx1JQGPPaxAKuYK9MAM3ro+yIx/RaO7GVYFIsLottxR1d/edw8v Bio0cdd/KMLuFV8/Gb/H/b2XqJBsIKU78C/Unu5iqPSQ2wKEwGWApDAWmbwP7dgbQZki g+mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DJ/4GCErlUoCMQt2h9EmsDUT2X3tpzSmSLV71jIkXP4=; b=o4EP1MlcHLee97MLOPVP3ZjFnwI+T/yLBLuT+BLZPYgvBwMNeQiG0S14NpPDVmeNCx 30BrAbJ1qlnIomv2oVjPZlfzGVxuwTCPmG/xuAikgXHaLdZ8jGrrA0KwGCnZQOjziqVM huXiPUvhro/w4EnCdINMQLFvNP7dT9LmTchgQ8gWsda0uyrucTdCK563wH9Gbme1Ngqz L7mFrYNGzDZhrXMBHkmH5eJmp6K/EQnlX97G9/q4G6H6V7h+AO638Qfe4caOBZjTTUnZ +15OwBp7LsraQCl3RECABlZxQbqFVafRqSqfJjQLIf20vlCBhpUbG37iiWThi8otXLOb Ms0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=GBwhDkUt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w12si14847333jap.71.2021.05.03.23.52.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:52:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=GBwhDkUt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:56226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldovJ-00010r-GU for patch@linaro.org; Tue, 04 May 2021 02:52:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo16-0006oK-Ft; Tue, 04 May 2021 01:54:45 -0400 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:44789 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo13-0005EE-Iv; Tue, 04 May 2021 01:54:44 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CP65Xnz9t14; Tue, 4 May 2021 15:53:21 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107601; bh=lUbT/DZcYFCJPzC2E2B5W4lA3dAQag7zWEMrPssETfQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GBwhDkUtUd3A4KGb6Ht2V2sqNxs0GDZ6F4j2grs1H1SIRme67Qyiapk25baerH1fM XDgnwvmsYMx/7x7C1OEljb4nn1G0zmGGl+gCzbQpTBborZ+f5celHsfAFRANZcBoF2 Z+ZhECR/YBDius31r/PDkA6LhOJMhiswHHWP7znk= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 41/46] target/ppc: Clean up _spr_register et al Date: Tue, 4 May 2021 15:53:07 +1000 Message-Id: <20210504055312.306823-42-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Introduce 3 helper macros to elide arguments that we cannot supply. This reduces the repetition required to get the job done. Signed-off-by: Richard Henderson Message-Id: <20210501022923.1179736-2-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/translate_init.c.inc | 158 +++++++++++++++----------------- 1 file changed, 76 insertions(+), 82 deletions(-) -- 2.31.1 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index f92656b2f2..5cee94f16d 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -720,103 +720,97 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val) helper_mtvscr(env, val); } -#ifdef CONFIG_USER_ONLY -#define spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, initial_value) -#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, initial_value) -#else -#if !defined(CONFIG_KVM) -#define spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, oea_read, oea_write, initial_value) -#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, initial_value) +/** + * _spr_register + * + * Register an SPR with all the callbacks required for tcg, + * and the ID number for KVM. + * + * The reason for the conditional compilation is that the tcg functions + * may be compiled out, and the system kvm header may not be available + * for supplying the ID numbers. This is ugly, but the best we can do. + */ + +#ifdef CONFIG_TCG +# define USR_ARG(X) X, +# ifdef CONFIG_USER_ONLY +# define SYS_ARG(X) +# else +# define SYS_ARG(X) X, +# endif #else -#define spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, oea_read, oea_write, \ - one_reg_id, initial_value) -#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) \ - _spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - one_reg_id, initial_value) +# define USR_ARG(X) +# define SYS_ARG(X) #endif +#ifdef CONFIG_KVM +# define KVM_ARG(X) X, +#else +# define KVM_ARG(X) #endif -#define spr_register(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, initial_value) \ - spr_register_kvm(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, 0, initial_value) - -#define spr_register_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - initial_value) \ - spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ - oea_read, oea_write, hea_read, hea_write, \ - 0, initial_value) - -static inline void _spr_register(CPUPPCState *env, int num, - const char *name, - void (*uea_read)(DisasContext *ctx, - int gprn, int sprn), - void (*uea_write)(DisasContext *ctx, - int sprn, int gprn), -#if !defined(CONFIG_USER_ONLY) +typedef void spr_callback(DisasContext *, int, int); - void (*oea_read)(DisasContext *ctx, - int gprn, int sprn), - void (*oea_write)(DisasContext *ctx, - int sprn, int gprn), - void (*hea_read)(DisasContext *opaque, - int gprn, int sprn), - void (*hea_write)(DisasContext *opaque, - int sprn, int gprn), -#endif -#if defined(CONFIG_KVM) - uint64_t one_reg_id, -#endif - target_ulong initial_value) +static void _spr_register(CPUPPCState *env, int num, const char *name, + USR_ARG(spr_callback *uea_read) + USR_ARG(spr_callback *uea_write) + SYS_ARG(spr_callback *oea_read) + SYS_ARG(spr_callback *oea_write) + SYS_ARG(spr_callback *hea_read) + SYS_ARG(spr_callback *hea_write) + KVM_ARG(uint64_t one_reg_id) + target_ulong initial_value) { - ppc_spr_t *spr; + ppc_spr_t *spr = &env->spr_cb[num]; + + /* No SPR should be registered twice. */ + assert(spr->name == NULL); + assert(name != NULL); - spr = &env->spr_cb[num]; - if (spr->name != NULL || env->spr[num] != 0x00000000 || -#if !defined(CONFIG_USER_ONLY) - spr->oea_read != NULL || spr->oea_write != NULL || -#endif - spr->uea_read != NULL || spr->uea_write != NULL) { - printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); - exit(1); - } -#if defined(PPC_DEBUG_SPR) - printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, - name, initial_value); -#endif spr->name = name; + spr->default_value = initial_value; + env->spr[num] = initial_value; + +#ifdef CONFIG_TCG spr->uea_read = uea_read; spr->uea_write = uea_write; -#if !defined(CONFIG_USER_ONLY) +# ifndef CONFIG_USER_ONLY spr->oea_read = oea_read; spr->oea_write = oea_write; spr->hea_read = hea_read; spr->hea_write = hea_write; +# endif #endif -#if defined(CONFIG_KVM) - spr->one_reg_id = one_reg_id, -#endif - env->spr[num] = spr->default_value = initial_value; -} +#ifdef CONFIG_KVM + spr->one_reg_id = one_reg_id; +#endif +} + +/* spr_register_kvm_hv passes all required arguments. */ +#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, \ + one_reg_id, initial_value) \ + _spr_register(env, num, name, \ + USR_ARG(uea_read) USR_ARG(uea_write) \ + SYS_ARG(oea_read) SYS_ARG(oea_write) \ + SYS_ARG(hea_read) SYS_ARG(hea_write) \ + KVM_ARG(one_reg_id) initial_value) + +/* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ +#define spr_register_kvm(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, one_reg_id, ival) \ + spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ + oea_write, oea_read, oea_write, one_reg_id, ival) + +/* spr_register_hv and spr_register are similar, except there is no kvm id. */ +#define spr_register_hv(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, hea_read, hea_write, ival) \ + spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ + oea_write, hea_read, hea_write, 0, ival) + +#define spr_register(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, ival) \ + spr_register_kvm(env, num, name, uea_read, uea_write, \ + oea_read, oea_write, 0, ival) /* Generic PowerPC SPRs */ static void gen_spr_generic(CPUPPCState *env) From patchwork Tue May 4 05:53:08 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id y13si1913642qkl.179.2021.05.03.23.35.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:35:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b="Q//2GDmS"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:35908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoez-00051w-EA for patch@linaro.org; Tue, 04 May 2021 02:35:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo1F-0006w6-6Z; Tue, 04 May 2021 01:54:53 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:35131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo1D-0005JI-HC; Tue, 04 May 2021 01:54:52 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CQ0Stsz9t1C; Tue, 4 May 2021 15:53:21 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107602; bh=Waw0NZnem3odKQHfMNelimpPmlKaZSKhjMfc8vEz4Uc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q//2GDmSrjB/39ZwcWkqiI5k9oBJMqS17vx9aEhVUdYHpgkL2uYsA8yCTv+Nu2MhU lEEVqIkaCrepPK/6KYOKrLnLZ7Cdj0SeQoi+11A+VUfeKwJ5bLWTXoAkUIeFzMgLy4 KU6YLyltoRLDuZjbqkiPX+w3LJHewMFoKEz2pZ/0= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 42/46] target/ppc: Reduce the size of ppc_spr_t Date: Tue, 4 May 2021 15:53:08 +1000 Message-Id: <20210504055312.306823-43-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We elide values when registering sprs, we might as well save space in the array as well. Signed-off-by: Richard Henderson Message-Id: <20210501022923.1179736-3-richard.henderson@linaro.org> Signed-off-by: David Gibson --- target/ppc/cpu.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 2.31.1 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8a076fab48..733a2168c4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -192,17 +192,21 @@ typedef struct ppc_hash_pte64 ppc_hash_pte64_t; /* SPR access micro-ops generations callbacks */ struct ppc_spr_t { + const char *name; + target_ulong default_value; +#ifndef CONFIG_USER_ONLY + unsigned int gdb_id; +#endif +#ifdef CONFIG_TCG void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num); void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num); -#if !defined(CONFIG_USER_ONLY) +# ifndef CONFIG_USER_ONLY void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num); void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); - unsigned int gdb_id; +# endif #endif - const char *name; - target_ulong default_value; #ifdef CONFIG_KVM /* * We (ab)use the fact that all the SPRs will have ids for the From patchwork Tue May 4 05:53:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430826 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3518253jao; Mon, 3 May 2021 23:51:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzxH3guSp5e8+cdXUTdGxH4bw64NsEsuXY2xrg31AfoB4Rh/iRq9/SngAKPXxwIMERW9Y0W X-Received: by 2002:a6b:8fcc:: with SMTP id r195mr3102066iod.17.1620111083126; Mon, 03 May 2021 23:51:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620111083; cv=none; d=google.com; s=arc-20160816; b=gzY3+UHkIO7r+q5+IHjVNGr3csiVWZ9oZy7ULUq3B8rqLbiJlFKaLBqoA3uLw09VGx Cs97Hq49mnhfcEdmQFLCOHOBLT66D1HBZBoli0C8zC2goUNf4VzYHdixPpGee/ONptvN PNS4K6NgBC9pB1AA98jsJS6R6y96bnV23o9WvUvUTbqYcE+e3spzFQ0rWksxsOpwj6Ei W0aj+34vX/PdHohNS060Td43aCjm0A83YQvK9jTNuXyoTD2t3isnB7EN4NWIpGy1FPbC Ap62TfKYrejS0AB5aVfdEUyniblkBHF+3Unm3Cf3o0slLoUgfi+829JnWHfi8EmsUgFn QAWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WR9QS9ek4boumyNbYz6h6FEeOD+zYbo8SKEPKtN9MqA=; b=vCwJvxKmjjJhi90yckAQQhRasFfuW+Ey7OUJmYoZnyc/ogXT6nc01ulrcZRFuTV7id 3rsGVCocfv4H6t2FvFU8LhDKJEyCJppaHGJ3JvuCGMZ7BtC/JqCJ7E+AemJE0sbaxIpk wkAkHHrZ6Eb3lkH/R/CfcI/WTkvexpdLDOfx5muPscV1fMxDqurY6XRTAp+FSZNIRp/M 3JqjKHLKCXrB0YS1XHz0NEQnexXWfUIsZH1fvYa9ujHwXkdWIiROoQCBxyVdSf1xJY8V A3AZgy28wjVTjNfAfhvaTmtlACp0yyRYVUSsujjPEFN9969de8mwaTG6BnOAml8TOwWu M9qA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=KuXWazCA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n1si14184515ili.3.2021.05.03.23.51.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:51:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=KuXWazCA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:49926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldotu-0006TL-JM for patch@linaro.org; Tue, 04 May 2021 02:51:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo11-0006jK-E9; Tue, 04 May 2021 01:54:39 -0400 Received: from ozlabs.org ([203.11.71.1]:56557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo0z-0005MS-Ae; Tue, 04 May 2021 01:54:38 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CQ3FMvz9sVb; Tue, 4 May 2021 15:53:22 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107602; bh=qTTd1acHEOLOLfCLmBJ/7G0wh8ppvnqr7BiunJk5cBw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KuXWazCA+HIwtktR57Act7U3z5Fm5dslu/f4x6xt+pufQ5u0FeeEbIBHfhJXAbgUo +94WUT+02G8ZVUhN+0fegWTYT+SgRNUYC2uiCnfgu0AKPVP6OlvhCeus3EYqOUMWf+ 0PISQbH4P2/+eyIkMY6kjRJHTq6D5vC/NyRtx/HM= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 44/46] hw/intc/spapr_xive: Use device_cold_reset() instead of device_legacy_reset() Date: Tue, 4 May 2021 15:53:10 +1000 Message-Id: <20210504055312.306823-45-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The h_int_reset() function resets the XIVE interrupt controller via device_legacy_reset(). We know that the interrupt controller does not have a qbus of its own, so the new device_cold_reset() function (which resets both the device and its child buses) is equivalent here to device_legacy_reset() and we can just switch to the new API. Signed-off-by: Peter Maydell Message-Id: <20210503151849.8766-2-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/intc/spapr_xive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.31.1 diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 801bc19341..89cfa018f5 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -1798,7 +1798,7 @@ static target_ulong h_int_reset(PowerPCCPU *cpu, return H_PARAMETER; } - device_legacy_reset(DEVICE(xive)); + device_cold_reset(DEVICE(xive)); if (spapr_xive_in_kernel(xive)) { Error *local_err = NULL; From patchwork Tue May 4 05:53:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430824 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3516371jao; Mon, 3 May 2021 23:47:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxn7EhlXH2tFCE5bEjBphTmWbuGzKl92/JAqVE80Lz6GlWn8pTMY+DFhSUZSIvz8qcjVAgH X-Received: by 2002:a05:6e02:786:: with SMTP id q6mr13619361ils.84.1620110858500; Mon, 03 May 2021 23:47:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620110858; cv=none; d=google.com; s=arc-20160816; b=Pmssd8h39ZdJoJmqDKaUTHiTm3AXdR59v5zlcv+WKu1o59/hN2um9yXdQSyO1O2qOa UDLhJZTJXUisgyLxP2UTMYcxkQ4S0PEH6fpBWbKnVWUc9GM+2Oj/Ftew/hjhFuit0qZ7 8TLcPN4E8ggHtuSs3RNEmoFwOaEtQp4q8xC9Ok42G00O0MHe8eZAV7Ng090X5qMFXBZr BLJbiSsX7uENvoOLdpxsaf3oT66suorHdxdJSdsuio4bq9UJWJGml1CXFaYzsUnENEJ4 gCxpPZkQ7TakWv5Wt96r17m5FYiFxBm53qg0kx20AhvMd8WHfedODmqf+p3UAJBoaA9y uGEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0ALnroDjD53TLuga2+CRQ2Z3M7UfYHnG9tTmgW9xB58=; b=qalERLFg/G3NfdbrGRU/FlJZ22Wd2YZz4OahzizloYAvH+Yq6j7uT0jbp5qCrlO2lk Ob2arNZXXJrihACAuXOEdrR+7gPlrQvFqP9q246DiWH12ZsA6hEIz3K+cXTQXx+Jqqoj 0MTaz3ucm9+LHhxapQ8AnTp1Wf/0+aqCMzTMqLh6c/f3lSSzW6uE8VUcvrHT6DoEJMCi JPJurmKCzeqkIAOvztisowj8tkRz8s0B8sIXB8k/O+mWtpVVI2fxxbkwcF9rdRWhhd8I AARefBgw1L7wE9dN2UQn/f+IVWnsBUS3RP43ae0pWaiZeLvvQhxf9J/yG0lAdyIG+lUW /T8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=VbVsBSo4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g11si2219050ion.60.2021.05.03.23.47.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:47:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=VbVsBSo4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:43272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldoqH-0003ax-UG for patch@linaro.org; Tue, 04 May 2021 02:47:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo1N-00076i-Hx; Tue, 04 May 2021 01:55:01 -0400 Received: from ozlabs.org ([203.11.71.1]:39687) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo1L-0005OH-Hw; Tue, 04 May 2021 01:55:01 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CQ5sbFz9t1r; Tue, 4 May 2021 15:53:22 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107602; bh=fCKZKsqp44tDGeu7z15Q40LoupLPDQzipln+K2O5gIY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VbVsBSo45rI2WhDWrQ/aMmiiPXZUrcJovC6mcbgBGR2btWBNhm/bB4TUYvfF/kXEQ +2jKTxVHFn/+nKzojZWaJ9yzgju8uXplVpUpxTrSq7TS0AlWLiGPhTpb4TiA8fExVv MkIzinG08UGtuQSHO6CaUdZYkjLw5/NgBJUc4NX4= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 45/46] hw/ppc/spapr_vio: Reset TCE table object with device_cold_reset() Date: Tue, 4 May 2021 15:53:11 +1000 Message-Id: <20210504055312.306823-46-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The spapr_vio_quiesce_one() function resets the TCE table object (TYPE_SPAPR_TCE_TABLE) via device_legacy_reset(). We know that objects of that type do not have a qbus of their own, so the new device_cold_reset() function (which resets both the device and its child buses) is equivalent here to device_legacy_reset() and we can just switch to the new API. Signed-off-by: Peter Maydell Message-Id: <20210503151849.8766-3-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/ppc/spapr_vio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.31.1 diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index ef06e0362c..b59452bcd6 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -310,7 +310,7 @@ int spapr_vio_send_crq(SpaprVioDevice *dev, uint8_t *crq) static void spapr_vio_quiesce_one(SpaprVioDevice *dev) { if (dev->tcet) { - device_legacy_reset(DEVICE(dev->tcet)); + device_cold_reset(DEVICE(dev->tcet)); } free_crq(dev); } From patchwork Tue May 4 05:53:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 430825 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3517995jao; Mon, 3 May 2021 23:50:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2xHR00vPYCY26HrVBQprVhi0A10wY0tnzz9IjGkEoUw4LNU3Ron9iMu/8J3asJVHp+xIG X-Received: by 2002:a5d:9f01:: with SMTP id q1mr18170515iot.7.1620111053306; Mon, 03 May 2021 23:50:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620111053; cv=none; d=google.com; s=arc-20160816; b=XGjtqi00TqfGE+T9m3NTXGItFJKzHGwaC7omXVXoovkfK4CUBioabcGlh9eW+I5Iyy QJyprIW4XO+xIy3bcyCYG02MteTA45bZOTvg/hkMA7EC3CnJIOPA5/2oum0QYfX3lqcH KHgo0HNA4W0U50rNVwQoGhtSUKxGUlVfWE6NVS9xL4X5W6rgldLkm89GfleOcAuR61VU HOIiQjCVvoCKsL26cAeXis08wXURTGq0XBKl8iYtPvZAPVlqu9jxdYbEIuX6176kSMr1 Q8C39pGII+pXvWu7V6o5BAdIaJZk1h/R0wFIooGdPrQwySsCUJpEP4tb1v/4qhHFOy2X txQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=S3lGhdJpxpv9I/0RKgdISFV15MYVYDD3RJPIsrexMcE=; b=P6qo0NeVYfU2sqfqwwCsCeUImoNN76ON3XUKGC58fx7MpYi4haH7asR3J/1CWIgSZ5 vJIHKxiK06LkuqQjz6ymUDqpbr+eOhWz4kNCup8QjRkoVTOkmp/x37uUF1IVWxoTcdZM 4sSfQxthRgBVkX+5ZD4Y0Aco1QL/DbRFEBkyTLp+615zVzknunG1HP4HYsRIZRkdZbe7 YltZSNbc07UucCmTd8l/NE4iA6LghMHr96gFLY1uCjjMA4vnIZ+TbVUOBbpGnFIXPdra N7YVfcfPWOAmysPeAWgOxKzqSKR7EffLhDS/34p28L8sILQYkABMopILqAs+HQK1rSB/ KKDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=hq6T6klW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y23si1459564iot.95.2021.05.03.23.50.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 May 2021 23:50:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=hq6T6klW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:49576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ldotQ-0006Jz-OY for patch@linaro.org; Tue, 04 May 2021 02:50:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo1N-00077A-Ld; Tue, 04 May 2021 01:55:01 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:55873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ldo1L-0005OK-OX; Tue, 04 May 2021 01:55:01 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 4FZ8CQ4zFlz9t1s; Tue, 4 May 2021 15:53:22 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1620107602; bh=y9uyQJXG5pCTAYMMEsFQPkAKFM4i1KQ0n02I0GZk4yE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hq6T6klWkS8oHc0yWEps/9mxyicptvOKUyB3lTR75OYa69RMOoQdoO5vp2tzDApCI /jeiPcICKOtZFTi9K2EjllwX9OrdKPI0uW+7plkTtDY9C7UPw7e02UI2FC1BM6ABEb xQSBrr9DAWkS3M3MATWbSUabQHmCIZ8yCxQZ3hKo= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 46/46] hw/ppc/pnv_psi: Use device_cold_reset() instead of device_legacy_reset() Date: Tue, 4 May 2021 15:53:12 +1000 Message-Id: <20210504055312.306823-47-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210504055312.306823-1-david@gibson.dropbear.id.au> References: <20210504055312.306823-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The pnv_psi.c code uses device_legacy_reset() for two purposes: * to reset itself from its qemu_register_reset() handler * to reset a XiveSource object it has Neither it nor the XiveSource have any qbuses, so the new device_cold_reset() function (which resets both the device and its child buses) is equivalent here to device_legacy_reset() and we can just switch to the new API. Signed-off-by: Peter Maydell Message-Id: <20210503151849.8766-4-peter.maydell@linaro.org> Signed-off-by: David Gibson --- hw/ppc/pnv_psi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.31.1 diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 3e868c8c8d..292b373f93 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -466,7 +466,7 @@ static void pnv_psi_reset(DeviceState *dev) static void pnv_psi_reset_handler(void *dev) { - device_legacy_reset(DEVICE(dev)); + device_cold_reset(DEVICE(dev)); } static void pnv_psi_realize(DeviceState *dev, Error **errp) @@ -710,7 +710,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, break; case PSIHB9_INTERRUPT_CONTROL: if (val & PSIHB9_IRQ_RESET) { - device_legacy_reset(DEVICE(&psi9->source)); + device_cold_reset(DEVICE(&psi9->source)); } psi->regs[reg] = val; break;