From patchwork Fri May 7 10:17:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasad Malisetty X-Patchwork-Id: 432645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DFE3C433B4 for ; Fri, 7 May 2021 10:17:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 413936143F for ; Fri, 7 May 2021 10:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235938AbhEGKSv (ORCPT ); Fri, 7 May 2021 06:18:51 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:44780 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235930AbhEGKSv (ORCPT ); Fri, 7 May 2021 06:18:51 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1620382672; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=Oud0HTulzNKsdmkcfvYSmVRENN5uGQTLxbcyfMHMM3E=; b=h/Ml9XuIy6bmvCGgHXOmCQIrwp4HN8oFZ/DuWelzvlUmey0iQatCHh8GowL3l9WlEXwjOggb zLjXcxQytqNvWDCHgMWu32rgwkvFrZmtz2mz5RnfjXGus9tXm27Rif5Q8zueEOlAv/bMJIkP Q9m41w4b9pexxrYRR5KXUH0D7rk= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 609513cc03cfff3452bc1bc9 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 07 May 2021 10:17:48 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id B87F9C43145; Fri, 7 May 2021 10:17:47 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6C13BC433D3; Fri, 7 May 2021 10:17:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6C13BC433D3 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=pmaliset@codeaurora.org From: Prasad Malisetty To: Andy Gross , Bjorn Andersson , Rob Herring , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, mgautam@codeaurora.org, swboyd@chromium.org, dianders@chromium.org, mka@chromium.org, Prasad Malisetty Subject: [PATCH 1/3] dt-bindings: pci: qcom: Document PCIe bindings for SC720 Date: Fri, 7 May 2021 15:47:26 +0530 Message-Id: <1620382648-17395-2-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1620382648-17395-1-git-send-email-pmaliset@codeaurora.org> References: <1620382648-17395-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the PCIe DT bindings for SC7280 SoC.The PCIe IP is similar to the one used on SM8250. Add the compatible for SC7280. Signed-off-by: Prasad Malisetty Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 0da458a..e5245ed 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -12,6 +12,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sc7280" for sc7280 - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 @@ -133,6 +134,22 @@ - "slave_bus" AXI Slave clock - clock-names: + Usage: required for sc7280 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock + - "pipe" PIPE clock + - "pipe_src" PIPE MUX + - "pipe_ext" PIPE output clock + - "ref" REFERENCE clock + +- clock-names: Usage: required for sdm845 Value type: Definition: Should contain the following entries From patchwork Fri May 7 10:17:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasad Malisetty X-Patchwork-Id: 432174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8723FC43460 for ; Fri, 7 May 2021 10:17:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 55F1261443 for ; Fri, 7 May 2021 10:17:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235937AbhEGKSx (ORCPT ); Fri, 7 May 2021 06:18:53 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:44780 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235939AbhEGKSw (ORCPT ); Fri, 7 May 2021 06:18:52 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1620382672; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=VFlg6Efq4EyfdEuEbALBw5T6jHeBV2CP9PQl7VKbOrw=; b=DEGyPHT3L/LgUhZVzzNgszzY9dQ8NSpWZ2NpHAy+lXngt8y7ZL1hHsstEZOiPlYwiO4B4xgA ZKsyg+DLd+9ba1bS8U7/GAsvNAFkqmOYjMfQ33eb+FyGIwtzfIFFnCds6P1n/odVl/GSXWXA qt4XmMBy7PMQG9b7bkD77FgHWOE= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-west-2.postgun.com with SMTP id 609513d0febcffa80fc21d26 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 07 May 2021 10:17:52 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C8890C4338A; Fri, 7 May 2021 10:17:51 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id A8FA4C43148; Fri, 7 May 2021 10:17:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A8FA4C43148 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=pmaliset@codeaurora.org From: Prasad Malisetty To: Andy Gross , Bjorn Andersson , Rob Herring , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, mgautam@codeaurora.org, swboyd@chromium.org, dianders@chromium.org, mka@chromium.org, Prasad Malisetty Subject: [PATCH 2/3] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes Date: Fri, 7 May 2021 15:47:27 +0530 Message-Id: <1620382648-17395-3-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1620382648-17395-1-git-send-email-pmaliset@codeaurora.org> References: <1620382648-17395-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add PCIe controller and PHY nodes for sc7280 SOC. Signed-off-by: Prasad Malisetty --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 +++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 2cc4785..a9f25fc1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -316,6 +317,118 @@ }; }; + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sc7280", "qcom,pcie-sm8250", "snps,dw-pcie"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_lane 0>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>; + + clock-names = "pipe", + "pipe_src", + "pipe_ext", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + iommus = <&apps_smmu 0x1c80 0x1>; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c0e200 { + reg = <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ + <0 0x1c0e600 0 0x170>, /* tx1 */ + <0 0x1c0e800 0 0x200>, /* rx1 */ + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + #clock-cells = <1>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, @@ -871,6 +984,31 @@ pins = "gpio46", "gpio47"; function = "qup13"; }; + + pcie1_default_state: pcie1-default { + clkreq { + pins = "gpio79"; + function = "pcie1_clkreqn"; + bias-pull-up; + }; + + reset-n { + pins = "gpio2"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-disable; + }; + + wake-n { + pins = "gpio3"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { From patchwork Fri May 7 10:17:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prasad Malisetty X-Patchwork-Id: 432173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 733D7C43460 for ; Fri, 7 May 2021 10:18:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 471AF61468 for ; Fri, 7 May 2021 10:18:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236032AbhEGKTC (ORCPT ); Fri, 7 May 2021 06:19:02 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:35736 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235988AbhEGKS5 (ORCPT ); Fri, 7 May 2021 06:18:57 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1620382677; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=5jWPR1PEFpz2yfMbIlWUNf3ozREmqIJcTy1sDzOJYnQ=; b=CIqhfERE6l2d+YCn049wwTbgeqtqMAg7TKXQMfgO8tH2moZdHN7s1uvHW1mq1qo2cWC28j0t adGkEZik1Eu1cFQyzTtZdwp77Fa8WUSKt4VWnBtYGFoLjcVoDEKpuV7L1Y/Oe2IbiL/KRi/5 I/7mVfDFIqsLLvMrPSLV2DQrNt4= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-east-1.postgun.com with SMTP id 609513d48166b7eff75696d3 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 07 May 2021 10:17:56 GMT Sender: pmaliset=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 32F28C43143; Fri, 7 May 2021 10:17:56 +0000 (UTC) Received: from pmaliset-linux.qualcomm.com (unknown [202.46.22.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pmaliset) by smtp.codeaurora.org (Postfix) with ESMTPSA id E9443C43143; Fri, 7 May 2021 10:17:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E9443C43143 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=pmaliset@codeaurora.org From: Prasad Malisetty To: Andy Gross , Bjorn Andersson , Rob Herring , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, mgautam@codeaurora.org, swboyd@chromium.org, dianders@chromium.org, mka@chromium.org, Prasad Malisetty Subject: [PATCH 3/3] arm64: dts: qcom: sc7280: Add PCIe nodes for IDP board Date: Fri, 7 May 2021 15:47:28 +0530 Message-Id: <1620382648-17395-4-git-send-email-pmaliset@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1620382648-17395-1-git-send-email-pmaliset@codeaurora.org> References: <1620382648-17395-1-git-send-email-pmaliset@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add PCIe nodes for sc7280 IDP board. Signed-off-by: Prasad Malisetty --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 54d2cb3..9105a74 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -234,6 +234,19 @@ }; }; +&pcie1 { + status = "okay"; + + vdda-supply = <&vreg_l10c_0p8>; +}; + +&pcie1_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l10c_0p8>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; };