From patchwork Sat May 8 01:46:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432516 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp840412jao; Fri, 7 May 2021 18:49:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw1iWUrW3Lyqw3QrZgE1TVKw84jruOeq6lPynUIOiukxkuJeS0GAaF0k6A6PH8w3T6PHZOH X-Received: by 2002:a05:6602:8d0:: with SMTP id h16mr10059892ioz.145.1620438562646; Fri, 07 May 2021 18:49:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438562; cv=none; d=google.com; s=arc-20160816; b=ZYUI4DE19/IYGayqRQ9zaB7Ix+Ml7GCsPUdBDPHQ9Phys6NyH25SCKLrwo++4AoCun WlTnbRLIF7K/CpV8vXK0nlYkMr5Cla7B2x9oGKaFigSS4uwxDWH20d1dj2OIinNuW8y0 TI+UPvBMM83rkePLTjx1hKGnjnzwDHOKjCk6UJDpBep2NjqGa/J4jOVC0USmR3UGyj8I wnWThMB1AK+D2X+LSQjewsZenW2uQsTkfQTNr7qHT0LdiGFGnUxlC9R8S31APgdxURXa f7t1BRIPisci6cKiuTUcmCL5UqF5XpIA6VsGYh3DWutJeGnR0yKJ/pA5GDtpr80jFd9n 7Gkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kll+dPeHhZ1ZNnNxSh3IWKjU47wCoWRq1+9XapRC/iw=; b=S1/XvRnV+oqaSW4waC6NptzbllK3AIxn3gMQfJ6PZSwFZishUuRIODd4nGBvANGRE5 OxSw+lQkIBx+hxp/n/BBP8mrWhAjzVo3P7V5x9pPqV9xl1EF+bP04BChmtUdnRcXWJsk h8Zzd+CckuVOGW9hwQ8KdP0/i2v4vJIqI0sFF00PummkKBqfBzqdvvPYaXtv2BgWQCV7 03A82roNPH4BSb7R4YT2iyPMSyiW7mb2zer/h0y3YTpOKzApua9RfSht6inmlPN8ipzv u+UDxnkuh5zesfPIa6os+O521Zs3Fcq6oAqRQNrrFI+J9Mhl0f8E+ymaIwf0y8scCqmn SQXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rqZvmS7Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a8si9258707ilj.99.2021.05.07.18.49.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 18:49:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rqZvmS7Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfC5q-0003vZ-3K for patch@linaro.org; Fri, 07 May 2021 21:49:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC4d-0003ux-R1 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:07 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:34419) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4c-0003Ud-6O for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:07 -0400 Received: by mail-pl1-x62b.google.com with SMTP id h7so6156348plt.1 for ; Fri, 07 May 2021 18:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kll+dPeHhZ1ZNnNxSh3IWKjU47wCoWRq1+9XapRC/iw=; b=rqZvmS7YVE3xScwFbcjkv3pcDwAe2i+MSe3ozkVfLmG9xp81Oyg8zH4qDKqWF7E5SV FN0AEwSH6PgoYIk33tD4ukSZ06JUa+U1wwy+brWDSepKcOGPhsuBE5olrcyqWGv27puU LuM6re/SO7cA8p4ydAPayUbARSISXwlf4LE16EXPtkFSUh5ljKT913f9mChWjS1M+9rj PRyGbUPP7UO5Rl7rgnzfufoUvRn0waPwCaAUp7ykr+8zB+ofKpE9p61kJBgL5OoroLi4 OyXrnCEqbXEZJ1kLm6OjEcrgiiuG9WZ+pMp39hKxSA1bZImEfCqkjcv5KgpXxjgbnmU1 ijWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kll+dPeHhZ1ZNnNxSh3IWKjU47wCoWRq1+9XapRC/iw=; b=FsalIuW6ZiaElYby/W2/vEqhNF+U1L5Pl3MZYm7LxoZ65J6vaGjnc01EXb9KzQqTlz T3QWF5ddHpzBoJL73CU9egw2O1Y05ryX4vdq5CknZ1IlrMcrGpNktVeGkcN4U8cVQmkg xHuUz3kCEZsy4nn1ABYujibT/ch3lUWFDuqq8X9wQnIWo1p9+kY6esSkdhEu+SxugKNF SC6vrhRweLhHfSkP+uXovINOBI4KKBT5mdOeOZNzV/0cnG+UIiIGtjOszYngj9ErRwcn Hwl4p/VN55pOFkkKkQ7j5whWN+7SwpV9JAe1WucoD6GovK2XLr7i1VW57JEaSRZmy4Ss Bk5g== X-Gm-Message-State: AOAM531k+C8KHrRfXMGTXCaGtzjpl4z9rOQoC9sgERrmz1XCzShUHzvu yKnQuGtByv+WdmyMfhKWSXUZ1KDpqzLFaw== X-Received: by 2002:a17:90b:915:: with SMTP id bo21mr13130414pjb.27.1620438484793; Fri, 07 May 2021 18:48:04 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/72] qemu/host-utils: Use __builtin_bitreverseN Date: Fri, 7 May 2021 18:46:51 -0700 Message-Id: <20210508014802.892561-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Clang has added some builtins for these operations; use them if available. Signed-off-by: Richard Henderson --- include/qemu/host-utils.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.25.1 Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index cdca2991d8..f1e52851e0 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -272,6 +272,9 @@ static inline int ctpop64(uint64_t val) */ static inline uint8_t revbit8(uint8_t x) { +#if __has_builtin(__builtin_bitreverse8) + return __builtin_bitreverse8(x); +#else /* Assign the correct nibble position. */ x = ((x & 0xf0) >> 4) | ((x & 0x0f) << 4); @@ -281,6 +284,7 @@ static inline uint8_t revbit8(uint8_t x) | ((x & 0x22) << 1) | ((x & 0x11) << 3); return x; +#endif } /** @@ -289,6 +293,9 @@ static inline uint8_t revbit8(uint8_t x) */ static inline uint16_t revbit16(uint16_t x) { +#if __has_builtin(__builtin_bitreverse16) + return __builtin_bitreverse16(x); +#else /* Assign the correct byte position. */ x = bswap16(x); /* Assign the correct nibble position. */ @@ -300,6 +307,7 @@ static inline uint16_t revbit16(uint16_t x) | ((x & 0x2222) << 1) | ((x & 0x1111) << 3); return x; +#endif } /** @@ -308,6 +316,9 @@ static inline uint16_t revbit16(uint16_t x) */ static inline uint32_t revbit32(uint32_t x) { +#if __has_builtin(__builtin_bitreverse32) + return __builtin_bitreverse32(x); +#else /* Assign the correct byte position. */ x = bswap32(x); /* Assign the correct nibble position. */ @@ -319,6 +330,7 @@ static inline uint32_t revbit32(uint32_t x) | ((x & 0x22222222u) << 1) | ((x & 0x11111111u) << 3); return x; +#endif } /** @@ -327,6 +339,9 @@ static inline uint32_t revbit32(uint32_t x) */ static inline uint64_t revbit64(uint64_t x) { +#if __has_builtin(__builtin_bitreverse64) + return __builtin_bitreverse64(x); +#else /* Assign the correct byte position. */ x = bswap64(x); /* Assign the correct nibble position. */ @@ -338,6 +353,7 @@ static inline uint64_t revbit64(uint64_t x) | ((x & 0x2222222222222222ull) << 1) | ((x & 0x1111111111111111ull) << 3); return x; +#endif } /* Host type specific sizes of these routines. */ From patchwork Sat May 8 01:46:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432517 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp840414jao; Fri, 7 May 2021 18:49:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOQN8yZ6nHXkqZBsW5iC4Xmj2OkPb34S1oqfSTQLiKRjF03LPvfmgIamAaRT6dTvXf0mA9 X-Received: by 2002:a05:6638:101a:: with SMTP id r26mr11632536jab.15.1620438562878; Fri, 07 May 2021 18:49:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438562; cv=none; d=google.com; s=arc-20160816; b=HKePjbR2ERBIse57rghvs+gdEONgZuN74K6YyzlF+Ju2VagR+IHBiNO77Hko8D5Ryk x5K9aftrG/gmIAIU8EYOUETZ0++yXIDd/kC7uhpj3Gn/gxUZ3NOMJNtBV4iXA5Qstpks qJH4ZVxUvZexArbIwgdfSMMpn1WF8V0aO/mMHgRCMcK0JDgDdrWdMyTgDCu5otkf8bQs GYada9hC0SLozuGU05ekdnwhUwnvZsYrrMP34CAsO5X1otIITq2zZ1OovuaGSY2sHm2J 6MtQSMEFSwZjdDFuZ08m9t+sCg4MTjUkxNV/tAOdwKDWJ619HMKbm11S4bMuUzw4HmbA h/bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4FUAz053Q8O4lxDctUgjdKConowhJ6wTho8iZJwG5rg=; b=fVvFjWOb+02B5KbhoM3CM+sF2VxOK2vYy06gp9TubosBNb3cTMFCBdsGYJ6meFjqG5 1Q4rkKIUBSz5j2o6irj9bB6xdRgxznnOvnLC0G1H977qhjG0QXyfkNOxfRX1PlPkGzKH hRB0UAavsuIReZ5p2t5Q+AttV5O1jRaXovyLgIUA8fYAS/UHDOQ9fmaoy9ru2eQAI4+W pyOvtqCDMUeIo46/HIkD2jO/Who7BGophhigay741DtwaGwfEdkwEVEeM/fkP2kI/63r 1Cg7iN8YysDBKDOx56fL0hDo1DQ6UrsQuz//Sm5Sgf8zx7DtjcRLo3CsOGhMWwEtbt7Y HQvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DDoqlPhH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- include/qemu/host-utils.h | 225 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 225 insertions(+) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index f1e52851e0..fd76f0cbd3 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -356,6 +356,231 @@ static inline uint64_t revbit64(uint64_t x) #endif } +/** + * sadd32_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret = @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool sadd32_overflow(int32_t x, int32_t y, int32_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >= 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret = x + y; + return ((*ret ^ x) & ~(x ^ y)) < 0; +#endif +} + +/** + * sadd64_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret = @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool sadd64_overflow(int64_t x, int64_t y, int64_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >= 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret = x + y; + return ((*ret ^ x) & ~(x ^ y)) < 0; +#endif +} + +/** + * uadd32_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret = @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool uadd32_overflow(uint32_t x, uint32_t y, uint32_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >= 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret = x + y; + return *ret < x; +#endif +} + +/** + * uadd64_overflow - addition with overflow indication + * @x, @y: addends + * @ret: Output for sum + * + * Computes *@ret = @x + @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool uadd64_overflow(uint64_t x, uint64_t y, uint64_t *ret) +{ +#if __has_builtin(__builtin_add_overflow) || __GNUC__ >= 5 + return __builtin_add_overflow(x, y, ret); +#else + *ret = x + y; + return *ret < x; +#endif +} + +/** + * ssub32_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for difference + * + * Computes *@ret = @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool ssub32_overflow(int32_t x, int32_t y, int32_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >= 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret = x - y; + return ((*ret ^ x) & (x ^ y)) < 0; +#endif +} + +/** + * ssub64_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for sum + * + * Computes *@ret = @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool ssub64_overflow(int64_t x, int64_t y, int64_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >= 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret = x - y; + return ((*ret ^ x) & (x ^ y)) < 0; +#endif +} + +/** + * usub32_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for sum + * + * Computes *@ret = @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool usub32_overflow(uint32_t x, uint32_t y, uint32_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >= 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret = x - y; + return x < y; +#endif +} + +/** + * usub64_overflow - subtraction with overflow indication + * @x: Minuend + * @y: Subtrahend + * @ret: Output for sum + * + * Computes *@ret = @x - @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool usub64_overflow(uint64_t x, uint64_t y, uint64_t *ret) +{ +#if __has_builtin(__builtin_sub_overflow) || __GNUC__ >= 5 + return __builtin_sub_overflow(x, y, ret); +#else + *ret = x - y; + return x < y; +#endif +} + +/** + * smul32_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret = @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool smul32_overflow(int32_t x, int32_t y, int32_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >= 5 + return __builtin_mul_overflow(x, y, ret); +#else + int64_t z = (int64_t)x * y; + *ret = z; + return *ret != z; +#endif +} + +/** + * smul64_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret = @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool smul64_overflow(int64_t x, int64_t y, int64_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >= 5 + return __builtin_mul_overflow(x, y, ret); +#else + uint64_t hi, lo; + muls64(&lo, &hi, x, y); + *ret = lo; + return hi != ((int64_t)lo >> 63); +#endif +} + +/** + * umul32_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret = @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool umul32_overflow(uint32_t x, uint32_t y, uint32_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >= 5 + return __builtin_mul_overflow(x, y, ret); +#else + uint64_t z = (uint64_t)x * y; + *ret = z; + return z > UINT32_MAX; +#endif +} + +/** + * smul64_overflow - multiplication with overflow indication + * @x, @y: Input multipliers + * @ret: Output for product + * + * Computes *@ret = @x * @y, and returns true if and only if that + * value has been truncated. + */ +static inline bool umul64_overflow(uint64_t x, uint64_t y, uint64_t *ret) +{ +#if __has_builtin(__builtin_mul_overflow) || __GNUC__ >= 5 + return __builtin_mul_overflow(x, y, ret); +#else + uint64_t hi; + mulu64(ret, &hi, x, y); + return hi != 0; +#endif +} + /* Host type specific sizes of these routines. */ #if ULONG_MAX == UINT32_MAX From patchwork Sat May 8 01:46:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432515 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp840102jao; Fri, 7 May 2021 18:48:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHOZuNdRvg2Bw3Z3MOuqp8DC8aZjsjfufpSnjOOl/tWbqBSz1BVb8imnJaDsv45yyZgRB/ X-Received: by 2002:a05:6e02:1488:: with SMTP id n8mr12792642ilk.158.1620438529762; Fri, 07 May 2021 18:48:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438529; cv=none; d=google.com; s=arc-20160816; b=APkgGFkL6pcqUwA0G2UEc7uwFmldpv6kpgGrdVeH8Jkao24jhNfpILpwPJaljWQJvz h2F7HDBY8AFBE9VzyJHZIXTjwRJWnJjhn0FVF9FyYVF2fNeZnhFMtUJe8VdliBTYS8Nz pk7t/bCgFDWZkEJ7Ke9jQx5WWOjZCsEg0fnbH88voEZNdKjGjq9kIednCqxvE0O4Nenq S5fN4gQwZ1pywH9p7DeTMNbmprO/3PQZddIXU/7Nd2sojTetq0XJAunKQxLR+IKHbQNQ r1HAfZAhyIA5xMVeqPNf2EweMSY7+cYXIh81uOTghtPAzCfjPID/cxAWy0DZe0SnldoK UGdA== ARC-Message-Signature: i=1; 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Even in clang the optimization is not ideal except for x86_64, but no worse than the hand-coding that we currently do. Signed-off-by: Richard Henderson --- include/qemu/host-utils.h | 50 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index fd76f0cbd3..2ea8b3000b 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -26,6 +26,7 @@ #ifndef HOST_UTILS_H #define HOST_UTILS_H +#include "qemu/compiler.h" #include "qemu/bswap.h" #ifdef CONFIG_INT128 @@ -581,6 +582,55 @@ static inline bool umul64_overflow(uint64_t x, uint64_t y, uint64_t *ret) #endif } +/** + * uadd64_carry - addition with carry-in and carry-out + * @x, @y: addends + * @pcarry: in-out carry value + * + * Computes @x + @y + *@pcarry, placing the carry-out back + * into *@pcarry and returning the 64-bit sum. + */ +static inline uint64_t uadd64_carry(uint64_t x, uint64_t y, bool *pcarry) +{ +#if __has_builtin(__builtin_addcll) + unsigned long long c = *pcarry; + x = __builtin_addcll(x, y, c, &c); + *pcarry = c & 1; + return x; +#else + bool c = *pcarry; + /* This is clang's internal expansion of __builtin_addc. */ + c = uadd64_overflow(x, c, &x); + c |= uadd64_overflow(x, y, &x); + *pcarry = c; + return x; +#endif +} + +/** + * usub64_borrow - subtraction with borrow-in and borrow-out + * @x, @y: addends + * @pborrow: in-out borrow value + * + * Computes @x - @y - *@pborrow, placing the borrow-out back + * into *@pborrow and returning the 64-bit sum. + */ +static inline uint64_t usub64_borrow(uint64_t x, uint64_t y, bool *pborrow) +{ +#if __has_builtin(__builtin_subcll) + unsigned long long b = *pborrow; + x = __builtin_subcll(x, y, b, &b); + *pborrow = b & 1; + return x; +#else + bool b = *pborrow; + b = usub64_overflow(x, b, &x); + b |= usub64_overflow(x, y, &x); + *pborrow = b; + return x; +#endif +} + /* Host type specific sizes of these routines. */ #if ULONG_MAX == UINT32_MAX From patchwork Sat May 8 01:46:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432518 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp840447jao; Fri, 7 May 2021 18:49:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQZiLzwsTKaBQtYWE4Y2JRYibfhuUrlsUp+a9Jr7NIhOh8Ws3qui06mpKd7hwICKn8la5P X-Received: by 2002:a02:a04d:: with SMTP id f13mr11758397jah.38.1620438566037; Fri, 07 May 2021 18:49:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438566; cv=none; d=google.com; s=arc-20160816; b=uVGodtQNq7k2xEv/gUQO6/Qeb00/f3TkXoz+YYb8uJQ/ddgC81WTjhiWZ8WkHVFdIW iL6kWeagMF1DRORxmyg88Hg1CjFGqyszM3jfQE/hIVds8B8y59X/5xFPhXU+YpPjrL1r +zoZgifX2yuav3jn4CYcm6bnbzg1gwW3h5w3HeKFtWL5C9TpKGEmgP5BpPtGEIr3uRF0 qiflVrw8ou14+ROmL51j48N3vzZxjFDEkmsxHlY0JzCVqMDgbYTEz6xOUTcQ8rLtHLZu rxKo87/lLVN6woSTAS6loKLEQ+nNPu10IKN8P4CnMCN6jfDRnHXZ1qmSJ9+ET1Ff05c5 XoWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=62inUraaTVgAI6l4Edj8J42LMU7wWh7GjwLbvqFnK/4=; b=IZ25rDliilcu/FrluT5qHg8xHC5obfBh0nIbFK1f9h6nUhlRkVeWwwMZcI261asss0 +C4KCn+30cARmd/H80Fteixfwk+LwLWsirj7Cf0hrIRgOW9WCIaBv8CaDD2PN/TgdcJc Kb4DAepC8+upISH/TRb7KVJqQzIRXy9MAr0SGFsnyDXVVz90Kg3McVhJfWCMfr1HWkeR t1+N62yM5bs1+3H8wktAoo8EQnhABPc5iQ0lp/Hv7XXcrx+gq/mKTnWFXuaPdPLPQQ+u sds1kwm+x911TjJzbb7YSBoEGkTHMThyLDW+Xa8vS5fRBk9623jBSAXdKp8dkxPkruR4 AGZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fFy18+Oa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime-gvec.c | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 521da4a813..ac7d28c251 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -1073,9 +1073,8 @@ void HELPER(gvec_ssadd32)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(int32_t)) { int32_t ai = *(int32_t *)(a + i); int32_t bi = *(int32_t *)(b + i); - int32_t di = ai + bi; - if (((di ^ ai) &~ (ai ^ bi)) < 0) { - /* Signed overflow. */ + int32_t di; + if (sadd32_overflow(ai, bi, &di)) { di = (di < 0 ? INT32_MAX : INT32_MIN); } *(int32_t *)(d + i) = di; @@ -1091,9 +1090,8 @@ void HELPER(gvec_ssadd64)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(int64_t)) { int64_t ai = *(int64_t *)(a + i); int64_t bi = *(int64_t *)(b + i); - int64_t di = ai + bi; - if (((di ^ ai) &~ (ai ^ bi)) < 0) { - /* Signed overflow. */ + int64_t di; + if (sadd64_overflow(ai, bi, &di)) { di = (di < 0 ? INT64_MAX : INT64_MIN); } *(int64_t *)(d + i) = di; @@ -1143,9 +1141,8 @@ void HELPER(gvec_sssub32)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(int32_t)) { int32_t ai = *(int32_t *)(a + i); int32_t bi = *(int32_t *)(b + i); - int32_t di = ai - bi; - if (((di ^ ai) & (ai ^ bi)) < 0) { - /* Signed overflow. */ + int32_t di; + if (ssub32_overflow(ai, bi, &di)) { di = (di < 0 ? INT32_MAX : INT32_MIN); } *(int32_t *)(d + i) = di; @@ -1161,9 +1158,8 @@ void HELPER(gvec_sssub64)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(int64_t)) { int64_t ai = *(int64_t *)(a + i); int64_t bi = *(int64_t *)(b + i); - int64_t di = ai - bi; - if (((di ^ ai) & (ai ^ bi)) < 0) { - /* Signed overflow. */ + int64_t di; + if (ssub64_overflow(ai, bi, &di)) { di = (di < 0 ? INT64_MAX : INT64_MIN); } *(int64_t *)(d + i) = di; @@ -1209,8 +1205,8 @@ void HELPER(gvec_usadd32)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(uint32_t)) { uint32_t ai = *(uint32_t *)(a + i); uint32_t bi = *(uint32_t *)(b + i); - uint32_t di = ai + bi; - if (di < ai) { + uint32_t di; + if (uadd32_overflow(ai, bi, &di)) { di = UINT32_MAX; } *(uint32_t *)(d + i) = di; @@ -1226,8 +1222,8 @@ void HELPER(gvec_usadd64)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(uint64_t)) { uint64_t ai = *(uint64_t *)(a + i); uint64_t bi = *(uint64_t *)(b + i); - uint64_t di = ai + bi; - if (di < ai) { + uint64_t di; + if (uadd64_overflow(ai, bi, &di)) { di = UINT64_MAX; } *(uint64_t *)(d + i) = di; @@ -1273,8 +1269,8 @@ void HELPER(gvec_ussub32)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(uint32_t)) { uint32_t ai = *(uint32_t *)(a + i); uint32_t bi = *(uint32_t *)(b + i); - uint32_t di = ai - bi; - if (ai < bi) { + uint32_t di; + if (usub32_overflow(ai, bi, &di)) { di = 0; } *(uint32_t *)(d + i) = di; @@ -1290,8 +1286,8 @@ void HELPER(gvec_ussub64)(void *d, void *a, void *b, uint32_t desc) for (i = 0; i < oprsz; i += sizeof(uint64_t)) { uint64_t ai = *(uint64_t *)(a + i); uint64_t bi = *(uint64_t *)(b + i); - uint64_t di = ai - bi; - if (ai < bi) { + uint64_t di; + if (usub64_overflow(ai, bi, &di)) { di = 0; } *(uint64_t *)(d + i) = di; From patchwork Sat May 8 01:46:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432525 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp843611jao; Fri, 7 May 2021 18:55:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3JMKh8A8lbo7Y2RaiKmi+ksvQC0YM3LdA9yqvLxjjwjpjVmmX3IiDRuTC4Zqy0MJJfuvd X-Received: by 2002:a5d:9a11:: with SMTP id s17mr9645031iol.32.1620438943036; Fri, 07 May 2021 18:55:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438943; cv=none; d=google.com; s=arc-20160816; b=wwMHXpDHaX5nsTFFtZdqE+YyYBetuNENr67pzewgZv8ASadHfAfQMzQ/bs3nnyHZQC R5DfzfJvju/HnpMu70jFzy2jrcMCO+Pr+ef+cSql2PrHBu2kXLuBfBn/nCyQeuP7s7ng t4n0Yh1dC3Gq39W2X09Kx+iauOJHpb0JJC0b9opLz6j6OAd6No72M5Z1GKlRWT2e/LaU wgigMl8JGlUMcRLWDfm5rNjNy6HC9z63cdXnhYKU6a8c561UHrGZByQYVVqxZN1XoKDD WPXOF+G05rtK+ubqJ+f7s13kf2rjU9oXRl+3rz0GsybpKVmC+DCUFFdGjdtqgYnpZ5xl maow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=g4+K3m2LZd6+POKVjFNctLT1gVSINE33R4eVJ09cL3Y=; b=hm76sE738CxEw8j4eQjL5TNAnCOHVwl5D2kLi1PUTGVizQ9yOP9veFJFWbQDy8kxO4 8wu0GXqiBKN7KmijsvqCKYL5+ERFNlMJFIniS0Np0m1rcLFZSXZfAHMdIIsH4hfn7G/k zRucOUWxpqT79Wf6m75brx3K44tmLoCpkBDC8gx4zYEjUVodPN+rA5REGX3XxJ0Lhm/G s8yMbDQwUipr5gXtknfsmA+Oqhjw1iTL6FWVANwzUU/yktutCFioePCC1g/L9v2mu9IG qkayCUOSGArMOJzii0h9LwoD/94Q7IObZsEcRAPNDBuUgcmCTNSWfZRS45bgNyO7beMq MeyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YvUHLDxs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The 3 op muladd operation is currently unimplemented so commented out for now. Signed-off-by: Alex Bennée Message-Id: <20201020163738.27700-8-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- tests/fp/fp-bench.c | 88 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 5 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 4ba5e1d2d4..d319993280 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -14,6 +14,7 @@ #include #include #include "qemu/timer.h" +#include "qemu/int128.h" #include "fpu/softfloat.h" /* amortize the computation of random inputs */ @@ -50,8 +51,10 @@ static const char * const op_names[] = { enum precision { PREC_SINGLE, PREC_DOUBLE, + PREC_QUAD, PREC_FLOAT32, PREC_FLOAT64, + PREC_FLOAT128, PREC_MAX_NR, }; @@ -89,6 +92,7 @@ union fp { double d; float32 f32; float64 f64; + float128 f128; uint64_t u64; }; @@ -113,6 +117,10 @@ struct op_desc { static uint64_t random_ops[MAX_OPERANDS] = { SEED_A, SEED_B, SEED_C, }; + +static float128 random_quad_ops[MAX_OPERANDS] = { + {SEED_A, SEED_B}, {SEED_B, SEED_C}, {SEED_C, SEED_A}, +}; static float_status soft_status; static enum precision precision; static enum op operation; @@ -141,25 +149,45 @@ static void update_random_ops(int n_ops, enum precision prec) int i; for (i = 0; i < n_ops; i++) { - uint64_t r = random_ops[i]; switch (prec) { case PREC_SINGLE: case PREC_FLOAT32: + { + uint64_t r = random_ops[i]; do { r = xorshift64star(r); } while (!float32_is_normal(r)); + random_ops[i] = r; break; + } case PREC_DOUBLE: case PREC_FLOAT64: + { + uint64_t r = random_ops[i]; do { r = xorshift64star(r); } while (!float64_is_normal(r)); + random_ops[i] = r; break; + } + case PREC_QUAD: + case PREC_FLOAT128: + { + float128 r = random_quad_ops[i]; + uint64_t hi = r.high; + uint64_t lo = r.low; + do { + hi = xorshift64star(hi); + lo = xorshift64star(lo); + r = make_float128(hi, lo); + } while (!float128_is_normal(r)); + random_quad_ops[i] = r; + break; + } default: g_assert_not_reached(); } - random_ops[i] = r; } } @@ -184,6 +212,13 @@ static void fill_random(union fp *ops, int n_ops, enum precision prec, ops[i].f64 = float64_chs(ops[i].f64); } break; + case PREC_QUAD: + case PREC_FLOAT128: + ops[i].f128 = random_quad_ops[i]; + if (no_neg && float128_is_neg(ops[i].f128)) { + ops[i].f128 = float128_chs(ops[i].f128); + } + break; default: g_assert_not_reached(); } @@ -345,6 +380,41 @@ static void bench(enum precision prec, enum op op, int n_ops, bool no_neg) } } break; + case PREC_FLOAT128: + fill_random(ops, n_ops, prec, no_neg); + t0 = get_clock(); + for (i = 0; i < OPS_PER_ITER; i++) { + float128 a = ops[0].f128; + float128 b = ops[1].f128; + /* float128 c = ops[2].f128; */ + + switch (op) { + case OP_ADD: + res.f128 = float128_add(a, b, &soft_status); + break; + case OP_SUB: + res.f128 = float128_sub(a, b, &soft_status); + break; + case OP_MUL: + res.f128 = float128_mul(a, b, &soft_status); + break; + case OP_DIV: + res.f128 = float128_div(a, b, &soft_status); + break; + /* case OP_FMA: */ + /* res.f128 = float128_muladd(a, b, c, 0, &soft_status); */ + /* break; */ + case OP_SQRT: + res.f128 = float128_sqrt(a, &soft_status); + break; + case OP_CMP: + res.u64 = float128_compare_quiet(a, b, &soft_status); + break; + default: + g_assert_not_reached(); + } + } + break; default: g_assert_not_reached(); } @@ -369,7 +439,8 @@ static void bench(enum precision prec, enum op op, int n_ops, bool no_neg) GEN_BENCH(bench_ ## opname ## _float, float, PREC_SINGLE, op, n_ops) \ GEN_BENCH(bench_ ## opname ## _double, double, PREC_DOUBLE, op, n_ops) \ GEN_BENCH(bench_ ## opname ## _float32, float32, PREC_FLOAT32, op, n_ops) \ - GEN_BENCH(bench_ ## opname ## _float64, float64, PREC_FLOAT64, op, n_ops) + GEN_BENCH(bench_ ## opname ## _float64, float64, PREC_FLOAT64, op, n_ops) \ + GEN_BENCH(bench_ ## opname ## _float128, float128, PREC_FLOAT128, op, n_ops) GEN_BENCH_ALL_TYPES(add, OP_ADD, 2) GEN_BENCH_ALL_TYPES(sub, OP_SUB, 2) @@ -383,7 +454,8 @@ GEN_BENCH_ALL_TYPES(cmp, OP_CMP, 2) GEN_BENCH_NO_NEG(bench_ ## name ## _float, float, PREC_SINGLE, op, n) \ GEN_BENCH_NO_NEG(bench_ ## name ## _double, double, PREC_DOUBLE, op, n) \ GEN_BENCH_NO_NEG(bench_ ## name ## _float32, float32, PREC_FLOAT32, op, n) \ - GEN_BENCH_NO_NEG(bench_ ## name ## _float64, float64, PREC_FLOAT64, op, n) + GEN_BENCH_NO_NEG(bench_ ## name ## _float64, float64, PREC_FLOAT64, op, n) \ + GEN_BENCH_NO_NEG(bench_ ## name ## _float128, float128, PREC_FLOAT128, op, n) GEN_BENCH_ALL_TYPES_NO_NEG(sqrt, OP_SQRT, 1) #undef GEN_BENCH_ALL_TYPES_NO_NEG @@ -397,6 +469,7 @@ GEN_BENCH_ALL_TYPES_NO_NEG(sqrt, OP_SQRT, 1) [PREC_DOUBLE] = bench_ ## opname ## _double, \ [PREC_FLOAT32] = bench_ ## opname ## _float32, \ [PREC_FLOAT64] = bench_ ## opname ## _float64, \ + [PREC_FLOAT128] = bench_ ## opname ## _float128, \ } static const bench_func_t bench_funcs[OP_MAX_NR][PREC_MAX_NR] = { @@ -445,7 +518,7 @@ static void usage_complete(int argc, char *argv[]) fprintf(stderr, " -h = show this help message.\n"); fprintf(stderr, " -o = floating point operation (%s). Default: %s\n", op_list, op_names[0]); - fprintf(stderr, " -p = floating point precision (single, double). " + fprintf(stderr, " -p = floating point precision (single, double, quad[soft only]). " "Default: single\n"); fprintf(stderr, " -r = rounding mode (even, zero, down, up, tieaway). " "Default: even\n"); @@ -565,6 +638,8 @@ static void parse_args(int argc, char *argv[]) precision = PREC_SINGLE; } else if (!strcmp(optarg, "double")) { precision = PREC_DOUBLE; + } else if (!strcmp(optarg, "quad")) { + precision = PREC_QUAD; } else { fprintf(stderr, "Unsupported precision '%s'\n", optarg); exit(EXIT_FAILURE); @@ -608,6 +683,9 @@ static void parse_args(int argc, char *argv[]) case PREC_DOUBLE: precision = PREC_FLOAT64; break; + case PREC_QUAD: + precision = PREC_FLOAT128; + break; default: g_assert_not_reached(); } From patchwork Sat May 8 01:46:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432532 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp847772jao; Fri, 7 May 2021 19:02:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGsO/oyRcZSzRRkCpKxaq1MK8aqKFpLO4DVBWPBocjIpXpUy+7K4rvWwJEh+zBxFg+r+2Z X-Received: by 2002:a05:6102:e90:: with SMTP id l16mr11365940vst.43.1620439357963; Fri, 07 May 2021 19:02:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439357; cv=none; d=google.com; s=arc-20160816; b=QinQhp405RfmoFfv2Ss5UN/FJhSn6NHTVhdbm/8nigKZuaypprbzZ7kLdFVnJhfGck DJvhnpNMFRA0LYnLNYYajYEoh4GpBU2u8cBegfO0Y2k6a/573qH9Yl8Sf7ivOjwMCrnG vp46DhClirtHz09b8kULPxfrXJFhDRFfBCe/ctYbNOf9c/bJXfzDp9GpIWdUBy2iERC8 LWkHyrwNhwzWOdCqRoY342Bsaozlw5EFeKZf8NUpRjBW4BE8EZBh2zyd21q/+5SB1T5a 2s2dCUcn0xcj8y0y/NiJEnrbgkFcPG87zJX30JE0znpiMuxlr8fZElbx9auZ4ctavVIv yEjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Tsoe+BVssAGH6OVs2DygacO7h0Tml9zLW3atLp8I1f0=; b=WUpDFkvNmu9TwCZS5xkR2dsAgltF7puRbqtDYvd2txtZDYTiFZFzUiK2kqsaHic/aP 0MEw2qcGo8mINF3CRlEh8sMsKc4xHKoQCJb1pgSDpRqgL7xOOLuusZuEPeueeBevA+Ff s6KXuEQtPyycAzopjK+mVPEpl+1RNlI9zRrI1pOzWLev3VUjN5B80ysfiYqHYkCgu6e3 r7Zp5XkOEyXnO8C3qM7N4928BjAe4IY6AmiOnkr4hwQYdN0N24FJ3MpPhJqIVlF4yV00 /Djz3fVBwLn+Ttm4wUzU+KZ8EFEMdA8sOQ5jbpYoZIOE5c8aFIxoWQDL+1/d+ezBsjst FZ1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=M0SObHiq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use uadd64_overflow to detect when addition overflows instead of DECOMPOSED_OVERFLOW_BIT. This reduces the number of special cases within the code, such as shifting an int64_t either left or right during conversion. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 169 +++++++++++++++++++----------------------------- 1 file changed, 66 insertions(+), 103 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 67cfa0fd82..cd777743f1 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -503,9 +503,8 @@ typedef struct { bool sign; } FloatParts; -#define DECOMPOSED_BINARY_POINT (64 - 2) +#define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) -#define DECOMPOSED_OVERFLOW_BIT (DECOMPOSED_IMPLICIT_BIT << 1) /* Structure holding all of the relevant parameters for a format. * exp_size: the size of the exponent field @@ -657,7 +656,7 @@ static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm, part.cls = float_class_zero; part.frac = 0; } else { - int shift = clz64(part.frac) - 1; + int shift = clz64(part.frac); part.cls = float_class_normal; part.exp = parm->frac_shift - parm->exp_bias - shift + 1; part.frac <<= shift; @@ -727,9 +726,8 @@ static FloatParts round_canonical(FloatParts p, float_status *s, if (likely(exp > 0)) { if (frac & round_mask) { flags |= float_flag_inexact; - frac += inc; - if (frac & DECOMPOSED_OVERFLOW_BIT) { - frac >>= 1; + if (uadd64_overflow(frac, inc, &frac)) { + frac = (frac >> 1) | DECOMPOSED_IMPLICIT_BIT; exp++; } } @@ -758,9 +756,12 @@ static FloatParts round_canonical(FloatParts p, float_status *s, p.cls = float_class_zero; goto do_zero; } else { - bool is_tiny = s->tininess_before_rounding - || (exp < 0) - || !((frac + inc) & DECOMPOSED_OVERFLOW_BIT); + bool is_tiny = s->tininess_before_rounding || (exp < 0); + + if (!is_tiny) { + uint64_t discard; + is_tiny = !uadd64_overflow(frac, inc, &discard); + } shift64RightJamming(frac, 1 - exp, &frac); if (frac & round_mask) { @@ -985,7 +986,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, a.cls = float_class_zero; a.sign = s->float_rounding_mode == float_round_down; } else { - int shift = clz64(a.frac) - 1; + int shift = clz64(a.frac); a.frac = a.frac << shift; a.exp = a.exp - shift; a.sign = a_sign; @@ -1022,9 +1023,10 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); a.exp = b.exp; } - a.frac += b.frac; - if (a.frac & DECOMPOSED_OVERFLOW_BIT) { + + if (uadd64_overflow(a.frac, b.frac, &a.frac)) { shift64RightJamming(a.frac, 1, &a.frac); + a.frac |= DECOMPOSED_IMPLICIT_BIT; a.exp += 1; } return a; @@ -1219,16 +1221,17 @@ static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) int exp = a.exp + b.exp; mul64To128(a.frac, b.frac, &hi, &lo); - shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); - if (lo & DECOMPOSED_OVERFLOW_BIT) { - shift64RightJamming(lo, 1, &lo); + if (hi & DECOMPOSED_IMPLICIT_BIT) { exp += 1; + } else { + hi <<= 1; } + hi |= (lo != 0); /* Re-use a */ a.exp = exp; a.sign = sign; - a.frac = lo; + a.frac = hi; return a; } /* handle all the NaN cases */ @@ -1411,56 +1414,41 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, p_exp = a.exp + b.exp; - /* Multiply of 2 62-bit numbers produces a (2*62) == 124-bit - * result. - */ mul64To128(a.frac, b.frac, &hi, &lo); - /* binary point now at bit 124 */ - /* check for overflow */ - if (hi & (1ULL << (DECOMPOSED_BINARY_POINT * 2 + 1 - 64))) { - shift128RightJamming(hi, lo, 1, &hi, &lo); + /* Renormalize to the msb. */ + if (hi & DECOMPOSED_IMPLICIT_BIT) { p_exp += 1; + } else { + shortShift128Left(hi, lo, 1, &hi, &lo); } /* + add/sub */ - if (c.cls == float_class_zero) { - /* move binary point back to 62 */ - shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); - } else { + if (c.cls != float_class_zero) { int exp_diff = p_exp - c.exp; if (p_sign == c.sign) { /* Addition */ if (exp_diff <= 0) { - shift128RightJamming(hi, lo, - DECOMPOSED_BINARY_POINT - exp_diff, - &hi, &lo); - lo += c.frac; + shift64RightJamming(hi, -exp_diff, &hi); p_exp = c.exp; + if (uadd64_overflow(hi, c.frac, &hi)) { + shift64RightJamming(hi, 1, &hi); + hi |= DECOMPOSED_IMPLICIT_BIT; + p_exp += 1; + } } else { - uint64_t c_hi, c_lo; - /* shift c to the same binary point as the product (124) */ - c_hi = c.frac >> 2; - c_lo = 0; - shift128RightJamming(c_hi, c_lo, - exp_diff, - &c_hi, &c_lo); - add128(hi, lo, c_hi, c_lo, &hi, &lo); - /* move binary point back to 62 */ - shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo); + uint64_t c_hi, c_lo, over; + shift128RightJamming(c.frac, 0, exp_diff, &c_hi, &c_lo); + add192(0, hi, lo, 0, c_hi, c_lo, &over, &hi, &lo); + if (over) { + shift64RightJamming(hi, 1, &hi); + hi |= DECOMPOSED_IMPLICIT_BIT; + p_exp += 1; + } } - - if (lo & DECOMPOSED_OVERFLOW_BIT) { - shift64RightJamming(lo, 1, &lo); - p_exp += 1; - } - } else { /* Subtraction */ - uint64_t c_hi, c_lo; - /* make C binary point match product at bit 124 */ - c_hi = c.frac >> 2; - c_lo = 0; + uint64_t c_hi = c.frac, c_lo = 0; if (exp_diff <= 0) { shift128RightJamming(hi, lo, -exp_diff, &hi, &lo); @@ -1495,20 +1483,15 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, /* Normalizing to a binary point of 124 is the correct adjust for the exponent. However since we're shifting, we might as well put the binary point back - at 62 where we really want it. Therefore shift as + at 63 where we really want it. Therefore shift as if we're leaving 1 bit at the top of the word, but adjust the exponent as if we're leaving 3 bits. */ - shift -= 1; - if (shift >= 64) { - lo = lo << (shift - 64); - } else { - hi = (hi << shift) | (lo >> (64 - shift)); - lo = hi | ((lo << shift) != 0); - } - p_exp -= shift - 2; + shift128Left(hi, lo, shift, &hi, &lo); + p_exp -= shift; } } } + hi |= (lo != 0); if (flags & float_muladd_halve_result) { p_exp -= 1; @@ -1518,7 +1501,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, a.cls = float_class_normal; a.sign = p_sign ^ sign_flip; a.exp = p_exp; - a.frac = lo; + a.frac = hi; return a; } @@ -1742,25 +1725,17 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) * exponent to match. * * The udiv_qrnnd algorithm that we're using requires normalization, - * i.e. the msb of the denominator must be set. Since we know that - * DECOMPOSED_BINARY_POINT is msb-1, the inputs must be shifted left - * by one (more), and the remainder must be shifted right by one. + * i.e. the msb of the denominator must be set, which is already true. */ if (a.frac < b.frac) { exp -= 1; - shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 2, &n1, &n0); - } else { shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, &n1, &n0); + } else { + shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT, &n1, &n0); } - q = udiv_qrnnd(&r, n1, n0, b.frac << 1); + q = udiv_qrnnd(&r, n1, n0, b.frac); - /* - * Set lsb if there is a remainder, to set inexact. - * As mentioned above, to find the actual value of the remainder we - * would need to shift right, but (1) we are only concerned about - * non-zero-ness, and (2) the remainder will always be even because - * both inputs to the division primitive are even. - */ + /* Set lsb if there is a remainder, to set inexact. */ a.frac = q | (r != 0); a.sign = sign; a.exp = exp; @@ -2135,12 +2110,12 @@ static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode, if (a.frac & rnd_mask) { s->float_exception_flags |= float_flag_inexact; - a.frac += inc; - a.frac &= ~rnd_mask; - if (a.frac & DECOMPOSED_OVERFLOW_BIT) { + if (uadd64_overflow(a.frac, inc, &a.frac)) { a.frac >>= 1; + a.frac |= DECOMPOSED_IMPLICIT_BIT; a.exp++; } + a.frac &= ~rnd_mask; } } break; @@ -2213,10 +2188,8 @@ static int64_t round_to_int_and_pack(FloatParts in, FloatRoundMode rmode, case float_class_zero: return 0; case float_class_normal: - if (p.exp < DECOMPOSED_BINARY_POINT) { + if (p.exp <= DECOMPOSED_BINARY_POINT) { r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - } else if (p.exp - DECOMPOSED_BINARY_POINT < 2) { - r = p.frac << (p.exp - DECOMPOSED_BINARY_POINT); } else { r = UINT64_MAX; } @@ -2498,10 +2471,8 @@ static uint64_t round_to_uint_and_pack(FloatParts in, FloatRoundMode rmode, return 0; } - if (p.exp < DECOMPOSED_BINARY_POINT) { + if (p.exp <= DECOMPOSED_BINARY_POINT) { r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - } else if (p.exp - DECOMPOSED_BINARY_POINT < 2) { - r = p.frac << (p.exp - DECOMPOSED_BINARY_POINT); } else { s->float_exception_flags = orig_flags | float_flag_invalid; return max; @@ -2765,11 +2736,11 @@ static FloatParts int_to_float(int64_t a, int scale, float_status *status) f = -f; r.sign = true; } - shift = clz64(f) - 1; + shift = clz64(f); scale = MIN(MAX(scale, -0x10000), 0x10000); r.exp = DECOMPOSED_BINARY_POINT - shift + scale; - r.frac = (shift < 0 ? DECOMPOSED_IMPLICIT_BIT : f << shift); + r.frac = f << shift; } return r; @@ -2920,21 +2891,16 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status *status) static FloatParts uint_to_float(uint64_t a, int scale, float_status *status) { FloatParts r = { .sign = false }; + int shift; if (a == 0) { r.cls = float_class_zero; } else { scale = MIN(MAX(scale, -0x10000), 0x10000); + shift = clz64(a); r.cls = float_class_normal; - if ((int64_t)a < 0) { - r.exp = DECOMPOSED_BINARY_POINT + 1 + scale; - shift64RightJamming(a, 1, &a); - r.frac = a; - } else { - int shift = clz64(a) - 1; - r.exp = DECOMPOSED_BINARY_POINT - shift + scale; - r.frac = a << shift; - } + r.exp = DECOMPOSED_BINARY_POINT - shift + scale; + r.frac = a << shift; } return r; @@ -3475,12 +3441,9 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) /* We need two overflow bits at the top. Adding room for that is a * right shift. If the exponent is odd, we can discard the low bit * by multiplying the fraction by 2; that's a left shift. Combine - * those and we shift right if the exponent is even. + * those and we shift right by 1 if the exponent is odd, otherwise 2. */ - a_frac = a.frac; - if (!(a.exp & 1)) { - a_frac >>= 1; - } + a_frac = a.frac >> (2 - (a.exp & 1)); a.exp >>= 1; /* Bit-by-bit computation of sqrt. */ @@ -3488,10 +3451,10 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) s_frac = 0; /* Iterate from implicit bit down to the 3 extra bits to compute a - * properly rounded result. Remember we've inserted one more bit - * at the top, so these positions are one less. + * properly rounded result. Remember we've inserted two more bits + * at the top, so these positions are two less. */ - bit = DECOMPOSED_BINARY_POINT - 1; + bit = DECOMPOSED_BINARY_POINT - 2; last_bit = MAX(p->frac_shift - 4, 0); do { uint64_t q = 1ULL << bit; @@ -3507,7 +3470,7 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) /* Undo the right shift done above. If there is any remaining * fraction, the result is inexact. Set the sticky bit. */ - a.frac = (r_frac << 1) + (a_frac != 0); + a.frac = (r_frac << 2) + (a_frac != 0); return a; } From patchwork Sat May 8 01:46:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432529 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp845585jao; Fri, 7 May 2021 18:59:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwlyljHmWkMo7R4FAWvOi/0/RvICCvRJg2vupCTwQn7ZwHkS4R0Nh9+OhcFcY7MTLOXW5+2 X-Received: by 2002:a05:6e02:4e:: with SMTP id i14mr1917586ilr.145.1620439151687; Fri, 07 May 2021 18:59:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439151; cv=none; d=google.com; s=arc-20160816; b=bHDhaFmp4DDvdOBP9tK0ziTURx8KlpO81ttd42t99qYauhWso/2VPMWbhrBfaHA7sQ JkBk1pU3NWCCPSzfBXcmoG+9ZtTz+Ne4ssei/HghfHaWnvZkbIoOuP7romUrmGXZo5Zv JiOEEOF8ud+KIlxLVJQbk3ydNU6e3whaZcgdTQXhLcB2wRBfC1N9eXI2ath/UmS5LzWF PpDtmQUtnyx8RhfL1u9Euek2O3aq9MvuXdSzfYSkXapV0KhVBR66XJXfBXVJ1j160QDp 50rcPseEHQxb5Ovi3YY3S7jugB9jtWNS1LHQP53H9Ipe9ypvw2XyU8D1yeiCj4tgo7jg egqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+lENBfCn+Nf5//dPYW1SMMYldoBTpdzj3Cr2k1/SLCM=; b=p0durxOk5ktZhn6S3fIb+nDZd7rpp8M9xSnEzwWH0eGRT5Z7r1iudJFWlygHbIHyri XGuu4nJvvmy3gsYEdMz0QuEFk387BY/JLYQpWvDY6/57tmpJXEUln0s/HexIsKykl1aV vyLyathjzNxwwkk+A+ftn2z+4RjrFdU4BOydjXk04o5Ac8Ft/8BJeFfpPHugEOI3v8Jx 32/2MaLrZwScbvX0dV0fQOLR/0w0xjuMumLFJg1qAoEg/aDQo2yfydCTquDfbto0khpP iFUpxI5/Q5asXU1e6l3wBqAa81UtjamNqD+9U9Vp0MF0BOHkDiR7cIojIRNy1OI6wE79 NnxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aFrWMwUe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:48:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/72] softfloat: Inline float_raise Date: Fri, 7 May 2021 18:46:57 -0700 Message-Id: <20210508014802.892561-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- include/fpu/softfloat.h | 5 ++++- fpu/softfloat-specialize.c.inc | 12 ------------ 2 files changed, 4 insertions(+), 13 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 78ad5ca738..019c2ec66d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -100,7 +100,10 @@ typedef enum { | Routine to raise any or all of the software IEC/IEEE floating-point | exception flags. *----------------------------------------------------------------------------*/ -void float_raise(uint8_t flags, float_status *status); +static inline void float_raise(uint8_t flags, float_status *status) +{ + status->float_exception_flags |= flags; +} /*---------------------------------------------------------------------------- | If `a' is denormal and we are in flush-to-zero mode then set the diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9ea318f3e2..487b29155c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -228,18 +228,6 @@ floatx80 floatx80_default_nan(float_status *status) const floatx80 floatx80_infinity = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); -/*---------------------------------------------------------------------------- -| Raises the exceptions specified by `flags'. Floating-point traps can be -| defined here if desired. It is currently not possible for such a trap -| to substitute a result value. If traps are not implemented, this routine -| should be simply `float_exception_flags |= flags;'. -*----------------------------------------------------------------------------*/ - -void float_raise(uint8_t flags, float_status *status) -{ - status->float_exception_flags |= flags; -} - /*---------------------------------------------------------------------------- | Internal canonical NaN format. *----------------------------------------------------------------------------*/ From patchwork Sat May 8 01:46:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432521 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp842089jao; Fri, 7 May 2021 18:52:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzM9+zi5LzKQh4evcP7V9pOxAh8EJ04DN76VZhPKjIlZCn+MpbZVszh5Z33eSBSqmex/i2j X-Received: by 2002:a6b:c981:: with SMTP id z123mr9627593iof.6.1620438757489; Fri, 07 May 2021 18:52:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438757; cv=none; d=google.com; s=arc-20160816; b=oJKx7WS79HRYMJmVHFO0DYiEEa1UDD2H0wzNSBmQJHGy3svCqDlUyDDQTVco/zjxOd F/0+cBcZgvjpvgliIH/OvcZ8LoshTb9nyevGYlwd+KEDsBgUFP4Jw9nhmUW6M3WZ5l2e Grm10rWLdNJD9ykEVMy+EZp2LPLlTfBlrOBVM6b/RRjrh+YwwOYRKQKbsc9HtNc5/mQ4 D5vrsmEgcxqvMEBTBTZYHUNzIv4lF/JU63+qggVELNUORgxg/bKzSlWq+/Ybo5Tw5CMn jd7/RXfCK4/JDN04YxAmNnl+wNhXzckCwMH2GwxanY66ylStGSkRyUVPhhNfyv+egXZy NRog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9QCF/HdaJHPJuKZrGemLd6T9FbrC4amm92/ME+k+NiA=; b=qBKBMDxY3OyHZ2F+7plEjov0bIXmw0S5kKc07m8jjN3HJNTs6dvM49Cz3V3ClAoHo0 PFMBrksxRaci50vBafqYqS9q7Mt/O8CVm4uF0O5GaHr+upZWfQXdz40gFgevMgUqcH+i NmN4gi8ZJV6wUMUNZpgPOk2bVpOmHisLXP3eCmqfm9SRKCkoVqiVQAJ9iZlNFzZnQw33 5Kc/nzytzfly7PWmq72lz3E34VL4PNtsFJQmSkm65DaIaxUpsGiso8G0tXPrwqkFtMU4 Osa59vVYcSWenH4MWRx3Io5XUiUMZV758ceHc8kINGtd9xAUYKLJN75i3eA7isov2S+5 g/Hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SE0+KI5V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 87 +++++++++++++++++++++++++------------------------ 1 file changed, 44 insertions(+), 43 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cd777743f1..93fe785809 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -132,7 +132,7 @@ this code that are retained. if (unlikely(soft_t ## _is_denormal(*a))) { \ *a = soft_t ## _set_sign(soft_t ## _zero, \ soft_t ## _is_neg(*a)); \ - s->float_exception_flags |= float_flag_input_denormal; \ + float_raise(float_flag_input_denormal, s); \ } \ } @@ -360,7 +360,7 @@ float32_gen2(float32 xa, float32 xb, float_status *s, ur.h = hard(ua.h, ub.h); if (unlikely(f32_is_inf(ur))) { - s->float_exception_flags |= float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabsf(ur.h) <= FLT_MIN) && post(ua, ub)) { goto soft; } @@ -391,7 +391,7 @@ float64_gen2(float64 xa, float64 xb, float_status *s, ur.h = hard(ua.h, ub.h); if (unlikely(f64_is_inf(ur))) { - s->float_exception_flags |= float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabs(ur.h) <= DBL_MIN) && post(ua, ub)) { goto soft; } @@ -880,7 +880,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) { switch (a.cls) { case float_class_snan: - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); a = parts_silence_nan(a, s); /* fall through */ case float_class_qnan: @@ -898,7 +898,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); } if (s->default_nan_mode) { @@ -922,7 +922,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, int which; if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); } which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); @@ -1241,7 +1241,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) /* Inf * Zero == NaN */ if ((a.cls == float_class_inf && b.cls == float_class_zero) || (a.cls == float_class_zero && b.cls == float_class_inf)) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } /* Multiply by 0 or Inf */ @@ -1356,6 +1356,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, } if (inf_zero) { + float_raise(float_flag_invalid, s); s->float_exception_flags |= float_flag_invalid; return parts_default_nan(s); } @@ -1380,7 +1381,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, if (c.cls == float_class_inf) { if (p_class == float_class_inf && p_sign != c.sign) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } else { a.cls = float_class_inf; @@ -1598,7 +1599,7 @@ float32_muladd(float32 xa, float32 xb, float32 xc, int flags, float_status *s) ur.h = fmaf(ua.h, ub.h, uc.h); if (unlikely(f32_is_inf(ur))) { - s->float_exception_flags |= float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabsf(ur.h) <= FLT_MIN)) { ua = ua_orig; uc = uc_orig; @@ -1669,7 +1670,7 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) ur.h = fma(ua.h, ub.h, uc.h); if (unlikely(f64_is_inf(ur))) { - s->float_exception_flags |= float_flag_overflow; + float_raise(float_flag_overflow, s); } else if (unlikely(fabs(ur.h) <= FLT_MIN)) { ua = ua_orig; uc = uc_orig; @@ -1749,7 +1750,7 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) if (a.cls == b.cls && (a.cls == float_class_inf || a.cls == float_class_zero)) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } /* Inf / x or 0 / x */ @@ -1759,7 +1760,7 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) } /* Div 0 => Inf */ if (b.cls == float_class_zero) { - s->float_exception_flags |= float_flag_divbyzero; + float_raise(float_flag_divbyzero, s); a.cls = float_class_inf; a.sign = sign; return a; @@ -1895,7 +1896,7 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, /* There is no NaN in the destination format. Raise Invalid * and return a zero with the sign of the input NaN. */ - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); a.cls = float_class_zero; a.frac = 0; a.exp = 0; @@ -1905,7 +1906,7 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, /* There is no Inf in the destination format. Raise Invalid * and return the maximum normal with the correct sign. */ - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); a.cls = float_class_normal; a.exp = dstf->exp_max; a.frac = ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; @@ -1916,7 +1917,7 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, } } else if (is_nan(a.cls)) { if (is_snan(a.cls)) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); a = parts_silence_nan(a, s); } if (s->default_nan_mode) { @@ -2048,7 +2049,7 @@ static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode, if (a.exp < 0) { bool one; /* all fractional */ - s->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, s); switch (rmode) { case float_round_nearest_even: one = a.exp == -1 && a.frac > DECOMPOSED_IMPLICIT_BIT; @@ -2109,7 +2110,7 @@ static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode, } if (a.frac & rnd_mask) { - s->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, s); if (uadd64_overflow(a.frac, inc, &a.frac)) { a.frac >>= 1; a.frac |= DECOMPOSED_IMPLICIT_BIT; @@ -3188,7 +3189,7 @@ static FloatRelation compare_floats(FloatParts a, FloatParts b, bool is_quiet, if (!is_quiet || a.cls == float_class_snan || b.cls == float_class_snan) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); } return float_relation_unordered; } @@ -3429,7 +3430,7 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) return a; /* sqrt(+-0) = +-0 */ } if (a.sign) { - s->float_exception_flags |= float_flag_invalid; + float_raise(float_flag_invalid, s); return parts_default_nan(s); } if (a.cls == float_class_inf) { @@ -3760,7 +3761,7 @@ static int32_t roundAndPackInt32(bool zSign, uint64_t absZ, return zSign ? INT32_MIN : INT32_MAX; } if (roundBits) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; @@ -3822,7 +3823,7 @@ static int64_t roundAndPackInt64(bool zSign, uint64_t absZ0, uint64_t absZ1, return zSign ? INT64_MIN : INT64_MAX; } if (absZ1) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; @@ -3883,7 +3884,7 @@ static int64_t roundAndPackUint64(bool zSign, uint64_t absZ0, } if (absZ1) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return absZ0; } @@ -3994,7 +3995,7 @@ static float32 roundAndPackFloat32(bool zSign, int zExp, uint32_t zSig, } } if (roundBits) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig = ( zSig + roundIncrement )>>7; if (!(roundBits ^ 0x40) && roundNearestEven) { @@ -4150,7 +4151,7 @@ static float64 roundAndPackFloat64(bool zSign, int zExp, uint64_t zSig, } } if (roundBits) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig = ( zSig + roundIncrement )>>10; if (!(roundBits ^ 0x200) && roundNearestEven) { @@ -4284,7 +4285,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, float_raise(float_flag_underflow, status); } if (roundBits) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig0 += roundIncrement; if ( (int64_t) zSig0 < 0 ) zExp = 1; @@ -4297,7 +4298,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, } } if (roundBits) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } zSig0 += roundIncrement; if ( zSig0 < roundIncrement ) { @@ -4360,7 +4361,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, float_raise(float_flag_underflow, status); } if (zSig1) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } switch (roundingMode) { case float_round_nearest_even: @@ -4390,7 +4391,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, } } if (zSig1) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } if ( increment ) { ++zSig0; @@ -4667,7 +4668,7 @@ static float128 roundAndPackFloat128(bool zSign, int32_t zExp, } } if (zSig2) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } if ( increment ) { add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 ); @@ -5405,7 +5406,7 @@ int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *status) } else if ( aExp < 0x3FFF ) { if (aExp || aSig) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } @@ -5420,7 +5421,7 @@ int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *status) return aSign ? (int32_t) 0x80000000 : 0x7FFFFFFF; } if ( ( aSig<float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; @@ -5504,13 +5505,13 @@ int64_t floatx80_to_int64_round_to_zero(floatx80 a, float_status *status) } else if ( aExp < 0x3FFF ) { if (aExp | aSig) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } z = aSig>>( - shiftCount ); if ( (uint64_t) ( aSig<<( shiftCount & 63 ) ) ) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } if ( aSign ) z = - z; return z; @@ -5661,7 +5662,7 @@ floatx80 floatx80_round_to_int(floatx80 a, float_status *status) && ( (uint64_t) ( extractFloatx80Frac( a ) ) == 0 ) ) { return a; } - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); aSign = extractFloatx80Sign( a ); switch (status->float_rounding_mode) { case float_round_nearest_even: @@ -5728,7 +5729,7 @@ floatx80 floatx80_round_to_int(floatx80 a, float_status *status) z.low = UINT64_C(0x8000000000000000); } if (z.low != a.low) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; @@ -6364,7 +6365,7 @@ int32_t float128_to_int32_round_to_zero(float128 a, float_status *status) } else if ( aExp < 0x3FFF ) { if (aExp || aSig0) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } @@ -6380,7 +6381,7 @@ int32_t float128_to_int32_round_to_zero(float128 a, float_status *status) return aSign ? INT32_MIN : INT32_MAX; } if ( ( aSig0<float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; @@ -6458,7 +6459,7 @@ int64_t float128_to_int64_round_to_zero(float128 a, float_status *status) if ( ( a.high == UINT64_C(0xC03E000000000000) ) && ( aSig1 < UINT64_C(0x0002000000000000) ) ) { if (aSig1) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } } else { @@ -6471,20 +6472,20 @@ int64_t float128_to_int64_round_to_zero(float128 a, float_status *status) } z = ( aSig0<>( ( - shiftCount ) & 63 ) ); if ( (uint64_t) ( aSig1<float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } } else { if ( aExp < 0x3FFF ) { if ( aExp | aSig0 | aSig1 ) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return 0; } z = aSig0>>( - shiftCount ); if ( aSig1 || ( shiftCount && (uint64_t) ( aSig0<<( shiftCount & 63 ) ) ) ) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } } if ( aSign ) z = - z; @@ -6793,7 +6794,7 @@ float128 float128_round_to_int(float128 a, float_status *status) else { if ( aExp < 0x3FFF ) { if ( ( ( (uint64_t) ( a.high<<1 ) ) | a.low ) == 0 ) return a; - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); aSign = extractFloat128Sign( a ); switch (status->float_rounding_mode) { case float_round_nearest_even: @@ -6867,7 +6868,7 @@ float128 float128_round_to_int(float128 a, float_status *status) z.high &= ~ roundBitsMask; } if ( ( z.low != a.low ) || ( z.high != a.high ) ) { - status->float_exception_flags |= float_flag_inexact; + float_raise(float_flag_inexact, status); } return z; From patchwork Sat May 8 01:46:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432526 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp843630jao; Fri, 7 May 2021 18:55:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzO7Q22myzPioXY1dwvz3ZnVxmzrRnUZc+q1HATwreRgNSrngpDvHfJnq6E/nnxIXRggMmz X-Received: by 2002:a92:c952:: with SMTP id i18mr12145721ilq.218.1620438945471; Fri, 07 May 2021 18:55:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438945; cv=none; d=google.com; s=arc-20160816; b=Oe0QEDWeTXwK6btlEzwK6DQfSfubpxciu9WpoSd1O5s5ROuqKMPjjibP0PYFO8YzKU b1nmKfKtnwZSwgfbCFqKZv6K2k8gB+rvZSA8g8FMnNAv/CZAPtoudaX5adkbazyCLnXb 5No62kkhKTwmwaHBiOdm+14I48oJ8WCTzY94GAFGm5A6shwUCZ/D/kgZ066IXG8HKre0 n+DxnAKPMn0EsUcsXZiUzlkM19Gk4ENF3gom00ef/mftOih05nwsGlhBivS/mn+Fd5cO W/bRGs0N34G2PBJwFatIiRGlmFiz55L3sSRB8/AXcVe5ncwmOr3mJkcQaIdQSTsYUbO0 G2Ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZKeNDHnMG1Vsy9FW47wdnzGiSOuMJBBVUnKRaVqfH0g=; b=qaJUEs0tKXyqoAGZ64656VZWcDJD2hdKBDMUARqyH3Otes61TtdnOW+DmO6cG+10ux 9q1YQTWrg+lX44etZgoNySTToG6j6RkJWztafVvKst8PQkIO/7LkUhDn/Hp1sfS1r5md JjfJ0cvln0WoDDLBPLUht3cNbqgHqIurNo9h+tGfXLOZPmoJ6+ifG5LvMFHlgThQz5YB D/+iqWkCUt1YmNqm2oteK23vt74f04NBJbPPwfFtCzGFd7833ldSqJ5Q5Op5h/8YWQlU c5bmpQLhla7H+6SuWAeVb/Jao6c+5rXFr9lbwyhEHOjyPOs/+otXmCiyRovmMWP0h8Ku Kqjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="oO/gx93z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g2si7798605ilk.84.2021.05.07.18.55.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 18:55:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="oO/gx93z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCC0-0007Qf-Pm for patch@linaro.org; Fri, 07 May 2021 21:55:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40564) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC4k-00048Y-Lz for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:14 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:39454) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4h-0003Y6-CQ for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:14 -0400 Received: by mail-pg1-x531.google.com with SMTP id s22so8628767pgk.6 for ; Fri, 07 May 2021 18:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZKeNDHnMG1Vsy9FW47wdnzGiSOuMJBBVUnKRaVqfH0g=; b=oO/gx93zWnMzhrE1cdfAndYhjl8nz8nrizqkANgfOfpf2lx6E5OtgHHRzXaKX/YSqH fep+9IzrgiW4e+b9N7oDzxy/+XcYtAaAuFsDceUFL9o4po00+fvc4u7VX8nOnO4BFdkr jU2BgeMVW6ere6EkP0KB90wvehZ6/mdchGidUcDoc3ng6Ac83vHoh5/X0HrSoCl6WN3W rchcF4BdGEF8dqqsoKI+E06Yd78S0aZ0ZYIxJ8flqjxClVkqSRmoPgYZuOQX44kYwU6B Rm8zEuAWeuxHHW810Xu1x1+dknF5DbcHVDYtaIPocebUoqBxKA6JWaGCU9g47hWZwFIG STtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZKeNDHnMG1Vsy9FW47wdnzGiSOuMJBBVUnKRaVqfH0g=; b=Wq3U3wZSE4lxQhU5gtVadPnwzVH5K2t6fiBhjYcXpcih0/vlzZT59Q1sXXwETry23y Jz6qkSikrznGzkEwc3U/Lv/X9nxriTKzyZEO+d5eQ759uZFvPsFGf9J2Qs+aZvk7KYa6 4KSnCSTunuNfms1dBq+mrOXRMto8+W6NDXLPWpukRN8ogPDS6G9w+nWlHx/XEnPwwgCE OOf9ZaZJw9ZjJ7HPHUTdBI04PYxjnzu9cqvFiXDUW8SgVQaS78IPQTzxXLfamONPaZaS rlS6nxnWe7iZJmOR/bipfwwsLZD9+1Kr4m/ons74Bf3WYisYU2YXCEgYuZBiktYM95hA heVg== X-Gm-Message-State: AOAM533deju43w3wQ+6CUWG2y1xTFeNLAXcsSGRSFQ6WJragR8m+zs7I i5raAX1507U5rP9orMgYAivQqsImvjtFeQ== X-Received: by 2002:a05:6a00:168d:b029:23f:376d:a2f8 with SMTP id k13-20020a056a00168db029023f376da2f8mr13455495pfc.20.1620438489723; Fri, 07 May 2021 18:48:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/72] softfloat: Tidy a * b + inf return Date: Fri, 7 May 2021 18:46:59 -0700 Message-Id: <20210508014802.892561-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" No reason to set values in 'a', when we already have float_class_inf in 'c', and can flip that sign. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- fpu/softfloat.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 93fe785809..ee4b5073b6 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1384,9 +1384,8 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, float_raise(float_flag_invalid, s); return parts_default_nan(s); } else { - a.cls = float_class_inf; - a.sign = c.sign ^ sign_flip; - return a; + c.sign ^= sign_flip; + return c; } } From patchwork Sat May 8 01:47:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432520 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp841600jao; Fri, 7 May 2021 18:51:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjOJN9qVZkogAXd8BefekAj/uaJ7hl5HYpOIy9ShVx5Q2cIFI3ZKpSkJobxCKSo0gG7sEW X-Received: by 2002:a92:d80f:: with SMTP id y15mr11619721ilm.305.1620438691638; Fri, 07 May 2021 18:51:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438691; cv=none; d=google.com; s=arc-20160816; b=MaS3ezw7bXj447hHrawaLUTERM0oFdrbxTPIwzFPyB5ghEVyxKrM9k2McJS9AUMEkb p9is8ftKZVUYopUi0DDOCUly0g1sBzv9T5C1oV/CnnRhHErTOqAGICw9pkDSs7VtIDvi W/tHmLnOkxdM1fvoGTSX7mLvUY5VZqftJ51BL6Wnol4QVr0i7Kbptx3SZpw9a/FYnT50 u8vqHUVLJlK/tGrwvKrGBzolS00iEVJMEwklzhyX+a/n9WPJc92Ch8PvYbKqMeBCf4g4 V1qR/RedrqQ8wiACtW9vtzCy3pOpiSAeF832Gsl1HE1Erg2PjjFnLl2iVDdZA1P92uG1 jBkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=J2jECUv0KB/VRaKbNWjXBjsVAbH6ZqCf4a3f43XZat8=; b=tnE2U6FnnwSSTwelrmoEnmkK1rtZWuoXfI7XUEWHcBx6+SoJef1y2bQ0t9hh7DXiS+ WLM0rxPXUNsIoW2yjrgBGhIcnNCEibUJkUu2Q8VP1CiFKHUnFBo6glbQkFF/hHYgDRoA mcBzQjAr8PjBLjCFxJ20G/5lup/Cb27DgL3qi3kGBZaGp8FIL3AscfUSFPzhOmvJCbbX +oSN1B2gzaKj6mviTPDpdg95S38yO+U7i7SCv/mZ3/LDbzHj4FLxigOGTA+8U7DQWOpy kV3oTE85+2zb2zME3ZxcfAvoNjaj71PLecUQO9jRmdrBi6yjggmmva9h2hdgEBgUCE8C iH8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gshKE4ND; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y13si5107833ilu.37.2021.05.07.18.51.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 18:51:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gshKE4ND; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfC7v-0001fJ-42 for patch@linaro.org; Fri, 07 May 2021 21:51:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC4l-0004A5-Ff for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:15 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:47063) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4h-0003YO-Lw for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:15 -0400 Received: by mail-pf1-x42b.google.com with SMTP id q2so9076801pfh.13 for ; Fri, 07 May 2021 18:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J2jECUv0KB/VRaKbNWjXBjsVAbH6ZqCf4a3f43XZat8=; b=gshKE4ND++11vkoO3VO4AgFOqNGFofzNHQ+eBPT5aS0Tly5wzIwj/xtgl218eHWG3w iCPH2HlwiE6pf2TRAmxJEZB6V01CkGtcbHrbACRt3dAyLVDPYkkIrcomLox08xtvgKZ9 UNJ8k97EzzGJvCpR2LEk2fK7QTix/PB/mWTXkrGwOG8FV4BPXSGKNwOuMrgJwqeucEO7 C10n33fv6kdrkt6UsvedUXGv1iREIOL8EeVSBrjbpWFF0ivoXCvY2aZtqCqhaUbn4GTc Z4m5hz17LEmaGg5QDRBYQt6W4xPJV8C1/aix2PAOxV5UCOA3d8m4MJ0gP6u1ZerJ2sD7 9TiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J2jECUv0KB/VRaKbNWjXBjsVAbH6ZqCf4a3f43XZat8=; b=pbu0/+miB81BzzOGdTEQmSBJCBDZTEoR5dHIxx3sW8Phcz2Zk7Hfki6FzuKQLBNlV3 ipnn7TWqAx9eJIOXlUSYjkSz9aqK38CloXUuCBHYPdoSgEnnOWIvSmi8lycHQOg6Vp75 yKynBjewhB3OlskHseoOIBC5rOW9mUnJLNVf2494AzocwGUl/B9baCr3bJ9KEaaL9Jab 1UTdXRbccMsxgs9tRdBZ6/cnNjmCZiDBGy3qMY1uzjUUN4TiXZfwdy4OuH4uKp3FSNIN 2W9CQdy/MkXK8tbDDnJ6S1wtf4SyqeLxjPXEerRLzSaxe1QK+jIi6UksDsnwI5Zo0hpz VDjQ== X-Gm-Message-State: AOAM532Lm3Gi1qV+yFiWBedQ6Akm3ryZ9s8p33hxy/uvWM403fMvmSJ9 5PWEG7T2QpOW+PNmxYxmufwVfN4L+tPioA== X-Received: by 2002:a63:4c26:: with SMTP id z38mr13542949pga.415.1620438490406; Fri, 07 May 2021 18:48:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/72] softfloat: Add float_cmask and constants Date: Fri, 7 May 2021 18:47:00 -0700 Message-Id: <20210508014802.892561-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Testing more than one class at a time is better done with masks. This reduces the static branch count. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- fpu/softfloat.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ee4b5073b6..64edb23793 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -469,6 +469,20 @@ typedef enum __attribute__ ((__packed__)) { float_class_snan, } FloatClass; +#define float_cmask(bit) (1u << (bit)) + +enum { + float_cmask_zero = float_cmask(float_class_zero), + float_cmask_normal = float_cmask(float_class_normal), + float_cmask_inf = float_cmask(float_class_inf), + float_cmask_qnan = float_cmask(float_class_qnan), + float_cmask_snan = float_cmask(float_class_snan), + + float_cmask_infzero = float_cmask_zero | float_cmask_inf, + float_cmask_anynan = float_cmask_qnan | float_cmask_snan, +}; + + /* Simple helpers for checking if, or what kind of, NaN we have */ static inline __attribute__((unused)) bool is_nan(FloatClass c) { @@ -1338,26 +1352,28 @@ bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, int flags, float_status *s) { - bool inf_zero = ((1 << a.cls) | (1 << b.cls)) == - ((1 << float_class_inf) | (1 << float_class_zero)); - bool p_sign; + bool inf_zero, p_sign; bool sign_flip = flags & float_muladd_negate_result; FloatClass p_class; uint64_t hi, lo; int p_exp; + int ab_mask, abc_mask; + + ab_mask = float_cmask(a.cls) | float_cmask(b.cls); + abc_mask = float_cmask(c.cls) | ab_mask; + inf_zero = ab_mask == float_cmask_infzero; /* It is implementation-defined whether the cases of (0,inf,qnan) * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN * they return if they do), so we have to hand this information * off to the target-specific pick-a-NaN routine. */ - if (is_nan(a.cls) || is_nan(b.cls) || is_nan(c.cls)) { + if (unlikely(abc_mask & float_cmask_anynan)) { return pick_nan_muladd(a, b, c, inf_zero, s); } if (inf_zero) { float_raise(float_flag_invalid, s); - s->float_exception_flags |= float_flag_invalid; return parts_default_nan(s); } @@ -1371,9 +1387,9 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, p_sign ^= 1; } - if (a.cls == float_class_inf || b.cls == float_class_inf) { + if (ab_mask & float_cmask_inf) { p_class = float_class_inf; - } else if (a.cls == float_class_zero || b.cls == float_class_zero) { + } else if (ab_mask & float_cmask_zero) { p_class = float_class_zero; } else { p_class = float_class_normal; From patchwork Sat May 8 01:47:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432530 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp845615jao; Fri, 7 May 2021 18:59:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJMQ/LmfzQgEyKZ9IAD2Ad5g+Zo2FpiR7v8UN45e9BbALWTEzc4Q1LFx72b/u4CxMHX39l X-Received: by 2002:a05:6602:25c1:: with SMTP id d1mr7337545iop.182.1620439155205; Fri, 07 May 2021 18:59:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439155; cv=none; d=google.com; s=arc-20160816; b=eKptChX196WdcwZxqBbf8XI8vvkijlPKzkd6nY0FZ+yKJyH20F5dObHy64zhX4MG4U N94dUwqUlB6ReshKbHaiZ/eTeMNJLqfurfrDgQ9ACpZHPlW9xS9O/JdMM8dqB08HO6ii CJOszOrMDKEPqI5qqttTa6/o+ubeVUWgQdSeOC6kr0rGR5UQjgq0Jdrq5y3qvQ7577PL lp/U6SDyYplpGXmmNY1VrKVQLFR1jshMIC4Mi2gtGduGXB13Npq12fBpGjXzufQFtiny prIR12OsEbmkNejiAsGhvSjytlOBtTHa9ntbb9RJ0pv2r6606XBWTj0ycTZ+Po54T//O ZcJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6bhXtvo5B12zNIaDrjXDyWAVuDsp1zJyuk3Qd7d0A8g=; b=c/uzVR6NlwtLRV62PY6gXw6YX/8ybejHCoXcf8qTlIKalArXFmpsdcXGj2vdH8UlrI mx5QRXdM1z4rQGM/c4Y6I6kBFLtrbhgazagj9f7dlOLBy2em1xeAJGlL9dXxYQ5SP07m uYEYYB+uocxL3fqmTSUp+3CPepxsP0bZlKCt1JSlLSwBs0vwA9duxJo+qbIAqQmhPnso AP/YJSn1dShyLhdzpwSyPmJkjXWn+LDx4qsA9LVOLof01x7nKsKjuJMIE8SwREg5ofJi zc5+u5gU93QLWvafHO3tN9pXmpnwz/CjuNAmEFgH3BNmRRNhGAmxzozAJSZNuPAcNaWN UXpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GUM1XZJt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/72] softfloat: Use return_nan in float_to_float Date: Fri, 7 May 2021 18:47:01 -0700 Message-Id: <20210508014802.892561-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 64edb23793..b694e38522 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1931,13 +1931,7 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, break; } } else if (is_nan(a.cls)) { - if (is_snan(a.cls)) { - float_raise(float_flag_invalid, s); - a = parts_silence_nan(a, s); - } - if (s->default_nan_mode) { - return parts_default_nan(s); - } + return return_nan(a, s); } return a; } From patchwork Sat May 8 01:47:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432534 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp848282jao; Fri, 7 May 2021 19:03:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyB+zfER+2qZnKlIdJcaHv7yiyod0csWJmVC/SdSsvDabBHcpIWFKX4OaiI9q5AjI8PwC5t X-Received: by 2002:ac8:44b8:: with SMTP id a24mr3306815qto.195.1620439410293; Fri, 07 May 2021 19:03:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439410; cv=none; d=google.com; s=arc-20160816; b=Ji+4NlTATlDPdTVvCyWIgEEh7qyz0MPI2Zyg4GGNqnRnxNZXUz8MLn5q5lhy6B3h48 ttb704HVQwdSYZiR4UJn6Re+X09DhYAZi3WSKjceoiOnobftea1UI39pAisfxNylSYP4 +XUzxNRO3A59ZrXHTI9roEmFaBY+yWfd4TxQ0265N3b4CELYACveYQMR2y4PA4b0zLqp c2OCz5GVSXDomfkwJtj5MOUq37hAuWQg42aWfppZn7fEZp3zq93UeDNXPNq7eyDVsDHs zev5kv1GVwHGfKXlvchJyVN2IrGom8BxyDMCXMAo1JOgYCqvbtiJnzl3kKxxtcx565TT R1BA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id g14si2603458qtx.28.2021.05.07.19.03.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:03:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b73ETn1l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCJV-00021t-Ku for patch@linaro.org; Fri, 07 May 2021 22:03:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC4o-0004BJ-WC for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:22 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:54055) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4i-0003Yq-Oa for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:18 -0400 Received: by mail-pj1-x102f.google.com with SMTP id p17so6206406pjz.3 for ; Fri, 07 May 2021 18:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZkAPsJpFKYLwHKnqQJYxgfiNUgUoOxofSZa6fTNKj+E=; b=b73ETn1ljStaXoeH3oWYISHItx2sRYf/rAzjBU7RxjwJsWFc3O4g+GInCiFUHSdXFX zbEo6aO1xr7kzVmDp/1DSH56L0cIT2DKE1GbDzjk5Hq3LWizAc0XdrL9+lxzS/pZYG8w reuhKe5o8Z9NGj1XL4GVaEClMeaYcVOG5LLYQFQ1Gc+gjJ92eqNjkDtnEmB9dAFRUqaE EL2ZGieARAS5O4EdMqXVvVzQSjhQHo6IjZTfIRiHQgFecL2IMQcZR4vKphCBzy4qAB3r DkpbbHi+pn18A2uM+3dnMQB1GBvl0IirtWHyWBWyxGKe0PgWqCkEUCCqDoZATWrRTBFR nC8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZkAPsJpFKYLwHKnqQJYxgfiNUgUoOxofSZa6fTNKj+E=; b=rFR+MGd8Ik9mPfIl7GYXmKL5WGN1R7wx5GTAkDNzB+5rARJytBwZODINH0nfwiizUc vEMLaBLtP9ZV/+hqXLCYgZ9PxgvmpPcsJIQYwQt5ANutc4BaZi0k85ebEuBUGzJHqxoI ds5VqUqsQQQDo/GIgwcscPphMZ6N17N+XxY68vO6JCT4lnkjKKpsfHVWCrDQ1YVPtCyH 7Km2amcYukrsJLFsrPAvhkMHdNENEVmIpb7PczgGqwRecHBuF0RFqCZ/tYfPRJKZDR3g dFv55GXG1FOWlIjJvPPEvVkOtAHFj5O6hWvqUBGjRiniG3lY8c62T8PW2ZxF/nAaLZ5f zLyw== X-Gm-Message-State: AOAM530ZBry6/WwuX91fugxGG245yDzD/nXKeMD7xR80/19p3OkbNLjM vnDb8ZGD6V0MSDjoyZk4m6+X3RAurguB7w== X-Received: by 2002:a17:90a:1c02:: with SMTP id s2mr13256859pjs.17.1620438491557; Fri, 07 May 2021 18:48:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/72] softfloat: fix return_nan vs default_nan_mode Date: Fri, 7 May 2021 18:47:02 -0700 Message-Id: <20210508014802.892561-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not call parts_silence_nan when default_nan_mode is in effect. This will avoid an assert in a later patch. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b694e38522..6589f00b23 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -892,21 +892,16 @@ static float64 float64_round_pack_canonical(FloatParts p, float_status *s) static FloatParts return_nan(FloatParts a, float_status *s) { - switch (a.cls) { - case float_class_snan: + g_assert(is_nan(a.cls)); + if (is_snan(a.cls)) { float_raise(float_flag_invalid, s); - a = parts_silence_nan(a, s); - /* fall through */ - case float_class_qnan: - if (s->default_nan_mode) { - return parts_default_nan(s); + if (!s->default_nan_mode) { + return parts_silence_nan(a, s); } - break; - - default: - g_assert_not_reached(); + } else if (!s->default_nan_mode) { + return a; } - return a; + return parts_default_nan(s); } static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) From patchwork Sat May 8 01:47:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432541 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp850710jao; Fri, 7 May 2021 19:08:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzoQ74P2OZouYIYjxw6ZTaRD1/vqwA+AT88yyxPOTnbClmZWAdeGRoAGFJ8HKTGaixk2LVg X-Received: by 2002:a6b:d213:: with SMTP id q19mr9760823iob.203.1620439681450; Fri, 07 May 2021 19:08:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439681; cv=none; d=google.com; s=arc-20160816; b=cAMlNtOz8GFfHLjelwl3bP86QNSBs3I594UXKE97Qz6c/rn64dtTYFUfdejrfeznwp XxeH7G4mej45zbqqNFjee1/3vIFJKz/2867IPfCJyybE3zLhvKHWbYa5BjD+m/V6L6K+ jcoqpF0NjVYeFdv97wQKaVe1JMe7yvGlyw4j4Nig0dJivMX12YIvu9O76ODOg5khtEfV u+1IzUqefSv0ikIvZKirp7S8LqBD9u1EfivwHeqplx2qsMEf7DCZ9cobrEelmjZUjhxr Q8IC1jb45T7CzL7ydjD3yY080I8445NpM0wl1ynY21Vg4pklPQTv/mfHYB0mz+LJDjag eL7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MiCAsnwsyr5jz7kk+vBhCEvkm3DwoUGr8DX9RFGFP2o=; b=RtRWXVmHCaEEMUKNHOfMkwL/Ryw5Eur3NjOtdTg81y/a4W74B42kmKHOYn+SSFLnRe 5orJZkbrVKPh+inFpOx40mJX6M6gvqdYaEoPYlQZDUKXI4BdwGee59fN1F2m14UrzV2p U+6xHu1ynFm+NhERIR8M2LCz4nN4P7S6d+ZVHIhApNpwVRCYfYIN/Q2ycbXiwsVhsIWm z8xWfYlx67+619NkOUdNaSTEdMZuFvJ+Se297wCYu6QbUPo2MFdrzLS3JZ+6f04wKHNg k8DdFEKG08Fg42BzSpN14AZFRyDrpo4cRmZTAtTjPy1bGAKdZts3bs1L2VK8DvHYWSzK tlEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uVG5rDFZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d12si3341718ioi.7.2021.05.07.19.08.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:08:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uVG5rDFZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCNs-00059c-TI for patch@linaro.org; Fri, 07 May 2021 22:08:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40746) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC4x-0004Ch-6T for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:28 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:38543) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4j-0003a9-FN for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:24 -0400 Received: by mail-pg1-x529.google.com with SMTP id i14so8638823pgk.5 for ; Fri, 07 May 2021 18:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MiCAsnwsyr5jz7kk+vBhCEvkm3DwoUGr8DX9RFGFP2o=; b=uVG5rDFZT9+qZpClEs74s87kBgMFSSZfl/I4V0itU+4bsTWqr6Y6Emgna2h9Wf/Zf4 uTyxhSiQY5P0zjS8kaedSIwSaMXC1N/hba7C44Q1GqFMHOYsHf+tvKC/GrBnmeCBMPIL 94AOVFW6P8stGtFOUaKwwSmqtG89kC4e5JGz6+dtW1fT6jp6d//Ob3s/tsO5nDRqsN1b g0wNFb7ElbikAkqxCTrjwMM9NmES+OM27LWsFFj3VHzH9MVKK/GjKeYGkLmSHjqkRx5p oWnzLVYY+sMcuoSSQPUCvAF+MuOBymKm6D9eOd2/Qm3h6AhrbkidE17KnG42B2TMXRwj xE7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MiCAsnwsyr5jz7kk+vBhCEvkm3DwoUGr8DX9RFGFP2o=; b=oHsDHD4SbrDPc8JMf61MZoFfL0Nyp+Z6PVZH3SgaoVPip7/47kTfA4f7ggyd8ZDolE Nz9f5/92WHR2VL5VGZLdLxplxbwxqCNG12VQtJ2ZasD9zXTv7TUzXI1si64GRscN1CU6 QMzoxWDwmCOtXg0/UGyEGdk3BO/pakQbZ360QVTXUBITxgqe+0CuXUVwCB7Dnv2690LO 0/PByqoODEDhrpGZxQqzCQbYPOj/aD/p7wD43wTcvuRiX9IQ9e0Xb7UItzPTURWisSjJ 4kRPr42B9zFF1kK7aF7FJh4jvsc40KDFJv49flEVdlwJI1KgAzHXgXjH/I0C8zLeIrLl Zq8g== X-Gm-Message-State: AOAM530HTz7OYsAa4CT+4ggyzkpgQ/DF/eetmAvP0YeoT8ujrqXtbHoN coqQSS+/C1epnOU9KJcECWqRohADkHbJ2g== X-Received: by 2002:a63:d710:: with SMTP id d16mr13190101pgg.214.1620438492139; Fri, 07 May 2021 18:48:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/72] target/mips: Set set_default_nan_mode with set_snan_bit_is_one Date: Fri, 7 May 2021 18:47:03 -0700 Message-Id: <20210508014802.892561-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This behavior is currently hard-coded in parts_silence_nan, but setting this bit properly will allow this to be cleaned up. Signed-off-by: Richard Henderson --- target/mips/fpu_helper.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 1c2d6d35a7..ad1116e8c1 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -27,8 +27,14 @@ static inline void restore_flush_mode(CPUMIPSState *env) static inline void restore_snan_bit_mode(CPUMIPSState *env) { - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, - &env->active_fpu.fp_status); + bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); + + /* + * With nan2008, SNaNs are silenced in the usual way. + * Before that, SNaNs are not silenced; default nans are produced. + */ + set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); + set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); } static inline void restore_fp_status(CPUMIPSState *env) From patchwork Sat May 8 01:47:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432524 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp843138jao; Fri, 7 May 2021 18:54:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzM0LXTP2YQcXHLwcZGlY9doa5Tey3YCzZS6uvd/PVL0zuTmvTkaG2gdwDK78g3erjsXvPK X-Received: by 2002:a05:6638:2591:: with SMTP id s17mr11247135jat.87.1620438883915; Fri, 07 May 2021 18:54:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438883; cv=none; d=google.com; s=arc-20160816; b=J4Aji9sBseVbsPMLgqbV6AkTFSiL2TKzUrSR+0jUuYCm521MSlKRiFdCZLwjIsvxhO cLZ+it/WHHLicxmHst7ckQdJgBp6vu+qgokDhU/k/BXnll520nR4aaLSGDl/gw8PUN7U k6ePcGLNMexJ2lrB9De4ybh8jpbn/1+yr5kncJHGCLSv+2oP1VvgKoXcttR8czPkxNj0 UFgZ4ddBN+45aB65sNpcrxYIwy+uaC2AoCKYIxE/JIUKQzDknwkzNpZRDo2XkXakV7CO 40kqJQcvHsLXxY1fflQQQlm8rL99tlq2VaHkZ5WCgecUb+av0GBoEanlDtQFYa9pjxOn Q7Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1XFPaqmhZZujk8i6xDVlzhC8z+OKd1ONOKE68PwhM5k=; b=JaPzjWVqr5GGXiMRIlIqMA8+/hb9ubU7ajJOKbivJBh2PDG+of1iGgTN7cFlYPPtGi xVwKJ4BiFZk4nBdtiixLrYspbRiuVhHJbGQFLN2ps8TasAQnuwcto/LLRmOfPBKqmGeR ZPGzAX3dzNSBCHuJ35D2gWSPb2AstsBZqZowpLdTvQnd+zIeRHsPKJwzrcj1tx+xjCsh VPAZkc24FP8SHU5ZTVJct6oB+DivM4mykf0oErjH8M9c7OINwO/Ocy6NefaWXFOWKuCT qKIMBPgIennyDLuEel37dKnjzBKcok6725lf5Rlt0PtVeDfpHmBUY5P9hS4Babi/iTez lIJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pHgCeEDU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand Reviewed-by: Alex Bennée diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 487b29155c..5988830c16 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -180,16 +180,15 @@ static FloatParts parts_default_nan(float_status *status) static FloatParts parts_silence_nan(FloatParts a, float_status *status) { g_assert(!no_signaling_nans(status)); -#if defined(TARGET_HPPA) - a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); - a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); -#else + g_assert(!status->default_nan_mode); + + /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ if (snan_bit_is_one(status)) { - return parts_default_nan(status); + a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); } else { a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); } -#endif a.cls = float_class_qnan; return a; } From patchwork Sat May 8 01:47:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432537 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp849091jao; Fri, 7 May 2021 19:04:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzE1bq/0GgzLdwOXSsMqhEIiJg7ecZB7OSLcjkgeDVUuJSePDItZLBM0Y3ajjWlVhGlrjcI X-Received: by 2002:ac8:5806:: with SMTP id g6mr12533090qtg.152.1620439499728; Fri, 07 May 2021 19:04:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439499; cv=none; d=google.com; s=arc-20160816; b=k6W7Q31XW8ZuZle6kQ+F3ZjLTTeBVIHOa2PNKZRfXppF50G4zIw2Cnyekwp1TAIMTz ryrJuP2jVYT3+6N02K5x9EOaK2AvKS/Z68u4AVK+ogmqJsdoxjCpndiiVRmtPD8BaTtA rsk2egklrSuOF3quFUi1XzdsxlOHxYkgzaDBut4oaZ6qQHuG/uaRJmPeCu6eapBFjeqZ bCTIsWxiKC73NX4vlFbFgQwzFkoi9/zqeCyMlXrZmFP6kVaZ0HBJeS9sNaa6ZYIG2Kad EH89riioGtK4T4jW8TvqJ9pnVJAW9uy4qYY8y+4UFuw7947odTPuv9BocSaFWvoSFIZ1 7GaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CTft5gBrUD6MnXZkZyjYyUchTRH6b2xyA6TvzbAPqzc=; b=yT8If3j4Zf2xJTCxzW+SF10tVrQQEfCa1blPj5D3wm0kve0JDSinS6Azzwo5cvMeml L9WJMHjvg2UA7LqYFBJAuiTXsE/3Kh+EvyfnLKJH4LHq0Nx0xQelUGWmIVznhBdyVWAg 8VGTjWhjAPrYsac9VLOBjHry9ABCFbfVDGIZrzvb3vAP6CVubOebkBoo74C9SDXt4RhI uzNlg4qlFNC7qbjO4Pasguiq/cFZ6oBY7fpLqeqbmFdRVM/kSdF2E0SspYEm1K/kCs+t O8Qbt3bHzS07dnl3p8o+Fsg3m4M6yd0fQyjGlsTiw3LIis/ef0rKDHbIzW5g+x1ySGUA r80g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=u21InNkF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:48:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/72] softfloat: Rename FloatParts to FloatParts64 Date: Fri, 7 May 2021 18:47:05 -0700 Message-Id: <20210508014802.892561-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 362 ++++++++++++++++----------------- fpu/softfloat-specialize.c.inc | 6 +- 2 files changed, 184 insertions(+), 184 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6589f00b23..27b51659c9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -515,7 +515,7 @@ typedef struct { int32_t exp; FloatClass cls; bool sign; -} FloatParts; +} FloatParts64; #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) @@ -580,11 +580,11 @@ static const FloatFmt float64_params = { }; /* Unpack a float to parts, but do not canonicalize. */ -static inline FloatParts unpack_raw(FloatFmt fmt, uint64_t raw) +static inline FloatParts64 unpack_raw(FloatFmt fmt, uint64_t raw) { const int sign_pos = fmt.frac_size + fmt.exp_size; - return (FloatParts) { + return (FloatParts64) { .cls = float_class_unclassified, .sign = extract64(raw, sign_pos, 1), .exp = extract64(raw, fmt.frac_size, fmt.exp_size), @@ -592,50 +592,50 @@ static inline FloatParts unpack_raw(FloatFmt fmt, uint64_t raw) }; } -static inline FloatParts float16_unpack_raw(float16 f) +static inline FloatParts64 float16_unpack_raw(float16 f) { return unpack_raw(float16_params, f); } -static inline FloatParts bfloat16_unpack_raw(bfloat16 f) +static inline FloatParts64 bfloat16_unpack_raw(bfloat16 f) { return unpack_raw(bfloat16_params, f); } -static inline FloatParts float32_unpack_raw(float32 f) +static inline FloatParts64 float32_unpack_raw(float32 f) { return unpack_raw(float32_params, f); } -static inline FloatParts float64_unpack_raw(float64 f) +static inline FloatParts64 float64_unpack_raw(float64 f) { return unpack_raw(float64_params, f); } /* Pack a float from parts, but do not canonicalize. */ -static inline uint64_t pack_raw(FloatFmt fmt, FloatParts p) +static inline uint64_t pack_raw(FloatFmt fmt, FloatParts64 p) { const int sign_pos = fmt.frac_size + fmt.exp_size; uint64_t ret = deposit64(p.frac, fmt.frac_size, fmt.exp_size, p.exp); return deposit64(ret, sign_pos, 1, p.sign); } -static inline float16 float16_pack_raw(FloatParts p) +static inline float16 float16_pack_raw(FloatParts64 p) { return make_float16(pack_raw(float16_params, p)); } -static inline bfloat16 bfloat16_pack_raw(FloatParts p) +static inline bfloat16 bfloat16_pack_raw(FloatParts64 p) { return pack_raw(bfloat16_params, p); } -static inline float32 float32_pack_raw(FloatParts p) +static inline float32 float32_pack_raw(FloatParts64 p) { return make_float32(pack_raw(float32_params, p)); } -static inline float64 float64_pack_raw(FloatParts p) +static inline float64 float64_pack_raw(FloatParts64 p) { return make_float64(pack_raw(float64_params, p)); } @@ -651,7 +651,7 @@ static inline float64 float64_pack_raw(FloatParts p) #include "softfloat-specialize.c.inc" /* Canonicalize EXP and FRAC, setting CLS. */ -static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm, +static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm, float_status *status) { if (part.exp == parm->exp_max && !parm->arm_althp) { @@ -689,7 +689,7 @@ static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm, * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. */ -static FloatParts round_canonical(FloatParts p, float_status *s, +static FloatParts64 round_canonical(FloatParts64 p, float_status *s, const FloatFmt *parm) { const uint64_t frac_lsb = parm->frac_lsb; @@ -838,59 +838,59 @@ static FloatParts round_canonical(FloatParts p, float_status *s, } /* Explicit FloatFmt version */ -static FloatParts float16a_unpack_canonical(float16 f, float_status *s, +static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, const FloatFmt *params) { return sf_canonicalize(float16_unpack_raw(f), params, s); } -static FloatParts float16_unpack_canonical(float16 f, float_status *s) +static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) { return float16a_unpack_canonical(f, s, &float16_params); } -static FloatParts bfloat16_unpack_canonical(bfloat16 f, float_status *s) +static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) { return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); } -static float16 float16a_round_pack_canonical(FloatParts p, float_status *s, +static float16 float16a_round_pack_canonical(FloatParts64 p, float_status *s, const FloatFmt *params) { return float16_pack_raw(round_canonical(p, s, params)); } -static float16 float16_round_pack_canonical(FloatParts p, float_status *s) +static float16 float16_round_pack_canonical(FloatParts64 p, float_status *s) { return float16a_round_pack_canonical(p, s, &float16_params); } -static bfloat16 bfloat16_round_pack_canonical(FloatParts p, float_status *s) +static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status *s) { return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); } -static FloatParts float32_unpack_canonical(float32 f, float_status *s) +static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) { return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); } -static float32 float32_round_pack_canonical(FloatParts p, float_status *s) +static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) { return float32_pack_raw(round_canonical(p, s, &float32_params)); } -static FloatParts float64_unpack_canonical(float64 f, float_status *s) +static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) { return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); } -static float64 float64_round_pack_canonical(FloatParts p, float_status *s) +static float64 float64_round_pack_canonical(FloatParts64 p, float_status *s) { return float64_pack_raw(round_canonical(p, s, &float64_params)); } -static FloatParts return_nan(FloatParts a, float_status *s) +static FloatParts64 return_nan(FloatParts64 a, float_status *s) { g_assert(is_nan(a.cls)); if (is_snan(a.cls)) { @@ -904,7 +904,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) return parts_default_nan(s); } -static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) +static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { float_raise(float_flag_invalid, s); @@ -925,7 +925,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) return a; } -static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, +static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 c, bool inf_zero, float_status *s) { int which; @@ -971,7 +971,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, * Arithmetic. */ -static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, +static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract, float_status *s) { bool a_sign = a.sign; @@ -1062,18 +1062,18 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *status) { - FloatParts pa = float16_unpack_canonical(a, status); - FloatParts pb = float16_unpack_canonical(b, status); - FloatParts pr = addsub_floats(pa, pb, false, status); + FloatParts64 pa = float16_unpack_canonical(a, status); + FloatParts64 pb = float16_unpack_canonical(b, status); + FloatParts64 pr = addsub_floats(pa, pb, false, status); return float16_round_pack_canonical(pr, status); } float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status) { - FloatParts pa = float16_unpack_canonical(a, status); - FloatParts pb = float16_unpack_canonical(b, status); - FloatParts pr = addsub_floats(pa, pb, true, status); + FloatParts64 pa = float16_unpack_canonical(a, status); + FloatParts64 pb = float16_unpack_canonical(b, status); + FloatParts64 pr = addsub_floats(pa, pb, true, status); return float16_round_pack_canonical(pr, status); } @@ -1081,9 +1081,9 @@ float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) { - FloatParts pa = float32_unpack_canonical(a, status); - FloatParts pb = float32_unpack_canonical(b, status); - FloatParts pr = addsub_floats(pa, pb, subtract, status); + FloatParts64 pa = float32_unpack_canonical(a, status); + FloatParts64 pb = float32_unpack_canonical(b, status); + FloatParts64 pr = addsub_floats(pa, pb, subtract, status); return float32_round_pack_canonical(pr, status); } @@ -1101,9 +1101,9 @@ static inline float32 soft_f32_sub(float32 a, float32 b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) { - FloatParts pa = float64_unpack_canonical(a, status); - FloatParts pb = float64_unpack_canonical(b, status); - FloatParts pr = addsub_floats(pa, pb, subtract, status); + FloatParts64 pa = float64_unpack_canonical(a, status); + FloatParts64 pb = float64_unpack_canonical(b, status); + FloatParts64 pr = addsub_floats(pa, pb, subtract, status); return float64_round_pack_canonical(pr, status); } @@ -1199,18 +1199,18 @@ float64_sub(float64 a, float64 b, float_status *s) */ bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts pa = bfloat16_unpack_canonical(a, status); - FloatParts pb = bfloat16_unpack_canonical(b, status); - FloatParts pr = addsub_floats(pa, pb, false, status); + FloatParts64 pa = bfloat16_unpack_canonical(a, status); + FloatParts64 pb = bfloat16_unpack_canonical(b, status); + FloatParts64 pr = addsub_floats(pa, pb, false, status); return bfloat16_round_pack_canonical(pr, status); } bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts pa = bfloat16_unpack_canonical(a, status); - FloatParts pb = bfloat16_unpack_canonical(b, status); - FloatParts pr = addsub_floats(pa, pb, true, status); + FloatParts64 pa = bfloat16_unpack_canonical(a, status); + FloatParts64 pb = bfloat16_unpack_canonical(b, status); + FloatParts64 pr = addsub_floats(pa, pb, true, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1221,7 +1221,7 @@ bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) * for Binary Floating-Point Arithmetic. */ -static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) +static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s) { bool sign = a.sign ^ b.sign; @@ -1267,9 +1267,9 @@ static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status) { - FloatParts pa = float16_unpack_canonical(a, status); - FloatParts pb = float16_unpack_canonical(b, status); - FloatParts pr = mul_floats(pa, pb, status); + FloatParts64 pa = float16_unpack_canonical(a, status); + FloatParts64 pb = float16_unpack_canonical(b, status); + FloatParts64 pr = mul_floats(pa, pb, status); return float16_round_pack_canonical(pr, status); } @@ -1277,9 +1277,9 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_mul(float32 a, float32 b, float_status *status) { - FloatParts pa = float32_unpack_canonical(a, status); - FloatParts pb = float32_unpack_canonical(b, status); - FloatParts pr = mul_floats(pa, pb, status); + FloatParts64 pa = float32_unpack_canonical(a, status); + FloatParts64 pb = float32_unpack_canonical(b, status); + FloatParts64 pr = mul_floats(pa, pb, status); return float32_round_pack_canonical(pr, status); } @@ -1287,9 +1287,9 @@ soft_f32_mul(float32 a, float32 b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_mul(float64 a, float64 b, float_status *status) { - FloatParts pa = float64_unpack_canonical(a, status); - FloatParts pb = float64_unpack_canonical(b, status); - FloatParts pr = mul_floats(pa, pb, status); + FloatParts64 pa = float64_unpack_canonical(a, status); + FloatParts64 pb = float64_unpack_canonical(b, status); + FloatParts64 pr = mul_floats(pa, pb, status); return float64_round_pack_canonical(pr, status); } @@ -1325,9 +1325,9 @@ float64_mul(float64 a, float64 b, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts pa = bfloat16_unpack_canonical(a, status); - FloatParts pb = bfloat16_unpack_canonical(b, status); - FloatParts pr = mul_floats(pa, pb, status); + FloatParts64 pa = bfloat16_unpack_canonical(a, status); + FloatParts64 pb = bfloat16_unpack_canonical(b, status); + FloatParts64 pr = mul_floats(pa, pb, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1344,7 +1344,7 @@ bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) * NaNs.) */ -static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, +static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c, int flags, float_status *s) { bool inf_zero, p_sign; @@ -1520,10 +1520,10 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, int flags, float_status *status) { - FloatParts pa = float16_unpack_canonical(a, status); - FloatParts pb = float16_unpack_canonical(b, status); - FloatParts pc = float16_unpack_canonical(c, status); - FloatParts pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa = float16_unpack_canonical(a, status); + FloatParts64 pb = float16_unpack_canonical(b, status); + FloatParts64 pc = float16_unpack_canonical(c, status); + FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); return float16_round_pack_canonical(pr, status); } @@ -1532,10 +1532,10 @@ static float32 QEMU_SOFTFLOAT_ATTR soft_f32_muladd(float32 a, float32 b, float32 c, int flags, float_status *status) { - FloatParts pa = float32_unpack_canonical(a, status); - FloatParts pb = float32_unpack_canonical(b, status); - FloatParts pc = float32_unpack_canonical(c, status); - FloatParts pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa = float32_unpack_canonical(a, status); + FloatParts64 pb = float32_unpack_canonical(b, status); + FloatParts64 pc = float32_unpack_canonical(c, status); + FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); return float32_round_pack_canonical(pr, status); } @@ -1544,10 +1544,10 @@ static float64 QEMU_SOFTFLOAT_ATTR soft_f64_muladd(float64 a, float64 b, float64 c, int flags, float_status *status) { - FloatParts pa = float64_unpack_canonical(a, status); - FloatParts pb = float64_unpack_canonical(b, status); - FloatParts pc = float64_unpack_canonical(c, status); - FloatParts pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa = float64_unpack_canonical(a, status); + FloatParts64 pb = float64_unpack_canonical(b, status); + FloatParts64 pc = float64_unpack_canonical(c, status); + FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); return float64_round_pack_canonical(pr, status); } @@ -1705,10 +1705,10 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { - FloatParts pa = bfloat16_unpack_canonical(a, status); - FloatParts pb = bfloat16_unpack_canonical(b, status); - FloatParts pc = bfloat16_unpack_canonical(c, status); - FloatParts pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa = bfloat16_unpack_canonical(a, status); + FloatParts64 pb = bfloat16_unpack_canonical(b, status); + FloatParts64 pc = bfloat16_unpack_canonical(c, status); + FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1719,7 +1719,7 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. */ -static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) +static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s) { bool sign = a.sign ^ b.sign; @@ -1786,9 +1786,9 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) float16 float16_div(float16 a, float16 b, float_status *status) { - FloatParts pa = float16_unpack_canonical(a, status); - FloatParts pb = float16_unpack_canonical(b, status); - FloatParts pr = div_floats(pa, pb, status); + FloatParts64 pa = float16_unpack_canonical(a, status); + FloatParts64 pb = float16_unpack_canonical(b, status); + FloatParts64 pr = div_floats(pa, pb, status); return float16_round_pack_canonical(pr, status); } @@ -1796,9 +1796,9 @@ float16 float16_div(float16 a, float16 b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_div(float32 a, float32 b, float_status *status) { - FloatParts pa = float32_unpack_canonical(a, status); - FloatParts pb = float32_unpack_canonical(b, status); - FloatParts pr = div_floats(pa, pb, status); + FloatParts64 pa = float32_unpack_canonical(a, status); + FloatParts64 pb = float32_unpack_canonical(b, status); + FloatParts64 pr = div_floats(pa, pb, status); return float32_round_pack_canonical(pr, status); } @@ -1806,9 +1806,9 @@ soft_f32_div(float32 a, float32 b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_div(float64 a, float64 b, float_status *status) { - FloatParts pa = float64_unpack_canonical(a, status); - FloatParts pb = float64_unpack_canonical(b, status); - FloatParts pr = div_floats(pa, pb, status); + FloatParts64 pa = float64_unpack_canonical(a, status); + FloatParts64 pb = float64_unpack_canonical(b, status); + FloatParts64 pr = div_floats(pa, pb, status); return float64_round_pack_canonical(pr, status); } @@ -1878,9 +1878,9 @@ float64_div(float64 a, float64 b, float_status *s) bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts pa = bfloat16_unpack_canonical(a, status); - FloatParts pb = bfloat16_unpack_canonical(b, status); - FloatParts pr = div_floats(pa, pb, status); + FloatParts64 pa = bfloat16_unpack_canonical(a, status); + FloatParts64 pb = bfloat16_unpack_canonical(b, status); + FloatParts64 pr = div_floats(pa, pb, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1896,7 +1896,7 @@ bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) * invalid exceptions and handling the conversion on NaNs. */ -static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, +static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf, float_status *s) { if (dstf->arm_althp) { @@ -1934,32 +1934,32 @@ static FloatParts float_to_float(FloatParts a, const FloatFmt *dstf, float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts p = float16a_unpack_canonical(a, s, fmt16); - FloatParts pr = float_to_float(p, &float32_params, s); + FloatParts64 p = float16a_unpack_canonical(a, s, fmt16); + FloatParts64 pr = float_to_float(p, &float32_params, s); return float32_round_pack_canonical(pr, s); } float64 float16_to_float64(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts p = float16a_unpack_canonical(a, s, fmt16); - FloatParts pr = float_to_float(p, &float64_params, s); + FloatParts64 p = float16a_unpack_canonical(a, s, fmt16); + FloatParts64 pr = float_to_float(p, &float64_params, s); return float64_round_pack_canonical(pr, s); } float16 float32_to_float16(float32 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts p = float32_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, fmt16, s); + FloatParts64 p = float32_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } static float64 QEMU_SOFTFLOAT_ATTR soft_float32_to_float64(float32 a, float_status *s) { - FloatParts p = float32_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float64_params, s); + FloatParts64 p = float32_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, &float64_params, s); return float64_round_pack_canonical(pr, s); } @@ -1982,43 +1982,43 @@ float64 float32_to_float64(float32 a, float_status *s) float16 float64_to_float16(float64 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts p = float64_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, fmt16, s); + FloatParts64 p = float64_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } float32 float64_to_float32(float64 a, float_status *s) { - FloatParts p = float64_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float32_params, s); + FloatParts64 p = float64_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, &float32_params, s); return float32_round_pack_canonical(pr, s); } float32 bfloat16_to_float32(bfloat16 a, float_status *s) { - FloatParts p = bfloat16_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float32_params, s); + FloatParts64 p = bfloat16_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, &float32_params, s); return float32_round_pack_canonical(pr, s); } float64 bfloat16_to_float64(bfloat16 a, float_status *s) { - FloatParts p = bfloat16_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &float64_params, s); + FloatParts64 p = bfloat16_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, &float64_params, s); return float64_round_pack_canonical(pr, s); } bfloat16 float32_to_bfloat16(float32 a, float_status *s) { - FloatParts p = float32_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &bfloat16_params, s); + FloatParts64 p = float32_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } bfloat16 float64_to_bfloat16(float64 a, float_status *s) { - FloatParts p = float64_unpack_canonical(a, s); - FloatParts pr = float_to_float(p, &bfloat16_params, s); + FloatParts64 p = float64_unpack_canonical(a, s); + FloatParts64 pr = float_to_float(p, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } @@ -2029,7 +2029,7 @@ bfloat16 float64_to_bfloat16(float64 a, float_status *s) * Arithmetic. */ -static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode, +static FloatParts64 round_to_int(FloatParts64 a, FloatRoundMode rmode, int scale, float_status *s) { switch (a.cls) { @@ -2132,22 +2132,22 @@ static FloatParts round_to_int(FloatParts a, FloatRoundMode rmode, float16 float16_round_to_int(float16 a, float_status *s) { - FloatParts pa = float16_unpack_canonical(a, s); - FloatParts pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa = float16_unpack_canonical(a, s); + FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); return float16_round_pack_canonical(pr, s); } float32 float32_round_to_int(float32 a, float_status *s) { - FloatParts pa = float32_unpack_canonical(a, s); - FloatParts pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa = float32_unpack_canonical(a, s); + FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); return float32_round_pack_canonical(pr, s); } float64 float64_round_to_int(float64 a, float_status *s) { - FloatParts pa = float64_unpack_canonical(a, s); - FloatParts pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa = float64_unpack_canonical(a, s); + FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); return float64_round_pack_canonical(pr, s); } @@ -2158,8 +2158,8 @@ float64 float64_round_to_int(float64 a, float_status *s) bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) { - FloatParts pa = bfloat16_unpack_canonical(a, s); - FloatParts pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa = bfloat16_unpack_canonical(a, s); + FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); return bfloat16_round_pack_canonical(pr, s); } @@ -2174,13 +2174,13 @@ bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) * is returned. */ -static int64_t round_to_int_and_pack(FloatParts in, FloatRoundMode rmode, +static int64_t round_to_int_and_pack(FloatParts64 in, FloatRoundMode rmode, int scale, int64_t min, int64_t max, float_status *s) { uint64_t r; int orig_flags = get_float_exception_flags(s); - FloatParts p = round_to_int(in, rmode, scale, s); + FloatParts64 p = round_to_int(in, rmode, scale, s); switch (p.cls) { case float_class_snan: @@ -2452,12 +2452,12 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a, float_status *s) * flag. */ -static uint64_t round_to_uint_and_pack(FloatParts in, FloatRoundMode rmode, +static uint64_t round_to_uint_and_pack(FloatParts64 in, FloatRoundMode rmode, int scale, uint64_t max, float_status *s) { int orig_flags = get_float_exception_flags(s); - FloatParts p = round_to_int(in, rmode, scale, s); + FloatParts64 p = round_to_int(in, rmode, scale, s); uint64_t r; switch (p.cls) { @@ -2726,9 +2726,9 @@ uint64_t bfloat16_to_uint64_round_to_zero(bfloat16 a, float_status *s) * to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. */ -static FloatParts int_to_float(int64_t a, int scale, float_status *status) +static FloatParts64 int_to_float(int64_t a, int scale, float_status *status) { - FloatParts r = { .sign = false }; + FloatParts64 r = { .sign = false }; if (a == 0) { r.cls = float_class_zero; @@ -2753,7 +2753,7 @@ static FloatParts int_to_float(int64_t a, int scale, float_status *status) float16 int64_to_float16_scalbn(int64_t a, int scale, float_status *status) { - FloatParts pa = int_to_float(a, scale, status); + FloatParts64 pa = int_to_float(a, scale, status); return float16_round_pack_canonical(pa, status); } @@ -2789,7 +2789,7 @@ float16 int8_to_float16(int8_t a, float_status *status) float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { - FloatParts pa = int_to_float(a, scale, status); + FloatParts64 pa = int_to_float(a, scale, status); return float32_round_pack_canonical(pa, status); } @@ -2820,7 +2820,7 @@ float32 int16_to_float32(int16_t a, float_status *status) float64 int64_to_float64_scalbn(int64_t a, int scale, float_status *status) { - FloatParts pa = int_to_float(a, scale, status); + FloatParts64 pa = int_to_float(a, scale, status); return float64_round_pack_canonical(pa, status); } @@ -2856,7 +2856,7 @@ float64 int16_to_float64(int16_t a, float_status *status) bfloat16 int64_to_bfloat16_scalbn(int64_t a, int scale, float_status *status) { - FloatParts pa = int_to_float(a, scale, status); + FloatParts64 pa = int_to_float(a, scale, status); return bfloat16_round_pack_canonical(pa, status); } @@ -2893,9 +2893,9 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status *status) * IEC/IEEE Standard for Binary Floating-Point Arithmetic. */ -static FloatParts uint_to_float(uint64_t a, int scale, float_status *status) +static FloatParts64 uint_to_float(uint64_t a, int scale, float_status *status) { - FloatParts r = { .sign = false }; + FloatParts64 r = { .sign = false }; int shift; if (a == 0) { @@ -2913,7 +2913,7 @@ static FloatParts uint_to_float(uint64_t a, int scale, float_status *status) float16 uint64_to_float16_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts pa = uint_to_float(a, scale, status); + FloatParts64 pa = uint_to_float(a, scale, status); return float16_round_pack_canonical(pa, status); } @@ -2949,7 +2949,7 @@ float16 uint8_to_float16(uint8_t a, float_status *status) float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts pa = uint_to_float(a, scale, status); + FloatParts64 pa = uint_to_float(a, scale, status); return float32_round_pack_canonical(pa, status); } @@ -2980,7 +2980,7 @@ float32 uint16_to_float32(uint16_t a, float_status *status) float64 uint64_to_float64_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts pa = uint_to_float(a, scale, status); + FloatParts64 pa = uint_to_float(a, scale, status); return float64_round_pack_canonical(pa, status); } @@ -3016,7 +3016,7 @@ float64 uint16_to_float64(uint16_t a, float_status *status) bfloat16 uint64_to_bfloat16_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts pa = uint_to_float(a, scale, status); + FloatParts64 pa = uint_to_float(a, scale, status); return bfloat16_round_pack_canonical(pa, status); } @@ -3061,7 +3061,7 @@ bfloat16 uint16_to_bfloat16(uint16_t a, float_status *status) * minnummag() and maxnummag() functions correspond to minNumMag() * and minNumMag() from the IEEE-754 2008. */ -static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, +static FloatParts64 minmax_floats(FloatParts64 a, FloatParts64 b, bool ismin, bool ieee, bool ismag, float_status *s) { if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { @@ -3136,9 +3136,9 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin, float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ { \ - FloatParts pa = float ## sz ## _unpack_canonical(a, s); \ - FloatParts pb = float ## sz ## _unpack_canonical(b, s); \ - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + FloatParts64 pa = float ## sz ## _unpack_canonical(a, s); \ + FloatParts64 pb = float ## sz ## _unpack_canonical(b, s); \ + FloatParts64 pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ \ return float ## sz ## _round_pack_canonical(pr, s); \ } @@ -3169,9 +3169,9 @@ MINMAX(64, maxnummag, false, true, true) #define BF16_MINMAX(name, ismin, isiee, ismag) \ bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ { \ - FloatParts pa = bfloat16_unpack_canonical(a, s); \ - FloatParts pb = bfloat16_unpack_canonical(b, s); \ - FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ + FloatParts64 pa = bfloat16_unpack_canonical(a, s); \ + FloatParts64 pb = bfloat16_unpack_canonical(b, s); \ + FloatParts64 pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ \ return bfloat16_round_pack_canonical(pr, s); \ } @@ -3186,7 +3186,7 @@ BF16_MINMAX(maxnummag, false, true, true) #undef BF16_MINMAX /* Floating point compare */ -static FloatRelation compare_floats(FloatParts a, FloatParts b, bool is_quiet, +static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool is_quiet, float_status *s) { if (is_nan(a.cls) || is_nan(b.cls)) { @@ -3247,8 +3247,8 @@ static FloatRelation compare_floats(FloatParts a, FloatParts b, bool is_quiet, static int attr \ name(float ## sz a, float ## sz b, bool is_quiet, float_status *s) \ { \ - FloatParts pa = float ## sz ## _unpack_canonical(a, s); \ - FloatParts pb = float ## sz ## _unpack_canonical(b, s); \ + FloatParts64 pa = float ## sz ## _unpack_canonical(a, s); \ + FloatParts64 pb = float ## sz ## _unpack_canonical(b, s); \ return compare_floats(pa, pb, is_quiet, s); \ } @@ -3349,8 +3349,8 @@ FloatRelation float64_compare_quiet(float64 a, float64 b, float_status *s) static FloatRelation QEMU_FLATTEN soft_bf16_compare(bfloat16 a, bfloat16 b, bool is_quiet, float_status *s) { - FloatParts pa = bfloat16_unpack_canonical(a, s); - FloatParts pb = bfloat16_unpack_canonical(b, s); + FloatParts64 pa = bfloat16_unpack_canonical(a, s); + FloatParts64 pb = bfloat16_unpack_canonical(b, s); return compare_floats(pa, pb, is_quiet, s); } @@ -3365,16 +3365,16 @@ FloatRelation bfloat16_compare_quiet(bfloat16 a, bfloat16 b, float_status *s) } /* Multiply A by 2 raised to the power N. */ -static FloatParts scalbn_decomposed(FloatParts a, int n, float_status *s) +static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status *s) { if (unlikely(is_nan(a.cls))) { return return_nan(a, s); } if (a.cls == float_class_normal) { - /* The largest float type (even though not supported by FloatParts) + /* The largest float type (even though not supported by FloatParts64) * is float128, which has a 15 bit exponent. Bounding N to 16 bits * still allows rounding to infinity, without allowing overflow - * within the int32_t that backs FloatParts.exp. + * within the int32_t that backs FloatParts64.exp. */ n = MIN(MAX(n, -0x10000), 0x10000); a.exp += n; @@ -3384,29 +3384,29 @@ static FloatParts scalbn_decomposed(FloatParts a, int n, float_status *s) float16 float16_scalbn(float16 a, int n, float_status *status) { - FloatParts pa = float16_unpack_canonical(a, status); - FloatParts pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa = float16_unpack_canonical(a, status); + FloatParts64 pr = scalbn_decomposed(pa, n, status); return float16_round_pack_canonical(pr, status); } float32 float32_scalbn(float32 a, int n, float_status *status) { - FloatParts pa = float32_unpack_canonical(a, status); - FloatParts pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa = float32_unpack_canonical(a, status); + FloatParts64 pr = scalbn_decomposed(pa, n, status); return float32_round_pack_canonical(pr, status); } float64 float64_scalbn(float64 a, int n, float_status *status) { - FloatParts pa = float64_unpack_canonical(a, status); - FloatParts pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa = float64_unpack_canonical(a, status); + FloatParts64 pr = scalbn_decomposed(pa, n, status); return float64_round_pack_canonical(pr, status); } bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) { - FloatParts pa = bfloat16_unpack_canonical(a, status); - FloatParts pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa = bfloat16_unpack_canonical(a, status); + FloatParts64 pr = scalbn_decomposed(pa, n, status); return bfloat16_round_pack_canonical(pr, status); } @@ -3422,7 +3422,7 @@ bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) * especially for 64 bit floats. */ -static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) +static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt *p) { uint64_t a_frac, r_frac, s_frac; int bit, last_bit; @@ -3482,24 +3482,24 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) float16 QEMU_FLATTEN float16_sqrt(float16 a, float_status *status) { - FloatParts pa = float16_unpack_canonical(a, status); - FloatParts pr = sqrt_float(pa, status, &float16_params); + FloatParts64 pa = float16_unpack_canonical(a, status); + FloatParts64 pr = sqrt_float(pa, status, &float16_params); return float16_round_pack_canonical(pr, status); } static float32 QEMU_SOFTFLOAT_ATTR soft_f32_sqrt(float32 a, float_status *status) { - FloatParts pa = float32_unpack_canonical(a, status); - FloatParts pr = sqrt_float(pa, status, &float32_params); + FloatParts64 pa = float32_unpack_canonical(a, status); + FloatParts64 pr = sqrt_float(pa, status, &float32_params); return float32_round_pack_canonical(pr, status); } static float64 QEMU_SOFTFLOAT_ATTR soft_f64_sqrt(float64 a, float_status *status) { - FloatParts pa = float64_unpack_canonical(a, status); - FloatParts pr = sqrt_float(pa, status, &float64_params); + FloatParts64 pa = float64_unpack_canonical(a, status); + FloatParts64 pr = sqrt_float(pa, status, &float64_params); return float64_round_pack_canonical(pr, status); } @@ -3559,8 +3559,8 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { - FloatParts pa = bfloat16_unpack_canonical(a, status); - FloatParts pr = sqrt_float(pa, status, &bfloat16_params); + FloatParts64 pa = bfloat16_unpack_canonical(a, status); + FloatParts64 pr = sqrt_float(pa, status, &bfloat16_params); return bfloat16_round_pack_canonical(pr, status); } @@ -3570,28 +3570,28 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) float16 float16_default_nan(float_status *status) { - FloatParts p = parts_default_nan(status); + FloatParts64 p = parts_default_nan(status); p.frac >>= float16_params.frac_shift; return float16_pack_raw(p); } float32 float32_default_nan(float_status *status) { - FloatParts p = parts_default_nan(status); + FloatParts64 p = parts_default_nan(status); p.frac >>= float32_params.frac_shift; return float32_pack_raw(p); } float64 float64_default_nan(float_status *status) { - FloatParts p = parts_default_nan(status); + FloatParts64 p = parts_default_nan(status); p.frac >>= float64_params.frac_shift; return float64_pack_raw(p); } float128 float128_default_nan(float_status *status) { - FloatParts p = parts_default_nan(status); + FloatParts64 p = parts_default_nan(status); float128 r; /* Extrapolate from the choices made by parts_default_nan to fill @@ -3608,7 +3608,7 @@ float128 float128_default_nan(float_status *status) bfloat16 bfloat16_default_nan(float_status *status) { - FloatParts p = parts_default_nan(status); + FloatParts64 p = parts_default_nan(status); p.frac >>= bfloat16_params.frac_shift; return bfloat16_pack_raw(p); } @@ -3619,7 +3619,7 @@ bfloat16 bfloat16_default_nan(float_status *status) float16 float16_silence_nan(float16 a, float_status *status) { - FloatParts p = float16_unpack_raw(a); + FloatParts64 p = float16_unpack_raw(a); p.frac <<= float16_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float16_params.frac_shift; @@ -3628,7 +3628,7 @@ float16 float16_silence_nan(float16 a, float_status *status) float32 float32_silence_nan(float32 a, float_status *status) { - FloatParts p = float32_unpack_raw(a); + FloatParts64 p = float32_unpack_raw(a); p.frac <<= float32_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float32_params.frac_shift; @@ -3637,7 +3637,7 @@ float32 float32_silence_nan(float32 a, float_status *status) float64 float64_silence_nan(float64 a, float_status *status) { - FloatParts p = float64_unpack_raw(a); + FloatParts64 p = float64_unpack_raw(a); p.frac <<= float64_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float64_params.frac_shift; @@ -3646,7 +3646,7 @@ float64 float64_silence_nan(float64 a, float_status *status) bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) { - FloatParts p = bfloat16_unpack_raw(a); + FloatParts64 p = bfloat16_unpack_raw(a); p.frac <<= bfloat16_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= bfloat16_params.frac_shift; @@ -3658,7 +3658,7 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) | input-denormal exception and return zero. Otherwise just return the value. *----------------------------------------------------------------------------*/ -static bool parts_squash_denormal(FloatParts p, float_status *status) +static bool parts_squash_denormal(FloatParts64 p, float_status *status) { if (p.exp == 0 && p.frac != 0) { float_raise(float_flag_input_denormal, status); @@ -3671,7 +3671,7 @@ static bool parts_squash_denormal(FloatParts p, float_status *status) float16 float16_squash_input_denormal(float16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p = float16_unpack_raw(a); + FloatParts64 p = float16_unpack_raw(a); if (parts_squash_denormal(p, status)) { return float16_set_sign(float16_zero, p.sign); } @@ -3682,7 +3682,7 @@ float16 float16_squash_input_denormal(float16 a, float_status *status) float32 float32_squash_input_denormal(float32 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p = float32_unpack_raw(a); + FloatParts64 p = float32_unpack_raw(a); if (parts_squash_denormal(p, status)) { return float32_set_sign(float32_zero, p.sign); } @@ -3693,7 +3693,7 @@ float32 float32_squash_input_denormal(float32 a, float_status *status) float64 float64_squash_input_denormal(float64 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p = float64_unpack_raw(a); + FloatParts64 p = float64_unpack_raw(a); if (parts_squash_denormal(p, status)) { return float64_set_sign(float64_zero, p.sign); } @@ -3704,7 +3704,7 @@ float64 float64_squash_input_denormal(float64 a, float_status *status) bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts p = bfloat16_unpack_raw(a); + FloatParts64 p = bfloat16_unpack_raw(a); if (parts_squash_denormal(p, status)) { return bfloat16_set_sign(bfloat16_zero, p.sign); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5988830c16..52fc76d800 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -129,7 +129,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) | The pattern for a default generated deconstructed floating-point NaN. *----------------------------------------------------------------------------*/ -static FloatParts parts_default_nan(float_status *status) +static FloatParts64 parts_default_nan(float_status *status) { bool sign = 0; uint64_t frac; @@ -164,7 +164,7 @@ static FloatParts parts_default_nan(float_status *status) } #endif - return (FloatParts) { + return (FloatParts64) { .cls = float_class_qnan, .sign = sign, .exp = INT_MAX, @@ -177,7 +177,7 @@ static FloatParts parts_default_nan(float_status *status) | floating-point parts. *----------------------------------------------------------------------------*/ -static FloatParts parts_silence_nan(FloatParts a, float_status *status) +static FloatParts64 parts_silence_nan(FloatParts64 a, float_status *status) { g_assert(!no_signaling_nans(status)); g_assert(!status->default_nan_mode); From patchwork Sat May 8 01:47:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432533 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp847788jao; Fri, 7 May 2021 19:02:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwwpIET2IJn4VxmgIhetS7rtJuuNg0s5Wqd7uQqCV7SyvzpIc8szYirgoz+fSSBfrXR+OXQ X-Received: by 2002:ac8:7f83:: with SMTP id z3mr3409554qtj.239.1620439358929; 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 109 +++++++++++++++++++++++++----------------------- 1 file changed, 56 insertions(+), 53 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 27b51659c9..398a068b58 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -837,59 +837,6 @@ static FloatParts64 round_canonical(FloatParts64 p, float_status *s, return p; } -/* Explicit FloatFmt version */ -static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, - const FloatFmt *params) -{ - return sf_canonicalize(float16_unpack_raw(f), params, s); -} - -static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) -{ - return float16a_unpack_canonical(f, s, &float16_params); -} - -static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) -{ - return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); -} - -static float16 float16a_round_pack_canonical(FloatParts64 p, float_status *s, - const FloatFmt *params) -{ - return float16_pack_raw(round_canonical(p, s, params)); -} - -static float16 float16_round_pack_canonical(FloatParts64 p, float_status *s) -{ - return float16a_round_pack_canonical(p, s, &float16_params); -} - -static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status *s) -{ - return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); -} - -static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) -{ - return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); -} - -static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) -{ - return float32_pack_raw(round_canonical(p, s, &float32_params)); -} - -static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) -{ - return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); -} - -static float64 float64_round_pack_canonical(FloatParts64 p, float_status *s) -{ - return float64_pack_raw(round_canonical(p, s, &float64_params)); -} - static FloatParts64 return_nan(FloatParts64 a, float_status *s) { g_assert(is_nan(a.cls)); @@ -964,6 +911,62 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 return a; } +/* + * Pack/unpack routines with a specific FloatFmt. + */ + +static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, + const FloatFmt *params) +{ + return sf_canonicalize(float16_unpack_raw(f), params, s); +} + +static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) +{ + return float16a_unpack_canonical(f, s, &float16_params); +} + +static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) +{ + return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); +} + +static float16 float16a_round_pack_canonical(FloatParts64 p, float_status *s, + const FloatFmt *params) +{ + return float16_pack_raw(round_canonical(p, s, params)); +} + +static float16 float16_round_pack_canonical(FloatParts64 p, float_status *s) +{ + return float16a_round_pack_canonical(p, s, &float16_params); +} + +static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status *s) +{ + return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); +} + +static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) +{ + return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); +} + +static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) +{ + return float32_pack_raw(round_canonical(p, s, &float32_params)); +} + +static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) +{ + return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); +} + +static float64 float64_round_pack_canonical(FloatParts64 p, float_status *s) +{ + return float64_pack_raw(round_canonical(p, s, &float64_params)); +} + /* * Returns the result of adding or subtracting the values of the * floating-point values `a' and `b'. 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[209.51.188.17]) by mx.google.com with ESMTPS id i3si9880950iom.69.2021.05.07.18.58.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 18:58:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Sjoxa2mq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCEn-0004kW-9r for patch@linaro.org; Fri, 07 May 2021 21:58:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC4r-0004C4-PB for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:25 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:42872) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4n-0003bC-90 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:20 -0400 Received: by mail-pf1-x429.google.com with SMTP id h127so9114410pfe.9 for ; Fri, 07 May 2021 18:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lv754BNFiT0WY9Gu5PCjCwyGp1j/2FG0ontxfnvbfDM=; b=Sjoxa2mqfi4r66N+hnftKUFzK057DD1/8IQ8xizex+7dZIi6GVO/eNAXhc42yGAjJM X70AjE6WisguHC80JJixoGFXzuQG0F8GBqfkO1blzypxOwAFW/NaWDHpF83cCIW+i/uR OL4iDwUZTlznV6eUIRS7o9HUXREvyf1dt2+XgCboQSF2jshNY31ZvvtqvW6797EirEew AVyyhpva+95gVnGlm1K/5nIdnW6F/dsDrIWURCj8eh+9uStc0sjn2zEuRy7LyRkjN38X mOl5H87lGIqQqxCs/quUH7XIzV6A1FDdgk4BB1lfdDAs2OGzQp3UaK2upolhk3nf8B7j YlFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lv754BNFiT0WY9Gu5PCjCwyGp1j/2FG0ontxfnvbfDM=; b=Ei7GdosivteC7a74B3djPcAhXUmAlVonelEIMlC5LDzbv9+kQebM5nGyGQIlkxDGKi owssR+9Xd6cOenewNH4mk/a4P35N6kekwQ8QuzQYxhAFbQpS/bVbIhE5TxUAkKYfW9gg MtGTEk6KN2e8oIle7iirQKg0V1iOLi0L6vLj9ljSnWOqtHiG6k04JH1UMbAtmFKUKhPS /EBY8Tkj7ZG+v5DNHoK7DIBK/vRkfDU4WCiR+ZHDNWf5sjF8ErkrUxc88K6WvIjTJ3Wn /xaclBZ4coczA7sCJvT8pS7uEc/cHGAedxUa3tLJjsnZf9hWLJFX30t/P0UHsvM731VX B8Wg== X-Gm-Message-State: AOAM533PKNWSYaAUERax3ThiMXEioKAi0cT6mByoUNkgILq1xhte+etO uw+/aC/bhgdK4q52xWcmBkDX9uAunL3Wbw== X-Received: by 2002:a65:538d:: with SMTP id x13mr13248453pgq.108.1620438494826; Fri, 07 May 2021 18:48:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/72] softfloat: Use pointers with parts_default_nan Date: Fri, 7 May 2021 18:47:07 -0700 Message-Id: <20210508014802.892561-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, rename to parts64_default_nan and define a macro for parts_default_nan using QEMU_GENERIC. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 47 +++++++++++++++++++++++----------- fpu/softfloat-specialize.c.inc | 4 +-- 2 files changed, 34 insertions(+), 17 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 398a068b58..c7f95961cf 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -650,6 +650,8 @@ static inline float64 float64_pack_raw(FloatParts64 p) *----------------------------------------------------------------------------*/ #include "softfloat-specialize.c.inc" +#define parts_default_nan parts64_default_nan + /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm, float_status *status) @@ -848,7 +850,8 @@ static FloatParts64 return_nan(FloatParts64 a, float_status *s) } else if (!s->default_nan_mode) { return a; } - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) @@ -858,7 +861,7 @@ static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) } if (s->default_nan_mode) { - return parts_default_nan(s); + parts_default_nan(&a, s); } else { if (pickNaN(a.cls, b.cls, a.frac > b.frac || @@ -900,7 +903,8 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 a = c; break; case 3: - return parts_default_nan(s); + parts_default_nan(&a, s); + break; default: g_assert_not_reached(); } @@ -1011,7 +1015,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract, if (a.cls == float_class_inf) { if (b.cls == float_class_inf) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); } return a; } @@ -1254,7 +1258,8 @@ static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s) if ((a.cls == float_class_inf && b.cls == float_class_zero) || (a.cls == float_class_zero && b.cls == float_class_inf)) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } /* Multiply by 0 or Inf */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -1372,7 +1377,8 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c if (inf_zero) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } if (flags & float_muladd_negate_c) { @@ -1396,11 +1402,11 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c if (c.cls == float_class_inf) { if (p_class == float_class_inf && p_sign != c.sign) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&c, s); } else { c.sign ^= sign_flip; - return c; } + return c; } if (p_class == float_class_inf) { @@ -1764,7 +1770,8 @@ static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s) && (a.cls == float_class_inf || a.cls == float_class_zero)) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } /* Inf / x or 0 / x */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -3438,7 +3445,8 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt * } if (a.sign) { float_raise(float_flag_invalid, s); - return parts_default_nan(s); + parts_default_nan(&a, s); + return a; } if (a.cls == float_class_inf) { return a; /* sqrt(+inf) = +inf */ @@ -3573,30 +3581,37 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) float16 float16_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= float16_params.frac_shift; return float16_pack_raw(p); } float32 float32_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= float32_params.frac_shift; return float32_pack_raw(p); } float64 float64_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= float64_params.frac_shift; return float64_pack_raw(p); } float128 float128_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; float128 r; + parts_default_nan(&p, status); /* Extrapolate from the choices made by parts_default_nan to fill * in the quad-floating format. If the low bit is set, assume we * want to set all non-snan bits. @@ -3611,7 +3626,9 @@ float128 float128_default_nan(float_status *status) bfloat16 bfloat16_default_nan(float_status *status) { - FloatParts64 p = parts_default_nan(status); + FloatParts64 p; + + parts_default_nan(&p, status); p.frac >>= bfloat16_params.frac_shift; return bfloat16_pack_raw(p); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 52fc76d800..085ddea62b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -129,7 +129,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) | The pattern for a default generated deconstructed floating-point NaN. *----------------------------------------------------------------------------*/ -static FloatParts64 parts_default_nan(float_status *status) +static void parts64_default_nan(FloatParts64 *p, float_status *status) { bool sign = 0; uint64_t frac; @@ -164,7 +164,7 @@ static FloatParts64 parts_default_nan(float_status *status) } #endif - return (FloatParts64) { + *p = (FloatParts64) { .cls = float_class_qnan, .sign = sign, .exp = INT_MAX, From patchwork Sat May 8 01:47:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432538 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp849633jao; Fri, 7 May 2021 19:05:58 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxi/w9BkrRr9Ec6dzk0GXD9eymHfUuNDkMOGA2KZiy1FihjLSFb28pb7IDu5MaxAprUGYwi X-Received: by 2002:a92:b751:: with SMTP id c17mr12466366ilm.121.1620439558396; Fri, 07 May 2021 19:05:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439558; cv=none; d=google.com; s=arc-20160816; b=cyus1/Or7G0Jn54uwYCpi+C2+rdEKBIrNyMxZGmTWJZqhNZ989IyCr24qkakNVhc++ NuCnf1HgSDwjM36nklWot2iBygmqDROXqTpVP1pz3VNDAvZyg7idtV14V20hwYonU9Bv YSHj9cqSxYBoSDy809x2YCd1MV89obwaNzVl4rf6Ugmcvpodom9MF9dQNDIlLFmWz/2d WdzxTlAmBtviEh6WOuK9mRZ2auzD4ozY5KRSu3jwQ/KGJ5bYOiVWrEIlG3MecseqRLDo WcqtSeBFcaeG5DsIBauq0KXfwUZ2DlDYnUcjBnL35rd//EwMW5zNKyuLKQHNSC7W410m 3QoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=K1gA4ou0gWluj4i3I5ZQAgi8eRSRO7pa0sBtkx8u1fc=; b=lnfxt4jOoMx2Eaq0wsdtH/lXLCUEt5etpICcqSstgI2uLRpO6JxSlsZupohZRTONO3 DAulCGlXvCZgBBTOEE/0Hg9q0b/NeNmoLryeqAe3UQXhTLKszF57uCD6f5pWeKnMRzfH 7FPyBjOwvLgaWlodQJfp6WAe3b9NEcgoIXOdXrPYgptkD7Vc3QY2K+qdMX/1VbzO4mNL od9t/AwBAOvryZ6mE9764MhFtkNp5Ll/utmjtcw4zVHHuB5eMyV877P1ikdGmzGQWq9d rSCCtViu+KF5ZoivcKeLJgnISHiwvA9C7nCnf+rPEgemJAIFUL2vKOMQPMIZWeapprKg EWSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=z42ci9DK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c7f95961cf..5ff9368012 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -580,36 +580,45 @@ static const FloatFmt float64_params = { }; /* Unpack a float to parts, but do not canonicalize. */ -static inline FloatParts64 unpack_raw(FloatFmt fmt, uint64_t raw) +static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t raw) { - const int sign_pos = fmt.frac_size + fmt.exp_size; + const int f_size = fmt->frac_size; + const int e_size = fmt->exp_size; - return (FloatParts64) { + *r = (FloatParts64) { .cls = float_class_unclassified, - .sign = extract64(raw, sign_pos, 1), - .exp = extract64(raw, fmt.frac_size, fmt.exp_size), - .frac = extract64(raw, 0, fmt.frac_size), + .sign = extract64(raw, f_size + e_size, 1), + .exp = extract64(raw, f_size, e_size), + .frac = extract64(raw, 0, f_size) }; } static inline FloatParts64 float16_unpack_raw(float16 f) { - return unpack_raw(float16_params, f); + FloatParts64 p; + unpack_raw64(&p, &float16_params, f); + return p; } static inline FloatParts64 bfloat16_unpack_raw(bfloat16 f) { - return unpack_raw(bfloat16_params, f); + FloatParts64 p; + unpack_raw64(&p, &bfloat16_params, f); + return p; } static inline FloatParts64 float32_unpack_raw(float32 f) { - return unpack_raw(float32_params, f); + FloatParts64 p; + unpack_raw64(&p, &float32_params, f); + return p; } static inline FloatParts64 float64_unpack_raw(float64 f) { - return unpack_raw(float64_params, f); + FloatParts64 p; + unpack_raw64(&p, &float64_params, f); + return p; } /* Pack a float from parts, but do not canonicalize. */ From patchwork Sat May 8 01:47:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432539 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp849665jao; Fri, 7 May 2021 19:06:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzAck3LhSoCQkR5Oqlte4AcP3VqGsYX+gOYFF+PnpnVlmvHxfF5kxbWz6+QahccqLhH5jhh X-Received: by 2002:a05:6e02:1a8c:: with SMTP id k12mr12082551ilv.161.1620439560926; Fri, 07 May 2021 19:06:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439560; cv=none; d=google.com; s=arc-20160816; b=Qkky0m4ruCK5RmBNw78IrQf7fHYGcJibPr5p87SuDEURdxIHIXQkWjFnjuSbGm0qvh QP093DwsvYG2RdnUWtMjWdRnXviEGHctsfReePpadXumuRIwtP4xlCiluCsTFfpwgNi5 f4G+2dyY7+2SOKS8rbFUvBI8a+64B0Szp6Ei1sGa7st0R7uwoRkoibdbk1P4yJhPeVyh p5sKkSJABrKkJLTgY3Ub2DapvQVGrKoH9RDT7dhxDtikJmGIaptyMmoZLczGpZq+dcJJ PA1mJR269k3BPAU7XWTVaCv5Tm2Ly4T2SCCu16qvnXzWfGDgr4HZKC814zHXXCvTsyPA tCNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=haSDSlpUM8p9DuI0N+XPpsqo4opBjSRscJfYOaISZlo=; b=UNO8DBarf0XR8AaF0Jm/RqUgDAUGkS87E2vkSUZKAOcQBrYSdZDVz9BtYwjibEgZyC jIeg2MWWXS+eFU1VFtNuuv3VYyrvdzFNk54yc12+KCvPRnnMhHQddOT4WyHDQRX+FLzF 18IeAzRnMVae+AiWPwELnQf4ihLDQbLrOvydPGLWzZPMlSsFN1UCsf/4rjZS8+7tqUuI 158FohsL92z6zBi3CA7BrUvXA7vbUZsocahTHJbCmZ3eiEoWMV69TzxfqjeFUTmfC4n4 hAPF5VtR5CXalHhg0y0n0u5V3N4QBo+4B58k0rT5tU3j1v73XYCTwvz0oxYWA4PmxO1r QOKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Hn97pC6a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:48:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 19/72] softfloat: Use pointers with ftype_unpack_raw Date: Fri, 7 May 2021 18:47:09 -0700 Message-Id: <20210508014802.892561-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 76 +++++++++++++++++++++++++++++++------------------ 1 file changed, 48 insertions(+), 28 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5ff9368012..5a736a46cf 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -593,32 +593,24 @@ static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t raw) }; } -static inline FloatParts64 float16_unpack_raw(float16 f) +static inline void float16_unpack_raw(FloatParts64 *p, float16 f) { - FloatParts64 p; - unpack_raw64(&p, &float16_params, f); - return p; + unpack_raw64(p, &float16_params, f); } -static inline FloatParts64 bfloat16_unpack_raw(bfloat16 f) +static inline void bfloat16_unpack_raw(FloatParts64 *p, bfloat16 f) { - FloatParts64 p; - unpack_raw64(&p, &bfloat16_params, f); - return p; + unpack_raw64(p, &bfloat16_params, f); } -static inline FloatParts64 float32_unpack_raw(float32 f) +static inline void float32_unpack_raw(FloatParts64 *p, float32 f) { - FloatParts64 p; - unpack_raw64(&p, &float32_params, f); - return p; + unpack_raw64(p, &float32_params, f); } -static inline FloatParts64 float64_unpack_raw(float64 f) +static inline void float64_unpack_raw(FloatParts64 *p, float64 f) { - FloatParts64 p; - unpack_raw64(&p, &float64_params, f); - return p; + unpack_raw64(p, &float64_params, f); } /* Pack a float from parts, but do not canonicalize. */ @@ -931,7 +923,10 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, const FloatFmt *params) { - return sf_canonicalize(float16_unpack_raw(f), params, s); + FloatParts64 p; + + float16_unpack_raw(&p, f); + return sf_canonicalize(p, params, s); } static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) @@ -941,7 +936,10 @@ static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) { - return sf_canonicalize(bfloat16_unpack_raw(f), &bfloat16_params, s); + FloatParts64 p; + + bfloat16_unpack_raw(&p, f); + return sf_canonicalize(p, &bfloat16_params, s); } static float16 float16a_round_pack_canonical(FloatParts64 p, float_status *s, @@ -962,7 +960,10 @@ static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status *s) static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) { - return sf_canonicalize(float32_unpack_raw(f), &float32_params, s); + FloatParts64 p; + + float32_unpack_raw(&p, f); + return sf_canonicalize(p, &float32_params, s); } static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) @@ -972,7 +973,10 @@ static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) { - return sf_canonicalize(float64_unpack_raw(f), &float64_params, s); + FloatParts64 p; + + float64_unpack_raw(&p, f); + return sf_canonicalize(p, &float64_params, s); } static float64 float64_round_pack_canonical(FloatParts64 p, float_status *s) @@ -3648,7 +3652,9 @@ bfloat16 bfloat16_default_nan(float_status *status) float16 float16_silence_nan(float16 a, float_status *status) { - FloatParts64 p = float16_unpack_raw(a); + FloatParts64 p; + + float16_unpack_raw(&p, a); p.frac <<= float16_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float16_params.frac_shift; @@ -3657,7 +3663,9 @@ float16 float16_silence_nan(float16 a, float_status *status) float32 float32_silence_nan(float32 a, float_status *status) { - FloatParts64 p = float32_unpack_raw(a); + FloatParts64 p; + + float32_unpack_raw(&p, a); p.frac <<= float32_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float32_params.frac_shift; @@ -3666,7 +3674,9 @@ float32 float32_silence_nan(float32 a, float_status *status) float64 float64_silence_nan(float64 a, float_status *status) { - FloatParts64 p = float64_unpack_raw(a); + FloatParts64 p; + + float64_unpack_raw(&p, a); p.frac <<= float64_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float64_params.frac_shift; @@ -3675,7 +3685,9 @@ float64 float64_silence_nan(float64 a, float_status *status) bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) { - FloatParts64 p = bfloat16_unpack_raw(a); + FloatParts64 p; + + bfloat16_unpack_raw(&p, a); p.frac <<= bfloat16_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= bfloat16_params.frac_shift; @@ -3700,7 +3712,9 @@ static bool parts_squash_denormal(FloatParts64 p, float_status *status) float16 float16_squash_input_denormal(float16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p = float16_unpack_raw(a); + FloatParts64 p; + + float16_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return float16_set_sign(float16_zero, p.sign); } @@ -3711,7 +3725,9 @@ float16 float16_squash_input_denormal(float16 a, float_status *status) float32 float32_squash_input_denormal(float32 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p = float32_unpack_raw(a); + FloatParts64 p; + + float32_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return float32_set_sign(float32_zero, p.sign); } @@ -3722,7 +3738,9 @@ float32 float32_squash_input_denormal(float32 a, float_status *status) float64 float64_squash_input_denormal(float64 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p = float64_unpack_raw(a); + FloatParts64 p; + + float64_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return float64_set_sign(float64_zero, p.sign); } @@ -3733,7 +3751,9 @@ float64 float64_squash_input_denormal(float64 a, float_status *status) bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status) { if (status->flush_inputs_to_zero) { - FloatParts64 p = bfloat16_unpack_raw(a); + FloatParts64 p; + + bfloat16_unpack_raw(&p, a); if (parts_squash_denormal(p, status)) { return bfloat16_set_sign(bfloat16_zero, p.sign); } From patchwork Sat May 8 01:47:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432542 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp850720jao; 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5a736a46cf..b59b777bca 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -614,31 +614,36 @@ static inline void float64_unpack_raw(FloatParts64 *p, float64 f) } /* Pack a float from parts, but do not canonicalize. */ -static inline uint64_t pack_raw(FloatFmt fmt, FloatParts64 p) +static uint64_t pack_raw64(const FloatParts64 *p, const FloatFmt *fmt) { - const int sign_pos = fmt.frac_size + fmt.exp_size; - uint64_t ret = deposit64(p.frac, fmt.frac_size, fmt.exp_size, p.exp); - return deposit64(ret, sign_pos, 1, p.sign); + const int f_size = fmt->frac_size; + const int e_size = fmt->exp_size; + uint64_t ret; + + ret = (uint64_t)p->sign << (f_size + e_size); + ret = deposit64(ret, f_size, e_size, p->exp); + ret = deposit64(ret, 0, f_size, p->frac); + return ret; } static inline float16 float16_pack_raw(FloatParts64 p) { - return make_float16(pack_raw(float16_params, p)); + return make_float16(pack_raw64(&p, &float16_params)); } static inline bfloat16 bfloat16_pack_raw(FloatParts64 p) { - return pack_raw(bfloat16_params, p); + return pack_raw64(&p, &bfloat16_params); } static inline float32 float32_pack_raw(FloatParts64 p) { - return make_float32(pack_raw(float32_params, p)); + return make_float32(pack_raw64(&p, &float32_params)); } static inline float64 float64_pack_raw(FloatParts64 p) { - return make_float64(pack_raw(float64_params, p)); + return make_float64(pack_raw64(&p, &float64_params)); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432523 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp842722jao; Fri, 7 May 2021 18:53:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzHAr0P8xoJSy+Qd5YgAxYVpL3ciB339YRP4vtQB4MVSLAdpvOXVqkp7NjwBpFjgtKFb3oi X-Received: by 2002:ac8:124a:: with SMTP id g10mr2219345qtj.347.1620438828426; Fri, 07 May 2021 18:53:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438828; cv=none; d=google.com; s=arc-20160816; b=wCAWW3lA/d7pX1dmelwMRA3txEBvFgpPFOKAnMl0CZSJwJpGYydtOh7KH13WlpSuwD CIvEf6mGS4369IXDWGeURnresWAWARahAYfE2zeWC7T8lTtHMwcHorc9vEbeYFkc3rf6 0m9R7OFJLbsJWaPdH2ip97SoegLs9Wn/JovfvMgXDGNG8AqDBEp8iJzYM/ItSSqsEIYm r9RyvJ6TXVaaRp1qPdKH+rJBwFjNkozE1RwjvFeY/OnEykluGo5p9NbSvofThxpNMdHh 5fGYpfgG8wDgwBTp4ml1SFgKuEHNahXhoufNSamSwxRHe5TF8HFdF9bvOzuyM5eHkxQo 1qsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=klq5tF3eUBw1b5IWfv55EAVbPnpG6rjwX1EUfobNPG4=; b=IuvTZ+SJQ5EkA/t+4+5ivIHiBGuvuxYkezXScHpQqqIwhn2iiMf7ci62ihZDBh2wBG sKE7x7jUzae97jDJ8yA8JmnlqhL51OuMayvq1nQD6OFX/pWncXPz70MRzLU2FgMBUL0e yX1//RWADKZRiZEIh7uX68i7JlE+h/pTTyWdaM/eVPeadbDLNQ06MPbhesydys4Hh50L z9mOEded40Q0ItHa9OFbVWL4snRGF0nF+hIUoAe/uVGfa3iBDc4kSIUC0thcF48shwip Slf0o0va4oYiQCsEWZp7647lz4zX2KS3n+6SnauZ3zfDWzdK7nPOPSkTIeMEX3QnB6Bw bF0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i7+FYbFJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:48:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 21/72] softfloat: Use pointers with ftype_pack_raw Date: Fri, 7 May 2021 18:47:11 -0700 Message-Id: <20210508014802.892561-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b59b777bca..e02cbafaf9 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -626,24 +626,24 @@ static uint64_t pack_raw64(const FloatParts64 *p, const FloatFmt *fmt) return ret; } -static inline float16 float16_pack_raw(FloatParts64 p) +static inline float16 float16_pack_raw(const FloatParts64 *p) { - return make_float16(pack_raw64(&p, &float16_params)); + return make_float16(pack_raw64(p, &float16_params)); } -static inline bfloat16 bfloat16_pack_raw(FloatParts64 p) +static inline bfloat16 bfloat16_pack_raw(const FloatParts64 *p) { - return pack_raw64(&p, &bfloat16_params); + return pack_raw64(p, &bfloat16_params); } -static inline float32 float32_pack_raw(FloatParts64 p) +static inline float32 float32_pack_raw(const FloatParts64 *p) { - return make_float32(pack_raw64(&p, &float32_params)); + return make_float32(pack_raw64(p, &float32_params)); } -static inline float64 float64_pack_raw(FloatParts64 p) +static inline float64 float64_pack_raw(const FloatParts64 *p) { - return make_float64(pack_raw64(&p, &float64_params)); + return make_float64(pack_raw64(p, &float64_params)); } /*---------------------------------------------------------------------------- @@ -950,7 +950,8 @@ static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) static float16 float16a_round_pack_canonical(FloatParts64 p, float_status *s, const FloatFmt *params) { - return float16_pack_raw(round_canonical(p, s, params)); + p = round_canonical(p, s, params); + return float16_pack_raw(&p); } static float16 float16_round_pack_canonical(FloatParts64 p, float_status *s) @@ -960,7 +961,8 @@ static float16 float16_round_pack_canonical(FloatParts64 p, float_status *s) static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status *s) { - return bfloat16_pack_raw(round_canonical(p, s, &bfloat16_params)); + p = round_canonical(p, s, &bfloat16_params); + return bfloat16_pack_raw(&p); } static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) @@ -973,7 +975,8 @@ static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) { - return float32_pack_raw(round_canonical(p, s, &float32_params)); + p = round_canonical(p, s, &float32_params); + return float32_pack_raw(&p); } static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) @@ -986,7 +989,8 @@ static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) static float64 float64_round_pack_canonical(FloatParts64 p, float_status *s) { - return float64_pack_raw(round_canonical(p, s, &float64_params)); + p = round_canonical(p, s, &float64_params); + return float64_pack_raw(&p); } /* @@ -3603,7 +3607,7 @@ float16 float16_default_nan(float_status *status) parts_default_nan(&p, status); p.frac >>= float16_params.frac_shift; - return float16_pack_raw(p); + return float16_pack_raw(&p); } float32 float32_default_nan(float_status *status) @@ -3612,7 +3616,7 @@ float32 float32_default_nan(float_status *status) parts_default_nan(&p, status); p.frac >>= float32_params.frac_shift; - return float32_pack_raw(p); + return float32_pack_raw(&p); } float64 float64_default_nan(float_status *status) @@ -3621,7 +3625,7 @@ float64 float64_default_nan(float_status *status) parts_default_nan(&p, status); p.frac >>= float64_params.frac_shift; - return float64_pack_raw(p); + return float64_pack_raw(&p); } float128 float128_default_nan(float_status *status) @@ -3648,7 +3652,7 @@ bfloat16 bfloat16_default_nan(float_status *status) parts_default_nan(&p, status); p.frac >>= bfloat16_params.frac_shift; - return bfloat16_pack_raw(p); + return bfloat16_pack_raw(&p); } /*---------------------------------------------------------------------------- @@ -3663,7 +3667,7 @@ float16 float16_silence_nan(float16 a, float_status *status) p.frac <<= float16_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float16_params.frac_shift; - return float16_pack_raw(p); + return float16_pack_raw(&p); } float32 float32_silence_nan(float32 a, float_status *status) @@ -3674,7 +3678,7 @@ float32 float32_silence_nan(float32 a, float_status *status) p.frac <<= float32_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float32_params.frac_shift; - return float32_pack_raw(p); + return float32_pack_raw(&p); } float64 float64_silence_nan(float64 a, float_status *status) @@ -3685,7 +3689,7 @@ float64 float64_silence_nan(float64 a, float_status *status) p.frac <<= float64_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= float64_params.frac_shift; - return float64_pack_raw(p); + return float64_pack_raw(&p); } bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) @@ -3696,7 +3700,7 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) p.frac <<= bfloat16_params.frac_shift; p = parts_silence_nan(p, status); p.frac >>= bfloat16_params.frac_shift; - return bfloat16_pack_raw(p); + return bfloat16_pack_raw(&p); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432527 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp843949jao; Fri, 7 May 2021 18:56:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxPKXHMs2+qu28lsAI6L9QAa6jAyRt4xvQHX3ZH6FhqaKR/FQDMcMiJ5pYLrcJs0iAOoLMS X-Received: by 2002:a05:6e02:1ba3:: with SMTP id n3mr5327317ili.20.1620438982281; Fri, 07 May 2021 18:56:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620438982; cv=none; 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Fri, 07 May 2021 18:48:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 22/72] softfloat: Use pointers with ftype_unpack_canonical Date: Fri, 7 May 2021 18:47:12 -0700 Message-Id: <20210508014802.892561-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 509 ++++++++++++++++++++++++++++++------------------ 1 file changed, 320 insertions(+), 189 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e02cbafaf9..e53d4a138f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -925,26 +925,24 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 * Pack/unpack routines with a specific FloatFmt. */ -static FloatParts64 float16a_unpack_canonical(float16 f, float_status *s, - const FloatFmt *params) +static void float16a_unpack_canonical(FloatParts64 *p, float16 f, + float_status *s, const FloatFmt *params) { - FloatParts64 p; - - float16_unpack_raw(&p, f); - return sf_canonicalize(p, params, s); + float16_unpack_raw(p, f); + *p = sf_canonicalize(*p, params, s); } -static FloatParts64 float16_unpack_canonical(float16 f, float_status *s) +static void float16_unpack_canonical(FloatParts64 *p, float16 f, + float_status *s) { - return float16a_unpack_canonical(f, s, &float16_params); + float16a_unpack_canonical(p, f, s, &float16_params); } -static FloatParts64 bfloat16_unpack_canonical(bfloat16 f, float_status *s) +static void bfloat16_unpack_canonical(FloatParts64 *p, bfloat16 f, + float_status *s) { - FloatParts64 p; - - bfloat16_unpack_raw(&p, f); - return sf_canonicalize(p, &bfloat16_params, s); + bfloat16_unpack_raw(p, f); + *p = sf_canonicalize(*p, &bfloat16_params, s); } static float16 float16a_round_pack_canonical(FloatParts64 p, float_status *s, @@ -965,12 +963,11 @@ static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status *s) return bfloat16_pack_raw(&p); } -static FloatParts64 float32_unpack_canonical(float32 f, float_status *s) +static void float32_unpack_canonical(FloatParts64 *p, float32 f, + float_status *s) { - FloatParts64 p; - - float32_unpack_raw(&p, f); - return sf_canonicalize(p, &float32_params, s); + float32_unpack_raw(p, f); + *p = sf_canonicalize(*p, &float32_params, s); } static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) @@ -979,12 +976,11 @@ static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) return float32_pack_raw(&p); } -static FloatParts64 float64_unpack_canonical(float64 f, float_status *s) +static void float64_unpack_canonical(FloatParts64 *p, float64 f, + float_status *s) { - FloatParts64 p; - - float64_unpack_raw(&p, f); - return sf_canonicalize(p, &float64_params, s); + float64_unpack_raw(p, f); + *p = sf_canonicalize(*p, &float64_params, s); } static float64 float64_round_pack_canonical(FloatParts64 p, float_status *s) @@ -1091,18 +1087,22 @@ static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract, float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *status) { - FloatParts64 pa = float16_unpack_canonical(a, status); - FloatParts64 pb = float16_unpack_canonical(b, status); - FloatParts64 pr = addsub_floats(pa, pb, false, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr = addsub_floats(pa, pb, false, status); return float16_round_pack_canonical(pr, status); } float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status) { - FloatParts64 pa = float16_unpack_canonical(a, status); - FloatParts64 pb = float16_unpack_canonical(b, status); - FloatParts64 pr = addsub_floats(pa, pb, true, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr = addsub_floats(pa, pb, true, status); return float16_round_pack_canonical(pr, status); } @@ -1110,9 +1110,11 @@ float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) { - FloatParts64 pa = float32_unpack_canonical(a, status); - FloatParts64 pb = float32_unpack_canonical(b, status); - FloatParts64 pr = addsub_floats(pa, pb, subtract, status); + FloatParts64 pa, pb, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr = addsub_floats(pa, pb, subtract, status); return float32_round_pack_canonical(pr, status); } @@ -1130,9 +1132,11 @@ static inline float32 soft_f32_sub(float32 a, float32 b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) { - FloatParts64 pa = float64_unpack_canonical(a, status); - FloatParts64 pb = float64_unpack_canonical(b, status); - FloatParts64 pr = addsub_floats(pa, pb, subtract, status); + FloatParts64 pa, pb, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = addsub_floats(pa, pb, subtract, status); return float64_round_pack_canonical(pr, status); } @@ -1228,18 +1232,22 @@ float64_sub(float64 a, float64 b, float_status *s) */ bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa = bfloat16_unpack_canonical(a, status); - FloatParts64 pb = bfloat16_unpack_canonical(b, status); - FloatParts64 pr = addsub_floats(pa, pb, false, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr = addsub_floats(pa, pb, false, status); return bfloat16_round_pack_canonical(pr, status); } bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa = bfloat16_unpack_canonical(a, status); - FloatParts64 pb = bfloat16_unpack_canonical(b, status); - FloatParts64 pr = addsub_floats(pa, pb, true, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr = addsub_floats(pa, pb, true, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1297,9 +1305,11 @@ static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s) float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status) { - FloatParts64 pa = float16_unpack_canonical(a, status); - FloatParts64 pb = float16_unpack_canonical(b, status); - FloatParts64 pr = mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr = mul_floats(pa, pb, status); return float16_round_pack_canonical(pr, status); } @@ -1307,9 +1317,11 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_mul(float32 a, float32 b, float_status *status) { - FloatParts64 pa = float32_unpack_canonical(a, status); - FloatParts64 pb = float32_unpack_canonical(b, status); - FloatParts64 pr = mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr = mul_floats(pa, pb, status); return float32_round_pack_canonical(pr, status); } @@ -1317,9 +1329,11 @@ soft_f32_mul(float32 a, float32 b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_mul(float64 a, float64 b, float_status *status) { - FloatParts64 pa = float64_unpack_canonical(a, status); - FloatParts64 pb = float64_unpack_canonical(b, status); - FloatParts64 pr = mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = mul_floats(pa, pb, status); return float64_round_pack_canonical(pr, status); } @@ -1355,9 +1369,11 @@ float64_mul(float64 a, float64 b, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa = bfloat16_unpack_canonical(a, status); - FloatParts64 pb = bfloat16_unpack_canonical(b, status); - FloatParts64 pr = mul_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr = mul_floats(pa, pb, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1551,10 +1567,12 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, int flags, float_status *status) { - FloatParts64 pa = float16_unpack_canonical(a, status); - FloatParts64 pb = float16_unpack_canonical(b, status); - FloatParts64 pc = float16_unpack_canonical(c, status); - FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + float16_unpack_canonical(&pc, c, status); + pr = muladd_floats(pa, pb, pc, flags, status); return float16_round_pack_canonical(pr, status); } @@ -1563,10 +1581,12 @@ static float32 QEMU_SOFTFLOAT_ATTR soft_f32_muladd(float32 a, float32 b, float32 c, int flags, float_status *status) { - FloatParts64 pa = float32_unpack_canonical(a, status); - FloatParts64 pb = float32_unpack_canonical(b, status); - FloatParts64 pc = float32_unpack_canonical(c, status); - FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + float32_unpack_canonical(&pc, c, status); + pr = muladd_floats(pa, pb, pc, flags, status); return float32_round_pack_canonical(pr, status); } @@ -1575,10 +1595,12 @@ static float64 QEMU_SOFTFLOAT_ATTR soft_f64_muladd(float64 a, float64 b, float64 c, int flags, float_status *status) { - FloatParts64 pa = float64_unpack_canonical(a, status); - FloatParts64 pb = float64_unpack_canonical(b, status); - FloatParts64 pc = float64_unpack_canonical(c, status); - FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + float64_unpack_canonical(&pc, c, status); + pr = muladd_floats(pa, pb, pc, flags, status); return float64_round_pack_canonical(pr, status); } @@ -1736,10 +1758,12 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { - FloatParts64 pa = bfloat16_unpack_canonical(a, status); - FloatParts64 pb = bfloat16_unpack_canonical(b, status); - FloatParts64 pc = bfloat16_unpack_canonical(c, status); - FloatParts64 pr = muladd_floats(pa, pb, pc, flags, status); + FloatParts64 pa, pb, pc, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + bfloat16_unpack_canonical(&pc, c, status); + pr = muladd_floats(pa, pb, pc, flags, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1818,9 +1842,11 @@ static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s) float16 float16_div(float16 a, float16 b, float_status *status) { - FloatParts64 pa = float16_unpack_canonical(a, status); - FloatParts64 pb = float16_unpack_canonical(b, status); - FloatParts64 pr = div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float16_unpack_canonical(&pa, a, status); + float16_unpack_canonical(&pb, b, status); + pr = div_floats(pa, pb, status); return float16_round_pack_canonical(pr, status); } @@ -1828,9 +1854,11 @@ float16 float16_div(float16 a, float16 b, float_status *status) static float32 QEMU_SOFTFLOAT_ATTR soft_f32_div(float32 a, float32 b, float_status *status) { - FloatParts64 pa = float32_unpack_canonical(a, status); - FloatParts64 pb = float32_unpack_canonical(b, status); - FloatParts64 pr = div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr = div_floats(pa, pb, status); return float32_round_pack_canonical(pr, status); } @@ -1838,9 +1866,11 @@ soft_f32_div(float32 a, float32 b, float_status *status) static float64 QEMU_SOFTFLOAT_ATTR soft_f64_div(float64 a, float64 b, float_status *status) { - FloatParts64 pa = float64_unpack_canonical(a, status); - FloatParts64 pb = float64_unpack_canonical(b, status); - FloatParts64 pr = div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = div_floats(pa, pb, status); return float64_round_pack_canonical(pr, status); } @@ -1910,9 +1940,11 @@ float64_div(float64 a, float64 b, float_status *s) bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa = bfloat16_unpack_canonical(a, status); - FloatParts64 pb = bfloat16_unpack_canonical(b, status); - FloatParts64 pr = div_floats(pa, pb, status); + FloatParts64 pa, pb, pr; + + bfloat16_unpack_canonical(&pa, a, status); + bfloat16_unpack_canonical(&pb, b, status); + pr = div_floats(pa, pb, status); return bfloat16_round_pack_canonical(pr, status); } @@ -1966,32 +1998,40 @@ static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf, float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p = float16a_unpack_canonical(a, s, fmt16); - FloatParts64 pr = float_to_float(p, &float32_params, s); + FloatParts64 pa, pr; + + float16a_unpack_canonical(&pa, a, s, fmt16); + pr = float_to_float(pa, &float32_params, s); return float32_round_pack_canonical(pr, s); } float64 float16_to_float64(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p = float16a_unpack_canonical(a, s, fmt16); - FloatParts64 pr = float_to_float(p, &float64_params, s); + FloatParts64 pa, pr; + + float16a_unpack_canonical(&pa, a, s, fmt16); + pr = float_to_float(pa, &float64_params, s); return float64_round_pack_canonical(pr, s); } float16 float32_to_float16(float32 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p = float32_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, fmt16, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } static float64 QEMU_SOFTFLOAT_ATTR soft_float32_to_float64(float32 a, float_status *s) { - FloatParts64 p = float32_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, &float64_params, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, &float64_params, s); return float64_round_pack_canonical(pr, s); } @@ -2014,43 +2054,55 @@ float64 float32_to_float64(float32 a, float_status *s) float16 float64_to_float16(float64 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 p = float64_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, fmt16, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, fmt16, s); return float16a_round_pack_canonical(pr, s, fmt16); } float32 float64_to_float32(float64 a, float_status *s) { - FloatParts64 p = float64_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, &float32_params, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, &float32_params, s); return float32_round_pack_canonical(pr, s); } float32 bfloat16_to_float32(bfloat16 a, float_status *s) { - FloatParts64 p = bfloat16_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, &float32_params, s); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, &float32_params, s); return float32_round_pack_canonical(pr, s); } float64 bfloat16_to_float64(bfloat16 a, float_status *s) { - FloatParts64 p = bfloat16_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, &float64_params, s); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, &float64_params, s); return float64_round_pack_canonical(pr, s); } bfloat16 float32_to_bfloat16(float32 a, float_status *s) { - FloatParts64 p = float32_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, &bfloat16_params, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } bfloat16 float64_to_bfloat16(float64 a, float_status *s) { - FloatParts64 p = float64_unpack_canonical(a, s); - FloatParts64 pr = float_to_float(p, &bfloat16_params, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr = float_to_float(pa, &bfloat16_params, s); return bfloat16_round_pack_canonical(pr, s); } @@ -2164,22 +2216,28 @@ static FloatParts64 round_to_int(FloatParts64 a, FloatRoundMode rmode, float16 float16_round_to_int(float16 a, float_status *s) { - FloatParts64 pa = float16_unpack_canonical(a, s); - FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + float16_unpack_canonical(&pa, a, s); + pr = round_to_int(pa, s->float_rounding_mode, 0, s); return float16_round_pack_canonical(pr, s); } float32 float32_round_to_int(float32 a, float_status *s) { - FloatParts64 pa = float32_unpack_canonical(a, s); - FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, s); + pr = round_to_int(pa, s->float_rounding_mode, 0, s); return float32_round_pack_canonical(pr, s); } float64 float64_round_to_int(float64 a, float_status *s) { - FloatParts64 pa = float64_unpack_canonical(a, s); - FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, s); + pr = round_to_int(pa, s->float_rounding_mode, 0, s); return float64_round_pack_canonical(pr, s); } @@ -2190,8 +2248,10 @@ float64 float64_round_to_int(float64 a, float_status *s) bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) { - FloatParts64 pa = bfloat16_unpack_canonical(a, s); - FloatParts64 pr = round_to_int(pa, s->float_rounding_mode, 0, s); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, s); + pr = round_to_int(pa, s->float_rounding_mode, 0, s); return bfloat16_round_pack_canonical(pr, s); } @@ -2253,71 +2313,91 @@ static int64_t round_to_int_and_pack(FloatParts64 in, FloatRoundMode rmode, int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT8_MIN, INT8_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT8_MIN, INT8_MAX, s); } int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } int32_t float16_to_int32_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } int64_t float16_to_int64_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float16_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } int16_t float32_to_int16_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float32_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } int32_t float32_to_int32_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float32_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } int64_t float32_to_int64_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float32_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } int16_t float64_to_int16_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float64_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } int32_t float64_to_int32_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float64_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(float64_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } int8_t float16_to_int8(float16 a, float_status *s) @@ -2423,22 +2503,28 @@ int64_t float64_to_int64_round_to_zero(float64 a, float_status *s) int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, INT16_MIN, INT16_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); } int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, INT32_MIN, INT32_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); } int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_int_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, INT64_MIN, INT64_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); } int16_t bfloat16_to_int16(bfloat16 a, float_status *s) @@ -2532,71 +2618,91 @@ static uint64_t round_to_uint_and_pack(FloatParts64 in, FloatRoundMode rmode, uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT8_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT8_MAX, s); } uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float16_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + float16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } uint16_t float32_to_uint16_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float32_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } uint32_t float32_to_uint32_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float32_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } uint64_t float32_to_uint64_scalbn(float32 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float32_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } uint16_t float64_to_uint16_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float64_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } uint32_t float64_to_uint32_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float64_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(float64_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } uint8_t float16_to_uint8(float16 a, float_status *s) @@ -2702,22 +2808,28 @@ uint64_t float64_to_uint64_round_to_zero(float64 a, float_status *s) uint16_t bfloat16_to_uint16_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, UINT16_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); } uint32_t bfloat16_to_uint32_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, UINT32_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); } uint64_t bfloat16_to_uint64_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, float_status *s) { - return round_to_uint_and_pack(bfloat16_unpack_canonical(a, s), - rmode, scale, UINT64_MAX, s); + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); } uint16_t bfloat16_to_uint16(bfloat16 a, float_status *s) @@ -3168,10 +3280,10 @@ static FloatParts64 minmax_floats(FloatParts64 a, FloatParts64 b, bool ismin, float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float_status *s) \ { \ - FloatParts64 pa = float ## sz ## _unpack_canonical(a, s); \ - FloatParts64 pb = float ## sz ## _unpack_canonical(b, s); \ - FloatParts64 pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - \ + FloatParts64 pa, pb, pr; \ + float ## sz ## _unpack_canonical(&pa, a, s); \ + float ## sz ## _unpack_canonical(&pb, b, s); \ + pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ return float ## sz ## _round_pack_canonical(pr, s); \ } @@ -3201,10 +3313,10 @@ MINMAX(64, maxnummag, false, true, true) #define BF16_MINMAX(name, ismin, isiee, ismag) \ bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ { \ - FloatParts64 pa = bfloat16_unpack_canonical(a, s); \ - FloatParts64 pb = bfloat16_unpack_canonical(b, s); \ - FloatParts64 pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - \ + FloatParts64 pa, pb, pr; \ + bfloat16_unpack_canonical(&pa, a, s); \ + bfloat16_unpack_canonical(&pb, b, s); \ + pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ return bfloat16_round_pack_canonical(pr, s); \ } @@ -3279,8 +3391,9 @@ static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool is_quie static int attr \ name(float ## sz a, float ## sz b, bool is_quiet, float_status *s) \ { \ - FloatParts64 pa = float ## sz ## _unpack_canonical(a, s); \ - FloatParts64 pb = float ## sz ## _unpack_canonical(b, s); \ + FloatParts64 pa, pb; \ + float ## sz ## _unpack_canonical(&pa, a, s); \ + float ## sz ## _unpack_canonical(&pb, b, s); \ return compare_floats(pa, pb, is_quiet, s); \ } @@ -3381,8 +3494,10 @@ FloatRelation float64_compare_quiet(float64 a, float64 b, float_status *s) static FloatRelation QEMU_FLATTEN soft_bf16_compare(bfloat16 a, bfloat16 b, bool is_quiet, float_status *s) { - FloatParts64 pa = bfloat16_unpack_canonical(a, s); - FloatParts64 pb = bfloat16_unpack_canonical(b, s); + FloatParts64 pa, pb; + + bfloat16_unpack_canonical(&pa, a, s); + bfloat16_unpack_canonical(&pb, b, s); return compare_floats(pa, pb, is_quiet, s); } @@ -3416,29 +3531,37 @@ static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status *s) float16 float16_scalbn(float16 a, int n, float_status *status) { - FloatParts64 pa = float16_unpack_canonical(a, status); - FloatParts64 pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + float16_unpack_canonical(&pa, a, status); + pr = scalbn_decomposed(pa, n, status); return float16_round_pack_canonical(pr, status); } float32 float32_scalbn(float32 a, int n, float_status *status) { - FloatParts64 pa = float32_unpack_canonical(a, status); - FloatParts64 pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, status); + pr = scalbn_decomposed(pa, n, status); return float32_round_pack_canonical(pr, status); } float64 float64_scalbn(float64 a, int n, float_status *status) { - FloatParts64 pa = float64_unpack_canonical(a, status); - FloatParts64 pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, status); + pr = scalbn_decomposed(pa, n, status); return float64_round_pack_canonical(pr, status); } bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) { - FloatParts64 pa = bfloat16_unpack_canonical(a, status); - FloatParts64 pr = scalbn_decomposed(pa, n, status); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, status); + pr = scalbn_decomposed(pa, n, status); return bfloat16_round_pack_canonical(pr, status); } @@ -3515,24 +3638,30 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt * float16 QEMU_FLATTEN float16_sqrt(float16 a, float_status *status) { - FloatParts64 pa = float16_unpack_canonical(a, status); - FloatParts64 pr = sqrt_float(pa, status, &float16_params); + FloatParts64 pa, pr; + + float16_unpack_canonical(&pa, a, status); + pr = sqrt_float(pa, status, &float16_params); return float16_round_pack_canonical(pr, status); } static float32 QEMU_SOFTFLOAT_ATTR soft_f32_sqrt(float32 a, float_status *status) { - FloatParts64 pa = float32_unpack_canonical(a, status); - FloatParts64 pr = sqrt_float(pa, status, &float32_params); + FloatParts64 pa, pr; + + float32_unpack_canonical(&pa, a, status); + pr = sqrt_float(pa, status, &float32_params); return float32_round_pack_canonical(pr, status); } static float64 QEMU_SOFTFLOAT_ATTR soft_f64_sqrt(float64 a, float_status *status) { - FloatParts64 pa = float64_unpack_canonical(a, status); - FloatParts64 pr = sqrt_float(pa, status, &float64_params); + FloatParts64 pa, pr; + + float64_unpack_canonical(&pa, a, status); + pr = sqrt_float(pa, status, &float64_params); return float64_round_pack_canonical(pr, status); } @@ -3592,8 +3721,10 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { - FloatParts64 pa = bfloat16_unpack_canonical(a, status); - FloatParts64 pr = sqrt_float(pa, status, &bfloat16_params); + FloatParts64 pa, pr; + + bfloat16_unpack_canonical(&pa, a, status); + pr = sqrt_float(pa, status, &bfloat16_params); return bfloat16_round_pack_canonical(pr, status); } From patchwork Sat May 8 01:47:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432547 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp853271jao; Fri, 7 May 2021 19:12:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzNsrd7OHfk3eds2aBkqfbvActvuwx+LPNv04/6japrkgAUKQ4mO5AOlU4XU5+/ATk7lgBC X-Received: by 2002:a05:6e02:12b3:: with SMTP id f19mr12318672ilr.219.1620439939240; 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envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 131 +++++++++++++++++++++++++----------------------- 1 file changed, 68 insertions(+), 63 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e53d4a138f..b0cbd5941c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -945,22 +945,25 @@ static void bfloat16_unpack_canonical(FloatParts64 *p, bfloat16 f, *p = sf_canonicalize(*p, &bfloat16_params, s); } -static float16 float16a_round_pack_canonical(FloatParts64 p, float_status *s, +static float16 float16a_round_pack_canonical(FloatParts64 *p, + float_status *s, const FloatFmt *params) { - p = round_canonical(p, s, params); - return float16_pack_raw(&p); + *p = round_canonical(*p, s, params); + return float16_pack_raw(p); } -static float16 float16_round_pack_canonical(FloatParts64 p, float_status *s) +static float16 float16_round_pack_canonical(FloatParts64 *p, + float_status *s) { return float16a_round_pack_canonical(p, s, &float16_params); } -static bfloat16 bfloat16_round_pack_canonical(FloatParts64 p, float_status *s) +static bfloat16 bfloat16_round_pack_canonical(FloatParts64 *p, + float_status *s) { - p = round_canonical(p, s, &bfloat16_params); - return bfloat16_pack_raw(&p); + *p = round_canonical(*p, s, &bfloat16_params); + return bfloat16_pack_raw(p); } static void float32_unpack_canonical(FloatParts64 *p, float32 f, @@ -970,10 +973,11 @@ static void float32_unpack_canonical(FloatParts64 *p, float32 f, *p = sf_canonicalize(*p, &float32_params, s); } -static float32 float32_round_pack_canonical(FloatParts64 p, float_status *s) +static float32 float32_round_pack_canonical(FloatParts64 *p, + float_status *s) { - p = round_canonical(p, s, &float32_params); - return float32_pack_raw(&p); + *p = round_canonical(*p, s, &float32_params); + return float32_pack_raw(p); } static void float64_unpack_canonical(FloatParts64 *p, float64 f, @@ -983,10 +987,11 @@ static void float64_unpack_canonical(FloatParts64 *p, float64 f, *p = sf_canonicalize(*p, &float64_params, s); } -static float64 float64_round_pack_canonical(FloatParts64 p, float_status *s) +static float64 float64_round_pack_canonical(FloatParts64 *p, + float_status *s) { - p = round_canonical(p, s, &float64_params); - return float64_pack_raw(&p); + *p = round_canonical(*p, s, &float64_params); + return float64_pack_raw(p); } /* @@ -1093,7 +1098,7 @@ float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *status) float16_unpack_canonical(&pb, b, status); pr = addsub_floats(pa, pb, false, status); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status) @@ -1104,7 +1109,7 @@ float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status) float16_unpack_canonical(&pb, b, status); pr = addsub_floats(pa, pb, true, status); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } static float32 QEMU_SOFTFLOAT_ATTR @@ -1116,7 +1121,7 @@ soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) float32_unpack_canonical(&pb, b, status); pr = addsub_floats(pa, pb, subtract, status); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } static inline float32 soft_f32_add(float32 a, float32 b, float_status *status) @@ -1138,7 +1143,7 @@ soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) float64_unpack_canonical(&pb, b, status); pr = addsub_floats(pa, pb, subtract, status); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } static inline float64 soft_f64_add(float64 a, float64 b, float_status *status) @@ -1238,7 +1243,7 @@ bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *status) bfloat16_unpack_canonical(&pb, b, status); pr = addsub_floats(pa, pb, false, status); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) @@ -1249,7 +1254,7 @@ bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) bfloat16_unpack_canonical(&pb, b, status); pr = addsub_floats(pa, pb, true, status); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } /* @@ -1311,7 +1316,7 @@ float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status) float16_unpack_canonical(&pb, b, status); pr = mul_floats(pa, pb, status); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } static float32 QEMU_SOFTFLOAT_ATTR @@ -1323,7 +1328,7 @@ soft_f32_mul(float32 a, float32 b, float_status *status) float32_unpack_canonical(&pb, b, status); pr = mul_floats(pa, pb, status); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } static float64 QEMU_SOFTFLOAT_ATTR @@ -1335,7 +1340,7 @@ soft_f64_mul(float64 a, float64 b, float_status *status) float64_unpack_canonical(&pb, b, status); pr = mul_floats(pa, pb, status); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } static float hard_f32_mul(float a, float b) @@ -1375,7 +1380,7 @@ bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) bfloat16_unpack_canonical(&pb, b, status); pr = mul_floats(pa, pb, status); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } /* @@ -1574,7 +1579,7 @@ float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, float16_unpack_canonical(&pc, c, status); pr = muladd_floats(pa, pb, pc, flags, status); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } static float32 QEMU_SOFTFLOAT_ATTR @@ -1588,7 +1593,7 @@ soft_f32_muladd(float32 a, float32 b, float32 c, int flags, float32_unpack_canonical(&pc, c, status); pr = muladd_floats(pa, pb, pc, flags, status); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } static float64 QEMU_SOFTFLOAT_ATTR @@ -1602,7 +1607,7 @@ soft_f64_muladd(float64 a, float64 b, float64 c, int flags, float64_unpack_canonical(&pc, c, status); pr = muladd_floats(pa, pb, pc, flags, status); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } static bool force_soft_fma; @@ -1765,7 +1770,7 @@ bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, bfloat16_unpack_canonical(&pc, c, status); pr = muladd_floats(pa, pb, pc, flags, status); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } /* @@ -1848,7 +1853,7 @@ float16 float16_div(float16 a, float16 b, float_status *status) float16_unpack_canonical(&pb, b, status); pr = div_floats(pa, pb, status); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } static float32 QEMU_SOFTFLOAT_ATTR @@ -1860,7 +1865,7 @@ soft_f32_div(float32 a, float32 b, float_status *status) float32_unpack_canonical(&pb, b, status); pr = div_floats(pa, pb, status); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } static float64 QEMU_SOFTFLOAT_ATTR @@ -1872,7 +1877,7 @@ soft_f64_div(float64 a, float64 b, float_status *status) float64_unpack_canonical(&pb, b, status); pr = div_floats(pa, pb, status); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } static float hard_f32_div(float a, float b) @@ -1946,7 +1951,7 @@ bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) bfloat16_unpack_canonical(&pb, b, status); pr = div_floats(pa, pb, status); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } /* @@ -2002,7 +2007,7 @@ float32 float16_to_float32(float16 a, bool ieee, float_status *s) float16a_unpack_canonical(&pa, a, s, fmt16); pr = float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } float64 float16_to_float64(float16 a, bool ieee, float_status *s) @@ -2012,7 +2017,7 @@ float64 float16_to_float64(float16 a, bool ieee, float_status *s) float16a_unpack_canonical(&pa, a, s, fmt16); pr = float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } float16 float32_to_float16(float32 a, bool ieee, float_status *s) @@ -2022,7 +2027,7 @@ float16 float32_to_float16(float32 a, bool ieee, float_status *s) float32_unpack_canonical(&pa, a, s); pr = float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(pr, s, fmt16); + return float16a_round_pack_canonical(&pr, s, fmt16); } static float64 QEMU_SOFTFLOAT_ATTR @@ -2032,7 +2037,7 @@ soft_float32_to_float64(float32 a, float_status *s) float32_unpack_canonical(&pa, a, s); pr = float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } float64 float32_to_float64(float32 a, float_status *s) @@ -2058,7 +2063,7 @@ float16 float64_to_float16(float64 a, bool ieee, float_status *s) float64_unpack_canonical(&pa, a, s); pr = float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(pr, s, fmt16); + return float16a_round_pack_canonical(&pr, s, fmt16); } float32 float64_to_float32(float64 a, float_status *s) @@ -2067,7 +2072,7 @@ float32 float64_to_float32(float64 a, float_status *s) float64_unpack_canonical(&pa, a, s); pr = float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } float32 bfloat16_to_float32(bfloat16 a, float_status *s) @@ -2076,7 +2081,7 @@ float32 bfloat16_to_float32(bfloat16 a, float_status *s) bfloat16_unpack_canonical(&pa, a, s); pr = float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } float64 bfloat16_to_float64(bfloat16 a, float_status *s) @@ -2085,7 +2090,7 @@ float64 bfloat16_to_float64(bfloat16 a, float_status *s) bfloat16_unpack_canonical(&pa, a, s); pr = float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } bfloat16 float32_to_bfloat16(float32 a, float_status *s) @@ -2094,7 +2099,7 @@ bfloat16 float32_to_bfloat16(float32 a, float_status *s) float32_unpack_canonical(&pa, a, s); pr = float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(pr, s); + return bfloat16_round_pack_canonical(&pr, s); } bfloat16 float64_to_bfloat16(float64 a, float_status *s) @@ -2103,7 +2108,7 @@ bfloat16 float64_to_bfloat16(float64 a, float_status *s) float64_unpack_canonical(&pa, a, s); pr = float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(pr, s); + return bfloat16_round_pack_canonical(&pr, s); } /* @@ -2220,7 +2225,7 @@ float16 float16_round_to_int(float16 a, float_status *s) float16_unpack_canonical(&pa, a, s); pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return float16_round_pack_canonical(pr, s); + return float16_round_pack_canonical(&pr, s); } float32 float32_round_to_int(float32 a, float_status *s) @@ -2229,7 +2234,7 @@ float32 float32_round_to_int(float32 a, float_status *s) float32_unpack_canonical(&pa, a, s); pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return float32_round_pack_canonical(pr, s); + return float32_round_pack_canonical(&pr, s); } float64 float64_round_to_int(float64 a, float_status *s) @@ -2238,7 +2243,7 @@ float64 float64_round_to_int(float64 a, float_status *s) float64_unpack_canonical(&pa, a, s); pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return float64_round_pack_canonical(pr, s); + return float64_round_pack_canonical(&pr, s); } /* @@ -2252,7 +2257,7 @@ bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) bfloat16_unpack_canonical(&pa, a, s); pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return bfloat16_round_pack_canonical(pr, s); + return bfloat16_round_pack_canonical(&pr, s); } /* @@ -2898,7 +2903,7 @@ static FloatParts64 int_to_float(int64_t a, int scale, float_status *status) float16 int64_to_float16_scalbn(int64_t a, int scale, float_status *status) { FloatParts64 pa = int_to_float(a, scale, status); - return float16_round_pack_canonical(pa, status); + return float16_round_pack_canonical(&pa, status); } float16 int32_to_float16_scalbn(int32_t a, int scale, float_status *status) @@ -2934,7 +2939,7 @@ float16 int8_to_float16(int8_t a, float_status *status) float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { FloatParts64 pa = int_to_float(a, scale, status); - return float32_round_pack_canonical(pa, status); + return float32_round_pack_canonical(&pa, status); } float32 int32_to_float32_scalbn(int32_t a, int scale, float_status *status) @@ -2965,7 +2970,7 @@ float32 int16_to_float32(int16_t a, float_status *status) float64 int64_to_float64_scalbn(int64_t a, int scale, float_status *status) { FloatParts64 pa = int_to_float(a, scale, status); - return float64_round_pack_canonical(pa, status); + return float64_round_pack_canonical(&pa, status); } float64 int32_to_float64_scalbn(int32_t a, int scale, float_status *status) @@ -3001,7 +3006,7 @@ float64 int16_to_float64(int16_t a, float_status *status) bfloat16 int64_to_bfloat16_scalbn(int64_t a, int scale, float_status *status) { FloatParts64 pa = int_to_float(a, scale, status); - return bfloat16_round_pack_canonical(pa, status); + return bfloat16_round_pack_canonical(&pa, status); } bfloat16 int32_to_bfloat16_scalbn(int32_t a, int scale, float_status *status) @@ -3058,7 +3063,7 @@ static FloatParts64 uint_to_float(uint64_t a, int scale, float_status *status) float16 uint64_to_float16_scalbn(uint64_t a, int scale, float_status *status) { FloatParts64 pa = uint_to_float(a, scale, status); - return float16_round_pack_canonical(pa, status); + return float16_round_pack_canonical(&pa, status); } float16 uint32_to_float16_scalbn(uint32_t a, int scale, float_status *status) @@ -3094,7 +3099,7 @@ float16 uint8_to_float16(uint8_t a, float_status *status) float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *status) { FloatParts64 pa = uint_to_float(a, scale, status); - return float32_round_pack_canonical(pa, status); + return float32_round_pack_canonical(&pa, status); } float32 uint32_to_float32_scalbn(uint32_t a, int scale, float_status *status) @@ -3125,7 +3130,7 @@ float32 uint16_to_float32(uint16_t a, float_status *status) float64 uint64_to_float64_scalbn(uint64_t a, int scale, float_status *status) { FloatParts64 pa = uint_to_float(a, scale, status); - return float64_round_pack_canonical(pa, status); + return float64_round_pack_canonical(&pa, status); } float64 uint32_to_float64_scalbn(uint32_t a, int scale, float_status *status) @@ -3161,7 +3166,7 @@ float64 uint16_to_float64(uint16_t a, float_status *status) bfloat16 uint64_to_bfloat16_scalbn(uint64_t a, int scale, float_status *status) { FloatParts64 pa = uint_to_float(a, scale, status); - return bfloat16_round_pack_canonical(pa, status); + return bfloat16_round_pack_canonical(&pa, status); } bfloat16 uint32_to_bfloat16_scalbn(uint32_t a, int scale, float_status *status) @@ -3284,7 +3289,7 @@ float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ float ## sz ## _unpack_canonical(&pa, a, s); \ float ## sz ## _unpack_canonical(&pb, b, s); \ pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return float ## sz ## _round_pack_canonical(pr, s); \ + return float ## sz ## _round_pack_canonical(&pr, s); \ } MINMAX(16, min, true, false, false) @@ -3317,7 +3322,7 @@ bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ bfloat16_unpack_canonical(&pa, a, s); \ bfloat16_unpack_canonical(&pb, b, s); \ pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return bfloat16_round_pack_canonical(pr, s); \ + return bfloat16_round_pack_canonical(&pr, s); \ } BF16_MINMAX(min, true, false, false) @@ -3535,7 +3540,7 @@ float16 float16_scalbn(float16 a, int n, float_status *status) float16_unpack_canonical(&pa, a, status); pr = scalbn_decomposed(pa, n, status); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } float32 float32_scalbn(float32 a, int n, float_status *status) @@ -3544,7 +3549,7 @@ float32 float32_scalbn(float32 a, int n, float_status *status) float32_unpack_canonical(&pa, a, status); pr = scalbn_decomposed(pa, n, status); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } float64 float64_scalbn(float64 a, int n, float_status *status) @@ -3553,7 +3558,7 @@ float64 float64_scalbn(float64 a, int n, float_status *status) float64_unpack_canonical(&pa, a, status); pr = scalbn_decomposed(pa, n, status); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) @@ -3562,7 +3567,7 @@ bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) bfloat16_unpack_canonical(&pa, a, status); pr = scalbn_decomposed(pa, n, status); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } /* @@ -3642,7 +3647,7 @@ float16 QEMU_FLATTEN float16_sqrt(float16 a, float_status *status) float16_unpack_canonical(&pa, a, status); pr = sqrt_float(pa, status, &float16_params); - return float16_round_pack_canonical(pr, status); + return float16_round_pack_canonical(&pr, status); } static float32 QEMU_SOFTFLOAT_ATTR @@ -3652,7 +3657,7 @@ soft_f32_sqrt(float32 a, float_status *status) float32_unpack_canonical(&pa, a, status); pr = sqrt_float(pa, status, &float32_params); - return float32_round_pack_canonical(pr, status); + return float32_round_pack_canonical(&pr, status); } static float64 QEMU_SOFTFLOAT_ATTR @@ -3662,7 +3667,7 @@ soft_f64_sqrt(float64 a, float_status *status) float64_unpack_canonical(&pa, a, status); pr = sqrt_float(pa, status, &float64_params); - return float64_round_pack_canonical(pr, status); + return float64_round_pack_canonical(&pr, status); } float32 QEMU_FLATTEN float32_sqrt(float32 xa, float_status *s) @@ -3725,7 +3730,7 @@ bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) bfloat16_unpack_canonical(&pa, a, status); pr = sqrt_float(pa, status, &bfloat16_params); - return bfloat16_round_pack_canonical(pr, status); + return bfloat16_round_pack_canonical(&pr, status); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432543 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp850827jao; Fri, 7 May 2021 19:08:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJGsJ/LeAb9hGhFYuG2YQ6ztFnoV0qp8C9gyg44LW1FIhuT03t0mVS+1H1vPTWX9+VSd88 X-Received: by 2002:a05:620a:1265:: with SMTP id b5mr13095698qkl.208.1620439691916; Fri, 07 May 2021 19:08:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[209.51.188.17]) by mx.google.com with ESMTPS id g18si5215373qvl.116.2021.05.07.19.08.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:08:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZEzQ62fu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCO3-0005Zk-Am for patch@linaro.org; Fri, 07 May 2021 22:08:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC53-0004GW-6r for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:35 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:41898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4r-0003dA-I6 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:32 -0400 Received: by mail-pl1-x635.google.com with SMTP id z18so2556712plg.8 for ; Fri, 07 May 2021 18:48:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7MJgtQMBS2ngXY709lmeRGrslyeOuJRTB/k5dCBY0b0=; b=ZEzQ62fuZL23i3KzUSjzVnFtRoMPgOLRz60W8vDr/iS/hpaEKguU9nNJbtqx7fos+j UakYvqmu3lgKRABCV3KAi8ie9klJvm0KW6lekdVZ97b+w+gFKDB/w2ztwMVbsty0Y1o1 kapRnJcqpxNGUrHEY7IUYScIqtbrH1Bq4fM7KWMg4hCdISa8I7AFeyMxUdvg1TUE7Jej T2hZyhKHrQlf6NngHDQG+tZ+qmMO7f1WTntO50v1J4hwXR6N9GEGNHp58CcZ4PMtDP4Q /pvWJpVelHzh25NIcy+etZRJHOlm4DCwnRMLFhDfwSWGqUiDtKJNGhogQKSxVxO+KK20 Pzrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7MJgtQMBS2ngXY709lmeRGrslyeOuJRTB/k5dCBY0b0=; b=BMQRvuV7VvUp4R9aaOmK6azY+5R+gBc0VZqCY+dqHe+DYWvFhgJ6KDYTOodan0K8FP v5wZPDogmfcB5Z38bKGeWRwan/Vut0FQ5d/ckhdgtMCW+VcWYg24d5Nc0fY8lDExuPj1 Em1GNFtcDZgRqvi0plZr1pH/McCFnBXSqqEBhEVyXL1H1XSdx/wL8EP5sf+5ROPmg/+K +QHPdUM+1gR3rXfR8WV82AZ5eAN6iboH1oPVK/wN6ED6xZQeR5EQwl/EoQftMLZVZnJF AxbKDasdWD+I9aBNt47mjnThpP81EHTNU/k0VhBmPXdrp6U+jC1jYR+QMywUR/Tj15q7 h2Kw== X-Gm-Message-State: AOAM530tVDyHr+BvmDNumAyxfL6fMGq/TVrC14o8WOG/iUUFtBhEpzQf 1JMngnKJKW3zoccw3gfq4/7Uz9WKA6+pnQ== X-Received: by 2002:a17:90a:6289:: with SMTP id d9mr13725072pjj.84.1620438499617; Fri, 07 May 2021 18:48:19 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 24/72] softfloat: Use pointers with parts_silence_nan Date: Fri, 7 May 2021 18:47:14 -0700 Message-Id: <20210508014802.892561-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, rename to parts64_silence_nan, split out parts_silence_nan_frac, and define a macro for parts_silence_nan. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 16 +++++++++------- fpu/softfloat-specialize.c.inc | 17 +++++++++++------ 2 files changed, 20 insertions(+), 13 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b0cbd5941c..2123453d40 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -657,6 +657,7 @@ static inline float64 float64_pack_raw(const FloatParts64 *p) #include "softfloat-specialize.c.inc" #define parts_default_nan parts64_default_nan +#define parts_silence_nan parts64_silence_nan /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm, @@ -851,7 +852,8 @@ static FloatParts64 return_nan(FloatParts64 a, float_status *s) if (is_snan(a.cls)) { float_raise(float_flag_invalid, s); if (!s->default_nan_mode) { - return parts_silence_nan(a, s); + parts_silence_nan(&a, s); + return a; } } else if (!s->default_nan_mode) { return a; @@ -875,7 +877,7 @@ static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) a = b; } if (is_snan(a.cls)) { - return parts_silence_nan(a, s); + parts_silence_nan(&a, s); } } return a; @@ -916,7 +918,7 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 } if (is_snan(a.cls)) { - return parts_silence_nan(a, s); + parts_silence_nan(&a, s); } return a; } @@ -3801,7 +3803,7 @@ float16 float16_silence_nan(float16 a, float_status *status) float16_unpack_raw(&p, a); p.frac <<= float16_params.frac_shift; - p = parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>= float16_params.frac_shift; return float16_pack_raw(&p); } @@ -3812,7 +3814,7 @@ float32 float32_silence_nan(float32 a, float_status *status) float32_unpack_raw(&p, a); p.frac <<= float32_params.frac_shift; - p = parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>= float32_params.frac_shift; return float32_pack_raw(&p); } @@ -3823,7 +3825,7 @@ float64 float64_silence_nan(float64 a, float_status *status) float64_unpack_raw(&p, a); p.frac <<= float64_params.frac_shift; - p = parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>= float64_params.frac_shift; return float64_pack_raw(&p); } @@ -3834,7 +3836,7 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) bfloat16_unpack_raw(&p, a); p.frac <<= bfloat16_params.frac_shift; - p = parts_silence_nan(p, status); + parts_silence_nan(&p, status); p.frac >>= bfloat16_params.frac_shift; return bfloat16_pack_raw(&p); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 085ddea62b..2a1bc66633 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -177,20 +177,25 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | floating-point parts. *----------------------------------------------------------------------------*/ -static FloatParts64 parts_silence_nan(FloatParts64 a, float_status *status) +static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status) { g_assert(!no_signaling_nans(status)); g_assert(!status->default_nan_mode); /* The only snan_bit_is_one target without default_nan_mode is HPPA. */ if (snan_bit_is_one(status)) { - a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); - a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); + frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); } else { - a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); + frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); } - a.cls = float_class_qnan; - return a; + return frac; +} + +static void parts64_silence_nan(FloatParts64 *p, float_status *status) +{ + p->frac = parts_silence_nan_frac(p->frac, status); + p->cls = float_class_qnan; } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432535 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp848760jao; 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Add frac_hi and frac_lo members to alias frac. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2123453d40..2d6f61ee7a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -511,10 +511,19 @@ static inline __attribute__((unused)) bool is_qnan(FloatClass c) */ typedef struct { - uint64_t frac; - int32_t exp; FloatClass cls; bool sign; + int32_t exp; + union { + /* Routines that know the structure may reference the singular name. */ + uint64_t frac; + /* + * Routines expanded with multiple structures reference "hi" and "lo". + * In this structure, the one word is both highest and lowest. + */ + uint64_t frac_hi; + uint64_t frac_lo; + }; } FloatParts64; #define DECOMPOSED_BINARY_POINT 63 From patchwork Sat May 8 01:47:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432545 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp853210jao; Fri, 7 May 2021 19:12:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0f/kVv/d0bUR3Bpin5BQvLiVwCDb60rWpXvG1IyydlFAIBvoHP8xhGGk9fFEcteYaFFxH X-Received: by 2002:a92:ab01:: with SMTP id v1mr12641076ilh.190.1620439931691; Fri, 07 May 2021 19:12:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439931; cv=none; d=google.com; s=arc-20160816; b=0I8Bsx0lbn0G/RD/MLGUv24pJ+CIPePQFJiv6brJNjfMH2ekpmrH/PciP9fuTFHmOz 9w1btQimwdxt00huW6Fsye3Igzx7Dt7X9Gpv8A9kfu/zEk4334oJXfQ617KdX/Tr8rSQ MriGi6xK9Eav0Z6aKn/wKx0rex8hoyjpmk7ybrqwOCd9Gd6jLTB/pM6B6JLFUOvVbXFF ydNSEpb13xtRAb/EOqVKjfA39XoywVCP7eaqM4PEt2RjRZPKgDfxrU0wNIFKEohC+tot 1grP0a9SA8Y0xXaAwOwCtk7IC8dGbgMBFMjXcAl78JeckKGLpfbPyY9b+XOMyFKkmFW6 IS3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jjUuhoqBIOcy9NWdDiV7IAwahvxH3LtTBG8RuCBSSl8=; b=SbdkiRmz8E2QLGnpQhlai1tElfAgWKXA/zjRVBTYJhw7nXs3gxBu1DvDhz0mrUL5Rl nF3Bajfmh/NohCdmGyrS/KROnOiMNm7/soCq9bPgA1wwlFicnA9VxgJykWa+Tbz12t66 IYTyPKOqao4Fm7j58fav5F1s+smwwJz+05qgyH+HngnLVTGtw47iQPadezDs0K+pFETo L+ngIM39SK//mhp0dyRYdu1CDsLxol7jkyBcPUjWpnYvW2Cbq1FKSGO/qv6z0BJgUFRS vhy0nAnxXruh3umDS5dEWJE4iQ/5usettLz3TZAozHHNqWsbwtF6be+NDikv14SIlxZN s26Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zJ6g6v9l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 96 +++++++++++++++++++++++++++++----- fpu/softfloat-specialize.c.inc | 25 +++------ 2 files changed, 89 insertions(+), 32 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2d6f61ee7a..073b80d502 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -500,14 +500,12 @@ static inline __attribute__((unused)) bool is_qnan(FloatClass c) } /* - * Structure holding all of the decomposed parts of a float. The - * exponent is unbiased and the fraction is normalized. All - * calculations are done with a 64 bit fraction and then rounded as - * appropriate for the final format. + * Structure holding all of the decomposed parts of a float. + * The exponent is unbiased and the fraction is normalized. * - * Thanks to the packed FloatClass a decent compiler should be able to - * fit the whole structure into registers and avoid using the stack - * for parameter passing. + * The fraction words are stored in big-endian word ordering, + * so that truncation from a larger format to a smaller format + * can be done simply by ignoring subsequent elements. */ typedef struct { @@ -526,6 +524,15 @@ typedef struct { }; } FloatParts64; +typedef struct { + FloatClass cls; + bool sign; + int32_t exp; + uint64_t frac_hi; + uint64_t frac_lo; +} FloatParts128; + +/* These apply to the most significant word of each FloatPartsN. */ #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) @@ -561,11 +568,11 @@ typedef struct { .exp_bias = ((1 << E) - 1) >> 1, \ .exp_max = (1 << E) - 1, \ .frac_size = F, \ - .frac_shift = DECOMPOSED_BINARY_POINT - F, \ - .frac_lsb = 1ull << (DECOMPOSED_BINARY_POINT - F), \ - .frac_lsbm1 = 1ull << ((DECOMPOSED_BINARY_POINT - F) - 1), \ - .round_mask = (1ull << (DECOMPOSED_BINARY_POINT - F)) - 1, \ - .roundeven_mask = (2ull << (DECOMPOSED_BINARY_POINT - F)) - 1 + .frac_shift = (-F - 1) & 63, \ + .frac_lsb = 1ull << ((-F - 1) & 63), \ + .frac_lsbm1 = 1ull << ((-F - 2) & 63), \ + .round_mask = (1ull << ((-F - 1) & 63)) - 1, \ + .roundeven_mask = (2ull << ((-F - 1) & 63)) - 1 static const FloatFmt float16_params = { FLOAT_PARAMS(5, 10) @@ -588,6 +595,10 @@ static const FloatFmt float64_params = { FLOAT_PARAMS(11, 52) }; +static const FloatFmt float128_params = { + FLOAT_PARAMS(15, 112) +}; + /* Unpack a float to parts, but do not canonicalize. */ static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t raw) { @@ -622,6 +633,20 @@ static inline void float64_unpack_raw(FloatParts64 *p, float64 f) unpack_raw64(p, &float64_params, f); } +static void float128_unpack_raw(FloatParts128 *p, float128 f) +{ + const int f_size = float128_params.frac_size - 64; + const int e_size = float128_params.exp_size; + + *p = (FloatParts128) { + .cls = float_class_unclassified, + .sign = extract64(f.high, f_size + e_size, 1), + .exp = extract64(f.high, f_size, e_size), + .frac_hi = extract64(f.high, 0, f_size), + .frac_lo = f.low, + }; +} + /* Pack a float from parts, but do not canonicalize. */ static uint64_t pack_raw64(const FloatParts64 *p, const FloatFmt *fmt) { @@ -655,6 +680,18 @@ static inline float64 float64_pack_raw(const FloatParts64 *p) return make_float64(pack_raw64(p, &float64_params)); } +static float128 float128_pack_raw(const FloatParts128 *p) +{ + const int f_size = float128_params.frac_size - 64; + const int e_size = float128_params.exp_size; + uint64_t hi; + + hi = (uint64_t)p->sign << (f_size + e_size); + hi = deposit64(hi, f_size, e_size, p->exp); + hi = deposit64(hi, 0, f_size, p->frac_hi); + return make_float128(hi, p->frac_lo); +} + /*---------------------------------------------------------------------------- | Functions and definitions to determine: (1) whether tininess for underflow | is detected before or after rounding by default, (2) what (if anything) @@ -665,8 +702,30 @@ static inline float64 float64_pack_raw(const FloatParts64 *p) *----------------------------------------------------------------------------*/ #include "softfloat-specialize.c.inc" +#define PARTS_GENERIC_64_128(NAME, P) \ + QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME) + #define parts_default_nan parts64_default_nan -#define parts_silence_nan parts64_silence_nan +#define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P, S) + + +/* + * Helper functions for softfloat-parts.c.inc, per-size operations. + */ + +static void frac128_shl(FloatParts128 *a, int c) +{ + shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); +} + +#define frac_shl(A, C) frac128_shl(A, C) + +static void frac128_shr(FloatParts128 *a, int c) +{ + shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); +} + +#define frac_shr(A, C) frac128_shr(A, C) /* Canonicalize EXP and FRAC, setting CLS. */ static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm, @@ -3850,6 +3909,17 @@ bfloat16 bfloat16_silence_nan(bfloat16 a, float_status *status) return bfloat16_pack_raw(&p); } +float128 float128_silence_nan(float128 a, float_status *status) +{ + FloatParts128 p; + + float128_unpack_raw(&p, a); + frac_shl(&p, float128_params.frac_shift); + parts_silence_nan(&p, status); + frac_shr(&p, float128_params.frac_shift); + return float128_pack_raw(&p); +} + /*---------------------------------------------------------------------------- | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the value. diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2a1bc66633..d892016f0f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -198,6 +198,12 @@ static void parts64_silence_nan(FloatParts64 *p, float_status *status) p->cls = float_class_qnan; } +static void parts128_silence_nan(FloatParts128 *p, float_status *status) +{ + p->frac_hi = parts_silence_nan_frac(p->frac_hi, status); + p->cls = float_class_qnan; +} + /*---------------------------------------------------------------------------- | The pattern for a default generated extended double-precision NaN. *----------------------------------------------------------------------------*/ @@ -1057,25 +1063,6 @@ bool float128_is_signaling_nan(float128 a, float_status *status) } } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN from a signalling NaN for the quadruple-precision -| floating point value `a'. -*----------------------------------------------------------------------------*/ - -float128 float128_silence_nan(float128 a, float_status *status) -{ - if (no_signaling_nans(status)) { - g_assert_not_reached(); - } else { - if (snan_bit_is_one(status)) { - return float128_default_nan(status); - } else { - a.high |= UINT64_C(0x0000800000000000); - return a; - } - } -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point NaN | `a' to the canonical NaN format. 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Fri, 07 May 2021 18:48:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 27/72] softfloat: Convert float128_default_nan to parts Date: Fri, 7 May 2021 18:47:17 -0700 Message-Id: <20210508014802.892561-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 17 ++++------------- fpu/softfloat-specialize.c.inc | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+), 13 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 073b80d502..6d5392aeab 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -705,7 +705,7 @@ static float128 float128_pack_raw(const FloatParts128 *p) #define PARTS_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME) -#define parts_default_nan parts64_default_nan +#define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P, S) #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P, S) @@ -3836,20 +3836,11 @@ float64 float64_default_nan(float_status *status) float128 float128_default_nan(float_status *status) { - FloatParts64 p; - float128 r; + FloatParts128 p; parts_default_nan(&p, status); - /* Extrapolate from the choices made by parts_default_nan to fill - * in the quad-floating format. If the low bit is set, assume we - * want to set all non-snan bits. - */ - r.low = -(p.frac & 1); - r.high = p.frac >> (DECOMPOSED_BINARY_POINT - 48); - r.high |= UINT64_C(0x7FFF000000000000); - r.high |= (uint64_t)p.sign << 63; - - return r; + frac_shr(&p, float128_params.frac_shift); + return float128_pack_raw(&p); } bfloat16 bfloat16_default_nan(float_status *status) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d892016f0f..a0cf016b4f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -172,6 +172,25 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) }; } +static void parts128_default_nan(FloatParts128 *p, float_status *status) +{ + /* + * Extrapolate from the choices made by parts64_default_nan to fill + * in the quad-floating format. If the low bit is set, assume we + * want to set all non-snan bits. + */ + FloatParts64 p64; + parts64_default_nan(&p64, status); + + *p = (FloatParts128) { + .cls = float_class_qnan, + .sign = p64.sign, + .exp = INT_MAX, + .frac_hi = p64.frac, + .frac_lo = -(p64.frac & 1) + }; +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN from a signalling NaN for the deconstructed | floating-point parts. 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[209.51.188.17]) by mx.google.com with ESMTPS id t16si9987901iov.11.2021.05.07.19.14.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:14:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b+2D+jy4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55180 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCUK-0008Df-AD for patch@linaro.org; Fri, 07 May 2021 22:14:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC58-0004Tv-Nj for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:38 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:40947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4t-0003e8-EE for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:38 -0400 Received: by mail-pl1-x634.google.com with SMTP id n16so6142830plf.7 for ; Fri, 07 May 2021 18:48:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wdvnl/BT8EpxSM2u6kGkXFgWaAcTOrO0eZtHA1yV7g8=; b=b+2D+jy47RtHzEaXEdKXxMlpv4MRONgMNHezoqY4AQqlpdHZ5NkJQqbpksVk2+S6e2 hIQaBQP7qqf9Dsz/akYSa9A++AJCie471KE8pFZjGNJ8pvM0MRvHasgZRjjintPWCGKl oa0hsz5QRudTmR3+Xcd1y5hw8ybHjjllGFwv8bZeVbLO3Apr8yej0UpvAbYtJJcapysT o6XwM5gtpCt64m1jxCsW+prlM1Eif2RqyQX7HXVorU1lLVKAb7GEC9AmFqAQbsZ+zTuh gJ0N0jzakBTKXX57gdFC+rcE+bG1fehX4BwQHJrboLrxMAtARkpIKjy44l7riC3X8i+n cmXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wdvnl/BT8EpxSM2u6kGkXFgWaAcTOrO0eZtHA1yV7g8=; b=fRN/jfiSUW7ARG7agnJrBClyLrALEz1i2b5FgAENF//0DGsCz1oD9Rsu4MFa1rbskI cWHzyltYGVkBaJLSEz+GgMiKjGdfgPsZCMRXkZOLxkjFJYmHdc2HBOK8AcPYkL+HFl1w EpCqPf1mq4R+L7kZaGtoShrtygZebWvl6/nqYAKwX39FpyKak0vOG/pSYa04sd6n8zHz dwxTgiRqfT+XdGIvOt4Z+/IpEjgWURwswb/zgPwuxtaFuRQmlcZXqmQ6u2XgaGbTTUDh d51RS/2iwwtgtvyNaTv7lK5cwl0irT8Rc08JL0iQXaeW6/bfF/hGAmuFZYJO9V+2Exj5 VyQg== X-Gm-Message-State: AOAM531k390MdhUizjnd0RGXPFaz2A6k8SGTcydioSTJVJEY7HFFwRMu TPtpn/GDJUsK8j/Gd79bQOTf25XA7p5JBQ== X-Received: by 2002:a17:90a:73c4:: with SMTP id n4mr25581579pjk.201.1620438501965; Fri, 07 May 2021 18:48:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 28/72] softfloat: Move return_nan to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:18 -0700 Message-Id: <20210508014802.892561-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, convert to pointers, rename to return_nan$N and define a macro for return_nan using QEMU_GENERIC. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 45 ++++++++++++++++++++++----------------- fpu/softfloat-parts.c.inc | 37 ++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 20 deletions(-) create mode 100644 fpu/softfloat-parts.c.inc -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6d5392aeab..5b26696078 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -708,6 +708,10 @@ static float128 float128_pack_raw(const FloatParts128 *p) #define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P, S) #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P, S) +static void parts64_return_nan(FloatParts64 *a, float_status *s); +static void parts128_return_nan(FloatParts128 *a, float_status *s); + +#define parts_return_nan(P, S) PARTS_GENERIC_64_128(return_nan, P)(P, S) /* * Helper functions for softfloat-parts.c.inc, per-size operations. @@ -914,22 +918,6 @@ static FloatParts64 round_canonical(FloatParts64 p, float_status *s, return p; } -static FloatParts64 return_nan(FloatParts64 a, float_status *s) -{ - g_assert(is_nan(a.cls)); - if (is_snan(a.cls)) { - float_raise(float_flag_invalid, s); - if (!s->default_nan_mode) { - parts_silence_nan(&a, s); - return a; - } - } else if (!s->default_nan_mode) { - return a; - } - parts_default_nan(&a, s); - return a; -} - static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) { if (is_snan(a.cls) || is_snan(b.cls)) { @@ -991,6 +979,21 @@ static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 return a; } +#define partsN(NAME) parts64_##NAME +#define FloatPartsN FloatParts64 + +#include "softfloat-parts.c.inc" + +#undef partsN +#undef FloatPartsN +#define partsN(NAME) parts128_##NAME +#define FloatPartsN FloatParts128 + +#include "softfloat-parts.c.inc" + +#undef partsN +#undef FloatPartsN + /* * Pack/unpack routines with a specific FloatFmt. */ @@ -2065,7 +2068,7 @@ static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf, break; } } else if (is_nan(a.cls)) { - return return_nan(a, s); + parts_return_nan(&a, s); } return a; } @@ -2194,7 +2197,8 @@ static FloatParts64 round_to_int(FloatParts64 a, FloatRoundMode rmode, switch (a.cls) { case float_class_qnan: case float_class_snan: - return return_nan(a, s); + parts_return_nan(&a, s); + break; case float_class_zero: case float_class_inf: @@ -3590,7 +3594,7 @@ FloatRelation bfloat16_compare_quiet(bfloat16 a, bfloat16 b, float_status *s) static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status *s) { if (unlikely(is_nan(a.cls))) { - return return_nan(a, s); + parts_return_nan(&a, s); } if (a.cls == float_class_normal) { /* The largest float type (even though not supported by FloatParts64) @@ -3658,7 +3662,8 @@ static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt * int bit, last_bit; if (is_nan(a.cls)) { - return return_nan(a, s); + parts_return_nan(&a, s); + return a; } if (a.cls == float_class_zero) { return a; /* sqrt(+-0) = +-0 */ diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc new file mode 100644 index 0000000000..2a3075d6fe --- /dev/null +++ b/fpu/softfloat-parts.c.inc @@ -0,0 +1,37 @@ +/* + * QEMU float support + * + * The code in this source file is derived from release 2a of the SoftFloat + * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and + * some later contributions) are provided under that license, as detailed below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file after December 1st 2014 will be + * taken to be licensed under the Softfloat-2a license unless specifically + * indicated otherwise. + */ + +static void partsN(return_nan)(FloatPartsN *a, float_status *s) +{ + switch (a->cls) { + case float_class_snan: + float_raise(float_flag_invalid, s); + if (s->default_nan_mode) { + parts_default_nan(a, s); + } else { + parts_silence_nan(a, s); + } + break; + case float_class_qnan: + if (s->default_nan_mode) { + parts_default_nan(a, s); + } + break; + default: + g_assert_not_reached(); + } +} From patchwork Sat May 8 01:47:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432550 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp854612jao; Fri, 7 May 2021 19:15:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw+yfIkVFVWRjctFNH2dIQdG1j6yTmBtHIo3SrspJNseu+ftwdGRQdBLX54Yegatg3AX7M2 X-Received: by 2002:a02:6d6c:: with SMTP id e44mr11396592jaf.81.1620440100586; Fri, 07 May 2021 19:15:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440100; cv=none; d=google.com; s=arc-20160816; b=ttQdQeUTCz6ONMZjV68mtLZ5ZXRvAiZIzvpQQhM6v1UCrZOMxmRvQMM8r8TvSCG+UO la/nnps93Jebup1Vw729Sus0os6jqtQfvAPtWMJkmYTaNAKNochw6zljUIfGnyG+M7Mp 1umbF2JcnesumP49xHdXR0B53LCKfdPUQh+IiUMZCfE2sXe3Jo9DcTRbfHzFhwe6wWe9 5OCIgMSYBTgf/Mt47CBoYfGBny9PHvWtVRg7nY2K+6CCdl2Fkv2Qxdj94s9eQx8DgQep jJrrUDtNTr/srGTRl154DBeT5G8ziqrnNhkNIBYac7T/saRvqiPIuXvE0YxJ5RZVshoV tCMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gajbVTC/w/ZxYm9yG0LEQm64t4i0pLPCyc/kXjmw2Fo=; b=ET/qHbTD34DxvkJyK8gv1i5nZ/Pv3AoZMWfe5/b0LDzxXBLoX8SthBsrZfaK/0sZ3l CViIIznxHrIXQdLHj+ze7IKHPbSTR87ztTdNoM3kbW5wqwND6/9ioLIwLgB4/2h2iC59 YRZWPMk1mLWwxZXZrWF+LMdBjCOAEV/peRf/xsjKI1g9Ni3WXWdGe4L+DvIFWXEp31WP EcAu3s2eXBx7P0C0i6YdsMqLeQFJov90sCcII7zXGz6M5CqHZop3hjBbmTmaU4n1btLE O8w0iLBjJmK3GPeaYQFMBqwJXH9Hcpe+cfngo8Wh4nSTAfS7G1uab4YLNS4BNtHUGMDR 5oaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rN6OohNK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z25si8835722ior.21.2021.05.07.19.15.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:15:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rN6OohNK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCUc-0000B4-A9 for patch@linaro.org; Fri, 07 May 2021 22:15:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40910) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC59-0004Wh-D0 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:39 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:39665) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4u-0003eF-OP for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:39 -0400 Received: by mail-pf1-x42d.google.com with SMTP id c17so9137550pfn.6 for ; Fri, 07 May 2021 18:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gajbVTC/w/ZxYm9yG0LEQm64t4i0pLPCyc/kXjmw2Fo=; b=rN6OohNKRX89WzvH5Xl4isUTNIxNQOXI3rrki+GhMOWVqb+51SMd9CJzW0FSZxFh/Y IlJALOuzrNKYJhuPJ0z5rAPtEXYvNBqDzlerZWn+nbpNmoVFrfgaqTozyLhydh0Vq5fz FucrUTs9pjb9DD87pm21Mh9NS+kYBazbo6p7EgAJBGz4LDogHqefT9kavPyGL9SOIRKm qgNPGsR4Wys9FbYxRlxHU2Imn9msMr2QHhe7/T5t8MvR7/F0UgnMROEIb4WsDsTrMoqj l4mfxnhmLe7+zSAEEOejM7byk2AthM9Ty253SmN6gpAVVedWP7Ja4XztTINbseA37BEv fjJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gajbVTC/w/ZxYm9yG0LEQm64t4i0pLPCyc/kXjmw2Fo=; b=hyRLpPKJAsqi//cRECxbacwGKA+QCYhGMvbUXVDvzdtoORovbHB1eflzlTav8cyQgL GBNOcDTrBYJNmhkbEaFfjbQirpsUzvPbENK4EVIS1207azuIAbb/D7AgM1ium9uEDw+9 M+qrRPM6eBzsYoMrF5mlqclFdftuge45rR2U//D5Gsk73eJGtmk8ybB05N374R9n9F05 3IQUqsOKvsxHHkJ9tEzPf9q4HhvOX+ydoPHlqcd6/rXHApr5tID0/nptqZmvs50i8k2r lRs+BE69SXxYY3SHXkIBSHpLIgYHmzftaplCQ6FPuiZamTP/qP7y3GEGaaSjfEi83u3X uvKg== X-Gm-Message-State: AOAM533Z97lN81ZWF6g/lCese/iuFIG+P2zVwgMxW/m/JGkOeYVynxBL E7hQnmuX4dn67tR4xIu+kYaJtpAdIPsbFg== X-Received: by 2002:a62:d108:0:b029:25d:497e:2dfd with SMTP id z8-20020a62d1080000b029025d497e2dfdmr13570459pfg.29.1620438502595; Fri, 07 May 2021 18:48:22 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 29/72] softfloat: Move pick_nan to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:19 -0700 Message-Id: <20210508014802.892561-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, convert to pointers, rename to parts$N_pick_nan and define a macro for parts_pick_nan using QEMU_GENERIC. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 62 ++++++++++++++++++++++----------------- fpu/softfloat-parts.c.inc | 25 ++++++++++++++++ 2 files changed, 60 insertions(+), 27 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5b26696078..77efaedeaa 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -713,10 +713,39 @@ static void parts128_return_nan(FloatParts128 *a, float_status *s); #define parts_return_nan(P, S) PARTS_GENERIC_64_128(return_nan, P)(P, S) +static FloatParts64 *parts64_pick_nan(FloatParts64 *a, FloatParts64 *b, + float_status *s); +static FloatParts128 *parts128_pick_nan(FloatParts128 *a, FloatParts128 *b, + float_status *s); + +#define parts_pick_nan(A, B, S) PARTS_GENERIC_64_128(pick_nan, A)(A, B, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ +#define FRAC_GENERIC_64_128(NAME, P) \ + QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) + +static int frac64_cmp(FloatParts64 *a, FloatParts64 *b) +{ + return a->frac == b->frac ? 0 : a->frac < b->frac ? -1 : 1; +} + +static int frac128_cmp(FloatParts128 *a, FloatParts128 *b) +{ + uint64_t ta = a->frac_hi, tb = b->frac_hi; + if (ta == tb) { + ta = a->frac_lo, tb = b->frac_lo; + if (ta == tb) { + return 0; + } + } + return ta < tb ? -1 : 1; +} + +#define frac_cmp(A, B) FRAC_GENERIC_64_128(cmp, A)(A, B) + static void frac128_shl(FloatParts128 *a, int c) { shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); @@ -918,27 +947,6 @@ static FloatParts64 round_canonical(FloatParts64 p, float_status *s, return p; } -static FloatParts64 pick_nan(FloatParts64 a, FloatParts64 b, float_status *s) -{ - if (is_snan(a.cls) || is_snan(b.cls)) { - float_raise(float_flag_invalid, s); - } - - if (s->default_nan_mode) { - parts_default_nan(&a, s); - } else { - if (pickNaN(a.cls, b.cls, - a.frac > b.frac || - (a.frac == b.frac && a.sign < b.sign), s)) { - a = b; - } - if (is_snan(a.cls)) { - parts_silence_nan(&a, s); - } - } - return a; -} - static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 c, bool inf_zero, float_status *s) { @@ -1106,7 +1114,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract, return a; } if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } if (a.cls == float_class_inf) { if (b.cls == float_class_inf) { @@ -1144,7 +1152,7 @@ static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract, return a; } if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } if (a.cls == float_class_inf || b.cls == float_class_zero) { return a; @@ -1360,7 +1368,7 @@ static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s) } /* handle all the NaN cases */ if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } /* Inf * Zero == NaN */ if ((a.cls == float_class_inf && b.cls == float_class_zero) || @@ -1887,7 +1895,7 @@ static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s) } /* handle all the NaN cases */ if (is_nan(a.cls) || is_nan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } /* 0/0 or Inf/Inf */ if (a.cls == b.cls @@ -3295,14 +3303,14 @@ static FloatParts64 minmax_floats(FloatParts64 a, FloatParts64 b, bool ismin, * the invalid exception is raised. */ if (is_snan(a.cls) || is_snan(b.cls)) { - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } else if (is_nan(a.cls) && !is_nan(b.cls)) { return b; } else if (is_nan(b.cls) && !is_nan(a.cls)) { return a; } } - return pick_nan(a, b, s); + return *parts_pick_nan(&a, &b, s); } else { int a_exp, b_exp; diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 2a3075d6fe..11a71650f7 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -35,3 +35,28 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) g_assert_not_reached(); } } + +static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, + float_status *s) +{ + if (is_snan(a->cls) || is_snan(b->cls)) { + float_raise(float_flag_invalid, s); + } + + if (s->default_nan_mode) { + parts_default_nan(a, s); + } else { + int cmp = frac_cmp(a, b); + if (cmp == 0) { + cmp = a->sign < b->sign; + } + + if (pickNaN(a->cls, b->cls, cmp > 0, s)) { + a = b; + } + if (is_snan(a->cls)) { + parts_silence_nan(a, s); + } + } + return a; +} From patchwork Sat May 8 01:47:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432531 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp845873jao; Fri, 7 May 2021 18:59:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3vjqotckL70KfHxstbc0Rt61LqqMTiVevcv/d8M1LMr1OvVMbpikea+N68n2gOEEwL5py X-Received: by 2002:a05:6602:2d8f:: with SMTP id k15mr9829155iow.114.1620439180616; Fri, 07 May 2021 18:59:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439180; cv=none; d=google.com; s=arc-20160816; b=QaA09tlI6CZu6Q12IvFIs81ur5vGFs69EL3QivKqFTdN9HCUclkHuN3TiHTBWxLq52 UHnBUN5pWZhFuPIjGN1ZtrclJwQi/tA8vGcdFmSzdPqvRKYprvdgBNPZuZVsdhVATwze lwwCjy0D49llGEZZMbbUDS5z2ln6q+8E+1ainMK61ewCwwSgYvbNjAFjiZOYaDJjT0CA fZqKIzL6rp2FzWIJr9kgRp4nj7qO+uKPLHFwKjquv1j4np2echZDskaULPbsY0cKwVmX Oe5jUACi0ePwd61GaYh2KVHh7XiIM1VO79pGNFlPbBj2AuwwEXfU3mP0EqGxqoSE1Zqx SCbA== ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 53 ++++++++++----------------------------- fpu/softfloat-parts.c.inc | 40 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 40 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 77efaedeaa..40ee294e35 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -720,6 +720,18 @@ static FloatParts128 *parts128_pick_nan(FloatParts128 *a, FloatParts128 *b, #define parts_pick_nan(A, B, S) PARTS_GENERIC_64_128(pick_nan, A)(A, B, S) +static FloatParts64 *parts64_pick_nan_muladd(FloatParts64 *a, FloatParts64 *b, + FloatParts64 *c, float_status *s, + int ab_mask, int abc_mask); +static FloatParts128 *parts128_pick_nan_muladd(FloatParts128 *a, + FloatParts128 *b, + FloatParts128 *c, + float_status *s, + int ab_mask, int abc_mask); + +#define parts_pick_nan_muladd(A, B, C, S, ABM, ABCM) \ + PARTS_GENERIC_64_128(pick_nan_muladd, A)(A, B, C, S, ABM, ABCM) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -947,45 +959,6 @@ static FloatParts64 round_canonical(FloatParts64 p, float_status *s, return p; } -static FloatParts64 pick_nan_muladd(FloatParts64 a, FloatParts64 b, FloatParts64 c, - bool inf_zero, float_status *s) -{ - int which; - - if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) { - float_raise(float_flag_invalid, s); - } - - which = pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s); - - if (s->default_nan_mode) { - /* Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag. - */ - which = 3; - } - - switch (which) { - case 0: - break; - case 1: - a = b; - break; - case 2: - a = c; - break; - case 3: - parts_default_nan(&a, s); - break; - default: - g_assert_not_reached(); - } - - if (is_snan(a.cls)) { - parts_silence_nan(&a, s); - } - return a; -} #define partsN(NAME) parts64_##NAME #define FloatPartsN FloatParts64 @@ -1496,7 +1469,7 @@ static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c * off to the target-specific pick-a-NaN routine. */ if (unlikely(abc_mask & float_cmask_anynan)) { - return pick_nan_muladd(a, b, c, inf_zero, s); + return *parts_pick_nan_muladd(&a, &b, &c, s, ab_mask, abc_mask); } if (inf_zero) { diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 11a71650f7..a78d61ea07 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -60,3 +60,43 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, } return a; } + +static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, + FloatPartsN *c, float_status *s, + int ab_mask, int abc_mask) +{ + int which; + + if (unlikely(abc_mask & float_cmask_snan)) { + float_raise(float_flag_invalid, s); + } + + which = pickNaNMulAdd(a->cls, b->cls, c->cls, + ab_mask == float_cmask_infzero, s); + + if (s->default_nan_mode || which == 3) { + /* + * Note that this check is after pickNaNMulAdd so that function + * has an opportunity to set the Invalid flag for infzero. + */ + parts_default_nan(a, s); + return a; + } + + switch (which) { + case 0: + break; + case 1: + a = b; + break; + case 2: + a = c; + break; + default: + g_assert_not_reached(); + } + if (is_snan(a->cls)) { + parts_silence_nan(a, s); + } + return a; +} From patchwork Sat May 8 01:47:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432551 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp854667jao; Fri, 7 May 2021 19:15:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy6IdV9BAPdFng5ibenXramQu6aYKLiExiRG9iReRicvqFO8gvcDi/SwD3hXwclSHFA9p4d X-Received: by 2002:a05:6e02:168f:: with SMTP id f15mr12813469ila.264.1620440107115; Fri, 07 May 2021 19:15:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440107; cv=none; d=google.com; s=arc-20160816; b=w8WhchfhLHE+jkt09rAORYM61UElIP68qD6AgzYPp0Ij3+SYeiPNV1pgyDIF1eCUyu o8+IF7arjIRWo/0S/fSGAj3UEnC6SNslh9KNS04+dZDTEaiMHsYhtcTd6c4EEy8HLjNk mcYXiqcmsP3pUhTDoLr9dll2/Kx2VWf3q/YhAghkoVPr0qkZoV0xHlz4A9My6kjPvQvq eBsTO9rdYvho2ppauvcFwas6iOXxqSkS4VwldwLsgzfegmWo6sEFyW7Ivrvhancg1HTH fR6LJ+XEiP2HNaC46kd2l1QrYtgUoI3WepjffFfUfPfVGN+AkYYvG60nDIz8L2H29Y23 pD8A== ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 117 +++++++++++++++++++++++++------------- fpu/softfloat-parts.c.inc | 33 +++++++++++ 2 files changed, 112 insertions(+), 38 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 40ee294e35..bad4b54cd2 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -732,6 +732,14 @@ static FloatParts128 *parts128_pick_nan_muladd(FloatParts128 *a, #define parts_pick_nan_muladd(A, B, C, S, ABM, ABCM) \ PARTS_GENERIC_64_128(pick_nan_muladd, A)(A, B, C, S, ABM, ABCM) +static void parts64_canonicalize(FloatParts64 *p, float_status *status, + const FloatFmt *fmt); +static void parts128_canonicalize(FloatParts128 *p, float_status *status, + const FloatFmt *fmt); + +#define parts_canonicalize(A, S, F) \ + PARTS_GENERIC_64_128(canonicalize, A)(A, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -758,52 +766,85 @@ static int frac128_cmp(FloatParts128 *a, FloatParts128 *b) #define frac_cmp(A, B) FRAC_GENERIC_64_128(cmp, A)(A, B) +static void frac64_clear(FloatParts64 *a) +{ + a->frac = 0; +} + +static void frac128_clear(FloatParts128 *a) +{ + a->frac_hi = a->frac_lo = 0; +} + +#define frac_clear(A) FRAC_GENERIC_64_128(clear, A)(A) + +static bool frac64_eqz(FloatParts64 *a) +{ + return a->frac == 0; +} + +static bool frac128_eqz(FloatParts128 *a) +{ + return (a->frac_hi | a->frac_lo) == 0; +} + +#define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A) + +static int frac64_normalize(FloatParts64 *a) +{ + if (a->frac) { + int shift = clz64(a->frac); + a->frac <<= shift; + return shift; + } + return 64; +} + +static int frac128_normalize(FloatParts128 *a) +{ + if (a->frac_hi) { + int shl = clz64(a->frac_hi); + if (shl) { + int shr = 64 - shl; + a->frac_hi = (a->frac_hi << shl) | (a->frac_lo >> shr); + a->frac_lo = (a->frac_lo << shl); + } + return shl; + } else if (a->frac_lo) { + int shl = clz64(a->frac_lo); + a->frac_hi = (a->frac_lo << shl); + a->frac_lo = 0; + return shl + 64; + } + return 128; +} + +#define frac_normalize(A) FRAC_GENERIC_64_128(normalize, A)(A) + +static void frac64_shl(FloatParts64 *a, int c) +{ + a->frac <<= c; +} + static void frac128_shl(FloatParts128 *a, int c) { shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); } -#define frac_shl(A, C) frac128_shl(A, C) +#define frac_shl(A, C) FRAC_GENERIC_64_128(shl, A)(A, C) + +static void frac64_shr(FloatParts64 *a, int c) +{ + a->frac >>= c; +} static void frac128_shr(FloatParts128 *a, int c) { shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); } -#define frac_shr(A, C) frac128_shr(A, C) +#define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C) -/* Canonicalize EXP and FRAC, setting CLS. */ -static FloatParts64 sf_canonicalize(FloatParts64 part, const FloatFmt *parm, - float_status *status) -{ - if (part.exp == parm->exp_max && !parm->arm_althp) { - if (part.frac == 0) { - part.cls = float_class_inf; - } else { - part.frac <<= parm->frac_shift; - part.cls = (parts_is_snan_frac(part.frac, status) - ? float_class_snan : float_class_qnan); - } - } else if (part.exp == 0) { - if (likely(part.frac == 0)) { - part.cls = float_class_zero; - } else if (status->flush_inputs_to_zero) { - float_raise(float_flag_input_denormal, status); - part.cls = float_class_zero; - part.frac = 0; - } else { - int shift = clz64(part.frac); - part.cls = float_class_normal; - part.exp = parm->frac_shift - parm->exp_bias - shift + 1; - part.frac <<= shift; - } - } else { - part.cls = float_class_normal; - part.exp -= parm->exp_bias; - part.frac = DECOMPOSED_IMPLICIT_BIT + (part.frac << parm->frac_shift); - } - return part; -} /* Round and uncanonicalize a floating-point number by parts. There * are FRAC_SHIFT bits that may require rounding at the bottom of the @@ -983,7 +1024,7 @@ static void float16a_unpack_canonical(FloatParts64 *p, float16 f, float_status *s, const FloatFmt *params) { float16_unpack_raw(p, f); - *p = sf_canonicalize(*p, params, s); + parts_canonicalize(p, s, params); } static void float16_unpack_canonical(FloatParts64 *p, float16 f, @@ -996,7 +1037,7 @@ static void bfloat16_unpack_canonical(FloatParts64 *p, bfloat16 f, float_status *s) { bfloat16_unpack_raw(p, f); - *p = sf_canonicalize(*p, &bfloat16_params, s); + parts_canonicalize(p, s, &bfloat16_params); } static float16 float16a_round_pack_canonical(FloatParts64 *p, @@ -1024,7 +1065,7 @@ static void float32_unpack_canonical(FloatParts64 *p, float32 f, float_status *s) { float32_unpack_raw(p, f); - *p = sf_canonicalize(*p, &float32_params, s); + parts_canonicalize(p, s, &float32_params); } static float32 float32_round_pack_canonical(FloatParts64 *p, @@ -1038,7 +1079,7 @@ static void float64_unpack_canonical(FloatParts64 *p, float64 f, float_status *s) { float64_unpack_raw(p, f); - *p = sf_canonicalize(*p, &float64_params, s); + parts_canonicalize(p, s, &float64_params); } static float64 float64_round_pack_canonical(FloatParts64 *p, diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a78d61ea07..25bf99bd0f 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -100,3 +100,36 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, } return a; } + +/* + * Canonicalize the FloatParts structure. Determine the class, + * unbias the exponent, and normalize the fraction. + */ +static void partsN(canonicalize)(FloatPartsN *p, float_status *status, + const FloatFmt *fmt) +{ + if (unlikely(p->exp == 0)) { + if (likely(frac_eqz(p))) { + p->cls = float_class_zero; + } else if (status->flush_inputs_to_zero) { + float_raise(float_flag_input_denormal, status); + p->cls = float_class_zero; + frac_clear(p); + } else { + int shift = frac_normalize(p); + p->cls = float_class_normal; + p->exp = fmt->frac_shift - fmt->exp_bias - shift + 1; + } + } else if (likely(p->exp < fmt->exp_max) || fmt->arm_althp) { + p->cls = float_class_normal; + p->exp -= fmt->exp_bias; + frac_shl(p, fmt->frac_shift); + p->frac_hi |= DECOMPOSED_IMPLICIT_BIT; + } else if (likely(frac_eqz(p))) { + p->cls = float_class_inf; + } else { + frac_shl(p, fmt->frac_shift); + p->cls = (parts_is_snan_frac(p->frac_hi, status) + ? float_class_snan : float_class_qnan); + } +} From patchwork Sat May 8 01:47:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432540 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp849917jao; Fri, 7 May 2021 19:06:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyV3PVwUpxq9xA8OOe9dSNNHhjGR2onKu5fdjkLxAe3hCnhKIzhHRMuNsQZCJCeHSa9sAkK X-Received: by 2002:a0c:e50e:: with SMTP id l14mr13396912qvm.52.1620439589425; Fri, 07 May 2021 19:06:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439589; cv=none; d=google.com; s=arc-20160816; b=r0sc4cV0JP4gsc6fgrQyTzgD6jORoibJgRaDQSyVgROqDSapEKnxMe4b3hmhszLc77 OT5q9Bn/IuO6OJ1Kc4jdSm5IvKHKR4Td/ZyPpUNZ4qlrbc/9V/jyy6tHkb6tMLSKkuMP qbW/SUup2aJXUyMA7hI6y+/lMmAC2mIO4zrJmx9A2xEJ/WzOAk48KDVl0oi3X0bnyzvF LFfnZHZ+FZd2SEfWhToCq7jv8dcxHMMjOB5WzW49ecWjUObMRWl2Q0qHqiJHeQigyVfj raDg5T36Q8Q3t0gHN1dujQoz9p/aVfndIsHEBAgq0SrUnQEMMvii/tOQrrjuKT18219M zpWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NGpOakjV0VOj6azWVGKzsBGpzQYOaN2R/8eKbyrZbMU=; b=F6LAvLlPBKYKbaUcBKH2/S26C/4ww3JBNRlMVhbGB0LHd2+DI9EL7aqBGRv/4jPfxn XXsn1ZhxltguIPWNjss1vdcnbmkULjKNZTzl/a5+NtFRCx8D4EStgLnIXMy0cUOz+MvH pxzygnH9MLPQB0PMbYvgMQiHB59tzoRRTkZs7IeNtKPeVYF60drLkyfgKxXko+oA0GZY d1KXN29yB+htL7wB80Sl4o/4YOtww8zqItWKrhyuF/T0P7GTietcCxPZyUSHcdIQD97t Kj/nWJmC8FdABzWZlqlCv/NjGcKMXEiUjgHONOBnAMiSuvwImouk85bfA0CpHtTPF6sw uEWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fLkgAwwH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o4si5071143qvh.161.2021.05.07.19.06.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:06:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fLkgAwwH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCMO-0001tW-PX for patch@linaro.org; Fri, 07 May 2021 22:06:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC5B-0004cm-8n for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:41 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:34603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4w-0003eb-Vn for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:40 -0400 Received: by mail-pj1-x1032.google.com with SMTP id t2-20020a17090a0242b0290155433387beso5535188pje.1 for ; Fri, 07 May 2021 18:48:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NGpOakjV0VOj6azWVGKzsBGpzQYOaN2R/8eKbyrZbMU=; b=fLkgAwwHg5gJQi23BooROnxI7JKl/nKSMGwyBQHIJWLlCJbtySSnOF6L2BOk752N8C P4EA4VdwLdpqlKk8dQOQlD35v+5cIuY96edZVw48Ud+5MyshnbeLJ7iCXjd5WHTv66v/ QKiqulcOHTbSTTL1cT5plxymw0ij6VuuyBe63hLCnyB7e3nNbM9JifLU8//SFY+OP8Lp iNDjz9ROQlgRuRuAFNkAtmwuxO6oWb+ceDJBQeUyxYHZXeeKWMm6U6luAl11/KAfY1NC RUji72/3PxQGye/qpwds8YmnhCkPjdy5GW1xZSx/dUy0+RA2rVwrYZqI0BCuyHqeaYbg m/sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NGpOakjV0VOj6azWVGKzsBGpzQYOaN2R/8eKbyrZbMU=; b=czqD0PycV2Zr9w+Dq14CTUTIBlCnfQTXQh1jVUcvWX8Jprvx2yETzOFe/JnoGSxsmJ 8IzIWNUBxlPTj7evVB6ZPMKZLZoSugdzHnqr/3UTRbO/pln5VsJZjqTxjcWORKlf3Fus Sw1wqOYR0iIruj5fp0VEVLfIkIyz1XxotvDk6xkHewAfWNXkxPPN+YqRSVINbl7fNmf5 g/k3pClN+O+DCb5Of5a+iIGsVpsYClISpC3tdg9KIXOKgVa7GwOshnpmDMHGZO2rym4Y mKiCxY5JIAwkCW8hDdnXcQdi7QQSDS1d1SdHsh3WmF2yPnToV/2e1tuWek+MV07D1O+Z ba9Q== X-Gm-Message-State: AOAM530AVUiGjQ4DbnF/xUF8EbdpoaSCbz+3/ojfpxAJUkj2u8pyQe43 xrgH02BoI8anF6gx4mY7gPYIU5ybXrvSHw== X-Received: by 2002:a17:902:4d:b029:ec:94df:c9aa with SMTP id 71-20020a170902004db02900ec94dfc9aamr13263991pla.7.1620438504470; Fri, 07 May 2021 18:48:24 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 32/72] softfloat: Move round_canonical to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:22 -0700 Message-Id: <20210508014802.892561-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, convert to pointers, renaming to parts$N_uncanon, and define a macro for parts_uncanon using QEMU_GENERIC. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 201 +++++++++----------------------------- fpu/softfloat-parts.c.inc | 148 ++++++++++++++++++++++++++++ 2 files changed, 193 insertions(+), 156 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index bad4b54cd2..e9d644385d 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -740,6 +740,14 @@ static void parts128_canonicalize(FloatParts128 *p, float_status *status, #define parts_canonicalize(A, S, F) \ PARTS_GENERIC_64_128(canonicalize, A)(A, S, F) +static void parts64_uncanon(FloatParts64 *p, float_status *status, + const FloatFmt *fmt); +static void parts128_uncanon(FloatParts128 *p, float_status *status, + const FloatFmt *fmt); + +#define parts_uncanon(A, S, F) \ + PARTS_GENERIC_64_128(uncanon, A)(A, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -747,6 +755,31 @@ static void parts128_canonicalize(FloatParts128 *p, float_status *status, #define FRAC_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) +static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c) +{ + return uadd64_overflow(a->frac, c, &r->frac); +} + +static bool frac128_addi(FloatParts128 *r, FloatParts128 *a, uint64_t c) +{ + c = uadd64_overflow(a->frac_lo, c, &r->frac_lo); + return uadd64_overflow(a->frac_hi, c, &r->frac_hi); +} + +#define frac_addi(R, A, C) FRAC_GENERIC_64_128(addi, R)(R, A, C) + +static void frac64_allones(FloatParts64 *a) +{ + a->frac = -1; +} + +static void frac128_allones(FloatParts128 *a) +{ + a->frac_hi = a->frac_lo = -1; +} + +#define frac_allones(A) FRAC_GENERIC_64_128(allones, A)(A) + static int frac64_cmp(FloatParts64 *a, FloatParts64 *b) { return a->frac == b->frac ? 0 : a->frac < b->frac ? -1 : 1; @@ -845,161 +878,17 @@ static void frac128_shr(FloatParts128 *a, int c) #define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C) - -/* Round and uncanonicalize a floating-point number by parts. There - * are FRAC_SHIFT bits that may require rounding at the bottom of the - * fraction; these bits will be removed. The exponent will be biased - * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. - */ - -static FloatParts64 round_canonical(FloatParts64 p, float_status *s, - const FloatFmt *parm) +static void frac64_shrjam(FloatParts64 *a, int c) { - const uint64_t frac_lsb = parm->frac_lsb; - const uint64_t frac_lsbm1 = parm->frac_lsbm1; - const uint64_t round_mask = parm->round_mask; - const uint64_t roundeven_mask = parm->roundeven_mask; - const int exp_max = parm->exp_max; - const int frac_shift = parm->frac_shift; - uint64_t frac, inc; - int exp, flags = 0; - bool overflow_norm; - - frac = p.frac; - exp = p.exp; - - switch (p.cls) { - case float_class_normal: - switch (s->float_rounding_mode) { - case float_round_nearest_even: - overflow_norm = false; - inc = ((frac & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0); - break; - case float_round_ties_away: - overflow_norm = false; - inc = frac_lsbm1; - break; - case float_round_to_zero: - overflow_norm = true; - inc = 0; - break; - case float_round_up: - inc = p.sign ? 0 : round_mask; - overflow_norm = p.sign; - break; - case float_round_down: - inc = p.sign ? round_mask : 0; - overflow_norm = !p.sign; - break; - case float_round_to_odd: - overflow_norm = true; - inc = frac & frac_lsb ? 0 : round_mask; - break; - default: - g_assert_not_reached(); - } - - exp += parm->exp_bias; - if (likely(exp > 0)) { - if (frac & round_mask) { - flags |= float_flag_inexact; - if (uadd64_overflow(frac, inc, &frac)) { - frac = (frac >> 1) | DECOMPOSED_IMPLICIT_BIT; - exp++; - } - } - frac >>= frac_shift; - - if (parm->arm_althp) { - /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ - if (unlikely(exp > exp_max)) { - /* Overflow. Return the maximum normal. */ - flags = float_flag_invalid; - exp = exp_max; - frac = -1; - } - } else if (unlikely(exp >= exp_max)) { - flags |= float_flag_overflow | float_flag_inexact; - if (overflow_norm) { - exp = exp_max - 1; - frac = -1; - } else { - p.cls = float_class_inf; - goto do_inf; - } - } - } else if (s->flush_to_zero) { - flags |= float_flag_output_denormal; - p.cls = float_class_zero; - goto do_zero; - } else { - bool is_tiny = s->tininess_before_rounding || (exp < 0); - - if (!is_tiny) { - uint64_t discard; - is_tiny = !uadd64_overflow(frac, inc, &discard); - } - - shift64RightJamming(frac, 1 - exp, &frac); - if (frac & round_mask) { - /* Need to recompute round-to-even. */ - switch (s->float_rounding_mode) { - case float_round_nearest_even: - inc = ((frac & roundeven_mask) != frac_lsbm1 - ? frac_lsbm1 : 0); - break; - case float_round_to_odd: - inc = frac & frac_lsb ? 0 : round_mask; - break; - default: - break; - } - flags |= float_flag_inexact; - frac += inc; - } - - exp = (frac & DECOMPOSED_IMPLICIT_BIT ? 1 : 0); - frac >>= frac_shift; - - if (is_tiny && (flags & float_flag_inexact)) { - flags |= float_flag_underflow; - } - if (exp == 0 && frac == 0) { - p.cls = float_class_zero; - } - } - break; - - case float_class_zero: - do_zero: - exp = 0; - frac = 0; - break; - - case float_class_inf: - do_inf: - assert(!parm->arm_althp); - exp = exp_max; - frac = 0; - break; - - case float_class_qnan: - case float_class_snan: - assert(!parm->arm_althp); - exp = exp_max; - frac >>= parm->frac_shift; - break; - - default: - g_assert_not_reached(); - } - - float_raise(flags, s); - p.exp = exp; - p.frac = frac; - return p; + shift64RightJamming(a->frac, c, &a->frac); } +static void frac128_shrjam(FloatParts128 *a, int c) +{ + shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); +} + +#define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C) #define partsN(NAME) parts64_##NAME #define FloatPartsN FloatParts64 @@ -1044,7 +933,7 @@ static float16 float16a_round_pack_canonical(FloatParts64 *p, float_status *s, const FloatFmt *params) { - *p = round_canonical(*p, s, params); + parts_uncanon(p, s, params); return float16_pack_raw(p); } @@ -1057,7 +946,7 @@ static float16 float16_round_pack_canonical(FloatParts64 *p, static bfloat16 bfloat16_round_pack_canonical(FloatParts64 *p, float_status *s) { - *p = round_canonical(*p, s, &bfloat16_params); + parts_uncanon(p, s, &bfloat16_params); return bfloat16_pack_raw(p); } @@ -1071,7 +960,7 @@ static void float32_unpack_canonical(FloatParts64 *p, float32 f, static float32 float32_round_pack_canonical(FloatParts64 *p, float_status *s) { - *p = round_canonical(*p, s, &float32_params); + parts_uncanon(p, s, &float32_params); return float32_pack_raw(p); } @@ -1085,7 +974,7 @@ static void float64_unpack_canonical(FloatParts64 *p, float64 f, static float64 float64_round_pack_canonical(FloatParts64 *p, float_status *s) { - *p = round_canonical(*p, s, &float64_params); + parts_uncanon(p, s, &float64_params); return float64_pack_raw(p); } diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 25bf99bd0f..efdc724770 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -133,3 +133,151 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status, ? float_class_snan : float_class_qnan); } } + +/* + * Round and uncanonicalize a floating-point number by parts. There + * are FRAC_SHIFT bits that may require rounding at the bottom of the + * fraction; these bits will be removed. The exponent will be biased + * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. + */ +static void partsN(uncanon)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt) +{ + const int exp_max = fmt->exp_max; + const int frac_shift = fmt->frac_shift; + const uint64_t frac_lsb = fmt->frac_lsb; + const uint64_t frac_lsbm1 = fmt->frac_lsbm1; + const uint64_t round_mask = fmt->round_mask; + const uint64_t roundeven_mask = fmt->roundeven_mask; + uint64_t inc; + bool overflow_norm; + int exp, flags = 0; + + if (unlikely(p->cls != float_class_normal)) { + switch (p->cls) { + case float_class_zero: + p->exp = 0; + frac_clear(p); + return; + case float_class_inf: + g_assert(!fmt->arm_althp); + p->exp = fmt->exp_max; + frac_clear(p); + return; + case float_class_qnan: + case float_class_snan: + g_assert(!fmt->arm_althp); + p->exp = fmt->exp_max; + frac_shr(p, fmt->frac_shift); + return; + default: + break; + } + g_assert_not_reached(); + } + + switch (s->float_rounding_mode) { + case float_round_nearest_even: + overflow_norm = false; + inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0); + break; + case float_round_ties_away: + overflow_norm = false; + inc = frac_lsbm1; + break; + case float_round_to_zero: + overflow_norm = true; + inc = 0; + break; + case float_round_up: + inc = p->sign ? 0 : round_mask; + overflow_norm = p->sign; + break; + case float_round_down: + inc = p->sign ? round_mask : 0; + overflow_norm = !p->sign; + break; + case float_round_to_odd: + overflow_norm = true; + inc = p->frac_lo & frac_lsb ? 0 : round_mask; + break; + default: + g_assert_not_reached(); + } + + exp = p->exp + fmt->exp_bias; + if (likely(exp > 0)) { + if (p->frac_lo & round_mask) { + flags |= float_flag_inexact; + if (frac_addi(p, p, inc)) { + frac_shr(p, 1); + p->frac_hi |= DECOMPOSED_IMPLICIT_BIT; + exp++; + } + } + frac_shr(p, frac_shift); + + if (fmt->arm_althp) { + /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ + if (unlikely(exp > exp_max)) { + /* Overflow. Return the maximum normal. */ + flags = float_flag_invalid; + exp = exp_max; + frac_allones(p); + } + } else if (unlikely(exp >= exp_max)) { + flags |= float_flag_overflow | float_flag_inexact; + if (overflow_norm) { + exp = exp_max - 1; + frac_allones(p); + } else { + p->cls = float_class_inf; + exp = exp_max; + frac_clear(p); + } + } + } else if (s->flush_to_zero) { + flags |= float_flag_output_denormal; + p->cls = float_class_zero; + exp = 0; + frac_clear(p); + } else { + bool is_tiny = s->tininess_before_rounding || exp < 0; + + if (!is_tiny) { + FloatPartsN discard; + is_tiny = !frac_addi(&discard, p, inc); + } + + frac_shrjam(p, 1 - exp); + + if (p->frac_lo & round_mask) { + /* Need to recompute round-to-even/round-to-odd. */ + switch (s->float_rounding_mode) { + case float_round_nearest_even: + inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 + ? frac_lsbm1 : 0); + break; + case float_round_to_odd: + inc = p->frac_lo & frac_lsb ? 0 : round_mask; + break; + default: + break; + } + flags |= float_flag_inexact; + frac_addi(p, p, inc); + } + + exp = (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) != 0; + frac_shr(p, frac_shift); + + if (is_tiny && (flags & float_flag_inexact)) { + flags |= float_flag_underflow; + } + if (exp == 0 && frac_eqz(p)) { + p->cls = float_class_zero; + } + } + p->exp = exp; + float_raise(flags, s); +} From patchwork Sat May 8 01:47:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432553 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp855866jao; Fri, 7 May 2021 19:17:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDxbnws0LBd0dHXrAec1MTje1fM/an9wyCQzMyKS0yc1T116K9vEczIRWs5TkP516SyCmD X-Received: by 2002:a05:6e02:1985:: with SMTP id g5mr11943550ilf.103.1620440233317; Fri, 07 May 2021 19:17:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440233; cv=none; d=google.com; s=arc-20160816; b=XqfpVvF1Kx9CeSIgvbkRydDkHM7oOq5V+WJObQkKdaFsXzBynXsRl3ayvjRwEuhgnX UZfnbFXpM5sN/O7hkgqgHKJBVhzkxS4N8weS164RrPTMMlRgxB74A5qwvCSqdDcgYJ75 6l27Tqj3RTREpJnaABWk+fppe+r3rkE5M8kQC252cLFBZLABizWdoB3jvtkOLeogWKpm Ut7gebyvsH/5OimYnXv6wtBXfpDfiSzikfXXAsSoXp4/PcYIm5lEaW+Y+zfwjv4wli3p 93j5/d8TJVsO9C+M5iqwiRdKSESbnJnsiUbeVISy/QF5BMr+bF5KRpP3wkR1y3VGgzfp zhJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MzK67c0LqpIZxoZVvjAbHdBDY8rBUVMdqwYx5iyXsWY=; b=VuvB3yD7ZpD+xqdWW1NQkJQrpDjDJ3TDYwi2DPOvZHtruAogCv09XwT4ESs6lGXgpc YHvK6I1+HVAgMegTyROzZCbQ/oOcQuSqKm60rLOnqvwTuDvpjH2JklZEVIkOP2aZuxSZ SB1HZoQDNnzxfdJkAPWwxn8AMnhMVyrAyzkgL6XPMBUnNAnNgnKZMefzpneXtlqwV7Qy OY0zacYEt4R0k3FQV9yGwW1RivSJPBagLc6e/EJxSgR3SZQlh7Gl2YaRCwZf8jP2pEZq 1SKFakUdKfZwkELtvun5fEKwvQWtFJco6e4Sxd0gEvLkZrGpx3/SRbdav1ElDiqa4rmI +mYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JR1h2RVs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 95 +++++++++------------------------- 1 file changed, 25 insertions(+), 70 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index a35ec2893a..2e3760a9c1 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -83,6 +83,7 @@ this code that are retained. #define FPU_SOFTFLOAT_MACROS_H #include "fpu/softfloat-types.h" +#include "qemu/host-utils.h" /*---------------------------------------------------------------------------- | Shifts `a' right by the number of bits given in `count'. If any nonzero @@ -403,16 +404,12 @@ static inline void | are stored at the locations pointed to by `z0Ptr' and `z1Ptr'. *----------------------------------------------------------------------------*/ -static inline void - add128( - uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, uint64_t *z1Ptr ) +static inline void add128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, + uint64_t *z0Ptr, uint64_t *z1Ptr) { - uint64_t z1; - - z1 = a1 + b1; - *z1Ptr = z1; - *z0Ptr = a0 + b0 + ( z1 < a1 ); - + bool c = 0; + *z1Ptr = uadd64_carry(a1, b1, &c); + *z0Ptr = uadd64_carry(a0, b0, &c); } /*---------------------------------------------------------------------------- @@ -423,34 +420,14 @@ static inline void | `z1Ptr', and `z2Ptr'. *----------------------------------------------------------------------------*/ -static inline void - add192( - uint64_t a0, - uint64_t a1, - uint64_t a2, - uint64_t b0, - uint64_t b1, - uint64_t b2, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr - ) +static inline void add192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2, + uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Ptr) { - uint64_t z0, z1, z2; - int8_t carry0, carry1; - - z2 = a2 + b2; - carry1 = ( z2 < a2 ); - z1 = a1 + b1; - carry0 = ( z1 < a1 ); - z0 = a0 + b0; - z1 += carry1; - z0 += ( z1 < carry1 ); - z0 += carry0; - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - + bool c = 0; + *z2Ptr = uadd64_carry(a2, b2, &c); + *z1Ptr = uadd64_carry(a1, b1, &c); + *z0Ptr = uadd64_carry(a0, b0, &c); } /*---------------------------------------------------------------------------- @@ -461,14 +438,12 @@ static inline void | `z1Ptr'. *----------------------------------------------------------------------------*/ -static inline void - sub128( - uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, uint64_t *z0Ptr, uint64_t *z1Ptr ) +static inline void sub128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1, + uint64_t *z0Ptr, uint64_t *z1Ptr) { - - *z1Ptr = a1 - b1; - *z0Ptr = a0 - b0 - ( a1 < b1 ); - + bool c = 0; + *z1Ptr = usub64_borrow(a1, b1, &c); + *z0Ptr = usub64_borrow(a0, b0, &c); } /*---------------------------------------------------------------------------- @@ -479,34 +454,14 @@ static inline void | pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'. *----------------------------------------------------------------------------*/ -static inline void - sub192( - uint64_t a0, - uint64_t a1, - uint64_t a2, - uint64_t b0, - uint64_t b1, - uint64_t b2, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr - ) +static inline void sub192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2, + uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Ptr) { - uint64_t z0, z1, z2; - int8_t borrow0, borrow1; - - z2 = a2 - b2; - borrow1 = ( a2 < b2 ); - z1 = a1 - b1; - borrow0 = ( a1 < b1 ); - z0 = a0 - b0; - z0 -= ( z1 < borrow1 ); - z1 -= borrow1; - z0 -= borrow0; - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; - + bool c = 0; + *z2Ptr = usub64_borrow(a2, b2, &c); + *z1Ptr = usub64_borrow(a1, b1, &c); + *z0Ptr = usub64_borrow(a0, b0, &c); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432557 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp858180jao; Fri, 7 May 2021 19:21:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzoqtSLeZRhAYlhR2r/mrgocoKd/j1DkTPfrilcEiBeA3xM/AZtNeS35aYEx/NQxOJD/0Qh X-Received: by 2002:a37:8403:: with SMTP id g3mr2815106qkd.469.1620440511824; Fri, 07 May 2021 19:21:51 -0700 (PDT) ARC-Seal: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id n15si5157219qkh.294.2021.05.07.19.21.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:21:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wZQBwzev; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCbH-00035K-0c for patch@linaro.org; Fri, 07 May 2021 22:21:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC5B-0004es-Ql for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:41 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:45738) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC4y-0003el-HA for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:41 -0400 Received: by mail-pg1-x530.google.com with SMTP id q15so4387614pgg.12 for ; Fri, 07 May 2021 18:48:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TWZr2C9rW9e8Gm21aL9j9NpbBIgKRrAvWFSjjtP/7/E=; b=wZQBwzevwlv1Ksd83Lp0s/lAV5XzmdSgSn+FsOCYj2JdSA2afqDj0+tzm6jdT0cA0+ iKv9KW3hbnSl+kkyp7reXTowt2ZsfU6tHhhCTPYLVe3isT3hs0GGLGcC2hMlV8bplGff H49fxHmFz343I4IP8Rg+5tWj9++eEFDiUke9+a5MFDLNkDuXktGlZkgh1ERO64Hb7SOu 9Gfbr/KfD2L5MgY8G1jHUvnEL3TSn6kWel4f/x4knNFTyM7CVkoUJJTecL7h/HUnKHKL 61zz3834m83GBvaJtHnk4axtuJWCGs8wTiI8b8ju8GMBswOzteOwF+SqjmToh4kkiE+1 ymtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TWZr2C9rW9e8Gm21aL9j9NpbBIgKRrAvWFSjjtP/7/E=; b=JPlUpchFeedCZ4tU10Q0K366tfJCIdtc7EVt5ePKRvf7QY+cNnhtsne2FnzMU8Q51R /2cE2kI6p/MAUpWu2MRI1vd+ZUxJXIi8Wf9RgqaktmDF0FPavrKWDZzhE12qrJB9zzqC OPz47+L3gYnIp70cLZMMWZ5rgOpBcIKuGeRvylJg95BBjrhG11HGxnnJ6tjzXDDPY5N1 R8h1Ds/nOD49v6nR9B5JViE3TZJeYNhgORumZnZoWzvDKpbE/a1T2pY+iiWzmylppIj5 wZZE6iBH7N6Mi4lx/dgvz25ONnkRUsPaSutynBxfIJNPvv9AlCluXjF+f6ue2k2eonWX fVkQ== X-Gm-Message-State: AOAM531+9CROrokKP1rNP3GmZWr/9lqeCx2+WR/rjAwtyBWE+xD8mfjS OEFMNkGq7ubZAWF7lwc+RhwBvzUX3MZmJA== X-Received: by 2002:aa7:914e:0:b029:28c:48d6:b27c with SMTP id 14-20020aa7914e0000b029028c48d6b27cmr13362801pfi.79.1620438505728; Fri, 07 May 2021 18:48:25 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 34/72] softfloat: Move addsub_floats to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:24 -0700 Message-Id: <20210508014802.892561-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for implementing multiple sizes. Rename to parts_addsub, split out parts_add/sub_normal for future reuse with muladd. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 253 ++++++++++++++----------------- fpu/softfloat-parts-addsub.c.inc | 62 ++++++++ fpu/softfloat-parts.c.inc | 81 ++++++++++ 3 files changed, 255 insertions(+), 141 deletions(-) create mode 100644 fpu/softfloat-parts-addsub.c.inc -- 2.25.1 Reviewed-by: Alex Bennée Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e9d644385d..22dc6da5ef 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -748,6 +748,26 @@ static void parts128_uncanon(FloatParts128 *p, float_status *status, #define parts_uncanon(A, S, F) \ PARTS_GENERIC_64_128(uncanon, A)(A, S, F) +static void parts64_add_normal(FloatParts64 *a, FloatParts64 *b); +static void parts128_add_normal(FloatParts128 *a, FloatParts128 *b); + +#define parts_add_normal(A, B) \ + PARTS_GENERIC_64_128(add_normal, A)(A, B) + +static bool parts64_sub_normal(FloatParts64 *a, FloatParts64 *b); +static bool parts128_sub_normal(FloatParts128 *a, FloatParts128 *b); + +#define parts_sub_normal(A, B) \ + PARTS_GENERIC_64_128(sub_normal, A)(A, B) + +static FloatParts64 *parts64_addsub(FloatParts64 *a, FloatParts64 *b, + float_status *s, bool subtract); +static FloatParts128 *parts128_addsub(FloatParts128 *a, FloatParts128 *b, + float_status *s, bool subtract); + +#define parts_addsub(A, B, S, Z) \ + PARTS_GENERIC_64_128(addsub, A)(A, B, S, Z) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -755,6 +775,21 @@ static void parts128_uncanon(FloatParts128 *p, float_status *status, #define FRAC_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) +static bool frac64_add(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) +{ + return uadd64_overflow(a->frac, b->frac, &r->frac); +} + +static bool frac128_add(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b) +{ + bool c = 0; + r->frac_lo = uadd64_carry(a->frac_lo, b->frac_lo, &c); + r->frac_hi = uadd64_carry(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_add(R, A, B) FRAC_GENERIC_64_128(add, R)(R, A, B) + static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c) { return uadd64_overflow(a->frac, c, &r->frac); @@ -823,6 +858,20 @@ static bool frac128_eqz(FloatParts128 *a) #define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A) +static void frac64_neg(FloatParts64 *a) +{ + a->frac = -a->frac; +} + +static void frac128_neg(FloatParts128 *a) +{ + bool c = 0; + a->frac_lo = usub64_borrow(0, a->frac_lo, &c); + a->frac_hi = usub64_borrow(0, a->frac_hi, &c); +} + +#define frac_neg(A) FRAC_GENERIC_64_128(neg, A)(A) + static int frac64_normalize(FloatParts64 *a) { if (a->frac) { @@ -890,18 +939,36 @@ static void frac128_shrjam(FloatParts128 *a, int c) #define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C) -#define partsN(NAME) parts64_##NAME -#define FloatPartsN FloatParts64 +static bool frac64_sub(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) +{ + return usub64_overflow(a->frac, b->frac, &r->frac); +} +static bool frac128_sub(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b) +{ + bool c = 0; + r->frac_lo = usub64_borrow(a->frac_lo, b->frac_lo, &c); + r->frac_hi = usub64_borrow(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B) + +#define partsN(NAME) glue(glue(glue(parts,N),_),NAME) +#define FloatPartsN glue(FloatParts,N) + +#define N 64 + +#include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" -#undef partsN -#undef FloatPartsN -#define partsN(NAME) parts128_##NAME -#define FloatPartsN FloatParts128 +#undef N +#define N 128 +#include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" +#undef N #undef partsN #undef FloatPartsN @@ -979,165 +1046,73 @@ static float64 float64_round_pack_canonical(FloatParts64 *p, } /* - * Returns the result of adding or subtracting the values of the - * floating-point values `a' and `b'. The operation is performed - * according to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic. + * Addition and subtraction */ -static FloatParts64 addsub_floats(FloatParts64 a, FloatParts64 b, bool subtract, - float_status *s) +static float16 QEMU_FLATTEN +float16_addsub(float16 a, float16 b, float_status *status, bool subtract) { - bool a_sign = a.sign; - bool b_sign = b.sign ^ subtract; - - if (a_sign != b_sign) { - /* Subtraction */ - - if (a.cls == float_class_normal && b.cls == float_class_normal) { - if (a.exp > b.exp || (a.exp == b.exp && a.frac >= b.frac)) { - shift64RightJamming(b.frac, a.exp - b.exp, &b.frac); - a.frac = a.frac - b.frac; - } else { - shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); - a.frac = b.frac - a.frac; - a.exp = b.exp; - a_sign ^= 1; - } - - if (a.frac == 0) { - a.cls = float_class_zero; - a.sign = s->float_rounding_mode == float_round_down; - } else { - int shift = clz64(a.frac); - a.frac = a.frac << shift; - a.exp = a.exp - shift; - a.sign = a_sign; - } - return a; - } - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - if (a.cls == float_class_inf) { - if (b.cls == float_class_inf) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - } - return a; - } - if (a.cls == float_class_zero && b.cls == float_class_zero) { - a.sign = s->float_rounding_mode == float_round_down; - return a; - } - if (a.cls == float_class_zero || b.cls == float_class_inf) { - b.sign = a_sign ^ 1; - return b; - } - if (b.cls == float_class_zero) { - return a; - } - } else { - /* Addition */ - if (a.cls == float_class_normal && b.cls == float_class_normal) { - if (a.exp > b.exp) { - shift64RightJamming(b.frac, a.exp - b.exp, &b.frac); - } else if (a.exp < b.exp) { - shift64RightJamming(a.frac, b.exp - a.exp, &a.frac); - a.exp = b.exp; - } - - if (uadd64_overflow(a.frac, b.frac, &a.frac)) { - shift64RightJamming(a.frac, 1, &a.frac); - a.frac |= DECOMPOSED_IMPLICIT_BIT; - a.exp += 1; - } - return a; - } - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - if (a.cls == float_class_inf || b.cls == float_class_zero) { - return a; - } - if (b.cls == float_class_inf || a.cls == float_class_zero) { - b.sign = b_sign; - return b; - } - } - g_assert_not_reached(); -} - -/* - * Returns the result of adding or subtracting the floating-point - * values `a' and `b'. The operation is performed according to the - * IEC/IEEE Standard for Binary Floating-Point Arithmetic. - */ - -float16 QEMU_FLATTEN float16_add(float16 a, float16 b, float_status *status) -{ - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); - pr = addsub_floats(pa, pb, false, status); + pr = parts_addsub(&pa, &pb, status, subtract); - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } -float16 QEMU_FLATTEN float16_sub(float16 a, float16 b, float_status *status) +float16 float16_add(float16 a, float16 b, float_status *status) { - FloatParts64 pa, pb, pr; + return float16_addsub(a, b, status, false); +} - float16_unpack_canonical(&pa, a, status); - float16_unpack_canonical(&pb, b, status); - pr = addsub_floats(pa, pb, true, status); - - return float16_round_pack_canonical(&pr, status); +float16 float16_sub(float16 a, float16 b, float_status *status) +{ + return float16_addsub(a, b, status, true); } static float32 QEMU_SOFTFLOAT_ATTR -soft_f32_addsub(float32 a, float32 b, bool subtract, float_status *status) +soft_f32_addsub(float32 a, float32 b, float_status *status, bool subtract) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); - pr = addsub_floats(pa, pb, subtract, status); + pr = parts_addsub(&pa, &pb, status, subtract); - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } -static inline float32 soft_f32_add(float32 a, float32 b, float_status *status) +static float32 soft_f32_add(float32 a, float32 b, float_status *status) { - return soft_f32_addsub(a, b, false, status); + return soft_f32_addsub(a, b, status, false); } -static inline float32 soft_f32_sub(float32 a, float32 b, float_status *status) +static float32 soft_f32_sub(float32 a, float32 b, float_status *status) { - return soft_f32_addsub(a, b, true, status); + return soft_f32_addsub(a, b, status, true); } static float64 QEMU_SOFTFLOAT_ATTR -soft_f64_addsub(float64 a, float64 b, bool subtract, float_status *status) +soft_f64_addsub(float64 a, float64 b, float_status *status, bool subtract) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); - pr = addsub_floats(pa, pb, subtract, status); + pr = parts_addsub(&pa, &pb, status, subtract); - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } -static inline float64 soft_f64_add(float64 a, float64 b, float_status *status) +static float64 soft_f64_add(float64 a, float64 b, float_status *status) { - return soft_f64_addsub(a, b, false, status); + return soft_f64_addsub(a, b, status, false); } -static inline float64 soft_f64_sub(float64 a, float64 b, float_status *status) +static float64 soft_f64_sub(float64 a, float64 b, float_status *status) { - return soft_f64_addsub(a, b, true, status); + return soft_f64_addsub(a, b, status, true); } static float hard_f32_add(float a, float b) @@ -1215,30 +1190,26 @@ float64_sub(float64 a, float64 b, float_status *s) return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub); } -/* - * Returns the result of adding or subtracting the bfloat16 - * values `a' and `b'. - */ -bfloat16 QEMU_FLATTEN bfloat16_add(bfloat16 a, bfloat16 b, float_status *status) +static bfloat16 QEMU_FLATTEN +bfloat16_addsub(bfloat16 a, bfloat16 b, float_status *status, bool subtract) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); - pr = addsub_floats(pa, pb, false, status); + pr = parts_addsub(&pa, &pb, status, subtract); - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); } -bfloat16 QEMU_FLATTEN bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) +bfloat16 bfloat16_add(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa, pb, pr; + return bfloat16_addsub(a, b, status, false); +} - bfloat16_unpack_canonical(&pa, a, status); - bfloat16_unpack_canonical(&pb, b, status); - pr = addsub_floats(pa, pb, true, status); - - return bfloat16_round_pack_canonical(&pr, status); +bfloat16 bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) +{ + return bfloat16_addsub(a, b, status, true); } /* diff --git a/fpu/softfloat-parts-addsub.c.inc b/fpu/softfloat-parts-addsub.c.inc new file mode 100644 index 0000000000..ae5c1017c5 --- /dev/null +++ b/fpu/softfloat-parts-addsub.c.inc @@ -0,0 +1,62 @@ +/* + * Floating point arithmetic implementation + * + * The code in this source file is derived from release 2a of the SoftFloat + * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and + * some later contributions) are provided under that license, as detailed below. + * It has subsequently been modified by contributors to the QEMU Project, + * so some portions are provided under: + * the SoftFloat-2a license + * the BSD license + * GPL-v2-or-later + * + * Any future contributions to this file after December 1st 2014 will be + * taken to be licensed under the Softfloat-2a license unless specifically + * indicated otherwise. + */ + +static void partsN(add_normal)(FloatPartsN *a, FloatPartsN *b) +{ + int exp_diff = a->exp - b->exp; + + if (exp_diff > 0) { + frac_shrjam(b, exp_diff); + } else if (exp_diff < 0) { + frac_shrjam(a, -exp_diff); + a->exp = b->exp; + } + + if (frac_add(a, a, b)) { + frac_shrjam(a, 1); + a->frac_hi |= DECOMPOSED_IMPLICIT_BIT; + a->exp += 1; + } +} + +static bool partsN(sub_normal)(FloatPartsN *a, FloatPartsN *b) +{ + int exp_diff = a->exp - b->exp; + int shift; + + if (exp_diff > 0) { + frac_shrjam(b, exp_diff); + frac_sub(a, a, b); + } else if (exp_diff < 0) { + a->exp = b->exp; + a->sign ^= 1; + frac_shrjam(a, -exp_diff); + frac_sub(a, b, a); + } else if (frac_sub(a, a, b)) { + /* Overflow means that A was less than B. */ + frac_neg(a); + a->sign ^= 1; + } + + shift = frac_normalize(a); + if (likely(shift < N)) { + a->exp -= shift; + return true; + } + a->cls = float_class_zero; + return false; +} diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index efdc724770..cfce9f6421 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -281,3 +281,84 @@ static void partsN(uncanon)(FloatPartsN *p, float_status *s, p->exp = exp; float_raise(flags, s); } + +/* + * Returns the result of adding or subtracting the values of the + * floating-point values `a' and `b'. The operation is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic. + */ +static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b, + float_status *s, bool subtract) +{ + bool b_sign = b->sign ^ subtract; + int ab_mask = float_cmask(a->cls) | float_cmask(b->cls); + + if (a->sign != b_sign) { + /* Subtraction */ + if (likely(ab_mask == float_cmask_normal)) { + if (parts_sub_normal(a, b)) { + return a; + } + /* Subtract was exact, fall through to set sign. */ + ab_mask = float_cmask_zero; + } + + if (ab_mask == float_cmask_zero) { + a->sign = s->float_rounding_mode == float_round_down; + return a; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + goto p_nan; + } + + if (ab_mask & float_cmask_inf) { + if (a->cls != float_class_inf) { + /* N - Inf */ + goto return_b; + } + if (b->cls != float_class_inf) { + /* Inf - N */ + return a; + } + /* Inf - Inf */ + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + } else { + /* Addition */ + if (likely(ab_mask == float_cmask_normal)) { + parts_add_normal(a, b); + return a; + } + + if (ab_mask == float_cmask_zero) { + return a; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + goto p_nan; + } + + if (ab_mask & float_cmask_inf) { + a->cls = float_class_inf; + return a; + } + } + + if (b->cls == float_class_zero) { + g_assert(a->cls == float_class_normal); + return a; + } + + g_assert(a->cls == float_class_zero); + g_assert(b->cls == float_class_normal); + return_b: + b->sign = b_sign; + return b; + + p_nan: + return parts_pick_nan(a, b, s); +} From patchwork Sat May 8 01:47:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432544 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp852207jao; Fri, 7 May 2021 19:10:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwyMx0xkA1B3QZrXzp+UUDUTHSDMa0bQ1lvMZq1HIh7b0cmKMAtAtdP1W3I1ztV693xUk/q X-Received: by 2002:a05:6e02:1384:: with SMTP id d4mr9240977ilo.25.1620439819897; Fri, 07 May 2021 19:10:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439819; cv=none; d=google.com; s=arc-20160816; b=ejpmnQ5gA8u1/N8HnnRwsc/RU9Ro1HUikw0sBd+vKeGk/AWj2EmjIpir8msQDGVkbl AlQycv50MBiQoSOzRPAqf9EerXhuper+MW0kAiup0TmmVuaUYSXsAwSofridNNReQDgw Ts7/hWvPzD5xQyyQTA8hxQ5kfJmgbqzG0z1I9GACGquWytPFEoqBSC7kCgYzdTERhJWE CFlJRupmScYUDj+2gofD5tU7HYwEBHrILYzEUpmVrigwLO7gEx2RuoYyvigbqcCa8TEf cyHHUzTdPZ9XhtfnSnIbN/w2qvcVAzMMCts7b0WxpIScgMdmwjizpOwDKD6Wx8RaUwG+ KuYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6i53BfFJgz07MWWKwgEBG9wk32Qsx014902OXCtKmIE=; b=xUGDMoslnyYZnxKikQ2zAd2WIxSMvSjBYk7LgWuppSYmABVVneD+PkHYEsivGcllk9 SXb1wU+lnhtNMmznL9kivJIxiERzoul7kKJxhprQQo41jvpx+j35Pa22rHNilfOZAVrK yjUozpv8VCzVvzHDPJmU1k9GpBrGoxo2gZ/h/Kvs9zA0qaq6E78ATrd6otf555q9N0SK bPZl3fIeonpCHs/v6p/cdKTcnNp3SATRulvZvl5x4T+SlLPg5iFDkl/Njo6PGPvLgxHy ULrJAOFQOQmo4spfciIGwLyBx2RmyF0WCuGvcCF8EqlcAebNdU2tMfhPgcAJ05v5br+C CYZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HQiX0aS7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- fpu/softfloat.c | 257 +++++++----------------------------------------- 1 file changed, 36 insertions(+), 221 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 22dc6da5ef..f48e6b1f64 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1045,6 +1045,20 @@ static float64 float64_round_pack_canonical(FloatParts64 *p, return float64_pack_raw(p); } +static void float128_unpack_canonical(FloatParts128 *p, float128 f, + float_status *s) +{ + float128_unpack_raw(p, f); + parts_canonicalize(p, s, &float128_params); +} + +static float128 float128_round_pack_canonical(FloatParts128 *p, + float_status *s) +{ + parts_uncanon(p, s, &float128_params); + return float128_pack_raw(p); +} + /* * Addition and subtraction */ @@ -1212,6 +1226,28 @@ bfloat16 bfloat16_sub(bfloat16 a, bfloat16 b, float_status *status) return bfloat16_addsub(a, b, status, true); } +static float128 QEMU_FLATTEN +float128_addsub(float128 a, float128 b, float_status *status, bool subtract) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr = parts_addsub(&pa, &pb, status, subtract); + + return float128_round_pack_canonical(pr, status); +} + +float128 float128_add(float128 a, float128 b, float_status *status) +{ + return float128_addsub(a, b, status, false); +} + +float128 float128_sub(float128 a, float128 b, float_status *status) +{ + return float128_addsub(a, b, status, true); +} + /* * Returns the result of multiplying the floating-point values `a' and * `b'. The operation is performed according to the IEC/IEEE Standard @@ -7031,227 +7067,6 @@ float128 float128_round_to_int(float128 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of adding the absolute values of the quadruple-precision -| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated -| before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float128 addFloat128Sigs(float128 a, float128 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2; - int32_t expDiff; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - expDiff = aExp - bExp; - if ( 0 < expDiff ) { - if ( aExp == 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig0 |= UINT64_C(0x0001000000000000); - } - shift128ExtraRightJamming( - bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 ); - zExp = aExp; - } - else if ( expDiff < 0 ) { - if ( bExp == 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig0 |= UINT64_C(0x0001000000000000); - } - shift128ExtraRightJamming( - aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 ); - zExp = bExp; - } - else { - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 | bSig0 | bSig1 ) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - if ( aExp == 0 ) { - if (status->flush_to_zero) { - if (zSig0 | zSig1) { - float_raise(float_flag_output_denormal, status); - } - return packFloat128(zSign, 0, 0, 0); - } - return packFloat128( zSign, 0, zSig0, zSig1 ); - } - zSig2 = 0; - zSig0 |= UINT64_C(0x0002000000000000); - zExp = aExp; - goto shiftRight1; - } - aSig0 |= UINT64_C(0x0001000000000000); - add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - --zExp; - if ( zSig0 < UINT64_C(0x0002000000000000) ) goto roundAndPack; - ++zExp; - shiftRight1: - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 ); - roundAndPack: - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the absolute values of the quadruple- -| precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static float128 subFloat128Sigs(float128 a, float128 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1; - int32_t expDiff; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - expDiff = aExp - bExp; - shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 ); - shortShift128Left( bSig0, bSig1, 14, &bSig0, &bSig1 ); - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 | bSig0 | bSig1 ) { - return propagateFloat128NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - if ( aExp == 0 ) { - aExp = 1; - bExp = 1; - } - if ( bSig0 < aSig0 ) goto aBigger; - if ( aSig0 < bSig0 ) goto bBigger; - if ( bSig1 < aSig1 ) goto aBigger; - if ( aSig1 < bSig1 ) goto bBigger; - return packFloat128(status->float_rounding_mode == float_round_down, - 0, 0, 0); - bExpBigger: - if ( bExp == 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return packFloat128( zSign ^ 1, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - ++expDiff; - } - else { - aSig0 |= UINT64_C(0x4000000000000000); - } - shift128RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 ); - bSig0 |= UINT64_C(0x4000000000000000); - bBigger: - sub128( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 ); - zExp = bExp; - zSign ^= 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp == 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - if ( bExp == 0 ) { - --expDiff; - } - else { - bSig0 |= UINT64_C(0x4000000000000000); - } - shift128RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 ); - aSig0 |= UINT64_C(0x4000000000000000); - aBigger: - sub128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 ); - zExp = aExp; - normalizeRoundAndPack: - --zExp; - return normalizeRoundAndPackFloat128(zSign, zExp - 14, zSig0, zSig1, - status); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the quadruple-precision floating-point values -| `a' and `b'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_add(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign; - - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign == bSign ) { - return addFloat128Sigs(a, b, aSign, status); - } - else { - return subFloat128Sigs(a, b, aSign, status); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the quadruple-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_sub(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign; - - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign == bSign ) { - return subFloat128Sigs(a, b, aSign, status); - } - else { - return addFloat128Sigs(a, b, aSign, status); - } - -} - /*---------------------------------------------------------------------------- | Returns the result of multiplying the quadruple-precision floating-point | values `a' and `b'. The operation is performed according to the IEC/IEEE From patchwork Sat May 8 01:47:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432548 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp853590jao; Fri, 7 May 2021 19:13:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFDNhDrP4tNYHLMoP2177pQF/e9BAXuUGjgiv0awIbfOWCf7rY+bdqLnzVCT0lpdGTTiCP X-Received: by 2002:a92:3f03:: with SMTP id m3mr11387164ila.34.1620439981795; Fri, 07 May 2021 19:13:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620439981; cv=none; d=google.com; s=arc-20160816; b=wQ7Ef9aj8gSHzCqkZUwmyXeMVoFOiTy4oOhr7+Z74jcLiG+ledDbOB1LnwFYi0NO3A hh7DdkUWIsYk3FvnUSJ/2N9TlwPiM0UsYAXgBrb1GwLGH7PyOiHf6jQl0jM8LpJl9Fdi fYtF533T8YzGttcIZDZ7BdVD3fP/SJ/+gHAda4wbHLwgfpw/J2wvArsiTk+XqXIHnBRV pbtZIvcQoxzuX3LEu1hZzwmlrP0lDSfKmiNWegp7TIbJcfl9SETW66KxLD/S+thDo20e gLRYsFicd91iOv8qauWcCGG0y53bOLHi4YT2YiMB4JakQa1loTslAfM0NqjuKxD1biA6 AK5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OpqyG4clDvy9/ZBezzF8wCxCOGnfsCBVBkWOeSJ/RSI=; b=XsBayT9RgKGNWP1TfV1t+YDrIjuRCAu/Xz8BjsSTaT28ae7G8FCt1izmb+SdRoF4cr ecOTwtrp8eRL/Eym9l8xWluccj8Z8zo1qlRGpN7/wwOR8JvxFfq+4rSHz02g4CT9biAn L30Vv8agTiJSGkFAKSaDzHBe6Xv4AbF+/0bf4iGtTBgQhTaIywaPUSpMHUT6cyRN+nfm wbiM1Zd2C0Pnn2jwmtfR3KiEO+gDvkrDrDRHT/mARIM7lGDtVP3xLzG2Bm36DXUAQDly 9+6Zf+QGBMPsYRev7Kqd9MDNRGb00/S7Unm/ElCzi4JDW6GUVy8iws+/IElQCy257b29 R9vQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lwvsxcDS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y18si7941569jak.36.2021.05.07.19.13.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:13:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=lwvsxcDS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCSj-00052q-91 for patch@linaro.org; Fri, 07 May 2021 22:13:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC5D-0004mb-Iu for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:43 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:40940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC50-0003fE-43 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:43 -0400 Received: by mail-pj1-x102c.google.com with SMTP id l10-20020a17090a850ab0290155b06f6267so6437416pjn.5 for ; Fri, 07 May 2021 18:48:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OpqyG4clDvy9/ZBezzF8wCxCOGnfsCBVBkWOeSJ/RSI=; b=lwvsxcDS643SVigpds6i6d9KkBW85XHcvAUecPc5RRrHDnMwj0JkTqlKToy3QB4VCc yXPBMJ/qdCklHat2QpWFp01n5ZvvOvH0DGe49VpGR+NSUl1hhDJPk4i9FVNNRZNxuyk1 Ke4e5EH+FQP/mOQPJ38YiGvzjJoFsPrw3F7wtA28Hm5qClYKFQdgK9rCDj9VTbt0vqyi RTFqShAPqJtPtKaGKgM0oVVTBD2KfxHLZEuSJBqt3qVrMRB8TvsjePNRzdncAEFmXjI5 10+d4fBbbb/Llz14Dda31P8c05tJfKS7k5lahBXRsF8Z4CIjzIzEozPmlB7suu8Z3ZfX 7MDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OpqyG4clDvy9/ZBezzF8wCxCOGnfsCBVBkWOeSJ/RSI=; b=f1ndCmFUqOdXQJPU/QwIM8ALXCjewkhvtxuvzd96Esc+zUW4ymjGjL8TpFYMjNeO/+ 6bheTx2cW3FDYKXLB6kM/h3QLvN15ZVo16BEOhLHUYeCdG19KXip7oHPfhibrAr7VjaR B2E8lz22lzlGT5EBqbtQngstWIlEwg0UBwzW9zJHwKy6oEm2JBaOkWK3zQIEuzBG5DHM XJuql0qR4YTYn8aXwNFdzEOoXfXB6sWTS3NLNDZBpBogGDyKGBCFe0vCwwMW2TSyqB9c EY67N/KJRrqmMy0MEv+DFJ0A/vJRHzBK+kOZHn8hP/BywAdQN8dJ5BaSOq7R1YcdwcB1 peuA== X-Gm-Message-State: AOAM53177Gb47bh4NHYmHizYweyVZCoUDaRRMVbdQBgI3X2DQ+DQ4SEO vUxpyUCKNw2CGqWj36+MaljYfIYPl6fRRQ== X-Received: by 2002:a17:902:123:b029:ee:f515:8835 with SMTP id 32-20020a1709020123b02900eef5158835mr13059823plb.54.1620438506940; Fri, 07 May 2021 18:48:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 36/72] softfloat: Move mul_floats to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:26 -0700 Message-Id: <20210508014802.892561-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_mul. Reimplement float128_mul with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 206 ++++++++++++++------------------------ fpu/softfloat-parts.c.inc | 51 ++++++++++ 2 files changed, 128 insertions(+), 129 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f48e6b1f64..4f498c11e5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -532,6 +532,16 @@ typedef struct { uint64_t frac_lo; } FloatParts128; +typedef struct { + FloatClass cls; + bool sign; + int32_t exp; + uint64_t frac_hi; + uint64_t frac_hm; /* high-middle */ + uint64_t frac_lm; /* low-middle */ + uint64_t frac_lo; +} FloatParts256; + /* These apply to the most significant word of each FloatPartsN. */ #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) @@ -768,6 +778,14 @@ static FloatParts128 *parts128_addsub(FloatParts128 *a, FloatParts128 *b, #define parts_addsub(A, B, S, Z) \ PARTS_GENERIC_64_128(addsub, A)(A, B, S, Z) +static FloatParts64 *parts64_mul(FloatParts64 *a, FloatParts64 *b, + float_status *s); +static FloatParts128 *parts128_mul(FloatParts128 *a, FloatParts128 *b, + float_status *s); + +#define parts_mul(A, B, S) \ + PARTS_GENERIC_64_128(mul, A)(A, B, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -858,6 +876,19 @@ static bool frac128_eqz(FloatParts128 *a) #define frac_eqz(A) FRAC_GENERIC_64_128(eqz, A)(A) +static void frac64_mulw(FloatParts128 *r, FloatParts64 *a, FloatParts64 *b) +{ + mulu64(&r->frac_lo, &r->frac_hi, a->frac, b->frac); +} + +static void frac128_mulw(FloatParts256 *r, FloatParts128 *a, FloatParts128 *b) +{ + mul128To256(a->frac_hi, a->frac_lo, b->frac_hi, b->frac_lo, + &r->frac_hi, &r->frac_hm, &r->frac_lm, &r->frac_lo); +} + +#define frac_mulw(R, A, B) FRAC_GENERIC_64_128(mulw, A)(R, A, B) + static void frac64_neg(FloatParts64 *a) { a->frac = -a->frac; @@ -954,23 +985,42 @@ static bool frac128_sub(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b) #define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B) +static void frac64_truncjam(FloatParts64 *r, FloatParts128 *a) +{ + r->frac = a->frac_hi | (a->frac_lo != 0); +} + +static void frac128_truncjam(FloatParts128 *r, FloatParts256 *a) +{ + r->frac_hi = a->frac_hi; + r->frac_lo = a->frac_hm | ((a->frac_lm | a->frac_lo) != 0); +} + +#define frac_truncjam(R, A) FRAC_GENERIC_64_128(truncjam, R)(R, A) + #define partsN(NAME) glue(glue(glue(parts,N),_),NAME) #define FloatPartsN glue(FloatParts,N) +#define FloatPartsW glue(FloatParts,W) #define N 64 +#define W 128 #include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" #undef N +#undef W #define N 128 +#define W 256 #include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" #undef N +#undef W #undef partsN #undef FloatPartsN +#undef FloatPartsW /* * Pack/unpack routines with a specific FloatFmt. @@ -1249,89 +1299,42 @@ float128 float128_sub(float128 a, float128 b, float_status *status) } /* - * Returns the result of multiplying the floating-point values `a' and - * `b'. The operation is performed according to the IEC/IEEE Standard - * for Binary Floating-Point Arithmetic. + * Multiplication */ -static FloatParts64 mul_floats(FloatParts64 a, FloatParts64 b, float_status *s) -{ - bool sign = a.sign ^ b.sign; - - if (a.cls == float_class_normal && b.cls == float_class_normal) { - uint64_t hi, lo; - int exp = a.exp + b.exp; - - mul64To128(a.frac, b.frac, &hi, &lo); - if (hi & DECOMPOSED_IMPLICIT_BIT) { - exp += 1; - } else { - hi <<= 1; - } - hi |= (lo != 0); - - /* Re-use a */ - a.exp = exp; - a.sign = sign; - a.frac = hi; - return a; - } - /* handle all the NaN cases */ - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - /* Inf * Zero == NaN */ - if ((a.cls == float_class_inf && b.cls == float_class_zero) || - (a.cls == float_class_zero && b.cls == float_class_inf)) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - /* Multiply by 0 or Inf */ - if (a.cls == float_class_inf || a.cls == float_class_zero) { - a.sign = sign; - return a; - } - if (b.cls == float_class_inf || b.cls == float_class_zero) { - b.sign = sign; - return b; - } - g_assert_not_reached(); -} - float16 QEMU_FLATTEN float16_mul(float16 a, float16 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); - pr = mul_floats(pa, pb, status); + pr = parts_mul(&pa, &pb, status); - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } static float32 QEMU_SOFTFLOAT_ATTR soft_f32_mul(float32 a, float32 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); - pr = mul_floats(pa, pb, status); + pr = parts_mul(&pa, &pb, status); - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } static float64 QEMU_SOFTFLOAT_ATTR soft_f64_mul(float64 a, float64 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); - pr = mul_floats(pa, pb, status); + pr = parts_mul(&pa, &pb, status); - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } static float hard_f32_mul(float a, float b) @@ -1358,20 +1361,28 @@ float64_mul(float64 a, float64 b, float_status *s) f64_is_zon2, f64_addsubmul_post); } -/* - * Returns the result of multiplying the bfloat16 - * values `a' and `b'. - */ - -bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) +bfloat16 QEMU_FLATTEN +bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); - pr = mul_floats(pa, pb, status); + pr = parts_mul(&pa, &pb, status); - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); +} + +float128 QEMU_FLATTEN +float128_mul(float128 a, float128 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr = parts_mul(&pa, &pb, status); + + return float128_round_pack_canonical(pr, status); } /* @@ -7067,69 +7078,6 @@ float128 float128_round_to_int(float128 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of multiplying the quadruple-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_mul(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - bSign = extractFloat128Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FFF ) { - if ( ( aSig0 | aSig1 ) - || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) { - return propagateFloat128NaN(a, b, status); - } - if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid; - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( bExp == 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - if ( ( aExp | aSig0 | aSig1 ) == 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - if ( bExp == 0 ) { - if ( ( bSig0 | bSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 ); - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - zExp = aExp + bExp - 0x4000; - aSig0 |= UINT64_C(0x0001000000000000); - shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 ); - mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 ); - add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 ); - zSig2 |= ( zSig3 != 0 ); - if (UINT64_C( 0x0002000000000000) <= zSig0 ) { - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 ); - ++zExp; - } - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - /*---------------------------------------------------------------------------- | Returns the result of dividing the quadruple-precision floating-point value | `a' by the corresponding value `b'. The operation is performed according to diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cfce9f6421..9a67ab2bea 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -362,3 +362,54 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b, p_nan: return parts_pick_nan(a, b, s); } + +/* + * Returns the result of multiplying the floating-point values `a' and + * `b'. The operation is performed according to the IEC/IEEE Standard + * for Binary Floating-Point Arithmetic. + */ +static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b, + float_status *s) +{ + int ab_mask = float_cmask(a->cls) | float_cmask(b->cls); + bool sign = a->sign ^ b->sign; + + if (likely(ab_mask == float_cmask_normal)) { + FloatPartsW tmp; + + frac_mulw(&tmp, a, b); + frac_truncjam(a, &tmp); + + a->exp += b->exp + 1; + if (!(a->frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + frac_add(a, a, a); + a->exp -= 1; + } + + a->sign = sign; + return a; + } + + /* Inf * Zero == NaN */ + if (unlikely(ab_mask == float_cmask_infzero)) { + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + return parts_pick_nan(a, b, s); + } + + /* Multiply by 0 or Inf */ + if (ab_mask & float_cmask_inf) { + a->cls = float_class_inf; + a->sign = sign; + return a; + } + + g_assert(ab_mask & float_cmask_zero); + a->cls = float_class_zero; + a->sign = sign; + return a; +} From patchwork Sat May 8 01:47:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432552 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp855434jao; Fri, 7 May 2021 19:16:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjbNfi+g9743a+jMxGYjMnBtsiykHs4MTRA4a7EM9ngjFEZizTxFT7DWT3kJ8k5Gq7mway X-Received: by 2002:a05:6e02:1bcb:: with SMTP id x11mr12302154ilv.87.1620440182248; Fri, 07 May 2021 19:16:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440182; cv=none; d=google.com; s=arc-20160816; b=0PNzdEEbpv7mTw6RPW3H1DAUyvVq0tIHcdZc2GHqWqKMnEQggp+KsZ8Ip2da8VVY77 x2zD8e1odwtvE9ztvmOEuleDPVu55S1YrAwYiXiNyiGg+Bd4S/hc5Fe0swe3bVwq0Lry eN5GdBLTok45dBZ5f3LBkjx8I21AZu2lykrznXAwsMDgN6inDj2LJz4YP1hqs5lCyVOS Aa2qhzYieRj6FTVTrKacSLw68csX4WyrDykpvQNzsQxYDORHn3DUsE1Q/vX1kXegD7Cr jdh8EppYOncueRjLhV+wY5ZvOt7opEmDxHlJ5BauLWjMGiSuFU6s2Z6ykghn24i+DGjr YelQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8Xkz1ybjWLeUjZCsE7o98Dkj/GU255PMCjv80HfDnbE=; b=E2c/44iYyN64K88/vHXZpz2dXMUxdk+aFb2GWnum/IojRzMgj/zWZ5IgzK4Q7K0tWB gdJV1GDLnOfnKRsNcpL+tdqBxoh6954dag9nqhaGcjWcWIpwASBxyLXHV42Xu7vEhfNZ 0cwgiMn6tt3RER59eqUMfbgATkCzKj6WApo5zTO9eIM4Fb1dxPBPmqrbLnNINnVILQbm 6m9I/QwTUXj/KwZMan9Qe/D95I1O+b+Ma7Oi+GiZ7VUBbI9tPRGsFfMCLjP8RMSKOjbO ION+vnYHFiHYyMaIolb7K/JEw5tgYoOJd9t5ZPThxHE0QoxpMWWSBCn1RBwrO6Mk8Q02 jMEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hYjABf28; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Implement float128_muladd with FloatParts128. Signed-off-by: Richard Henderson --- include/fpu/softfloat.h | 2 + fpu/softfloat.c | 406 ++++++++++++++++++-------------------- tests/fp/fp-bench.c | 8 +- tests/fp/fp-test.c | 2 +- fpu/softfloat-parts.c.inc | 126 ++++++++++++ tests/fp/wrap.c.inc | 12 ++ 6 files changed, 342 insertions(+), 214 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 019c2ec66d..53f2c2ea3c 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1197,6 +1197,8 @@ float128 float128_round_to_int(float128, float_status *status); float128 float128_add(float128, float128, float_status *status); float128 float128_sub(float128, float128, float_status *status); float128 float128_mul(float128, float128, float_status *status); +float128 float128_muladd(float128, float128, float128, int, + float_status *status); float128 float128_div(float128, float128, float_status *status); float128 float128_rem(float128, float128, float_status *status); float128 float128_sqrt(float128, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4f498c11e5..a9ee8498ae 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -715,6 +715,10 @@ static float128 float128_pack_raw(const FloatParts128 *p) #define PARTS_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, parts128_##NAME), parts64_##NAME) +#define PARTS_GENERIC_64_128_256(NAME, P) \ + QEMU_GENERIC(P, (FloatParts256 *, parts256_##NAME), \ + (FloatParts128 *, parts128_##NAME), parts64_##NAME) + #define parts_default_nan(P, S) PARTS_GENERIC_64_128(default_nan, P)(P, S) #define parts_silence_nan(P, S) PARTS_GENERIC_64_128(silence_nan, P)(P, S) @@ -760,15 +764,17 @@ static void parts128_uncanon(FloatParts128 *p, float_status *status, static void parts64_add_normal(FloatParts64 *a, FloatParts64 *b); static void parts128_add_normal(FloatParts128 *a, FloatParts128 *b); +static void parts256_add_normal(FloatParts256 *a, FloatParts256 *b); #define parts_add_normal(A, B) \ - PARTS_GENERIC_64_128(add_normal, A)(A, B) + PARTS_GENERIC_64_128_256(add_normal, A)(A, B) static bool parts64_sub_normal(FloatParts64 *a, FloatParts64 *b); static bool parts128_sub_normal(FloatParts128 *a, FloatParts128 *b); +static bool parts256_sub_normal(FloatParts256 *a, FloatParts256 *b); #define parts_sub_normal(A, B) \ - PARTS_GENERIC_64_128(sub_normal, A)(A, B) + PARTS_GENERIC_64_128_256(sub_normal, A)(A, B) static FloatParts64 *parts64_addsub(FloatParts64 *a, FloatParts64 *b, float_status *s, bool subtract); @@ -786,6 +792,16 @@ static FloatParts128 *parts128_mul(FloatParts128 *a, FloatParts128 *b, #define parts_mul(A, B, S) \ PARTS_GENERIC_64_128(mul, A)(A, B, S) +static FloatParts64 *parts64_muladd(FloatParts64 *a, FloatParts64 *b, + FloatParts64 *c, int flags, + float_status *s); +static FloatParts128 *parts128_muladd(FloatParts128 *a, FloatParts128 *b, + FloatParts128 *c, int flags, + float_status *s); + +#define parts_muladd(A, B, C, Z, S) \ + PARTS_GENERIC_64_128(muladd, A)(A, B, C, Z, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -793,6 +809,10 @@ static FloatParts128 *parts128_mul(FloatParts128 *a, FloatParts128 *b, #define FRAC_GENERIC_64_128(NAME, P) \ QEMU_GENERIC(P, (FloatParts128 *, frac128_##NAME), frac64_##NAME) +#define FRAC_GENERIC_64_128_256(NAME, P) \ + QEMU_GENERIC(P, (FloatParts256 *, frac256_##NAME), \ + (FloatParts128 *, frac128_##NAME), frac64_##NAME) + static bool frac64_add(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) { return uadd64_overflow(a->frac, b->frac, &r->frac); @@ -806,7 +826,17 @@ static bool frac128_add(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b) return c; } -#define frac_add(R, A, B) FRAC_GENERIC_64_128(add, R)(R, A, B) +static bool frac256_add(FloatParts256 *r, FloatParts256 *a, FloatParts256 *b) +{ + bool c = 0; + r->frac_lo = uadd64_carry(a->frac_lo, b->frac_lo, &c); + r->frac_lm = uadd64_carry(a->frac_lm, b->frac_lm, &c); + r->frac_hm = uadd64_carry(a->frac_hm, b->frac_hm, &c); + r->frac_hi = uadd64_carry(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_add(R, A, B) FRAC_GENERIC_64_128_256(add, R)(R, A, B) static bool frac64_addi(FloatParts64 *r, FloatParts64 *a, uint64_t c) { @@ -901,7 +931,16 @@ static void frac128_neg(FloatParts128 *a) a->frac_hi = usub64_borrow(0, a->frac_hi, &c); } -#define frac_neg(A) FRAC_GENERIC_64_128(neg, A)(A) +static void frac256_neg(FloatParts256 *a) +{ + bool c = 0; + a->frac_lo = usub64_borrow(0, a->frac_lo, &c); + a->frac_lm = usub64_borrow(0, a->frac_lm, &c); + a->frac_hm = usub64_borrow(0, a->frac_hm, &c); + a->frac_hi = usub64_borrow(0, a->frac_hi, &c); +} + +#define frac_neg(A) FRAC_GENERIC_64_128_256(neg, A)(A) static int frac64_normalize(FloatParts64 *a) { @@ -932,7 +971,55 @@ static int frac128_normalize(FloatParts128 *a) return 128; } -#define frac_normalize(A) FRAC_GENERIC_64_128(normalize, A)(A) +static int frac256_normalize(FloatParts256 *a) +{ + uint64_t a0 = a->frac_hi, a1 = a->frac_hm; + uint64_t a2 = a->frac_lm, a3 = a->frac_lo; + int ret, shl, shr; + + if (likely(a0)) { + shl = clz64(a0); + if (shl == 0) { + return 0; + } + ret = shl; + } else { + if (a1) { + ret = 64; + a0 = a1, a1 = a2, a2 = a3, a3 = 0; + } else if (a2) { + ret = 128; + a0 = a2, a1 = a3, a2 = 0, a3 = 0; + } else if (a3) { + ret = 192; + a0 = a3, a1 = 0, a2 = 0, a3 = 0; + } else { + ret = 256; + a0 = 0, a1 = 0, a2 = 0, a3 = 0; + goto done; + } + shl = clz64(a0); + if (shl == 0) { + goto done; + } + ret += shl; + } + + shr = -shl & 63; + a0 = (a0 << shl) | (a1 >> shr); + a1 = (a1 << shl) | (a2 >> shr); + a2 = (a2 << shl) | (a3 >> shr); + a3 = (a3 << shl); + + done: + a->frac_hi = a0; + a->frac_hm = a1; + a->frac_lm = a2; + a->frac_lo = a3; + return ret; +} + +#define frac_normalize(A) FRAC_GENERIC_64_128_256(normalize, A)(A) static void frac64_shl(FloatParts64 *a, int c) { @@ -968,7 +1055,51 @@ static void frac128_shrjam(FloatParts128 *a, int c) shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); } -#define frac_shrjam(A, C) FRAC_GENERIC_64_128(shrjam, A)(A, C) +static void frac256_shrjam(FloatParts256 *a, int c) +{ + uint64_t a0 = a->frac_hi, a1 = a->frac_hm; + uint64_t a2 = a->frac_lm, a3 = a->frac_lo; + uint64_t sticky = 0; + int invc; + + if (unlikely(c == 0)) { + return; + } else if (likely(c < 64)) { + /* nothing */ + } else if (likely(c < 256)) { + if (unlikely(c & 128)) { + sticky |= a2 | a3; + a3 = a1, a2 = a0, a1 = 0, a0 = 0; + } + if (unlikely(c & 64)) { + sticky |= a3; + a3 = a2, a2 = a1, a1 = a0, a0 = 0; + } + c &= 63; + if (c == 0) { + goto done; + } + } else { + sticky = a0 | a1 | a2 | a3; + a0 = a1 = a2 = a3 = 0; + goto done; + } + + invc = -c & 63; + sticky |= a3 << invc; + a3 = (a3 >> c) | (a2 << invc); + a2 = (a2 >> c) | (a1 << invc); + a1 = (a1 >> c) | (a0 << invc); + a0 = (a0 >> c); + + done: + a->frac_lo = a3 | (sticky != 0); + a->frac_lm = a2; + a->frac_hm = a1; + a->frac_hi = a0; +} + +#define frac_shrjam(A, C) FRAC_GENERIC_64_128_256(shrjam, A)(A, C) static bool frac64_sub(FloatParts64 *r, FloatParts64 *a, FloatParts64 *b) { @@ -983,7 +1114,17 @@ static bool frac128_sub(FloatParts128 *r, FloatParts128 *a, FloatParts128 *b) return c; } -#define frac_sub(R, A, B) FRAC_GENERIC_64_128(sub, R)(R, A, B) +static bool frac256_sub(FloatParts256 *r, FloatParts256 *a, FloatParts256 *b) +{ + bool c = 0; + r->frac_lo = usub64_borrow(a->frac_lo, b->frac_lo, &c); + r->frac_lm = usub64_borrow(a->frac_lm, b->frac_lm, &c); + r->frac_hm = usub64_borrow(a->frac_hm, b->frac_hm, &c); + r->frac_hi = usub64_borrow(a->frac_hi, b->frac_hi, &c); + return c; +} + +#define frac_sub(R, A, B) FRAC_GENERIC_64_128_256(sub, R)(R, A, B) static void frac64_truncjam(FloatParts64 *r, FloatParts128 *a) { @@ -998,6 +1139,22 @@ static void frac128_truncjam(FloatParts128 *r, FloatParts256 *a) #define frac_truncjam(R, A) FRAC_GENERIC_64_128(truncjam, R)(R, A) +static void frac64_widen(FloatParts128 *r, FloatParts64 *a) +{ + r->frac_hi = a->frac; + r->frac_lo = 0; +} + +static void frac128_widen(FloatParts256 *r, FloatParts128 *a) +{ + r->frac_hi = a->frac_hi; + r->frac_hm = a->frac_lo; + r->frac_lm = 0; + r->frac_lo = 0; +} + +#define frac_widen(A, B) FRAC_GENERIC_64_128(widen, B)(A, B) + #define partsN(NAME) glue(glue(glue(parts,N),_),NAME) #define FloatPartsN glue(FloatParts,N) #define FloatPartsW glue(FloatParts,W) @@ -1016,6 +1173,12 @@ static void frac128_truncjam(FloatParts128 *r, FloatParts256 *a) #include "softfloat-parts-addsub.c.inc" #include "softfloat-parts.c.inc" +#undef N +#undef W +#define N 256 + +#include "softfloat-parts-addsub.c.inc" + #undef N #undef W #undef partsN @@ -1386,230 +1549,48 @@ float128_mul(float128 a, float128 b, float_status *status) } /* - * Returns the result of multiplying the floating-point values `a' and - * `b' then adding 'c', with no intermediate rounding step after the - * multiplication. The operation is performed according to the - * IEC/IEEE Standard for Binary Floating-Point Arithmetic 754-2008. - * The flags argument allows the caller to select negation of the - * addend, the intermediate product, or the final result. (The - * difference between this and having the caller do a separate - * negation is that negating externally will flip the sign bit on - * NaNs.) + * Fused multiply-add */ -static FloatParts64 muladd_floats(FloatParts64 a, FloatParts64 b, FloatParts64 c, - int flags, float_status *s) -{ - bool inf_zero, p_sign; - bool sign_flip = flags & float_muladd_negate_result; - FloatClass p_class; - uint64_t hi, lo; - int p_exp; - int ab_mask, abc_mask; - - ab_mask = float_cmask(a.cls) | float_cmask(b.cls); - abc_mask = float_cmask(c.cls) | ab_mask; - inf_zero = ab_mask == float_cmask_infzero; - - /* It is implementation-defined whether the cases of (0,inf,qnan) - * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN - * they return if they do), so we have to hand this information - * off to the target-specific pick-a-NaN routine. - */ - if (unlikely(abc_mask & float_cmask_anynan)) { - return *parts_pick_nan_muladd(&a, &b, &c, s, ab_mask, abc_mask); - } - - if (inf_zero) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - - if (flags & float_muladd_negate_c) { - c.sign ^= 1; - } - - p_sign = a.sign ^ b.sign; - - if (flags & float_muladd_negate_product) { - p_sign ^= 1; - } - - if (ab_mask & float_cmask_inf) { - p_class = float_class_inf; - } else if (ab_mask & float_cmask_zero) { - p_class = float_class_zero; - } else { - p_class = float_class_normal; - } - - if (c.cls == float_class_inf) { - if (p_class == float_class_inf && p_sign != c.sign) { - float_raise(float_flag_invalid, s); - parts_default_nan(&c, s); - } else { - c.sign ^= sign_flip; - } - return c; - } - - if (p_class == float_class_inf) { - a.cls = float_class_inf; - a.sign = p_sign ^ sign_flip; - return a; - } - - if (p_class == float_class_zero) { - if (c.cls == float_class_zero) { - if (p_sign != c.sign) { - p_sign = s->float_rounding_mode == float_round_down; - } - c.sign = p_sign; - } else if (flags & float_muladd_halve_result) { - c.exp -= 1; - } - c.sign ^= sign_flip; - return c; - } - - /* a & b should be normals now... */ - assert(a.cls == float_class_normal && - b.cls == float_class_normal); - - p_exp = a.exp + b.exp; - - mul64To128(a.frac, b.frac, &hi, &lo); - - /* Renormalize to the msb. */ - if (hi & DECOMPOSED_IMPLICIT_BIT) { - p_exp += 1; - } else { - shortShift128Left(hi, lo, 1, &hi, &lo); - } - - /* + add/sub */ - if (c.cls != float_class_zero) { - int exp_diff = p_exp - c.exp; - if (p_sign == c.sign) { - /* Addition */ - if (exp_diff <= 0) { - shift64RightJamming(hi, -exp_diff, &hi); - p_exp = c.exp; - if (uadd64_overflow(hi, c.frac, &hi)) { - shift64RightJamming(hi, 1, &hi); - hi |= DECOMPOSED_IMPLICIT_BIT; - p_exp += 1; - } - } else { - uint64_t c_hi, c_lo, over; - shift128RightJamming(c.frac, 0, exp_diff, &c_hi, &c_lo); - add192(0, hi, lo, 0, c_hi, c_lo, &over, &hi, &lo); - if (over) { - shift64RightJamming(hi, 1, &hi); - hi |= DECOMPOSED_IMPLICIT_BIT; - p_exp += 1; - } - } - } else { - /* Subtraction */ - uint64_t c_hi = c.frac, c_lo = 0; - - if (exp_diff <= 0) { - shift128RightJamming(hi, lo, -exp_diff, &hi, &lo); - if (exp_diff == 0 - && - (hi > c_hi || (hi == c_hi && lo >= c_lo))) { - sub128(hi, lo, c_hi, c_lo, &hi, &lo); - } else { - sub128(c_hi, c_lo, hi, lo, &hi, &lo); - p_sign ^= 1; - p_exp = c.exp; - } - } else { - shift128RightJamming(c_hi, c_lo, - exp_diff, - &c_hi, &c_lo); - sub128(hi, lo, c_hi, c_lo, &hi, &lo); - } - - if (hi == 0 && lo == 0) { - a.cls = float_class_zero; - a.sign = s->float_rounding_mode == float_round_down; - a.sign ^= sign_flip; - return a; - } else { - int shift; - if (hi != 0) { - shift = clz64(hi); - } else { - shift = clz64(lo) + 64; - } - /* Normalizing to a binary point of 124 is the - correct adjust for the exponent. However since we're - shifting, we might as well put the binary point back - at 63 where we really want it. Therefore shift as - if we're leaving 1 bit at the top of the word, but - adjust the exponent as if we're leaving 3 bits. */ - shift128Left(hi, lo, shift, &hi, &lo); - p_exp -= shift; - } - } - } - hi |= (lo != 0); - - if (flags & float_muladd_halve_result) { - p_exp -= 1; - } - - /* finally prepare our result */ - a.cls = float_class_normal; - a.sign = p_sign ^ sign_flip; - a.exp = p_exp; - a.frac = hi; - - return a; -} - float16 QEMU_FLATTEN float16_muladd(float16 a, float16 b, float16 c, - int flags, float_status *status) + int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); float16_unpack_canonical(&pc, c, status); - pr = muladd_floats(pa, pb, pc, flags, status); + pr = parts_muladd(&pa, &pb, &pc, flags, status); - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } static float32 QEMU_SOFTFLOAT_ATTR soft_f32_muladd(float32 a, float32 b, float32 c, int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); float32_unpack_canonical(&pc, c, status); - pr = muladd_floats(pa, pb, pc, flags, status); + pr = parts_muladd(&pa, &pb, &pc, flags, status); - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } static float64 QEMU_SOFTFLOAT_ATTR soft_f64_muladd(float64 a, float64 b, float64 c, int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); float64_unpack_canonical(&pc, c, status); - pr = muladd_floats(pa, pb, pc, flags, status); + pr = parts_muladd(&pa, &pb, &pc, flags, status); - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } static bool force_soft_fma; @@ -1756,23 +1737,30 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s); } -/* - * Returns the result of multiplying the bfloat16 values `a' - * and `b' then adding 'c', with no intermediate rounding step after the - * multiplication. - */ - bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { - FloatParts64 pa, pb, pc, pr; + FloatParts64 pa, pb, pc, *pr; bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); bfloat16_unpack_canonical(&pc, c, status); - pr = muladd_floats(pa, pb, pc, flags, status); + pr = parts_muladd(&pa, &pb, &pc, flags, status); - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); +} + +float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c, + int flags, float_status *status) +{ + FloatParts128 pa, pb, pc, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + float128_unpack_canonical(&pc, c, status); + pr = parts_muladd(&pa, &pb, &pc, flags, status); + + return float128_round_pack_canonical(pr, status); } /* diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index d319993280..c24baf8535 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -386,7 +386,7 @@ static void bench(enum precision prec, enum op op, int n_ops, bool no_neg) for (i = 0; i < OPS_PER_ITER; i++) { float128 a = ops[0].f128; float128 b = ops[1].f128; - /* float128 c = ops[2].f128; */ + float128 c = ops[2].f128; switch (op) { case OP_ADD: @@ -401,9 +401,9 @@ static void bench(enum precision prec, enum op op, int n_ops, bool no_neg) case OP_DIV: res.f128 = float128_div(a, b, &soft_status); break; - /* case OP_FMA: */ - /* res.f128 = float128_muladd(a, b, c, 0, &soft_status); */ - /* break; */ + case OP_FMA: + res.f128 = float128_muladd(a, b, c, 0, &soft_status); + break; case OP_SQRT: res.f128 = float128_sqrt(a, &soft_status); break; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 5a4cad8c8b..ff131afbde 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -717,7 +717,7 @@ static void do_testfloat(int op, int rmode, bool exact) test_abz_f128(true_abz_f128M, subj_abz_f128M); break; case F128_MULADD: - not_implemented(); + test_abcz_f128(slow_f128M_mulAdd, qemu_f128M_mulAdd); break; case F128_SQRT: test_az_f128(slow_f128M_sqrt, qemu_f128M_sqrt); diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 9a67ab2bea..a203811299 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -413,3 +413,129 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b, a->sign = sign; return a; } + +/* + * Returns the result of multiplying the floating-point values `a' and + * `b' then adding 'c', with no intermediate rounding step after the + * multiplication. The operation is performed according to the + * IEC/IEEE Standard for Binary Floating-Point Arithmetic 754-2008. + * The flags argument allows the caller to select negation of the + * addend, the intermediate product, or the final result. (The + * difference between this and having the caller do a separate + * negation is that negating externally will flip the sign bit on NaNs.) + * + * Requires A and C extracted into a double-sized structure to provide the + * extra space for the widening multiply. + */ +static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, + FloatPartsN *c, int flags, float_status *s) +{ + int ab_mask, abc_mask; + FloatPartsW p_widen, c_widen; + + ab_mask = float_cmask(a->cls) | float_cmask(b->cls); + abc_mask = float_cmask(c->cls) | ab_mask; + + /* + * It is implementation-defined whether the cases of (0,inf,qnan) + * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN + * they return if they do), so we have to hand this information + * off to the target-specific pick-a-NaN routine. + */ + if (unlikely(abc_mask & float_cmask_anynan)) { + return parts_pick_nan_muladd(a, b, c, s, ab_mask, abc_mask); + } + + if (flags & float_muladd_negate_c) { + c->sign ^= 1; + } + + /* Compute the sign of the product into A. */ + a->sign ^= b->sign; + if (flags & float_muladd_negate_product) { + a->sign ^= 1; + } + + if (unlikely(ab_mask != float_cmask_normal)) { + if (unlikely(ab_mask == float_cmask_infzero)) { + goto d_nan; + } + + if (ab_mask & float_cmask_inf) { + if (c->cls == float_class_inf && a->sign != c->sign) { + goto d_nan; + } + goto return_inf; + } + + g_assert(ab_mask & float_cmask_zero); + if (c->cls == float_class_normal) { + *a = *c; + goto return_normal; + } + if (c->cls == float_class_zero) { + if (a->sign != c->sign) { + goto return_sub_zero; + } + goto return_zero; + } + g_assert(c->cls == float_class_inf); + } + + if (unlikely(c->cls == float_class_inf)) { + a->sign = c->sign; + goto return_inf; + } + + /* Perform the multiplication step. */ + p_widen.sign = a->sign; + p_widen.exp = a->exp + b->exp + 1; + frac_mulw(&p_widen, a, b); + if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + frac_add(&p_widen, &p_widen, &p_widen); + p_widen.exp -= 1; + } + + /* Perform the addition step. */ + if (c->cls != float_class_zero) { + /* Zero-extend C to less significant bits. */ + frac_widen(&c_widen, c); + c_widen.exp = c->exp; + + if (a->sign == c->sign) { + parts_add_normal(&p_widen, &c_widen); + } else if (!parts_sub_normal(&p_widen, &c_widen)) { + goto return_sub_zero; + } + } + + /* Narrow with sticky bit, for proper rounding later. */ + frac_truncjam(a, &p_widen); + a->sign = p_widen.sign; + a->exp = p_widen.exp; + + return_normal: + if (flags & float_muladd_halve_result) { + a->exp -= 1; + } + finish_sign: + if (flags & float_muladd_negate_result) { + a->sign ^= 1; + } + return a; + + return_sub_zero: + a->sign = s->float_rounding_mode == float_round_down; + return_zero: + a->cls = float_class_zero; + goto finish_sign; + + return_inf: + a->cls = float_class_inf; + goto finish_sign; + + d_nan: + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; +} diff --git a/tests/fp/wrap.c.inc b/tests/fp/wrap.c.inc index 0cbd20013e..cb1bb77e4c 100644 --- a/tests/fp/wrap.c.inc +++ b/tests/fp/wrap.c.inc @@ -574,6 +574,18 @@ WRAP_MULADD(qemu_f32_mulAdd, float32_muladd, float32) WRAP_MULADD(qemu_f64_mulAdd, float64_muladd, float64) #undef WRAP_MULADD +static void qemu_f128M_mulAdd(const float128_t *ap, const float128_t *bp, + const float128_t *cp, float128_t *res) +{ + float128 a, b, c, ret; + + a = soft_to_qemu128(*ap); + b = soft_to_qemu128(*bp); + c = soft_to_qemu128(*cp); + ret = float128_muladd(a, b, c, 0, &qsf); + *res = qemu_to_soft128(ret); +} + #define WRAP_CMP16(name, func, retcond) \ static bool name(float16_t a, float16_t b) \ { \ From patchwork Sat May 8 01:47:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432555 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp856235jao; Fri, 7 May 2021 19:18:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxr6SBBjhDXhZPrpeqivPB1ySEQI93BJitp98YFyq26SWlAVWl0sQyyKNoQhgE4L2qBYQUk X-Received: by 2002:a05:6e02:58c:: with SMTP id c12mr12290407ils.152.1620440280543; Fri, 07 May 2021 19:18:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440280; cv=none; d=google.com; s=arc-20160816; b=0FRQMB2r/uZ3QWQHxgLLPy6MdLTODggr5vGnOD3O1Dj+DroIB059xQh4oNWJbvQQS6 QryntSgkJ9+VgTvaQz/UKjOmkZ17Z5HUar2mYwkzeOxMUEDaP0UhAHNkNWodijMjcNMA N3qlQyNeBXPJxbSCjodS1tX62DS6bxsUz75QBFKdOE5nij+AXxab4OlwAW8vCj4baayS X/hen5i3nPcSVGI/CMqRpsJYWYScfdV0+sxQz+k1wId+bbQi5sQNnC67LDSliYX7ZGF0 nvAzG2wU+F7rmHiPGBk3740nwZFFF0BY2poOhH5rGFPZ/47zJ9hcVA4jhyNBu/4slGT7 6PZg== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id 16si8333266ilt.35.2021.05.07.19.18.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:18:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="c6tA/hOm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCXY-0007pi-0h for patch@linaro.org; Fri, 07 May 2021 22:18:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41004) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC5G-0004ro-1o for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:46 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:38815) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC50-0003g1-45 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:48:45 -0400 Received: by mail-pl1-x634.google.com with SMTP id 69so1536078plc.5 for ; Fri, 07 May 2021 18:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RndXytbTpyoZf87SoTBz0zxUXITxwgpEDPn6NB45UNI=; b=c6tA/hOmsdMywC7W6Ey8D5CCg+Rr2zLDoZgOe0uv18/UucQXgny8Uul1FftPE34/rw cXNLzgkJLuYZaFVgzX6J14kK6Hxp1jU7XOoQqRqoNFMbNoooL5qPZDQL1gmgAQELRa8u hH6amW3qXptSWEc14UNCwr93OnEvNqu2dQK3WddfS8SEeFDmyu+USLYn+fZMe5tG8JVT cHZPIpzff7CLJyajAtyVSxN98mte6WvoX7bq+Fy1OVAuyx8a8Y4E/JLMhWqAUoANy7JL ThffoUiqX2jrcdGJpGzFBXW5J10HWYESFYkAz/57aEScwvdFs/jzU8J6e+qT8lc4UXhr vqWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RndXytbTpyoZf87SoTBz0zxUXITxwgpEDPn6NB45UNI=; b=rVFr6l1mYHa20vI1528ERaEClsTTsjZkhjqPNm8jsjV++bFKtU5N37rRT+II7uqxC9 SXyj6bgPXs4lFOExdLTXZ6uieiFRuCI+m2SzsK5h+zIuXEsUXiUwvKQgmJNu2cmJeVeW PgCWmie7A26uPSFUCVB/gZ4N3icCMpCqIRfLUxmUh6/FMOmL9eu+nDkm8bLchOhkEOZN DEwbtN0EVgTEApsdj7WeQ9UIRykhpv6x3AlNHAOq0DJRc1N7sQkqXDNsGV3YBY4pRUMv r2BbuoKGHszKoUuP3oEx+APEl2wO3x+22uiJj9IYe8TILiHTsVxKOqV5ewQJcARUR09D vkgQ== X-Gm-Message-State: AOAM532gxzju3dx2VALkPaIyZRft1sLm7K9aqpeL5kv8vQyW1FxMhb+H uc1U+fj8mvGOddp1/evGtqbavpu8WKkudA== X-Received: by 2002:a17:902:a9cb:b029:ed:61be:2cfb with SMTP id b11-20020a170902a9cbb02900ed61be2cfbmr13180155plr.9.1620438508352; Fri, 07 May 2021 18:48:28 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id t4sm5819681pfq.165.2021.05.07.18.48.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:48:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 38/72] softfloat: Use mulu64 for mul64To128 Date: Fri, 7 May 2021 18:47:28 -0700 Message-Id: <20210508014802.892561-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Via host-utils.h, we use a host widening multiply for 64-bit hosts, and a common subroutine for 32-bit hosts. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 2e3760a9c1..f6dfbe108d 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -470,27 +470,10 @@ static inline void sub192(uint64_t a0, uint64_t a1, uint64_t a2, | `z0Ptr' and `z1Ptr'. *----------------------------------------------------------------------------*/ -static inline void mul64To128( uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr ) +static inline void +mul64To128(uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr) { - uint32_t aHigh, aLow, bHigh, bLow; - uint64_t z0, zMiddleA, zMiddleB, z1; - - aLow = a; - aHigh = a>>32; - bLow = b; - bHigh = b>>32; - z1 = ( (uint64_t) aLow ) * bLow; - zMiddleA = ( (uint64_t) aLow ) * bHigh; - zMiddleB = ( (uint64_t) aHigh ) * bLow; - z0 = ( (uint64_t) aHigh ) * bHigh; - zMiddleA += zMiddleB; - z0 += ( ( (uint64_t) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 ); - zMiddleA <<= 32; - z1 += zMiddleA; - z0 += ( z1 < zMiddleA ); - *z1Ptr = z1; - *z0Ptr = z0; - + mulu64(z1Ptr, z0Ptr, a, b); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432559 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp859363jao; Fri, 7 May 2021 19:24:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwbsHIzUDmoPb/OkdnoJDZXZdG2Sc6dePLBSw5wrULsPqM7jW7pdY8KhmOIjIY4OIS9WgHl X-Received: by 2002:a05:6e02:1488:: with SMTP id n8mr12901698ilk.158.1620440664231; Fri, 07 May 2021 19:24:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440664; cv=none; d=google.com; s=arc-20160816; b=fsaL6wmwwgeNz7TMh1socg9FcRsIWJScyBlCtWBPJ9ytWY0FGX+mocPoMQllX6A7cR ZZA5Cfr+QoRvKaj3bUqfNyqos7fOF8IoLOWDO55guUuye5wKFJXkO0Zv7k0sr0H3fZBW k7kQWLJHopHjq3uYFZIMENhUlY91Jo7yQejmQK2qmu+igbUbXn8spFfEAmTAPtvZv1fi mKgkm6OyR9bmzxg7rFOt5u8wevn4XXO0JnqYkUb2vdOX56m6l1ClOLd7q0VRM5ALrTV5 eWQE/Dsx+E1yBTgRAKu2fnVrMb0hVZpDF4UTIXBqNYg8B4VlNdC+gBoQB2G0nQ4pk3h+ DByg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MnGbP0t9ipMuFDDfgVLV3xJxRcipksJ9kWE5+MnyCZM=; b=HBPLxWeD8kJVqjrauyB+2cTOB2gbrpt1Nmzxc1awiRyrVTEcHw/GKFP20L5bxk4xez GTGVKgm24vPG8FhfsrEHBhSAVKY6AJZplyalC9/hawKLMJXEi8LWAFt5m/BIrfbiJHqf E4yuhwvEdidw4kCnD6jPPQShYFr/55rj1rICYQ4oRz5+g5T34dfyo7BcLXYo8qRLq3DX KJ2/JDRrxDw8iq4K4M8omlCX1GcmvC8/sYCKwrhNYQxUUrMoWn/3z6k03S1PM/Xg8oEg U3T/q5RHq/Ac36SX2IslKRWOu9AFq0vsv+xT/Q7pCpLlS7pftOE+KeD4ZiGWwcPbbTkv Cfzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tijmRvN3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 37 +++++++++++----------------------- 1 file changed, 12 insertions(+), 25 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée Tested-by: Alex Bennée diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index f6dfbe108d..76327d844d 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -511,34 +511,21 @@ static inline void | the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'. *----------------------------------------------------------------------------*/ -static inline void - mul128To256( - uint64_t a0, - uint64_t a1, - uint64_t b0, - uint64_t b1, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr, - uint64_t *z3Ptr - ) +static inline void mul128To256(uint64_t a0, uint64_t a1, + uint64_t b0, uint64_t b1, + uint64_t *z0Ptr, uint64_t *z1Ptr, + uint64_t *z2Ptr, uint64_t *z3Ptr) { - uint64_t z0, z1, z2, z3; - uint64_t more1, more2; + uint64_t z0, z1, z2; + uint64_t m0, m1, m2, n1, n2; - mul64To128( a1, b1, &z2, &z3 ); - mul64To128( a1, b0, &z1, &more2 ); - add128( z1, more2, 0, z2, &z1, &z2 ); - mul64To128( a0, b0, &z0, &more1 ); - add128( z0, more1, 0, z1, &z0, &z1 ); - mul64To128( a0, b1, &more1, &more2 ); - add128( more1, more2, 0, z2, &more1, &z2 ); - add128( z0, z1, 0, more1, &z0, &z1 ); - *z3Ptr = z3; - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; + mul64To128(a1, b0, &m1, &m2); + mul64To128(a0, b1, &n1, &n2); + mul64To128(a1, b1, &z2, z3Ptr); + mul64To128(a0, b0, &z0, &z1); + add192( 0, m1, m2, 0, n1, n2, &m0, &m1, &m2); + add192(m0, m1, m2, z0, z1, z2, z0Ptr, z1Ptr, z2Ptr); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432556 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp857528jao; Fri, 7 May 2021 19:20:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwRveRTd+/aEUHJCOk3XERpEoK4s/ceqECl266pX3IB29JTxB6KGIkI19cdjrIx4gYU9yve X-Received: by 2002:a25:2f0c:: with SMTP id v12mr17613364ybv.217.1620440435646; Fri, 07 May 2021 19:20:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440435; cv=none; d=google.com; s=arc-20160816; b=mSwjwWcFMfhXyF+eC3X6X6c1QVeWqZcDXbAeFp9MUYP3ExcbVBg0GBAf/1gsX17Dyb Hfsn+SsMx8drB3iDyWdc+Apk51crI+RaEi94JIO6yBZovVwR0WeAgH8jqgeIAb8xZEED MBmPyY+4Gmz4FECpNSDB5cBMKyMAJ4Us1SXaKKB419OFM4ndIxbu5vGlJXZn8rTM/FRL kARubrA84jwhfhL6NbIO4XQh4ZheneukOcZaXYZFVB5M03uFvVu2sSDMCghIjtgtUnJC LBlNbsxAL/aiLYzI16CXVmCU0lqddf6Y5n9vT2j7qs94xawfQISGZsfziB7EixTJT0+7 dArQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XXqS6PgcSZlxXGytmQAaetCCBR4/W9tsx3dsxyfVI/Y=; b=zbS+K5oJ+0Xy99kFIxJhuqXtNRAEGsPc7I74gDifWEMy8wK6Co0NyRQ85DNvEGNg+z sVD4tzCSMFFc21imwusLNN2fQESRD0h1UVb7kHcGnD1xsv/bWvhvEw2Tlxg83rrwUUwY i3ezjQiOs6eZFZzA8/6j2CrmBi7OskAmHHWHnF0iGmsYk1UmOOk5vyXC8SCg2ytli8A/ eqVad98dVLy0N6iZoHzxAEBCZPAgYWB8csn7BGDz9b4qiYYsV82++rV65d0JI7MRp06h PXhZhS/bcvjy6RMCX0kDCXthJdi7cwnwY9PzPzZeoQonzS4ixVowj40cNDM9+V/2ktL7 TKAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FPWUY0Jc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a6si6592526ybe.431.2021.05.07.19.20.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:20:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FPWUY0Jc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCa3-0001pF-58 for patch@linaro.org; Fri, 07 May 2021 22:20:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC7x-0002YV-23 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:33 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:38819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC7v-0005OM-Dc for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:32 -0400 Received: by mail-pl1-x632.google.com with SMTP id 69so1538212plc.5 for ; Fri, 07 May 2021 18:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XXqS6PgcSZlxXGytmQAaetCCBR4/W9tsx3dsxyfVI/Y=; b=FPWUY0JclDLztfx6qzMYlXc69eigfkVVOqzGCNuVWKVgTb+X9DWCiW7wnSKaVTh3Fy CcUttI4zPrjRtYW/mnKgQlA+T/haM+pEPEfO6cIu2VJncaxUE6by/SpEoXY9Ueuewihk o/mhN9hWNYpBmjqHLwqucDfryL5kLgN/0Mry9PfzJ/2fPL5KnFVn7QulInUuQt7w1GUI cUDF0nBTEOO21aJLm9IdbPFEF6s1z8aOriYd1kdvnBuzHtBl5Idagbk88CHbJH5lSkTG V6nAuIVnrTG1a3lpX13Hznh4rN++en1IF/KTb8tItQlQR+4nTq9oaQGmSa+p43FN6KFf Cqnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XXqS6PgcSZlxXGytmQAaetCCBR4/W9tsx3dsxyfVI/Y=; b=ET4aPWnNfkjd2/hZOQPyz8DkU3xj526nBk+doHqLN9R+xHF8bdhzcaTkIqbnVjmwVH E3TM8MqWjP1Wkcupwu6lc2Pkk463gnYK+MK2q2gKdwRCKonKxZ1kwCE+pUEcvSNY2nKg 8T2LB9hs/Pr8dxCKtnMnVo3teeYnK68AJCipZCIP7Y1+d/gmdjxERXUBcEOJNW451BYt ceEwwYH8EBdPL+Hojt/VNbLkXa75Zy3FBVTzfD/9kiYsrYh+BdKEgFEE0MNvgKyT65Mi KrlhrIRqpDdfRNWLlpmgep8j63176Qxttk53vfMNDVrrZXuDzw1eTLTuWWssqpcRsXJv fbZw== X-Gm-Message-State: AOAM532cT5xD9da6NPxo28HGFK643pMFZoteMORIOGmr2jgSTZT/enZ3 jV++j1dr3tMdjC1qS8y3JgQnfxvDP0PIlA== X-Received: by 2002:a17:90b:19c9:: with SMTP id nm9mr13107190pjb.98.1620438690003; Fri, 07 May 2021 18:51:30 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 40/72] softfloat: Tidy mul128By64To192 Date: Fri, 7 May 2021 18:47:30 -0700 Message-Id: <20210508014802.892561-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Clean up the formatting and variables; no functional change. Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 76327d844d..672c1db555 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -484,24 +484,14 @@ mul64To128(uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t *z1Ptr) *----------------------------------------------------------------------------*/ static inline void - mul128By64To192( - uint64_t a0, - uint64_t a1, - uint64_t b, - uint64_t *z0Ptr, - uint64_t *z1Ptr, - uint64_t *z2Ptr - ) +mul128By64To192(uint64_t a0, uint64_t a1, uint64_t b, + uint64_t *z0Ptr, uint64_t *z1Ptr, uint64_t *z2Ptr) { - uint64_t z0, z1, z2, more1; - - mul64To128( a1, b, &z1, &z2 ); - mul64To128( a0, b, &z0, &more1 ); - add128( z0, more1, 0, z1, &z0, &z1 ); - *z2Ptr = z2; - *z1Ptr = z1; - *z0Ptr = z0; + uint64_t z0, z1, m1; + mul64To128(a1, b, &m1, z2Ptr); + mul64To128(a0, b, &z0, &z1); + add128(z0, z1, 0, m1, z0Ptr, z1Ptr); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432558 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp858458jao; Fri, 7 May 2021 19:22:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxIDv0vExQaqB8cbgdKcKcMcW8TuZ93jvgkQDi/xLebNrHPCS6JonFctlEQEg/WenOu2+7M X-Received: by 2002:a05:620a:10a8:: with SMTP id h8mr12336039qkk.411.1620440547680; Fri, 07 May 2021 19:22:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440547; cv=none; d=google.com; s=arc-20160816; b=T8yvYm7PqaChbet6JGFW48Zxl8NvPTOK0njVf37DhIgaYI5Lx1Wvxv1PqZ1RWjOmqR FT9BqlfE7riuB8b5cONoO2YlJVXdS4HJtPRPC13bgFyUZdl5Q3MTqxv+7iBbnHJZTxDs i34hncQxQ22nfG2c/Q4FTetO+0uspPdqU9O2sDTbumKs6jKIKlh3ffLUJq76NHg5Jdum MDHX3PKN8dtt3cDwm9zP2Su+bxT7aRRAolg9ja2YtnPGujGfJH1RNCvtUjNbefUYJKE+ /B2+EsX62EbKAgKsGSM/YOlwzjXhGw9/SOoLvmRCEHOavS9MugW/tkGTEySH1CX0enVp kVhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DbYb1T7r/x3Vwe1nQCdfG81vfl3PJk8e2zSpVeaOReo=; b=avJi8GqDNt+wNtZ/LCO0aHhIKSGcKHKOpjMwMhZHhpDsQ3SMgunusSW+rPiHiiHyNh DaWPzvrjPaou4bIHSOKVKjwPPubypSfCBjT1hUAaNgiGkWtYqtGW6bIX9hm77e85zWKP Sg1Q2Qp4pDK/lzIs4trG1VqB1DP8zbF1cBh9nZK667kpq4ymlWhfno/TxauE5sLUX1oI e9Z74HnN9i1bYpMhLC/VUySWvGC0pUHs5xjmNYIdACm2VyKhkUa4pjUluj23Y6i2xatX o2FZ7pPDyVFVghVhdaELUMrl8n66a2BDGqDAdvZ5WwOgzIQPHHKbaSOzdDBUDduQlTr1 GPoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jk9Rb53g; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This avoids shuffling values through %cl in the x86 case. Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 36 ++++++++++++ fpu/softfloat.c | 102 +++++++++++++++++++++++++-------- 2 files changed, 115 insertions(+), 23 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 672c1db555..ec4e27a595 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -85,6 +85,42 @@ this code that are retained. #include "fpu/softfloat-types.h" #include "qemu/host-utils.h" +/** + * shl_double: double-word merging left shift + * @l: left or most-significant word + * @r: right or least-significant word + * @c: shift count + * + * Shift @l left by @c bits, shifting in bits from @r. + */ +static inline uint64_t shl_double(uint64_t l, uint64_t r, int c) +{ +#if defined(__x86_64__) + asm("shld %b2, %1, %0" : "+r"(l) : "r"(r), "ci"(c)); + return l; +#else + return c ? (l << c) | (r >> (64 - c)) : l; +#endif +} + +/** + * shr_double: double-word merging right shift + * @l: left or most-significant word + * @r: right or least-significant word + * @c: shift count + * + * Shift @r right by @c bits, shifting in bits from @l. + */ +static inline uint64_t shr_double(uint64_t l, uint64_t r, int c) +{ +#if defined(__x86_64__) + asm("shrd %b2, %1, %0" : "+r"(r) : "r"(l), "ci"(c)); + return r; +#else + return c ? (r >> c) | (l << (64 - c)) : r; +#endif +} + /*---------------------------------------------------------------------------- | Shifts `a' right by the number of bits given in `count'. If any nonzero | bits are shifted off, they are ``jammed'' into the least significant bit of diff --git a/fpu/softfloat.c b/fpu/softfloat.c index a9ee8498ae..a42c297828 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -956,15 +956,12 @@ static int frac128_normalize(FloatParts128 *a) { if (a->frac_hi) { int shl = clz64(a->frac_hi); - if (shl) { - int shr = 64 - shl; - a->frac_hi = (a->frac_hi << shl) | (a->frac_lo >> shr); - a->frac_lo = (a->frac_lo << shl); - } + a->frac_hi = shl_double(a->frac_hi, a->frac_lo, shl); + a->frac_lo <<= shl; return shl; } else if (a->frac_lo) { int shl = clz64(a->frac_lo); - a->frac_hi = (a->frac_lo << shl); + a->frac_hi = a->frac_lo << shl; a->frac_lo = 0; return shl + 64; } @@ -975,7 +972,7 @@ static int frac256_normalize(FloatParts256 *a) { uint64_t a0 = a->frac_hi, a1 = a->frac_hm; uint64_t a2 = a->frac_lm, a3 = a->frac_lo; - int ret, shl, shr; + int ret, shl; if (likely(a0)) { shl = clz64(a0); @@ -1005,11 +1002,10 @@ static int frac256_normalize(FloatParts256 *a) ret += shl; } - shr = -shl & 63; - a0 = (a0 << shl) | (a1 >> shr); - a1 = (a1 << shl) | (a2 >> shr); - a2 = (a2 << shl) | (a3 >> shr); - a3 = (a3 << shl); + a0 = shl_double(a0, a1, shl); + a1 = shl_double(a1, a2, shl); + a2 = shl_double(a2, a3, shl); + a3 <<= shl; done: a->frac_hi = a0; @@ -1028,7 +1024,20 @@ static void frac64_shl(FloatParts64 *a, int c) static void frac128_shl(FloatParts128 *a, int c) { - shift128Left(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); + uint64_t a0 = a->frac_hi, a1 = a->frac_lo; + + if (c & 64) { + a0 = a1, a1 = 0; + } + + c &= 63; + if (c) { + a0 = shl_double(a0, a1, c); + a1 = a1 << c; + } + + a->frac_hi = a0; + a->frac_lo = a1; } #define frac_shl(A, C) FRAC_GENERIC_64_128(shl, A)(A, C) @@ -1040,19 +1049,68 @@ static void frac64_shr(FloatParts64 *a, int c) static void frac128_shr(FloatParts128 *a, int c) { - shift128Right(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); + uint64_t a0 = a->frac_hi, a1 = a->frac_lo; + + if (c & 64) { + a1 = a0, a0 = 0; + } + + c &= 63; + if (c) { + a1 = shr_double(a0, a1, c); + a0 = a0 >> c; + } + + a->frac_hi = a0; + a->frac_lo = a1; } #define frac_shr(A, C) FRAC_GENERIC_64_128(shr, A)(A, C) static void frac64_shrjam(FloatParts64 *a, int c) { - shift64RightJamming(a->frac, c, &a->frac); + uint64_t a0 = a->frac; + + if (likely(c != 0)) { + if (likely(c < 64)) { + a0 = (a0 >> c) | (shr_double(a0, 0, c) != 0); + } else { + a0 = a0 != 0; + } + a->frac = a0; + } } static void frac128_shrjam(FloatParts128 *a, int c) { - shift128RightJamming(a->frac_hi, a->frac_lo, c, &a->frac_hi, &a->frac_lo); + uint64_t a0 = a->frac_hi, a1 = a->frac_lo; + uint64_t sticky = 0; + + if (unlikely(c == 0)) { + return; + } else if (likely(c < 64)) { + /* nothing */ + } else if (likely(c < 128)) { + sticky = a1; + a1 = a0; + a0 = 0; + c &= 63; + if (c == 0) { + goto done; + } + } else { + sticky = a0 | a1; + a0 = a1 = 0; + goto done; + } + + sticky |= shr_double(a1, 0, c); + a1 = shr_double(a0, a1, c); + a0 = a0 >> c; + + done: + a->frac_lo = a1 | (sticky != 0); + a->frac_hi = a0; } static void frac256_shrjam(FloatParts256 *a, int c) @@ -1060,7 +1118,6 @@ static void frac256_shrjam(FloatParts256 *a, int c) uint64_t a0 = a->frac_hi, a1 = a->frac_hm; uint64_t a2 = a->frac_lm, a3 = a->frac_lo; uint64_t sticky = 0; - int invc; if (unlikely(c == 0)) { return; @@ -1085,12 +1142,11 @@ static void frac256_shrjam(FloatParts256 *a, int c) goto done; } - invc = -c & 63; - sticky |= a3 << invc; - a3 = (a3 >> c) | (a2 << invc); - a2 = (a2 >> c) | (a1 << invc); - a1 = (a1 >> c) | (a0 << invc); - a0 = (a0 >> c); + sticky |= shr_double(a3, 0, c); + a3 = shr_double(a2, a3, c); + a2 = shr_double(a1, a2, c); + a1 = shr_double(a0, a1, c); + a0 = a0 >> c; done: a->frac_lo = a3 | (sticky != 0); From patchwork Sat May 8 01:47:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432562 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp860126jao; 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Implement float128_div with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 290 +++++++++++++++----------------------- fpu/softfloat-parts.c.inc | 55 ++++++++ 2 files changed, 171 insertions(+), 174 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index a42c297828..8efa52f7ec 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -802,6 +802,14 @@ static FloatParts128 *parts128_muladd(FloatParts128 *a, FloatParts128 *b, #define parts_muladd(A, B, C, Z, S) \ PARTS_GENERIC_64_128(muladd, A)(A, B, C, Z, S) +static FloatParts64 *parts64_div(FloatParts64 *a, FloatParts64 *b, + float_status *s); +static FloatParts128 *parts128_div(FloatParts128 *a, FloatParts128 *b, + float_status *s); + +#define parts_div(A, B, S) \ + PARTS_GENERIC_64_128(div, A)(A, B, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -894,6 +902,87 @@ static void frac128_clear(FloatParts128 *a) #define frac_clear(A) FRAC_GENERIC_64_128(clear, A)(A) +static bool frac64_div(FloatParts64 *a, FloatParts64 *b) +{ + uint64_t n1, n0, r, q; + bool ret; + + /* + * We want a 2*N / N-bit division to produce exactly an N-bit + * result, so that we do not lose any precision and so that we + * do not have to renormalize afterward. If A.frac < B.frac, + * then division would produce an (N-1)-bit result; shift A left + * by one to produce the an N-bit result, and return true to + * decrement the exponent to match. + * + * The udiv_qrnnd algorithm that we're using requires normalization, + * i.e. the msb of the denominator must be set, which is already true. + */ + ret = a->frac < b->frac; + if (ret) { + n0 = a->frac; + n1 = 0; + } else { + n0 = a->frac >> 1; + n1 = a->frac << 63; + } + q = udiv_qrnnd(&r, n0, n1, b->frac); + + /* Set lsb if there is a remainder, to set inexact. */ + a->frac = q | (r != 0); + + return ret; +} + +static bool frac128_div(FloatParts128 *a, FloatParts128 *b) +{ + uint64_t q0, q1, a0, a1, b0, b1; + uint64_t r0, r1, r2, r3, t0, t1, t2, t3; + bool ret = false; + + a0 = a->frac_hi, a1 = a->frac_lo; + b0 = b->frac_hi, b1 = b->frac_lo; + + ret = lt128(a0, a1, b0, b1); + if (!ret) { + a1 = shr_double(a0, a1, 1); + a0 = a0 >> 1; + } + + /* Use 128/64 -> 64 division as estimate for 192/128 -> 128 division. */ + q0 = estimateDiv128To64(a0, a1, b0); + + /* + * Estimate is high because B1 was not included (unless B1 == 0). + * Reduce quotient and increase remainder until remainder is non-negative. + * This loop will execute 0 to 2 times. + */ + mul128By64To192(b0, b1, q0, &t0, &t1, &t2); + sub192(a0, a1, 0, t0, t1, t2, &r0, &r1, &r2); + while (r0 != 0) { + q0--; + add192(r0, r1, r2, 0, b0, b1, &r0, &r1, &r2); + } + + /* Repeat using the remainder, producing a second word of quotient. */ + q1 = estimateDiv128To64(r1, r2, b0); + mul128By64To192(b0, b1, q1, &t1, &t2, &t3); + sub192(r1, r2, 0, t1, t2, t3, &r1, &r2, &r3); + while (r1 != 0) { + q1--; + add192(r1, r2, r3, 0, b0, b1, &r1, &r2, &r3); + } + + /* Any remainder indicates inexact; set sticky bit. */ + q1 |= (r2 | r3) != 0; + + a->frac_hi = q0; + a->frac_lo = q1; + return ret; +} + +#define frac_div(A, B) FRAC_GENERIC_64_128(div, A)(A, B) + static bool frac64_eqz(FloatParts64 *a) { return a->frac == 0; @@ -1820,110 +1909,42 @@ float128 QEMU_FLATTEN float128_muladd(float128 a, float128 b, float128 c, } /* - * Returns the result of dividing the floating-point value `a' by the - * corresponding value `b'. The operation is performed according to - * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + * Division */ -static FloatParts64 div_floats(FloatParts64 a, FloatParts64 b, float_status *s) -{ - bool sign = a.sign ^ b.sign; - - if (a.cls == float_class_normal && b.cls == float_class_normal) { - uint64_t n0, n1, q, r; - int exp = a.exp - b.exp; - - /* - * We want a 2*N / N-bit division to produce exactly an N-bit - * result, so that we do not lose any precision and so that we - * do not have to renormalize afterward. If A.frac < B.frac, - * then division would produce an (N-1)-bit result; shift A left - * by one to produce the an N-bit result, and decrement the - * exponent to match. - * - * The udiv_qrnnd algorithm that we're using requires normalization, - * i.e. the msb of the denominator must be set, which is already true. - */ - if (a.frac < b.frac) { - exp -= 1; - shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT + 1, &n1, &n0); - } else { - shift128Left(0, a.frac, DECOMPOSED_BINARY_POINT, &n1, &n0); - } - q = udiv_qrnnd(&r, n1, n0, b.frac); - - /* Set lsb if there is a remainder, to set inexact. */ - a.frac = q | (r != 0); - a.sign = sign; - a.exp = exp; - return a; - } - /* handle all the NaN cases */ - if (is_nan(a.cls) || is_nan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } - /* 0/0 or Inf/Inf */ - if (a.cls == b.cls - && - (a.cls == float_class_inf || a.cls == float_class_zero)) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - /* Inf / x or 0 / x */ - if (a.cls == float_class_inf || a.cls == float_class_zero) { - a.sign = sign; - return a; - } - /* Div 0 => Inf */ - if (b.cls == float_class_zero) { - float_raise(float_flag_divbyzero, s); - a.cls = float_class_inf; - a.sign = sign; - return a; - } - /* Div by Inf */ - if (b.cls == float_class_inf) { - a.cls = float_class_zero; - a.sign = sign; - return a; - } - g_assert_not_reached(); -} - float16 float16_div(float16 a, float16 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float16_unpack_canonical(&pa, a, status); float16_unpack_canonical(&pb, b, status); - pr = div_floats(pa, pb, status); + pr = parts_div(&pa, &pb, status); - return float16_round_pack_canonical(&pr, status); + return float16_round_pack_canonical(pr, status); } static float32 QEMU_SOFTFLOAT_ATTR soft_f32_div(float32 a, float32 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float32_unpack_canonical(&pa, a, status); float32_unpack_canonical(&pb, b, status); - pr = div_floats(pa, pb, status); + pr = parts_div(&pa, &pb, status); - return float32_round_pack_canonical(&pr, status); + return float32_round_pack_canonical(pr, status); } static float64 QEMU_SOFTFLOAT_ATTR soft_f64_div(float64 a, float64 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; float64_unpack_canonical(&pa, a, status); float64_unpack_canonical(&pb, b, status); - pr = div_floats(pa, pb, status); + pr = parts_div(&pa, &pb, status); - return float64_round_pack_canonical(&pr, status); + return float64_round_pack_canonical(pr, status); } static float hard_f32_div(float a, float b) @@ -1984,20 +2005,28 @@ float64_div(float64 a, float64 b, float_status *s) f64_div_pre, f64_div_post); } -/* - * Returns the result of dividing the bfloat16 - * value `a' by the corresponding value `b'. - */ - -bfloat16 bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) +bfloat16 QEMU_FLATTEN +bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { - FloatParts64 pa, pb, pr; + FloatParts64 pa, pb, *pr; bfloat16_unpack_canonical(&pa, a, status); bfloat16_unpack_canonical(&pb, b, status); - pr = div_floats(pa, pb, status); + pr = parts_div(&pa, &pb, status); - return bfloat16_round_pack_canonical(&pr, status); + return bfloat16_round_pack_canonical(pr, status); +} + +float128 QEMU_FLATTEN +float128_div(float128 a, float128 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr = parts_div(&pa, &pb, status); + + return float128_round_pack_canonical(pr, status); } /* @@ -7122,93 +7151,6 @@ float128 float128_round_to_int(float128 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of dividing the quadruple-precision floating-point value -| `a' by the corresponding value `b'. The operation is performed according to -| the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_div(float128 a, float128 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2; - uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - bSign = extractFloat128Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, b, status); - } - if ( bExp == 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - goto invalid; - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( bExp == 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return packFloat128( zSign, 0, 0, 0 ); - } - if ( bExp == 0 ) { - if ( ( bSig0 | bSig1 ) == 0 ) { - if ( ( aExp | aSig0 | aSig1 ) == 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - float_raise(float_flag_divbyzero, status); - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - zExp = aExp - bExp + 0x3FFD; - shortShift128Left( - aSig0 | UINT64_C(0x0001000000000000), aSig1, 15, &aSig0, &aSig1 ); - shortShift128Left( - bSig0 | UINT64_C(0x0001000000000000), bSig1, 15, &bSig0, &bSig1 ); - if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) { - shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 ); - ++zExp; - } - zSig0 = estimateDiv128To64( aSig0, aSig1, bSig0 ); - mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 ); - sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 ); - } - zSig1 = estimateDiv128To64( rem1, rem2, bSig0 ); - if ( ( zSig1 & 0x3FFF ) <= 4 ) { - mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 ); - sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 ); - } - zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 ); - } - shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 ); - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - /*---------------------------------------------------------------------------- | Returns the remainder of the quadruple-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a203811299..f8165d92f9 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -539,3 +539,58 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, parts_default_nan(a, s); return a; } + +/* + * Returns the result of dividing the floating-point value `a' by the + * corresponding value `b'. The operation is performed according to + * the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ +static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, + float_status *s) +{ + int ab_mask = float_cmask(a->cls) | float_cmask(b->cls); + bool sign = a->sign ^ b->sign; + + if (likely(ab_mask == float_cmask_normal)) { + a->sign = sign; + a->exp -= b->exp + frac_div(a, b); + return a; + } + + /* 0/0 or Inf/Inf => NaN */ + if (unlikely(ab_mask == float_cmask_zero) || + unlikely(ab_mask == float_cmask_inf)) { + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + + /* All the NaN cases */ + if (unlikely(ab_mask & float_cmask_anynan)) { + return parts_pick_nan(a, b, s); + } + + a->sign = sign; + + /* Inf / X */ + if (a->cls == float_class_inf) { + return a; + } + + /* 0 / X */ + if (a->cls == float_class_zero) { + return a; + } + + /* X / Inf */ + if (b->cls == float_class_inf) { + a->cls = float_class_zero; + return a; + } + + /* X / 0 => Inf */ + g_assert(b->cls == float_class_zero); + float_raise(float_flag_divbyzero, s); + a->cls = float_class_inf; + return a; +} From patchwork Sat May 8 01:47:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432566 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp861706jao; Fri, 7 May 2021 19:29:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyg6Opm2G7brRgB9DrmxhrLOC8GsczOhk8KugfzFEOTFX18EyExB0PWD32jtZi/MWOEZQes X-Received: by 2002:a92:6804:: with SMTP id d4mr12157309ilc.5.1620440953548; Fri, 07 May 2021 19:29:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440953; cv=none; d=google.com; s=arc-20160816; b=lPz41GZqMB5IDMYQVFh/zSu//6qEFdYhNbJYKx9BWppxTDOx/9LSmyXQKSoTtShUz2 TewRHpGHxrchGZgCr2+ii1ASdnP9XgunxobfoLCtf9VQnvfTcWWTae54MvStiIgu6bT2 Ppjg/NuznR23glo3k0ANSF0nmwWAEW9WBs9E87RUlgl4FLJvCamin8noMTd5viABhdQg LCSWjFZN9xUxTIzooKPW/61KIPJbazotrdg7ZzXrCDKzNIU8UAwcLCOeSnNfYkax1tvu FIfFSlUdjmZOxha8RoZYtwt6jkv4IZ1khytCxT9Tk1qu/Xd0MdDRUiGf1/orJwm7qQKb os6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PjO/WBUjzkzU9o07Kk08nMAvxZvCi1gtdxM9VqO6fzs=; b=qDMq4jCxsregiWk7uWfClBkNX08GxHHO0FBBlAkBDdCXsuiydGAYAt5WZpxisNOOER /rFzOdzmEiq0ll82694dnOdTHqjFoV1ATvFDlH5QSrjwPWws43elK8+3FReRkv8R0oHG tiRxMCRyvwvy8FRN3AXYdi5u7uy+S54rmwY30a6AZdqjtXI0NGdwl0Rgsn3TadtpE/Nd UY6U0MtYPRlXzoaGKICW0hHOMmtQznUqKsQhI9NztdcW99cqKi05gDZ+OJtR7DMa3Wq/ r5oAiSrfE/11CyjeVg1pllRase3dmxV+hiLqMyT3Q/5ThCqoUNtSsEO/gb9wcINNCkCT T0Rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zfAPywz0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d9si8963783ioh.18.2021.05.07.19.29.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:29:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zfAPywz0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCiO-0006Cr-Rl for patch@linaro.org; Fri, 07 May 2021 22:29:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC7z-0002hR-9B for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:35 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:56032) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC7x-0005Pm-5x for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:35 -0400 Received: by mail-pj1-x102d.google.com with SMTP id gj14so6202021pjb.5 for ; Fri, 07 May 2021 18:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PjO/WBUjzkzU9o07Kk08nMAvxZvCi1gtdxM9VqO6fzs=; b=zfAPywz0BDPYnh1ZJ/bLY7gJ/dpEoUUu5RZUhDNA+EFjXY61j0hf2Hu6RUltW/Dmb+ zj/rwiIEalT6AWYZNF/Lq6wYJiiR7hf7Rm2GPX+Cn9K+2jXpaTlTE6GZT4+hSc6nNvJB bfDJ/APxTv5uXiA8hldOKV/QLu7LK++oWqXFDsIlvgSMxnY/6GzKyS/jypg3zCfYLOME QVwLbbTATiCZjYDv7nTFxG2GtbflODNewkWJeEfhXfiRwubcEro42WfWgcq7SXZskGqu YN3fcKxEHdX7lhhh1TGnRXzVe0HGCv+hnv3WZuR/HzhYSm5Zs8GTEKyNyM/vtvIu8iDy TBdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PjO/WBUjzkzU9o07Kk08nMAvxZvCi1gtdxM9VqO6fzs=; b=d4NPPynUhHrJCCnqOuoXN1jN8VG5RWb27rmu0njY/R7W4vTOIUFzy5aYZ+5S+ajjCV GL5jqGCOyKc3ocnrMPxeurpelQXhc6De6eWMlMhv2hmxyHnbAew6aok9fQlP/3sZzRc/ uEvCt6p3S27wiKBlX/1clV3vohENhG3+EYTGySuCWtNogTURuOzjqF1DHCbwmVasmmno YyxbkGGCAM9TYfjhzEaGwqIuDSDjG7NaUUQEh/TaJf7cIUQJ/bOMYUg7xO12aU0e3vlW DTWMYmPnYr9Lr+oXeb7utkeCP7PWPodQTRFRvrlWVImPnbmHz3aLiNhR16SC9h8XwGy2 59UA== X-Gm-Message-State: AOAM5331kgOz+WGPyOn+RLPmMTPXLPfLod/C1jZSjweVWXKq1Wvufpsc XfyjTWnU+8PjdkBVibbQCeJAo7i3TRIDkQ== X-Received: by 2002:a17:90b:8d5:: with SMTP id ds21mr26119352pjb.65.1620438691840; Fri, 07 May 2021 18:51:31 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 43/72] softfloat: Split float_to_float Date: Fri, 7 May 2021 18:47:33 -0700 Message-Id: <20210508014802.892561-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split out parts_float_to_ahp and parts_float_to_float. Convert to pointers. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 174 ++++++++++++++++++++++++++++-------------------- 1 file changed, 101 insertions(+), 73 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8efa52f7ec..06fac8f41c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2036,83 +2036,105 @@ float128_div(float128 a, float128 b, float_status *status) * conversion is performed according to the IEC/IEEE Standard for * Binary Floating-Point Arithmetic. * - * The float_to_float helper only needs to take care of raising - * invalid exceptions and handling the conversion on NaNs. + * Usually this only needs to take care of raising invalid exceptions + * and handling the conversion on NaNs. */ -static FloatParts64 float_to_float(FloatParts64 a, const FloatFmt *dstf, - float_status *s) +static void parts_float_to_ahp(FloatParts64 *a, float_status *s) { - if (dstf->arm_althp) { - switch (a.cls) { - case float_class_qnan: - case float_class_snan: - /* There is no NaN in the destination format. Raise Invalid - * and return a zero with the sign of the input NaN. - */ - float_raise(float_flag_invalid, s); - a.cls = float_class_zero; - a.frac = 0; - a.exp = 0; - break; + switch (a->cls) { + case float_class_qnan: + case float_class_snan: + /* + * There is no NaN in the destination format. Raise Invalid + * and return a zero with the sign of the input NaN. + */ + float_raise(float_flag_invalid, s); + a->cls = float_class_zero; + break; - case float_class_inf: - /* There is no Inf in the destination format. Raise Invalid - * and return the maximum normal with the correct sign. - */ - float_raise(float_flag_invalid, s); - a.cls = float_class_normal; - a.exp = dstf->exp_max; - a.frac = ((1ull << dstf->frac_size) - 1) << dstf->frac_shift; - break; + case float_class_inf: + /* + * There is no Inf in the destination format. Raise Invalid + * and return the maximum normal with the correct sign. + */ + float_raise(float_flag_invalid, s); + a->cls = float_class_normal; + a->exp = float16_params_ahp.exp_max; + a->frac = MAKE_64BIT_MASK(float16_params_ahp.frac_shift, + float16_params_ahp.frac_size + 1); + break; - default: - break; - } - } else if (is_nan(a.cls)) { - parts_return_nan(&a, s); + case float_class_normal: + case float_class_zero: + break; + + default: + g_assert_not_reached(); } - return a; } +static void parts64_float_to_float(FloatParts64 *a, float_status *s) +{ + if (is_nan(a->cls)) { + parts_return_nan(a, s); + } +} + +static void parts128_float_to_float(FloatParts128 *a, float_status *s) +{ + if (is_nan(a->cls)) { + parts_return_nan(a, s); + } +} + +#define parts_float_to_float(P, S) \ + PARTS_GENERIC_64_128(float_to_float, P)(P, S) + float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; - float16a_unpack_canonical(&pa, a, s, fmt16); - pr = float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(&pr, s); + float16a_unpack_canonical(&p, a, s, fmt16); + parts_float_to_float(&p, s); + return float32_round_pack_canonical(&p, s); } float64 float16_to_float64(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; - float16a_unpack_canonical(&pa, a, s, fmt16); - pr = float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(&pr, s); + float16a_unpack_canonical(&p, a, s, fmt16); + parts_float_to_float(&p, s); + return float64_round_pack_canonical(&p, s); } float16 float32_to_float16(float32 a, bool ieee, float_status *s) { - const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; + const FloatFmt *fmt; - float32_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(&pr, s, fmt16); + float32_unpack_canonical(&p, a, s); + if (ieee) { + parts_float_to_float(&p, s); + fmt = &float16_params; + } else { + parts_float_to_ahp(&p, s); + fmt = &float16_params_ahp; + } + return float16a_round_pack_canonical(&p, s, fmt); } static float64 QEMU_SOFTFLOAT_ATTR soft_float32_to_float64(float32 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - float32_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(&pr, s); + float32_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float64_round_pack_canonical(&p, s); } float64 float32_to_float64(float32 a, float_status *s) @@ -2133,57 +2155,63 @@ float64 float32_to_float64(float32 a, float_status *s) float16 float64_to_float16(float64 a, bool ieee, float_status *s) { - const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; - FloatParts64 pa, pr; + FloatParts64 p; + const FloatFmt *fmt; - float64_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, fmt16, s); - return float16a_round_pack_canonical(&pr, s, fmt16); + float64_unpack_canonical(&p, a, s); + if (ieee) { + parts_float_to_float(&p, s); + fmt = &float16_params; + } else { + parts_float_to_ahp(&p, s); + fmt = &float16_params_ahp; + } + return float16a_round_pack_canonical(&p, s, fmt); } float32 float64_to_float32(float64 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - float64_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(&pr, s); + float64_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float32_round_pack_canonical(&p, s); } float32 bfloat16_to_float32(bfloat16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - bfloat16_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, &float32_params, s); - return float32_round_pack_canonical(&pr, s); + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float32_round_pack_canonical(&p, s); } float64 bfloat16_to_float64(bfloat16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - bfloat16_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, &float64_params, s); - return float64_round_pack_canonical(&pr, s); + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float64_round_pack_canonical(&p, s); } bfloat16 float32_to_bfloat16(float32 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - float32_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(&pr, s); + float32_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return bfloat16_round_pack_canonical(&p, s); } bfloat16 float64_to_bfloat16(float64 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - float64_unpack_canonical(&pa, a, s); - pr = float_to_float(pa, &bfloat16_params, s); - return bfloat16_round_pack_canonical(&pr, s); + float64_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return bfloat16_round_pack_canonical(&p, s); } /* From patchwork Sat May 8 01:47:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432570 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp862809jao; Fri, 7 May 2021 19:31:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz435S9qu91L2Mk9cMloh2vS4IDQGCisV0sTrBF8395P6b0fj6Oyb0nEsNJckVPCMQMexMu X-Received: by 2002:a92:d688:: with SMTP id p8mr11788252iln.268.1620441085562; Fri, 07 May 2021 19:31:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441085; cv=none; d=google.com; s=arc-20160816; b=oBai1MNXR31cckATSULtSgqolIZvplC526t2l/+JY/ZY9F1IBsSGkxD/Zk+AuLubqp maJ43Ir6xuT60suRlY4nMw9vPpY7akFKA//XxtmcyJby+3b0TObyMPZLTmn0FlYtgKLZ V6MamEyzMzBjw+Ji8Mh9OgMFwDaVEkbg0ZnoHU2e8nCDL5eKNhxYexkaJQiqZDBRbam3 GuMKkwSwtP8xJbdsdbueakPrv0kqtn+5JfIrpgfxi7higVqGTURs/eHlur/VEYaCwvOW PBZG5fWuiF65yRwZHpM+0STILYPtDeSiJ+zhReK96mZvLIV0HiOD7U5uF6qny3rKGLrb Ic+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NmfQRKXb4KL5cYYsxkAJAYTlB0HbS3cmX2hT3HN7i+I=; b=YEyOWxBgp5/j4Ht2jx4WaDtdStnnsXui8R3dKwOF127EdPdY3VRyGRp774f4mhp2nN 7OYV4PfLpor1MbNBB/GcNuPLXhq/r9TjLcukF03d5cws0PeIRDAaEG0wItL9e6/gCZn1 bthuCrBxtKoASfXlGGvJqvN6ov8kTRTfPWTJsozf+cEKizon7ctDpfjQDyCF5MV2MGAZ J50vB72/DkO39rqH/ATFYD2chu3Z9MRI4QvMWocSZDJnuTf8UOr41ocPcNlq59b2FSQS g8mN78xQECQGKdvBX9e90zoFl5dIWkwqZximsG2mBT2GC41DfekoGMoCi1KaR+3ig3E+ aVnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bf2u63eV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m5si8540411ili.151.2021.05.07.19.31.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:31:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bf2u63eV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCkW-0003QP-Vo for patch@linaro.org; Fri, 07 May 2021 22:31:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC80-0002kn-1P for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:36 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:33530) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC7x-0005Qd-Sd for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:35 -0400 Received: by mail-pg1-x530.google.com with SMTP id i5so3886826pgm.0 for ; Fri, 07 May 2021 18:51:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NmfQRKXb4KL5cYYsxkAJAYTlB0HbS3cmX2hT3HN7i+I=; b=bf2u63eVDvx6kgXw1fwgCnw3JkMlxALkwMBy6d6uIWrBH6aw+Nr3tqm2RyvZNomg5p Mrm495QltmimR2Hy+CPDXQBLKCtTR1CCmj/vxihUbxfEfxFiMAlpBfExSOOKTsoEUpGu NknGXBrWuSMwWPrJxHLAnBQrlw5eA285WmdKbHpQkC20PWY4ETOZx5yPBcYEfbMsLvPa 09sJ6pI6MQVih8FgPdmoA+C4mOeqCP8srDbKsLICarBh4e9QZcCYFzo8+/uwsYuygLYH zKnwXiDutqYghT0ulArXOAGA3iBVXVnlQ0zAi7cFfw6gw9pGKVphwhaS+y9eFYDXlvlE PHng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NmfQRKXb4KL5cYYsxkAJAYTlB0HbS3cmX2hT3HN7i+I=; b=TDilsDk2Wcs7U/O/ABMExC0Ycd+j215G6h0+ebnRGMuwkKGE8rHh8bcFjAA9tNpEbr Zq00bm0GYYwkBYI7nT1q1vkMr7qRtujKPKE2eRvV6fGhxCW+5I5G0YEYxxR8B/AH2FmF dI1kwTz5he9NGGLDarWVpu0F3w2zjUfCm0PeA8SNTOaJ0wT01iyprRnITVYWaRUXnmHM 8aQ0zcMFVT+F/WpC7jDLLV96A84v7Xcd7BZ+dziuGRPaXPJwGHBE9bkuOC6pEIxBLVFJ 0YGZ9KFpDwj6omyACb1hOZikt9EWlB2eIHhXWqk1S3BLfQnEZPBTSmmeYXdybq+2w+zD fu7Q== X-Gm-Message-State: AOAM533U83PIAf0DgQOYuxCxjEF+Hp8VY2bFmSwf1FR0LipAU/2Ov9ww zKVYthV0P702ehFsl5G76R/eb7xAWwilEw== X-Received: by 2002:a63:ff45:: with SMTP id s5mr13065095pgk.274.1620438692482; Fri, 07 May 2021 18:51:32 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 44/72] softfloat: Convert float-to-float conversions with float128 Date: Fri, 7 May 2021 18:47:34 -0700 Message-Id: <20210508014802.892561-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Introduce parts_float_to_float_widen and parts_float_to_float_narrow. Use them for float128_to_float{32,64} and float{32,64}_to_float128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 203 ++++++++++++++++-------------------------------- 1 file changed, 69 insertions(+), 134 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 06fac8f41c..1b86111279 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2091,6 +2091,35 @@ static void parts128_float_to_float(FloatParts128 *a, float_status *s) #define parts_float_to_float(P, S) \ PARTS_GENERIC_64_128(float_to_float, P)(P, S) +static void parts_float_to_float_narrow(FloatParts64 *a, FloatParts128 *b, + float_status *s) +{ + a->cls = b->cls; + a->sign = b->sign; + a->exp = b->exp; + + if (a->cls == float_class_normal) { + frac_truncjam(a, b); + } else if (is_nan(a->cls)) { + /* Discard the low bits of the NaN. */ + a->frac = b->frac_hi; + parts_return_nan(a, s); + } +} + +static void parts_float_to_float_widen(FloatParts128 *a, FloatParts64 *b, + float_status *s) +{ + a->cls = b->cls; + a->sign = b->sign; + a->exp = b->exp; + frac_widen(a, b); + + if (is_nan(a->cls)) { + parts_return_nan(a, s); + } +} + float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 = ieee ? &float16_params : &float16_params_ahp; @@ -2214,6 +2243,46 @@ bfloat16 float64_to_bfloat16(float64 a, float_status *s) return bfloat16_round_pack_canonical(&p, s); } +float32 float128_to_float32(float128 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float128_unpack_canonical(&p128, a, s); + parts_float_to_float_narrow(&p64, &p128, s); + return float32_round_pack_canonical(&p64, s); +} + +float64 float128_to_float64(float128 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float128_unpack_canonical(&p128, a, s); + parts_float_to_float_narrow(&p64, &p128, s); + return float64_round_pack_canonical(&p64, s); +} + +float128 float32_to_float128(float32 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float32_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return float128_round_pack_canonical(&p128, s); +} + +float128 float64_to_float128(float64 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float64_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return float128_round_pack_canonical(&p128, s); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. The operation is performed @@ -5174,38 +5243,6 @@ floatx80 float32_to_floatx80(float32 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the double-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float32_to_float128(float32 a, float_status *status) -{ - bool aSign; - int aExp; - uint32_t aSig; - - a = float32_squash_input_denormal(a, status); - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if (aSig) { - return commonNaNToFloat128(float32ToCommonNaN(a, status), status); - } - return packFloat128( aSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - return packFloat128( aSign, aExp + 0x3F80, ( (uint64_t) aSig )<<25, 0 ); - -} - /*---------------------------------------------------------------------------- | Returns the remainder of the single-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5479,40 +5516,6 @@ floatx80 float64_to_floatx80(float64 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the quadruple-precision floating-point format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float64_to_float128(float64 a, float_status *status) -{ - bool aSign; - int aExp; - uint64_t aSig, zSig0, zSig1; - - a = float64_squash_input_denormal(a, status); - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( aExp == 0x7FF ) { - if (aSig) { - return commonNaNToFloat128(float64ToCommonNaN(a, status), status); - } - return packFloat128( aSign, 0x7FFF, 0, 0 ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - --aExp; - } - shift128Right( aSig, 0, 4, &zSig0, &zSig1 ); - return packFloat128( aSign, aExp + 0x3C00, zSig0, zSig1 ); - -} - - /*---------------------------------------------------------------------------- | Returns the remainder of the double-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -6914,74 +6917,6 @@ uint32_t float128_to_uint32(float128 a, float_status *status) return res; } -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the single-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float128_to_float32(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - uint32_t zSig; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return commonNaNToFloat32(float128ToCommonNaN(a, status), status); - } - return packFloat32( aSign, 0xFF, 0 ); - } - aSig0 |= ( aSig1 != 0 ); - shift64RightJamming( aSig0, 18, &aSig0 ); - zSig = aSig0; - if ( aExp || zSig ) { - zSig |= 0x40000000; - aExp -= 0x3F81; - } - return roundAndPackFloat32(aSign, aExp, zSig, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the double-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float128_to_float64(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return commonNaNToFloat64(float128ToCommonNaN(a, status), status); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 ); - aSig0 |= ( aSig1 != 0 ); - if ( aExp || aSig0 ) { - aSig0 |= UINT64_C(0x4000000000000000); - aExp -= 0x3C01; - } - return roundAndPackFloat64(aSign, aExp, aSig0, status); - -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point | value `a' to the extended double-precision floating-point format. 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[209.51.188.17]) by mx.google.com with ESMTPS id g5si8711715ild.106.2021.05.07.19.32.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:32:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zXI42KrX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCm1-0000jB-LD for patch@linaro.org; Fri, 07 May 2021 22:32:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC81-0002rQ-PE for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:37 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:41903) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC7y-0005R4-Kt for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:37 -0400 Received: by mail-pl1-x634.google.com with SMTP id z18so2558961plg.8 for ; Fri, 07 May 2021 18:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lD4M3xdqIE8r914VjTd/jttQJ/e/mxQ3BCpgAvIfUlU=; b=zXI42KrXmJ8wWhg4UQfr5JLQwGxQRljTYOqIcseHFB6flqYrTX6QR7xJTTa8K/lqL+ BlZlA/VcbzdmZk3eRcVSVoYAAyUgaSUVWW5jTRSz2NZKgk078m3E2BQd4+rd6Iq5jnhv TviTToJ8Wtra1A/vSXAIbI8XdGoRufTsvhvUAW0dHvmAS3qsEfCqSDFqkLqUzRmKe703 VNgHPlh6o2U7XUZ7nSTg4qAcV3aS16/b5QSw+BQsxTxvXXMm8QB2z91Cyktq1g+2rk4n SHecCQmNLQ0AwUc+RuKbHXS80UUIHZ6YlexNWTmhDwHtVVP+XvTR0ur+e9sjiTWw9pQ3 bMkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lD4M3xdqIE8r914VjTd/jttQJ/e/mxQ3BCpgAvIfUlU=; b=nWfvdbt9ypVi81Gw4ThxuSONze4gflznSSxhQdTKufJKLht9AiZ4rkGFXWDqbH3FQ+ CRvXsB2WnqCMbNzfGrmE4OFO4sovjAg6rpXE+iADQMMBjOOzHqbhR/prNWwqUp8IAksy LB+wHjDuvlTPZowWyDiWar8pmPcJWkBs0qs73emAIGnKyNYyqdIqpAz8BSRsj2n7hLvv BKbul2Jq93MkTH9UZfpFwxLy32bYMbsDq20pOJ7afDayXtH5eYgV0zX7lFgXL+4FmAF1 Pfxb0GorRiD8PLwezjdJ9gZZaECOpjKlAnUzhBPHi26x1OZDBJTvR7caoHCm2vhMq3Nu xYHg== X-Gm-Message-State: AOAM530vu7hLk8F4xfmy0t7t2kPSKQ105Wx/sPiFdc84rlALM+BTx6bL NJF+BVsM5QRXfufyzL8wC311LOUzJ1Od/A== X-Received: by 2002:a17:90b:2390:: with SMTP id mr16mr13836588pjb.133.1620438693131; Fri, 07 May 2021 18:51:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 45/72] softfloat: Move round_to_int to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:35 -0700 Message-Id: <20210508014802.892561-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, convert to pointers, split out parts$N_round_to_int_normal, define a macro for parts_round_to_int using QEMU_GENERIC. This necessarily meant some rearrangement to the rount_to_{,u}int_and_pack routines, so go ahead and convert to parts_round_to_int_normal, which in turn allows cleaning up of the raised exception handling. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 434 ++++++++++---------------------------- fpu/softfloat-parts.c.inc | 157 ++++++++++++++ 2 files changed, 263 insertions(+), 328 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 1b86111279..ce96ea753c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -810,6 +810,24 @@ static FloatParts128 *parts128_div(FloatParts128 *a, FloatParts128 *b, #define parts_div(A, B, S) \ PARTS_GENERIC_64_128(div, A)(A, B, S) +static bool parts64_round_to_int_normal(FloatParts64 *a, FloatRoundMode rm, + int scale, int frac_size); +static bool parts128_round_to_int_normal(FloatParts128 *a, FloatRoundMode r, + int scale, int frac_size); + +#define parts_round_to_int_normal(A, R, C, F) \ + PARTS_GENERIC_64_128(round_to_int_normal, A)(A, R, C, F) + +static void parts64_round_to_int(FloatParts64 *a, FloatRoundMode rm, + int scale, float_status *s, + const FloatFmt *fmt); +static void parts128_round_to_int(FloatParts128 *a, FloatRoundMode r, + int scale, float_status *s, + const FloatFmt *fmt); + +#define parts_round_to_int(A, R, C, S, F) \ + PARTS_GENERIC_64_128(round_to_int, A)(A, R, C, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2284,153 +2302,52 @@ float128 float64_to_float128(float64 a, float_status *s) } /* - * Rounds the floating-point value `a' to an integer, and returns the - * result as a floating-point value. The operation is performed - * according to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic. + * Round to integral value */ -static FloatParts64 round_to_int(FloatParts64 a, FloatRoundMode rmode, - int scale, float_status *s) -{ - switch (a.cls) { - case float_class_qnan: - case float_class_snan: - parts_return_nan(&a, s); - break; - - case float_class_zero: - case float_class_inf: - /* already "integral" */ - break; - - case float_class_normal: - scale = MIN(MAX(scale, -0x10000), 0x10000); - a.exp += scale; - - if (a.exp >= DECOMPOSED_BINARY_POINT) { - /* already integral */ - break; - } - if (a.exp < 0) { - bool one; - /* all fractional */ - float_raise(float_flag_inexact, s); - switch (rmode) { - case float_round_nearest_even: - one = a.exp == -1 && a.frac > DECOMPOSED_IMPLICIT_BIT; - break; - case float_round_ties_away: - one = a.exp == -1 && a.frac >= DECOMPOSED_IMPLICIT_BIT; - break; - case float_round_to_zero: - one = false; - break; - case float_round_up: - one = !a.sign; - break; - case float_round_down: - one = a.sign; - break; - case float_round_to_odd: - one = true; - break; - default: - g_assert_not_reached(); - } - - if (one) { - a.frac = DECOMPOSED_IMPLICIT_BIT; - a.exp = 0; - } else { - a.cls = float_class_zero; - } - } else { - uint64_t frac_lsb = DECOMPOSED_IMPLICIT_BIT >> a.exp; - uint64_t frac_lsbm1 = frac_lsb >> 1; - uint64_t rnd_even_mask = (frac_lsb - 1) | frac_lsb; - uint64_t rnd_mask = rnd_even_mask >> 1; - uint64_t inc; - - switch (rmode) { - case float_round_nearest_even: - inc = ((a.frac & rnd_even_mask) != frac_lsbm1 ? frac_lsbm1 : 0); - break; - case float_round_ties_away: - inc = frac_lsbm1; - break; - case float_round_to_zero: - inc = 0; - break; - case float_round_up: - inc = a.sign ? 0 : rnd_mask; - break; - case float_round_down: - inc = a.sign ? rnd_mask : 0; - break; - case float_round_to_odd: - inc = a.frac & frac_lsb ? 0 : rnd_mask; - break; - default: - g_assert_not_reached(); - } - - if (a.frac & rnd_mask) { - float_raise(float_flag_inexact, s); - if (uadd64_overflow(a.frac, inc, &a.frac)) { - a.frac >>= 1; - a.frac |= DECOMPOSED_IMPLICIT_BIT; - a.exp++; - } - a.frac &= ~rnd_mask; - } - } - break; - default: - g_assert_not_reached(); - } - return a; -} - float16 float16_round_to_int(float16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - float16_unpack_canonical(&pa, a, s); - pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return float16_round_pack_canonical(&pr, s); + float16_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float16_params); + return float16_round_pack_canonical(&p, s); } float32 float32_round_to_int(float32 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - float32_unpack_canonical(&pa, a, s); - pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return float32_round_pack_canonical(&pr, s); + float32_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float32_params); + return float32_round_pack_canonical(&p, s); } float64 float64_round_to_int(float64 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - float64_unpack_canonical(&pa, a, s); - pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return float64_round_pack_canonical(&pr, s); + float64_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float64_params); + return float64_round_pack_canonical(&p, s); } -/* - * Rounds the bfloat16 value `a' to an integer, and returns the - * result as a bfloat16 value. - */ - bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) { - FloatParts64 pa, pr; + FloatParts64 p; - bfloat16_unpack_canonical(&pa, a, s); - pr = round_to_int(pa, s->float_rounding_mode, 0, s); - return bfloat16_round_pack_canonical(&pr, s); + bfloat16_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &bfloat16_params); + return bfloat16_round_pack_canonical(&p, s); +} + +float128 float128_round_to_int(float128 a, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + parts_round_to_int(&p, s->float_rounding_mode, 0, s, &float128_params); + return float128_round_pack_canonical(&p, s); } /* @@ -2444,48 +2361,58 @@ bfloat16 bfloat16_round_to_int(bfloat16 a, float_status *s) * is returned. */ -static int64_t round_to_int_and_pack(FloatParts64 in, FloatRoundMode rmode, +static int64_t round_to_int_and_pack(FloatParts64 p, FloatRoundMode rmode, int scale, int64_t min, int64_t max, float_status *s) { + int flags = 0; uint64_t r; - int orig_flags = get_float_exception_flags(s); - FloatParts64 p = round_to_int(in, rmode, scale, s); switch (p.cls) { case float_class_snan: case float_class_qnan: - s->float_exception_flags = orig_flags | float_flag_invalid; - return max; + flags = float_flag_invalid; + r = max; + break; + case float_class_inf: - s->float_exception_flags = orig_flags | float_flag_invalid; - return p.sign ? min : max; + flags = float_flag_invalid; + r = p.sign ? min : max; + break; + case float_class_zero: return 0; + case float_class_normal: + /* TODO: 62 = N - 2, frac_size for rounding */ + if (parts_round_to_int_normal(&p, rmode, scale, 62)) { + flags = float_flag_inexact; + } + if (p.exp <= DECOMPOSED_BINARY_POINT) { r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); } else { r = UINT64_MAX; } if (p.sign) { - if (r <= -(uint64_t) min) { - return -r; + if (r <= -(uint64_t)min) { + r = -r; } else { - s->float_exception_flags = orig_flags | float_flag_invalid; - return min; - } - } else { - if (r <= max) { - return r; - } else { - s->float_exception_flags = orig_flags | float_flag_invalid; - return max; + flags = float_flag_invalid; + r = min; } + } else if (r > max) { + flags = float_flag_invalid; + r = max; } + break; + default: g_assert_not_reached(); } + + float_raise(flags, s); + return r; } int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2748,49 +2675,59 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a, float_status *s) * flag. */ -static uint64_t round_to_uint_and_pack(FloatParts64 in, FloatRoundMode rmode, +static uint64_t round_to_uint_and_pack(FloatParts64 p, FloatRoundMode rmode, int scale, uint64_t max, float_status *s) { - int orig_flags = get_float_exception_flags(s); - FloatParts64 p = round_to_int(in, rmode, scale, s); + int flags = 0; uint64_t r; switch (p.cls) { case float_class_snan: case float_class_qnan: - s->float_exception_flags = orig_flags | float_flag_invalid; - return max; + flags = float_flag_invalid; + r = max; + break; + case float_class_inf: - s->float_exception_flags = orig_flags | float_flag_invalid; - return p.sign ? 0 : max; + flags = float_flag_invalid; + r = p.sign ? 0 : max; + break; + case float_class_zero: return 0; + case float_class_normal: + /* TODO: 62 = N - 2, frac_size for rounding */ + if (parts_round_to_int_normal(&p, rmode, scale, 62)) { + flags = float_flag_inexact; + if (p.cls == float_class_zero) { + r = 0; + break; + } + } + if (p.sign) { - s->float_exception_flags = orig_flags | float_flag_invalid; - return 0; - } - - if (p.exp <= DECOMPOSED_BINARY_POINT) { - r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); + flags = float_flag_invalid; + r = 0; + } else if (p.exp > DECOMPOSED_BINARY_POINT) { + flags = float_flag_invalid; + r = max; } else { - s->float_exception_flags = orig_flags | float_flag_invalid; - return max; + r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); + if (r > max) { + flags = float_flag_invalid; + r = max; + } } + break; - /* For uint64 this will never trip, but if p.exp is too large - * to shift a decomposed fraction we shall have exited via the - * 3rd leg above. - */ - if (r > max) { - s->float_exception_flags = orig_flags | float_flag_invalid; - return max; - } - return r; default: g_assert_not_reached(); } + + float_raise(flags, s); + return r; } uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -6955,165 +6892,6 @@ floatx80 float128_to_floatx80(float128 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Rounds the quadruple-precision floating-point value `a' to an integer, and -| returns the result as a quadruple-precision floating-point value. The -| operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_round_to_int(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t lastBitMask, roundBitsMask; - float128 z; - - aExp = extractFloat128Exp( a ); - if ( 0x402F <= aExp ) { - if ( 0x406F <= aExp ) { - if ( ( aExp == 0x7FFF ) - && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) - ) { - return propagateFloat128NaN(a, a, status); - } - return a; - } - lastBitMask = 1; - lastBitMask = ( lastBitMask<<( 0x406E - aExp ) )<<1; - roundBitsMask = lastBitMask - 1; - z = a; - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( lastBitMask ) { - add128( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low ); - if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask; - } - else { - if ( (int64_t) z.low < 0 ) { - ++z.high; - if ( (uint64_t) ( z.low<<1 ) == 0 ) z.high &= ~1; - } - } - break; - case float_round_ties_away: - if (lastBitMask) { - add128(z.high, z.low, 0, lastBitMask >> 1, &z.high, &z.low); - } else { - if ((int64_t) z.low < 0) { - ++z.high; - } - } - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat128Sign(z)) { - add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low); - } - break; - case float_round_down: - if (extractFloat128Sign(z)) { - add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low); - } - break; - case float_round_to_odd: - /* - * Note that if lastBitMask == 0, the last bit is the lsb - * of high, and roundBitsMask == -1. - */ - if ((lastBitMask ? z.low & lastBitMask : z.high & 1) == 0) { - add128(z.high, z.low, 0, roundBitsMask, &z.high, &z.low); - } - break; - default: - abort(); - } - z.low &= ~ roundBitsMask; - } - else { - if ( aExp < 0x3FFF ) { - if ( ( ( (uint64_t) ( a.high<<1 ) ) | a.low ) == 0 ) return a; - float_raise(float_flag_inexact, status); - aSign = extractFloat128Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp == 0x3FFE ) - && ( extractFloat128Frac0( a ) - | extractFloat128Frac1( a ) ) - ) { - return packFloat128( aSign, 0x3FFF, 0, 0 ); - } - break; - case float_round_ties_away: - if (aExp == 0x3FFE) { - return packFloat128(aSign, 0x3FFF, 0, 0); - } - break; - case float_round_down: - return - aSign ? packFloat128( 1, 0x3FFF, 0, 0 ) - : packFloat128( 0, 0, 0, 0 ); - case float_round_up: - return - aSign ? packFloat128( 1, 0, 0, 0 ) - : packFloat128( 0, 0x3FFF, 0, 0 ); - - case float_round_to_odd: - return packFloat128(aSign, 0x3FFF, 0, 0); - - case float_round_to_zero: - break; - } - return packFloat128( aSign, 0, 0, 0 ); - } - lastBitMask = 1; - lastBitMask <<= 0x402F - aExp; - roundBitsMask = lastBitMask - 1; - z.low = 0; - z.high = a.high; - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z.high += lastBitMask>>1; - if ( ( ( z.high & roundBitsMask ) | a.low ) == 0 ) { - z.high &= ~ lastBitMask; - } - break; - case float_round_ties_away: - z.high += lastBitMask>>1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloat128Sign(z)) { - z.high |= ( a.low != 0 ); - z.high += roundBitsMask; - } - break; - case float_round_down: - if (extractFloat128Sign(z)) { - z.high |= (a.low != 0); - z.high += roundBitsMask; - } - break; - case float_round_to_odd: - if ((z.high & lastBitMask) == 0) { - z.high |= (a.low != 0); - z.high += roundBitsMask; - } - break; - default: - abort(); - } - z.high &= ~ roundBitsMask; - } - if ( ( z.low != a.low ) || ( z.high != a.high ) ) { - float_raise(float_flag_inexact, status); - } - return z; - -} - /*---------------------------------------------------------------------------- | Returns the remainder of the quadruple-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index f8165d92f9..b2c4624d8c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -594,3 +594,160 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, a->cls = float_class_inf; return a; } + +/* + * Rounds the floating-point value `a' to an integer, and returns the + * result as a floating-point value. The operation is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic. + * + * parts_round_to_int_normal is an internal helper function for + * normal numbers only, returning true for inexact but not directly + * raising float_flag_inexact. + */ +static bool partsN(round_to_int_normal)(FloatPartsN *a, FloatRoundMode rmode, + int scale, int frac_size) +{ + uint64_t frac_lsb, frac_lsbm1, rnd_even_mask, rnd_mask, inc; + int shift_adj; + + scale = MIN(MAX(scale, -0x10000), 0x10000); + a->exp += scale; + + if (a->exp < 0) { + bool one; + + /* All fractional */ + switch (rmode) { + case float_round_nearest_even: + one = false; + if (a->exp == -1) { + FloatPartsN tmp; + /* Shift left one, discarding DECOMPOSED_IMPLICIT_BIT */ + frac_add(&tmp, a, a); + /* Anything remaining means frac > 0.5. */ + one = !frac_eqz(&tmp); + } + break; + case float_round_ties_away: + one = a->exp == -1; + break; + case float_round_to_zero: + one = false; + break; + case float_round_up: + one = !a->sign; + break; + case float_round_down: + one = a->sign; + break; + case float_round_to_odd: + one = true; + break; + default: + g_assert_not_reached(); + } + + frac_clear(a); + a->exp = 0; + if (one) { + a->frac_hi = DECOMPOSED_IMPLICIT_BIT; + } else { + a->cls = float_class_zero; + } + return true; + } + + if (a->exp >= frac_size) { + /* All integral */ + return false; + } + + if (N > 64 && a->exp < N - 64) { + /* + * Rounding is not in the low word -- shift lsb to bit 2, + * which leaves room for sticky and rounding bit. + */ + shift_adj = (N - 1) - (a->exp + 2); + frac_shrjam(a, shift_adj); + frac_lsb = 1 << 2; + } else { + shift_adj = 0; + frac_lsb = DECOMPOSED_IMPLICIT_BIT >> (a->exp & 63); + } + + frac_lsbm1 = frac_lsb >> 1; + rnd_mask = frac_lsb - 1; + rnd_even_mask = rnd_mask | frac_lsb; + + if (!(a->frac_lo & rnd_mask)) { + /* Fractional bits already clear, undo the shift above. */ + frac_shl(a, shift_adj); + return false; + } + + switch (rmode) { + case float_round_nearest_even: + inc = ((a->frac_lo & rnd_even_mask) != frac_lsbm1 ? frac_lsbm1 : 0); + break; + case float_round_ties_away: + inc = frac_lsbm1; + break; + case float_round_to_zero: + inc = 0; + break; + case float_round_up: + inc = a->sign ? 0 : rnd_mask; + break; + case float_round_down: + inc = a->sign ? rnd_mask : 0; + break; + case float_round_to_odd: + inc = a->frac_lo & frac_lsb ? 0 : rnd_mask; + break; + default: + g_assert_not_reached(); + } + + if (shift_adj == 0) { + if (frac_addi(a, a, inc)) { + frac_shr(a, 1); + a->frac_hi |= DECOMPOSED_IMPLICIT_BIT; + a->exp++; + } + a->frac_lo &= ~rnd_mask; + } else { + frac_addi(a, a, inc); + a->frac_lo &= ~rnd_mask; + /* Be careful shifting back, not to overflow */ + frac_shl(a, shift_adj - 1); + if (a->frac_hi & DECOMPOSED_IMPLICIT_BIT) { + a->exp++; + } else { + frac_add(a, a, a); + } + } + return true; +} + +static void partsN(round_to_int)(FloatPartsN *a, FloatRoundMode rmode, + int scale, float_status *s, + const FloatFmt *fmt) +{ + switch (a->cls) { + case float_class_qnan: + case float_class_snan: + parts_return_nan(a, s); + break; + case float_class_zero: + case float_class_inf: + break; + case float_class_normal: + if (parts_round_to_int_normal(a, rmode, scale, fmt->frac_size)) { + float_raise(float_flag_inexact, s); + } + break; + default: + g_assert_not_reached(); + } +} From patchwork Sat May 8 01:47:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432554 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp856226jao; Fri, 7 May 2021 19:17:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwyHqo3dk9evZSapAlZFc9ydcPvhO9FVXPpvX4oWxwBUzUJakwuilIKE7x4qjyzlIlQ2ASD X-Received: by 2002:a05:6e02:1a0c:: with SMTP id s12mr11940025ild.201.1620440279819; Fri, 07 May 2021 19:17:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440279; cv=none; d=google.com; s=arc-20160816; b=v73/Sp9Dkw5IQ23WYNzdyNlcmull4myZjaLcRKfzlZswBKCy+UWK3Ne8gWvrAYVgph Ixz6rjFxlI1t3fo/nBQd8e7Frj5uiV9XXovjF4sZJHxd9bpQFR7kFo6EZNz12ZJkNpWT /kriRxFkS/VNEj49u+dQiYCmJYRIAYxuOfWNd9g6LjpnPeGmK959VuMLonrUmY5jL/6j 2noOZtIcKZ7lzGRVMPiEfiq3tLAdm22QU0ruPtN5YYyYQfyTgydIIhK0WFY4+hgBISOL zA7T05Yh+FKsrYo4HAW/G5xuuFLqUwWTM7nt1rslCZi3HS+jCK9ZM26cO4d53OEy4hI3 LRdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Y6uAY0cHBxc9uLh6DxdxhC2/o85QcUgV9LbZfbE0CZw=; b=xMijGww4KByxsmjlYw2SHjoXiavKFx/U21zO0WUPHIA1RHJ16ijri4pKqDsRz3ZCNh B3tT+sEUIlb4F9R1Bhh7Kmw4MD/M7IdV40ZyafFkdHwUVjLpCwzLPHqOeER+EV8lUjki y8M5q1rB4hWnXE7vGu3iCMar4Hrnb4HfRw2iIJMq/VOwNjCqL4bfufzC01ETgCAEpwpb fY7B7HzO41FrEv/0ANgUxVbDjseF3tSxguelIzzPVTK/haiWCjA79iAKEBzrlLqXmS4E wkhZqO/FUnza0+Vucgpu0vOSVZjiqIiwAJ03KVEpwCK2cTtw6C4nMH9V6EKOiJD0ogz4 KEcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A7QrxQ7l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t2si2586777iof.85.2021.05.07.19.17.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:17:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A7QrxQ7l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCXX-0007kD-6q for patch@linaro.org; Fri, 07 May 2021 22:17:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC82-0002sl-4l for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:38 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:40944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC7z-0005RW-5Y for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:37 -0400 Received: by mail-pj1-x102a.google.com with SMTP id l10-20020a17090a850ab0290155b06f6267so6439959pjn.5 for ; Fri, 07 May 2021 18:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y6uAY0cHBxc9uLh6DxdxhC2/o85QcUgV9LbZfbE0CZw=; b=A7QrxQ7lYRcihn4Q21ndz0ZB2LptbRGh2ReFTsOWCA1OUSfvAXTIsUlOa/kgcU5QCn oCtnwcsbd9xzhAEiSYX48ZqYyYSrT7G4OUpPZNQzo8CjgNWMbXEsiYUK1YxMDL6jFgtC dfMNEcVwFlcsT1myo9a0BR0vXXlHmPxexWglaiMWCIZru0G4LXOGnMdo+qI5t4Bevtsb 5RpYin0M70Tn9rYmJ0tN2wXJSswZJcEpwcye5UUbkRpVL+1uvYmZSGWywuE1wSL9+qfo FGpYi7wvYTeVuvxIphNItxoMEY2HPVI4fSr0sl403Nn+hhai4bjBkQY2976i7Vc9BHj0 oMVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y6uAY0cHBxc9uLh6DxdxhC2/o85QcUgV9LbZfbE0CZw=; b=ehfzROZHeQiqr/JFlfrbTwlHyH1MC6CVHqq0d3E9/O2aX7HSMR6NBowaQLKmPEMLbv R56eylFroxd2fqAMISMnj02QPwlx0p0t42KfsqCYU35wpH0a58tNLFOSOQskLt9pJpxK pNCiQsyK0+t0nZsZwcYIn6Zq+e3VbRj/W26HZ3AHvzbM5HzUIK4H6Rb9COhvTh6ffuvj N8KfN6XB4KBDC1sIHs+nEKh1DO85BYJF6rJps3ygLVtsPs3axkhjOOLFpkEkrBeJ9unS kt2/OKBBWZqmtTDI9wHzbxUJB0nCxoZqV0PpDFA6Di+uaH4uqedJ3ZhHoR0dvdAXfmNa 69ng== X-Gm-Message-State: AOAM5336yPpFw84O9Njr05m6sJW1+a40ZQt/Bh9yYGbXJxsLqQ2j6ycE sP8J2bktAnOgcr9uMtANqjyI1MouEozNmg== X-Received: by 2002:a17:90a:7896:: with SMTP id x22mr13452585pjk.182.1620438693942; Fri, 07 May 2021 18:51:33 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 46/72] softfloat: Move rount_to_int_and_pack to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:36 -0700 Message-Id: <20210508014802.892561-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_float_to_sint. Reimplement float128_to_int{32,64}{_round_to_zero} with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 365 +++++++++----------------------------- fpu/softfloat-parts.c.inc | 64 +++++++ 2 files changed, 145 insertions(+), 284 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ce96ea753c..ac8e726935 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -828,6 +828,16 @@ static void parts128_round_to_int(FloatParts128 *a, FloatRoundMode r, #define parts_round_to_int(A, R, C, S, F) \ PARTS_GENERIC_64_128(round_to_int, A)(A, R, C, S, F) +static int64_t parts64_float_to_sint(FloatParts64 *p, FloatRoundMode rmode, + int scale, int64_t min, int64_t max, + float_status *s); +static int64_t parts128_float_to_sint(FloatParts128 *p, FloatRoundMode rmode, + int scale, int64_t min, int64_t max, + float_status *s); + +#define parts_float_to_sint(P, R, Z, MN, MX, S) \ + PARTS_GENERIC_64_128(float_to_sint, P)(P, R, Z, MN, MX, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2351,69 +2361,8 @@ float128 float128_round_to_int(float128 a, float_status *s) } /* - * Returns the result of converting the floating-point value `a' to - * the two's complement integer format. The conversion is performed - * according to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic---which means in particular that the conversion is - * rounded according to the current rounding mode. If `a' is a NaN, - * the largest positive integer is returned. Otherwise, if the - * conversion overflows, the largest integer with the same sign as `a' - * is returned. -*/ - -static int64_t round_to_int_and_pack(FloatParts64 p, FloatRoundMode rmode, - int scale, int64_t min, int64_t max, - float_status *s) -{ - int flags = 0; - uint64_t r; - - switch (p.cls) { - case float_class_snan: - case float_class_qnan: - flags = float_flag_invalid; - r = max; - break; - - case float_class_inf: - flags = float_flag_invalid; - r = p.sign ? min : max; - break; - - case float_class_zero: - return 0; - - case float_class_normal: - /* TODO: 62 = N - 2, frac_size for rounding */ - if (parts_round_to_int_normal(&p, rmode, scale, 62)) { - flags = float_flag_inexact; - } - - if (p.exp <= DECOMPOSED_BINARY_POINT) { - r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - } else { - r = UINT64_MAX; - } - if (p.sign) { - if (r <= -(uint64_t)min) { - r = -r; - } else { - flags = float_flag_invalid; - r = min; - } - } else if (r > max) { - flags = float_flag_invalid; - r = max; - } - break; - - default: - g_assert_not_reached(); - } - - float_raise(flags, s); - return r; -} + * Floating-point to signed integer conversions + */ int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) @@ -2421,7 +2370,7 @@ int8_t float16_to_int8_scalbn(float16 a, FloatRoundMode rmode, int scale, FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT8_MIN, INT8_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT8_MIN, INT8_MAX, s); } int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2430,7 +2379,7 @@ int16_t float16_to_int16_scalbn(float16 a, FloatRoundMode rmode, int scale, FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); } int32_t float16_to_int32_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2439,7 +2388,7 @@ int32_t float16_to_int32_scalbn(float16 a, FloatRoundMode rmode, int scale, FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); } int64_t float16_to_int64_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2448,7 +2397,7 @@ int64_t float16_to_int64_scalbn(float16 a, FloatRoundMode rmode, int scale, FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } int16_t float32_to_int16_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2457,7 +2406,7 @@ int16_t float32_to_int16_scalbn(float32 a, FloatRoundMode rmode, int scale, FloatParts64 p; float32_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); } int32_t float32_to_int32_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2466,7 +2415,7 @@ int32_t float32_to_int32_scalbn(float32 a, FloatRoundMode rmode, int scale, FloatParts64 p; float32_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); } int64_t float32_to_int64_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2475,7 +2424,7 @@ int64_t float32_to_int64_scalbn(float32 a, FloatRoundMode rmode, int scale, FloatParts64 p; float32_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } int16_t float64_to_int16_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2484,7 +2433,7 @@ int16_t float64_to_int16_scalbn(float64 a, FloatRoundMode rmode, int scale, FloatParts64 p; float64_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); } int32_t float64_to_int32_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2493,7 +2442,7 @@ int32_t float64_to_int32_scalbn(float64 a, FloatRoundMode rmode, int scale, FloatParts64 p; float64_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); } int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2502,7 +2451,52 @@ int64_t float64_to_int64_scalbn(float64 a, FloatRoundMode rmode, int scale, FloatParts64 p; float64_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); +} + +int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT16_MIN, INT16_MAX, s); +} + +int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); +} + +int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, + float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); +} + +static int32_t float128_to_int32_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); +} + +static int64_t float128_to_int64_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } int8_t float16_to_int8(float16 a, float_status *s) @@ -2555,6 +2549,16 @@ int64_t float64_to_int64(float64 a, float_status *s) return float64_to_int64_scalbn(a, s->float_rounding_mode, 0, s); } +int32_t float128_to_int32(float128 a, float_status *s) +{ + return float128_to_int32_scalbn(a, s->float_rounding_mode, 0, s); +} + +int64_t float128_to_int64(float128 a, float_status *s) +{ + return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s); +} + int16_t float16_to_int16_round_to_zero(float16 a, float_status *s) { return float16_to_int16_scalbn(a, float_round_to_zero, 0, s); @@ -2600,36 +2604,14 @@ int64_t float64_to_int64_round_to_zero(float64 a, float_status *s) return float64_to_int64_scalbn(a, float_round_to_zero, 0, s); } -/* - * Returns the result of converting the floating-point value `a' to - * the two's complement integer format. - */ - -int16_t bfloat16_to_int16_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, - float_status *s) +int32_t float128_to_int32_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT16_MIN, INT16_MAX, s); + return float128_to_int32_scalbn(a, float_round_to_zero, 0, s); } -int32_t bfloat16_to_int32_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, - float_status *s) +int64_t float128_to_int64_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT32_MIN, INT32_MAX, s); -} - -int64_t bfloat16_to_int64_scalbn(bfloat16 a, FloatRoundMode rmode, int scale, - float_status *s) -{ - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_int_and_pack(p, rmode, scale, INT64_MIN, INT64_MAX, s); + return float128_to_int64_scalbn(a, float_round_to_zero, 0, s); } int16_t bfloat16_to_int16(bfloat16 a, float_status *s) @@ -6553,191 +6535,6 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *status) 0, zExp, zSig0, zSig1, status); } -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit two's complement integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. Otherwise, if the conversion overflows, the -| largest integer with the same sign as `a' is returned. -*----------------------------------------------------------------------------*/ - -int32_t float128_to_int32(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig0, aSig1; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 0; - if ( aExp ) aSig0 |= UINT64_C(0x0001000000000000); - aSig0 |= ( aSig1 != 0 ); - shiftCount = 0x4028 - aExp; - if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 ); - return roundAndPackInt32(aSign, aSig0, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit two's complement integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic, except that the conversion is always rounded toward zero. If -| `a' is a NaN, the largest positive integer is returned. Otherwise, if the -| conversion overflows, the largest integer with the same sign as `a' is -| returned. -*----------------------------------------------------------------------------*/ - -int32_t float128_to_int32_round_to_zero(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig0, aSig1, savedASig; - int32_t z; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - aSig0 |= ( aSig1 != 0 ); - if ( 0x401E < aExp ) { - if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 0; - goto invalid; - } - else if ( aExp < 0x3FFF ) { - if (aExp || aSig0) { - float_raise(float_flag_inexact, status); - } - return 0; - } - aSig0 |= UINT64_C(0x0001000000000000); - shiftCount = 0x402F - aExp; - savedASig = aSig0; - aSig0 >>= shiftCount; - z = aSig0; - if ( aSign ) z = - z; - if ( ( z < 0 ) ^ aSign ) { - invalid: - float_raise(float_flag_invalid, status); - return aSign ? INT32_MIN : INT32_MAX; - } - if ( ( aSig0<>( ( - shiftCount ) & 63 ) ); - if ( (uint64_t) ( aSig1<>( - shiftCount ); - if ( aSig1 - || ( shiftCount && (uint64_t) ( aSig0<<( shiftCount & 63 ) ) ) ) { - float_raise(float_flag_inexact, status); - } - } - if ( aSign ) z = - z; - return z; - -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point value | `a' to the 64-bit unsigned integer format. The conversion is diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index b2c4624d8c..a897a5a743 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -751,3 +751,67 @@ static void partsN(round_to_int)(FloatPartsN *a, FloatRoundMode rmode, g_assert_not_reached(); } } + +/* + * Returns the result of converting the floating-point value `a' to + * the two's complement integer format. The conversion is performed + * according to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic---which means in particular that the conversion is + * rounded according to the current rounding mode. If `a' is a NaN, + * the largest positive integer is returned. Otherwise, if the + * conversion overflows, the largest integer with the same sign as `a' + * is returned. +*/ +static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, + int scale, int64_t min, int64_t max, + float_status *s) +{ + int flags = 0; + uint64_t r; + + switch (p->cls) { + case float_class_snan: + case float_class_qnan: + flags = float_flag_invalid; + r = max; + break; + + case float_class_inf: + flags = float_flag_invalid; + r = p->sign ? min : max; + break; + + case float_class_zero: + return 0; + + case float_class_normal: + /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ + if (parts_round_to_int_normal(p, rmode, scale, N - 2)) { + flags = float_flag_inexact; + } + + if (p->exp <= DECOMPOSED_BINARY_POINT) { + r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); + } else { + r = UINT64_MAX; + } + if (p->sign) { + if (r <= -(uint64_t)min) { + r = -r; + } else { + flags = float_flag_invalid; + r = min; + } + } else if (r > max) { + flags = float_flag_invalid; + r = max; + } + break; + + default: + g_assert_not_reached(); + } + + float_raise(flags, s); + return r; +} From patchwork Sat May 8 01:47:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432560 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp859369jao; Fri, 7 May 2021 19:24:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyctaix77Kt59dukc9U93DFWij/S0KBnoMogR2oiTQIooc6fDmuvTfUOGtoPUf/xEKQMGvT X-Received: by 2002:a05:6638:2410:: with SMTP id z16mr11757714jat.130.1620440664551; Fri, 07 May 2021 19:24:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440664; cv=none; d=google.com; s=arc-20160816; b=POVqm8YoXxcoPDaIoFTCtvHq7+/7Wjcddpg+VSEVfqY4i9jo39tZ6U7JRztt+T5xjd oxxD57kKORnfWktvyGffN+urh/i7loyv4vNyE9UF7lokPJBJ5hDUtxS65NXvcIhi0O9C yeiTOyaDOuuHZUdas37CfeJnXCJmkM55f4qAOrg9sqV9RX54ruCafZ8sUWgP6rzL+htZ CCE2430T1Le2P2P1lSYw8km2G1XQ+Q4AScblvv4O2Z9fZwCVjY1mFnBHJFMVMOfssswN Vw24lFGoRsH24kO77qdaDTDvwTT4RNWnIWZgknKWEUFIBA3YxWG9Gw9ke5rMknxi6DHF 48Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qGY7aCHNZkCzk37MB6QkE9/q/X8JPmp9I2EqeH2GHLs=; b=z8F0VlH0BfzrqznhSim8Kh3zWz+g2q391kgIonIJC38f/+kCpoY79WCu1Q5Rz1oseh 5O6ybDcQCFwqc4RZU/OGkUIIyGbwniAifpbqxfpHI9iW+noF4ANuOHThPqjyfzgFWTFh zA0T28iqfNSvWXpiCMBL/e1zUaYqnItJTtqGL364fIdNkGuPf+3mBP93m+vKyzN/CgMm yEYy9xMz80He6B5BsEmeFS49ZWnC1u8jCo6q7OycuPPXRrjPexWAj6w1VYLmIbeTpRir lGL2ESLFKNbcdgVb0sMQkVdYzQcaL20NuqfG/o4/0jB6LqeR9ieR+4YymrwnLJZsT8vP tvDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pg4shd14; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w9si9948061jad.47.2021.05.07.19.24.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:24:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pg4shd14; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCdj-0007HA-TZ for patch@linaro.org; Fri, 07 May 2021 22:24:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41528) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC83-0002zK-LX for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:39 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:45645) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC7z-0005Re-T8 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:39 -0400 Received: by mail-pj1-x102d.google.com with SMTP id gc22-20020a17090b3116b02901558435aec1so6554228pjb.4 for ; Fri, 07 May 2021 18:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qGY7aCHNZkCzk37MB6QkE9/q/X8JPmp9I2EqeH2GHLs=; b=pg4shd14mG+eOzHLBOi+i55J3HafWOLRzqg2FdJMkAvDqxNyOs3H8aURdtawdWB05J S4AcFpomYTUdDrrhSp4vVXtsqjzQCQduasCoG5m3jPlTppa8COGqdg+nO95ZANJ1RiTr yBrc4+gYbwA8farm7gy4ZP5QVdQ3Hi7cfVP+xzfLrgIluzUTw7PhgqnB7I6gAshmu/fU +VfEh9n7R3Z3WuC0wZYsNpRAwKpXeN7NgPgVxV2JFoJ6zHKAqSWhIAEZLjDh/B8QcUtX PE6z8zI98fOe8EM63UBYpTTToRrtwX3EacP8491IcnCDsN49j2GO99G6zu9s50w2E1aR bgfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qGY7aCHNZkCzk37MB6QkE9/q/X8JPmp9I2EqeH2GHLs=; b=K1qvcco6+6umSSiTPsp2lMl1vQDbpGHS5RsXR73LA/g4EI3wUTwWxFC3xSUnNRv8dA yE7bK86V7BiXc/kNOSJZbE940i6yh15kjHmzASPIMjPwwVwkvhQI7vDMVrj//LFXmBc/ 5PNlQUoMb+5kSiBFwq4zMsk+4ElP88qiOSjs6i4Kx1/V3JqhWyPpvrAvz/ymptXtxktb FDsyL++H6bJewEw5qvnBtmBu2qH0w/tVWSU2/uDFm1cnjCkW+ee2JhTtNFUANyEuwVNN flyjmJ1hv/PfOBi9emE2o/G1rh9nnGLsJR3XaHRkG3jmR/wUFu8hayz1nPZKzaf/2N/S bmWQ== X-Gm-Message-State: AOAM532xWrp1+zruHyQ5O6Lk6XxL37eAd9E3kBfi9mgxqNlVA/uXPwsX 0zGpcrfAIaqakYYLXfdT6A2BI/kcw+SIeg== X-Received: by 2002:a17:90b:514:: with SMTP id r20mr26854444pjz.193.1620438694536; Fri, 07 May 2021 18:51:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 47/72] softfloat: Move rount_to_uint_and_pack to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:37 -0700 Message-Id: <20210508014802.892561-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_float_to_uint. Reimplement float128_to_uint{32,64}{_round_to_zero} with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 357 +++++++++----------------------------- fpu/softfloat-parts.c.inc | 68 +++++++- 2 files changed, 147 insertions(+), 278 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ac8e726935..235ddda7a0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -838,6 +838,16 @@ static int64_t parts128_float_to_sint(FloatParts128 *p, FloatRoundMode rmode, #define parts_float_to_sint(P, R, Z, MN, MX, S) \ PARTS_GENERIC_64_128(float_to_sint, P)(P, R, Z, MN, MX, S) +static uint64_t parts64_float_to_uint(FloatParts64 *p, FloatRoundMode rmode, + int scale, uint64_t max, + float_status *s); +static uint64_t parts128_float_to_uint(FloatParts128 *p, FloatRoundMode rmode, + int scale, uint64_t max, + float_status *s); + +#define parts_float_to_uint(P, R, Z, M, S) \ + PARTS_GENERIC_64_128(float_to_uint, P)(P, R, Z, M, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2645,80 +2655,16 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a, float_status *s) } /* - * Returns the result of converting the floating-point value `a' to - * the unsigned integer format. The conversion is performed according - * to the IEC/IEEE Standard for Binary Floating-Point - * Arithmetic---which means in particular that the conversion is - * rounded according to the current rounding mode. If `a' is a NaN, - * the largest unsigned integer is returned. Otherwise, if the - * conversion overflows, the largest unsigned integer is returned. If - * the 'a' is negative, the result is rounded and zero is returned; - * values that do not round to zero will raise the inexact exception - * flag. + * Floating-point to unsigned integer conversions */ -static uint64_t round_to_uint_and_pack(FloatParts64 p, FloatRoundMode rmode, - int scale, uint64_t max, - float_status *s) -{ - int flags = 0; - uint64_t r; - - switch (p.cls) { - case float_class_snan: - case float_class_qnan: - flags = float_flag_invalid; - r = max; - break; - - case float_class_inf: - flags = float_flag_invalid; - r = p.sign ? 0 : max; - break; - - case float_class_zero: - return 0; - - case float_class_normal: - /* TODO: 62 = N - 2, frac_size for rounding */ - if (parts_round_to_int_normal(&p, rmode, scale, 62)) { - flags = float_flag_inexact; - if (p.cls == float_class_zero) { - r = 0; - break; - } - } - - if (p.sign) { - flags = float_flag_invalid; - r = 0; - } else if (p.exp > DECOMPOSED_BINARY_POINT) { - flags = float_flag_invalid; - r = max; - } else { - r = p.frac >> (DECOMPOSED_BINARY_POINT - p.exp); - if (r > max) { - flags = float_flag_invalid; - r = max; - } - } - break; - - default: - g_assert_not_reached(); - } - - float_raise(flags, s); - return r; -} - uint8_t float16_to_uint8_scalbn(float16 a, FloatRoundMode rmode, int scale, float_status *s) { FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT8_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT8_MAX, s); } uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2727,7 +2673,7 @@ uint16_t float16_to_uint16_scalbn(float16 a, FloatRoundMode rmode, int scale, FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); } uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2736,7 +2682,7 @@ uint32_t float16_to_uint32_scalbn(float16 a, FloatRoundMode rmode, int scale, FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); } uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode rmode, int scale, @@ -2745,7 +2691,7 @@ uint64_t float16_to_uint64_scalbn(float16 a, FloatRoundMode rmode, int scale, FloatParts64 p; float16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); } uint16_t float32_to_uint16_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2754,7 +2700,7 @@ uint16_t float32_to_uint16_scalbn(float32 a, FloatRoundMode rmode, int scale, FloatParts64 p; float32_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); } uint32_t float32_to_uint32_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2763,7 +2709,7 @@ uint32_t float32_to_uint32_scalbn(float32 a, FloatRoundMode rmode, int scale, FloatParts64 p; float32_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); } uint64_t float32_to_uint64_scalbn(float32 a, FloatRoundMode rmode, int scale, @@ -2772,7 +2718,7 @@ uint64_t float32_to_uint64_scalbn(float32 a, FloatRoundMode rmode, int scale, FloatParts64 p; float32_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); } uint16_t float64_to_uint16_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2781,7 +2727,7 @@ uint16_t float64_to_uint16_scalbn(float64 a, FloatRoundMode rmode, int scale, FloatParts64 p; float64_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); } uint32_t float64_to_uint32_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2790,7 +2736,7 @@ uint32_t float64_to_uint32_scalbn(float64 a, FloatRoundMode rmode, int scale, FloatParts64 p; float64_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); } uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int scale, @@ -2799,7 +2745,52 @@ uint64_t float64_to_uint64_scalbn(float64 a, FloatRoundMode rmode, int scale, FloatParts64 p; float64_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); +} + +uint16_t bfloat16_to_uint16_scalbn(bfloat16 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT16_MAX, s); +} + +uint32_t bfloat16_to_uint32_scalbn(bfloat16 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); +} + +uint64_t bfloat16_to_uint64_scalbn(bfloat16 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); +} + +static uint32_t float128_to_uint32_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT32_MAX, s); +} + +static uint64_t float128_to_uint64_scalbn(float128 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + return parts_float_to_uint(&p, rmode, scale, UINT64_MAX, s); } uint8_t float16_to_uint8(float16 a, float_status *s) @@ -2852,6 +2843,16 @@ uint64_t float64_to_uint64(float64 a, float_status *s) return float64_to_uint64_scalbn(a, s->float_rounding_mode, 0, s); } +uint32_t float128_to_uint32(float128 a, float_status *s) +{ + return float128_to_uint32_scalbn(a, s->float_rounding_mode, 0, s); +} + +uint64_t float128_to_uint64(float128 a, float_status *s) +{ + return float128_to_uint64_scalbn(a, s->float_rounding_mode, 0, s); +} + uint16_t float16_to_uint16_round_to_zero(float16 a, float_status *s) { return float16_to_uint16_scalbn(a, float_round_to_zero, 0, s); @@ -2897,36 +2898,14 @@ uint64_t float64_to_uint64_round_to_zero(float64 a, float_status *s) return float64_to_uint64_scalbn(a, float_round_to_zero, 0, s); } -/* - * Returns the result of converting the bfloat16 value `a' to - * the unsigned integer format. - */ - -uint16_t bfloat16_to_uint16_scalbn(bfloat16 a, FloatRoundMode rmode, - int scale, float_status *s) +uint32_t float128_to_uint32_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT16_MAX, s); + return float128_to_uint32_scalbn(a, float_round_to_zero, 0, s); } -uint32_t bfloat16_to_uint32_scalbn(bfloat16 a, FloatRoundMode rmode, - int scale, float_status *s) +uint64_t float128_to_uint64_round_to_zero(float128 a, float_status *s) { - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT32_MAX, s); -} - -uint64_t bfloat16_to_uint64_scalbn(bfloat16 a, FloatRoundMode rmode, - int scale, float_status *s) -{ - FloatParts64 p; - - bfloat16_unpack_canonical(&p, a, s); - return round_to_uint_and_pack(p, rmode, scale, UINT64_MAX, s); + return float128_to_uint64_scalbn(a, float_round_to_zero, 0, s); } uint16_t bfloat16_to_uint16(bfloat16 a, float_status *s) @@ -4122,66 +4101,6 @@ static int64_t roundAndPackInt64(bool zSign, uint64_t absZ0, uint64_t absZ1, } -/*---------------------------------------------------------------------------- -| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and -| `absZ1', with binary point between bits 63 and 64 (between the input words), -| and returns the properly rounded 64-bit unsigned integer corresponding to the -| input. Ordinarily, the fixed-point input is simply rounded to an integer, -| with the inexact exception raised if the input cannot be represented exactly -| as an integer. However, if the fixed-point input is too large, the invalid -| exception is raised and the largest unsigned integer is returned. -*----------------------------------------------------------------------------*/ - -static int64_t roundAndPackUint64(bool zSign, uint64_t absZ0, - uint64_t absZ1, float_status *status) -{ - int8_t roundingMode; - bool roundNearestEven, increment; - - roundingMode = status->float_rounding_mode; - roundNearestEven = (roundingMode == float_round_nearest_even); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment = ((int64_t)absZ1 < 0); - break; - case float_round_to_zero: - increment = 0; - break; - case float_round_up: - increment = !zSign && absZ1; - break; - case float_round_down: - increment = zSign && absZ1; - break; - case float_round_to_odd: - increment = !(absZ0 & 1) && absZ1; - break; - default: - abort(); - } - if (increment) { - ++absZ0; - if (absZ0 == 0) { - float_raise(float_flag_invalid, status); - return UINT64_MAX; - } - if (!(absZ1 << 1) && roundNearestEven) { - absZ0 &= ~1; - } - } - - if (zSign && absZ0) { - float_raise(float_flag_invalid, status); - return 0; - } - - if (absZ1) { - float_raise(float_flag_inexact, status); - } - return absZ0; -} - /*---------------------------------------------------------------------------- | Normalizes the subnormal single-precision floating-point value represented | by the denormalized significand `aSig'. The normalized exponent and @@ -6535,122 +6454,6 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *status) 0, zExp, zSig0, zSig1, status); } -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point value -| `a' to the 64-bit unsigned integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. If the conversion overflows, the -| largest unsigned integer is returned. If 'a' is negative, the value is -| rounded and zero is returned; negative values that do not round to zero -| will raise the inexact exception. -*----------------------------------------------------------------------------*/ - -uint64_t float128_to_uint64(float128 a, float_status *status) -{ - bool aSign; - int aExp; - int shiftCount; - uint64_t aSig0, aSig1; - - aSig0 = extractFloat128Frac0(a); - aSig1 = extractFloat128Frac1(a); - aExp = extractFloat128Exp(a); - aSign = extractFloat128Sign(a); - if (aSign && (aExp > 0x3FFE)) { - float_raise(float_flag_invalid, status); - if (float128_is_any_nan(a)) { - return UINT64_MAX; - } else { - return 0; - } - } - if (aExp) { - aSig0 |= UINT64_C(0x0001000000000000); - } - shiftCount = 0x402F - aExp; - if (shiftCount <= 0) { - if (0x403E < aExp) { - float_raise(float_flag_invalid, status); - return UINT64_MAX; - } - shortShift128Left(aSig0, aSig1, -shiftCount, &aSig0, &aSig1); - } else { - shift64ExtraRightJamming(aSig0, aSig1, shiftCount, &aSig0, &aSig1); - } - return roundAndPackUint64(aSign, aSig0, aSig1, status); -} - -uint64_t float128_to_uint64_round_to_zero(float128 a, float_status *status) -{ - uint64_t v; - signed char current_rounding_mode = status->float_rounding_mode; - - set_float_rounding_mode(float_round_to_zero, status); - v = float128_to_uint64(a, status); - set_float_rounding_mode(current_rounding_mode, status); - - return v; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the 32-bit unsigned integer format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic except that the conversion is always rounded toward zero. -| If `a' is a NaN, the largest positive integer is returned. Otherwise, -| if the conversion overflows, the largest unsigned integer is returned. -| If 'a' is negative, the value is rounded and zero is returned; negative -| values that do not round to zero will raise the inexact exception. -*----------------------------------------------------------------------------*/ - -uint32_t float128_to_uint32_round_to_zero(float128 a, float_status *status) -{ - uint64_t v; - uint32_t res; - int old_exc_flags = get_float_exception_flags(status); - - v = float128_to_uint64_round_to_zero(a, status); - if (v > 0xffffffff) { - res = 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point value -| `a' to the 32-bit unsigned integer format. The conversion is -| performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic---which means in particular that the conversion is rounded -| according to the current rounding mode. If `a' is a NaN, the largest -| positive integer is returned. If the conversion overflows, the -| largest unsigned integer is returned. If 'a' is negative, the value is -| rounded and zero is returned; negative values that do not round to zero -| will raise the inexact exception. -*----------------------------------------------------------------------------*/ - -uint32_t float128_to_uint32(float128 a, float_status *status) -{ - uint64_t v; - uint32_t res; - int old_exc_flags = get_float_exception_flags(status); - - v = float128_to_uint64(a, status); - if (v > 0xffffffff) { - res = 0xffffffff; - } else { - return v; - } - set_float_exception_flags(old_exc_flags, status); - float_raise(float_flag_invalid, status); - return res; -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point | value `a' to the extended double-precision floating-point format. The diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index a897a5a743..c6e327547f 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -761,7 +761,7 @@ static void partsN(round_to_int)(FloatPartsN *a, FloatRoundMode rmode, * the largest positive integer is returned. Otherwise, if the * conversion overflows, the largest integer with the same sign as `a' * is returned. -*/ + */ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, int scale, int64_t min, int64_t max, float_status *s) @@ -815,3 +815,69 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, float_raise(flags, s); return r; } + +/* + * Returns the result of converting the floating-point value `a' to + * the unsigned integer format. The conversion is performed according + * to the IEC/IEEE Standard for Binary Floating-Point + * Arithmetic---which means in particular that the conversion is + * rounded according to the current rounding mode. If `a' is a NaN, + * the largest unsigned integer is returned. Otherwise, if the + * conversion overflows, the largest unsigned integer is returned. If + * the 'a' is negative, the result is rounded and zero is returned; + * values that do not round to zero will raise the inexact exception + * flag. + */ +static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, + int scale, uint64_t max, float_status *s) +{ + int flags = 0; + uint64_t r; + + switch (p->cls) { + case float_class_snan: + case float_class_qnan: + flags = float_flag_invalid; + r = max; + break; + + case float_class_inf: + flags = float_flag_invalid; + r = p->sign ? 0 : max; + break; + + case float_class_zero: + return 0; + + case float_class_normal: + /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ + if (parts_round_to_int_normal(p, rmode, scale, N - 2)) { + flags = float_flag_inexact; + if (p->cls == float_class_zero) { + r = 0; + break; + } + } + + if (p->sign) { + flags = float_flag_invalid; + r = 0; + } else if (p->exp > DECOMPOSED_BINARY_POINT) { + flags = float_flag_invalid; + r = max; + } else { + r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); + if (r > max) { + flags = float_flag_invalid; + r = max; + } + } + break; + + default: + g_assert_not_reached(); + } + + float_raise(flags, s); + return r; +} From patchwork Sat May 8 01:47:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432567 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp862142jao; Fri, 7 May 2021 19:30:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzdUOUyxUeeDFadTJA0jFEKj8b/js8qSBtJV+F8539WaeI1VLon7AYC+Irhr5jcKq/bRuxS X-Received: by 2002:a92:6f11:: with SMTP id k17mr12186673ilc.200.1620441010419; Fri, 07 May 2021 19:30:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441010; cv=none; d=google.com; s=arc-20160816; b=n3VKk+Pb0PZxpmrtj+1WExVjU0bXLwuJN6QpWR/Fb8U3JY/nURcfw4UltJFFPz/ixl 4dgkxeV4U7blv++olg11Zk3+pyVTjpS/+iBGCxxAXD4vOOnI0UIKOAwf0MOZqLAY2dv/ hNYfSSEP8lctpmNfnMkp0miWbLilnDDpEUdakd0kSa6D9qzrEAuGeWvBtwTj509X2xGx 4en6I9X+8dM04YIjwGAdIB1yY0nXiLE0jkpdREY+TI4TzX+KmXKmvDD492NUsrZZ9mJ+ oI8FTtN2CH0JGsK1WTBpdTgiFuMudwD0ECPkH19fuFv1zTuc1uUlajg83eOop6s2P/4w oc8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1Od39KgKMdYhwkyR5c/sGxfaCPXmuk0Ca5kCuFG8rqg=; b=GFpmS7GYXdWd4kcFW/Zka4c9g2SFM0gS3PiUtAc/zusDJCdiG0bVfik7SY349la3Xt Fn0PVT4kWxYrzK3JJG6D53VCDpNr6l8LtKAyzJ3zKB8XVm73RZ3vbA9a/7y2RGMchpeA kZfjCCllTNABS2PYByDGTRxwe6HUn/00QJIfBYfzl47IeEz/ssAVVPPsAxzmZMn+YqYJ hpRrC925y7+6e9MMmPvxustfIrCn+68zr3GPZ6OvT86IclgVcjCbvjZrHfdTujJBUmTS bJfXa/YyvK+T78Ofy1iVrEAP0vm+NyjZkUGicNmTEX16l7on/cpjmOQl8zvK0vH1ekYD x8ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IF7kVHgR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s24si8533652ioc.50.2021.05.07.19.30.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:30:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IF7kVHgR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCjJ-0000DV-MJ for patch@linaro.org; Fri, 07 May 2021 22:30:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC82-0002vM-N0 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:38 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:46767) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC80-0005Rp-Ep for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:38 -0400 Received: by mail-pg1-x52f.google.com with SMTP id m124so8603148pgm.13 for ; Fri, 07 May 2021 18:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1Od39KgKMdYhwkyR5c/sGxfaCPXmuk0Ca5kCuFG8rqg=; b=IF7kVHgRdpduJYwf3ykC3rP1wJOb9RxNKG7me5v76JPWL3/rZrKtwg5S9e+7mrrcgx Zaiocmb6pnHrk3mcgttwIrDk4El8Jcm397Wl37Ie3ipU3RXcKeD7NDRUwuYMeS0bO0lB dflQQ3ZoFRmgg/tpxw+L2pje3eAgMyVmdOwB4M0KUYSVkYXvVQbyxjrVMTOWWxJvT9Vo B4jy/nxcsWg87CCg/p/wYkODgiORHRMEE2Nw6KA82PdsxHo8gfE4W9euU0Qj02lAKyWT YW5b2dsHZ36H5ISROCL0b5fdtDmkR1GsMDTY0e3vBFFiCwzo+WXjKrGi9NpynpZutOqM p5kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1Od39KgKMdYhwkyR5c/sGxfaCPXmuk0Ca5kCuFG8rqg=; b=Y7l2Pj/SfTf59RAuMbvoljeQOrsQEd0vgqEnunZAu/p+KaTRsxhX+dCi2IOzlOyDZ2 1wF283506/Zj+UKqz+Vfgejt/jolpAQbmertGnbka+dCwcRzj4czqA89+LCVt7bnQL8v 2sK1xKkbHhZ5P+72q8BopS3AkcYSVQC1qpHjTEb57JPfc66jRAtj5mm8JTlRdtPNjYJH jD4Oj4Kvlo3RGhEYaRYRrPPq1aeqdIHhDOA/sfRsguffMPYP1hJ9W82ERnYZW56NPp6h QpsxdcT3QgzXaI7u8xszd8InoyK7lL65UERubAsOwZBBh4gughkJ9mSuHLbDixxMVOe7 8kww== X-Gm-Message-State: AOAM532MC1f3jjuXKt8lF2TcM5Gr5frBza86fegntJI/0tdw3WudP83G ypEGheS0jWw849oWp8+l/dyVYF5XymzoJA== X-Received: by 2002:a62:8fd2:0:b029:28e:8c64:52a4 with SMTP id n201-20020a628fd20000b029028e8c6452a4mr13447910pfd.3.1620438695142; Fri, 07 May 2021 18:51:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 48/72] softfloat: Move int_to_float to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:38 -0700 Message-Id: <20210508014802.892561-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_sint_to_float. Reimplement int{32,64}_to_float128 with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 136 +++++++++++--------------------------- fpu/softfloat-parts.c.inc | 32 +++++++++ 2 files changed, 70 insertions(+), 98 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 235ddda7a0..d843ea67c4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -848,6 +848,14 @@ static uint64_t parts128_float_to_uint(FloatParts128 *p, FloatRoundMode rmode, #define parts_float_to_uint(P, R, Z, M, S) \ PARTS_GENERIC_64_128(float_to_uint, P)(P, R, Z, M, S) +static void parts64_sint_to_float(FloatParts64 *p, int64_t a, + int scale, float_status *s); +static void parts128_sint_to_float(FloatParts128 *p, int64_t a, + int scale, float_status *s); + +#define parts_sint_to_float(P, I, Z, S) \ + PARTS_GENERIC_64_128(sint_to_float, P)(P, I, Z, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -2939,42 +2947,15 @@ uint64_t bfloat16_to_uint64_round_to_zero(bfloat16 a, float_status *s) } /* - * Integer to float conversions - * - * Returns the result of converting the two's complement integer `a' - * to the floating-point format. The conversion is performed according - * to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. + * Signed integer to floating-point conversions */ -static FloatParts64 int_to_float(int64_t a, int scale, float_status *status) -{ - FloatParts64 r = { .sign = false }; - - if (a == 0) { - r.cls = float_class_zero; - } else { - uint64_t f = a; - int shift; - - r.cls = float_class_normal; - if (a < 0) { - f = -f; - r.sign = true; - } - shift = clz64(f); - scale = MIN(MAX(scale, -0x10000), 0x10000); - - r.exp = DECOMPOSED_BINARY_POINT - shift + scale; - r.frac = f << shift; - } - - return r; -} - float16 int64_to_float16_scalbn(int64_t a, int scale, float_status *status) { - FloatParts64 pa = int_to_float(a, scale, status); - return float16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_sint_to_float(&p, a, scale, status); + return float16_round_pack_canonical(&p, status); } float16 int32_to_float16_scalbn(int32_t a, int scale, float_status *status) @@ -3009,8 +2990,10 @@ float16 int8_to_float16(int8_t a, float_status *status) float32 int64_to_float32_scalbn(int64_t a, int scale, float_status *status) { - FloatParts64 pa = int_to_float(a, scale, status); - return float32_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts64_sint_to_float(&p, a, scale, status); + return float32_round_pack_canonical(&p, status); } float32 int32_to_float32_scalbn(int32_t a, int scale, float_status *status) @@ -3040,8 +3023,10 @@ float32 int16_to_float32(int16_t a, float_status *status) float64 int64_to_float64_scalbn(int64_t a, int scale, float_status *status) { - FloatParts64 pa = int_to_float(a, scale, status); - return float64_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_sint_to_float(&p, a, scale, status); + return float64_round_pack_canonical(&p, status); } float64 int32_to_float64_scalbn(int32_t a, int scale, float_status *status) @@ -3069,15 +3054,12 @@ float64 int16_to_float64(int16_t a, float_status *status) return int64_to_float64_scalbn(a, 0, status); } -/* - * Returns the result of converting the two's complement integer `a' - * to the bfloat16 format. - */ - bfloat16 int64_to_bfloat16_scalbn(int64_t a, int scale, float_status *status) { - FloatParts64 pa = int_to_float(a, scale, status); - return bfloat16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_sint_to_float(&p, a, scale, status); + return bfloat16_round_pack_canonical(&p, status); } bfloat16 int32_to_bfloat16_scalbn(int32_t a, int scale, float_status *status) @@ -3105,6 +3087,19 @@ bfloat16 int16_to_bfloat16(int16_t a, float_status *status) return int64_to_bfloat16_scalbn(a, 0, status); } +float128 int64_to_float128(int64_t a, float_status *status) +{ + FloatParts128 p; + + parts_sint_to_float(&p, a, 0, status); + return float128_round_pack_canonical(&p, status); +} + +float128 int32_to_float128(int32_t a, float_status *status) +{ + return int64_to_float128(a, status); +} + /* * Unsigned Integer to float conversions * @@ -4955,28 +4950,6 @@ floatx80 int32_to_floatx80(int32_t a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of converting the 32-bit two's complement integer `a' to -| the quadruple-precision floating-point format. The conversion is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 int32_to_float128(int32_t a, float_status *status) -{ - bool zSign; - uint32_t absA; - int8_t shiftCount; - uint64_t zSig0; - - if ( a == 0 ) return packFloat128( 0, 0, 0, 0 ); - zSign = ( a < 0 ); - absA = zSign ? - a : a; - shiftCount = clz32(absA) + 17; - zSig0 = absA; - return packFloat128( zSign, 0x402E - shiftCount, zSig0<cls = float_class_zero; + return; + } + + p->cls = float_class_normal; + if (a < 0) { + f = -f; + p->sign = true; + } + shift = clz64(f); + scale = MIN(MAX(scale, -0x10000), 0x10000); + + p->exp = DECOMPOSED_BINARY_POINT - shift + scale; + p->frac_hi = f << shift; +} From patchwork Sat May 8 01:47:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432561 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp859488jao; Fri, 7 May 2021 19:24:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKZ2HXWlUGDviGMi6JnQkQlk90VoNbSZj0eLfq6JqfNCbbmKcAwDuXQUQ+p4rMSWIyjMDE X-Received: by 2002:a92:cc0f:: with SMTP id s15mr11839899ilp.187.1620440683581; Fri, 07 May 2021 19:24:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440683; cv=none; d=google.com; s=arc-20160816; b=kiYjIZif4BaUX46dO3LYQ+QuCpdxDM6OCsHszgP825rxfcTKpZZAYxuaurEbnyBCNu BNcMJMWCFs78uu7Xnltm/I6YDPvIg5hR5yuLFcKliz3rBHu7q3IqT77Lz6KLW2Fs+h// uWjw+m44lrJUno9AE2jh4sU6/tYVUee34QkeSWI24NAdf5PNMunOGdnOZE161a7VOZXW gv9TGyePFRMuRkWzVK1NJVXNmU1W1Xn75jaH5FVKFvShZ0zu5pfz9k2rdTzpcq+Fw6UV p1j6GvaXbObmniDmrEZmIx/f2AqN9tAlVLpKXtdDjOwCKcdI9nu4BCFGPwrQwU1URL54 QRIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WxNVLgCyElMY37gn22Vy5J3sqRsrYp5DRRH+JnN2jwQ=; b=enlln0BwXq/vr+2sbjEVaopgw6+0E4QdLWp8jZpXxLu0xbuE0BfqwLmYbGzOvbqNfi /MYc2I78qAouBIVKOk5MlrEOEGQrGJjbgKyEuwFd3Hvjepf78ZkZz0xXG1XrUTGX434A GLKyoMzFe6lxouHEeDlXSXTne3nZSTdYSjWEdk485UEM4292HxDCXBQ9gjRFYFhvKcvJ TNoCnDrwobHBrjay2paJe1+1Aq1KF2Clib9Q7RYv9n98XfkZhRgVK20+qbZbzBaBQNmL QgF3nHTQOLbuNCbNi0IxBqtv1E4YumSDD/fl6Y7DDkfwmYjUIGzSbN3gXPqlFAu7XyLy U+jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fRFdX00L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z11si10770385ioq.81.2021.05.07.19.24.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:24:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fRFdX00L; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50934 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCe2-0007aj-U1 for patch@linaro.org; Fri, 07 May 2021 22:24:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC83-00030T-VB for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:40 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:44901) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC81-0005So-46 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:39 -0400 Received: by mail-pg1-x533.google.com with SMTP id y32so8617324pga.11 for ; Fri, 07 May 2021 18:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WxNVLgCyElMY37gn22Vy5J3sqRsrYp5DRRH+JnN2jwQ=; b=fRFdX00Lqr+Vz736N4H6f4pLbQA/G/fE5+tANfIl8AndT8+zWbYwKdpHuPnAfk30ov +6xpWLhR/4SaNyBw5QE1M8SF0VvN0ofdagbu1tTnekGy7X/uQ5KNz4mCVJFUQMmTD37i wMf7dugsii3SD9Ayqdp9dg1gYELG3i9NxD1BDBfpsy+snSfn5geoOoZyy4v+NFtsRrYJ WHXCBGguR21gji2VePNKxVke2TfOGpdlLiOHXYNta0uoU+JV+JmJSJl26xDtUuvRW14a Fs6hM7gqzozH8qbzp7pCA+S5nT8rMyzlRx9fIorixfpoy+w9JY5dd0N45ZQkabsI+gkN bQwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WxNVLgCyElMY37gn22Vy5J3sqRsrYp5DRRH+JnN2jwQ=; b=Ui4M19yNIKgmBZYDqq9jVImc7RRVsx6BpUVwZhAq/tWDc+xgn3IS8o9iKuVjcFQQFW QGdifkIMcYb6TkY2wEaAv4H7X5KYQmC5G+oKLRvt5KVSP/X4Fs9piKLiglygbJMz8O+r YwLakdCGqNOosy0lOn6IsZ1Q6Bo3Ajf8iijl6UkiiOoyAxPYjl4KgTYaZ5wIH6geco4I 7p2FrxmV78xt7kppFWa+dEMIvi/mnPVe7fOGUxDJD12me/MKafP67o2AlRStHN4LuAZ0 9Z+y8f1zilrAaA4DPtNeIHeph/0TvTR9IgALA8UA6HEKyaS4q2a0hcewNzWUehCjwR3x sNXw== X-Gm-Message-State: AOAM531NPrVfWwWEGDFc9ZwhTDbpEcR2+3Stpawi3KHJfcwCmLUxHewF M79EIjQ0qAHf5GUpI9ul6JcJWjWGD6zplA== X-Received: by 2002:a05:6a00:198f:b029:2a9:7589:e78a with SMTP id d15-20020a056a00198fb02902a97589e78amr5139566pfl.35.1620438695732; Fri, 07 May 2021 18:51:35 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 49/72] softfloat: Move uint_to_float to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:39 -0700 Message-Id: <20210508014802.892561-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_uint_to_float. Reimplement uint64_to_float128 with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 83 ++++++++++++++++----------------------- fpu/softfloat-parts.c.inc | 23 +++++++++++ 2 files changed, 56 insertions(+), 50 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d843ea67c4..586ea5d67a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -856,6 +856,14 @@ static void parts128_sint_to_float(FloatParts128 *p, int64_t a, #define parts_sint_to_float(P, I, Z, S) \ PARTS_GENERIC_64_128(sint_to_float, P)(P, I, Z, S) +static void parts64_uint_to_float(FloatParts64 *p, uint64_t a, + int scale, float_status *s); +static void parts128_uint_to_float(FloatParts128 *p, uint64_t a, + int scale, float_status *s); + +#define parts_uint_to_float(P, I, Z, S) \ + PARTS_GENERIC_64_128(uint_to_float, P)(P, I, Z, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3101,35 +3109,15 @@ float128 int32_to_float128(int32_t a, float_status *status) } /* - * Unsigned Integer to float conversions - * - * Returns the result of converting the unsigned integer `a' to the - * floating-point format. The conversion is performed according to the - * IEC/IEEE Standard for Binary Floating-Point Arithmetic. + * Unsigned Integer to floating-point conversions */ -static FloatParts64 uint_to_float(uint64_t a, int scale, float_status *status) -{ - FloatParts64 r = { .sign = false }; - int shift; - - if (a == 0) { - r.cls = float_class_zero; - } else { - scale = MIN(MAX(scale, -0x10000), 0x10000); - shift = clz64(a); - r.cls = float_class_normal; - r.exp = DECOMPOSED_BINARY_POINT - shift + scale; - r.frac = a << shift; - } - - return r; -} - float16 uint64_to_float16_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts64 pa = uint_to_float(a, scale, status); - return float16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return float16_round_pack_canonical(&p, status); } float16 uint32_to_float16_scalbn(uint32_t a, int scale, float_status *status) @@ -3164,8 +3152,10 @@ float16 uint8_to_float16(uint8_t a, float_status *status) float32 uint64_to_float32_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts64 pa = uint_to_float(a, scale, status); - return float32_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return float32_round_pack_canonical(&p, status); } float32 uint32_to_float32_scalbn(uint32_t a, int scale, float_status *status) @@ -3195,8 +3185,10 @@ float32 uint16_to_float32(uint16_t a, float_status *status) float64 uint64_to_float64_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts64 pa = uint_to_float(a, scale, status); - return float64_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return float64_round_pack_canonical(&p, status); } float64 uint32_to_float64_scalbn(uint32_t a, int scale, float_status *status) @@ -3224,15 +3216,12 @@ float64 uint16_to_float64(uint16_t a, float_status *status) return uint64_to_float64_scalbn(a, 0, status); } -/* - * Returns the result of converting the unsigned integer `a' to the - * bfloat16 format. - */ - bfloat16 uint64_to_bfloat16_scalbn(uint64_t a, int scale, float_status *status) { - FloatParts64 pa = uint_to_float(a, scale, status); - return bfloat16_round_pack_canonical(&pa, status); + FloatParts64 p; + + parts_uint_to_float(&p, a, scale, status); + return bfloat16_round_pack_canonical(&p, status); } bfloat16 uint32_to_bfloat16_scalbn(uint32_t a, int scale, float_status *status) @@ -3260,6 +3249,14 @@ bfloat16 uint16_to_bfloat16(uint16_t a, float_status *status) return uint64_to_bfloat16_scalbn(a, 0, status); } +float128 uint64_to_float128(uint64_t a, float_status *status) +{ + FloatParts128 p; + + parts_uint_to_float(&p, a, 0, status); + return float128_round_pack_canonical(&p, status); +} + /* Float Min/Max */ /* min() and max() functions. These can't be implemented as * 'compare and pick one input' because that would mishandle @@ -4971,20 +4968,6 @@ floatx80 int64_to_floatx80(int64_t a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of converting the 64-bit unsigned integer `a' -| to the quadruple-precision floating-point format. The conversion is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 uint64_to_float128(uint64_t a, float_status *status) -{ - if (a == 0) { - return float128_zero; - } - return normalizeRoundAndPackFloat128(0, 0x406E, 0, a, status); -} - /*---------------------------------------------------------------------------- | Returns the result of converting the single-precision floating-point value | `a' to the extended double-precision floating-point format. The conversion diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 8102de1307..f3c4f8c8d2 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -913,3 +913,26 @@ static void partsN(sint_to_float)(FloatPartsN *p, int64_t a, p->exp = DECOMPOSED_BINARY_POINT - shift + scale; p->frac_hi = f << shift; } + +/* + * Unsigned Integer to float conversions + * + * Returns the result of converting the unsigned integer `a' to the + * floating-point format. The conversion is performed according to the + * IEC/IEEE Standard for Binary Floating-Point Arithmetic. + */ +static void partsN(uint_to_float)(FloatPartsN *p, uint64_t a, + int scale, float_status *status) +{ + memset(p, 0, sizeof(*p)); + + if (a == 0) { + p->cls = float_class_zero; + } else { + int shift = clz64(a); + scale = MIN(MAX(scale, -0x10000), 0x10000); + p->cls = float_class_normal; + p->exp = DECOMPOSED_BINARY_POINT - shift + scale; + p->frac_hi = a << shift; + } +} From patchwork Sat May 8 01:47:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432563 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp860750jao; Fri, 7 May 2021 19:27:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzFmmbbVWNI32wpBcAVHFTrav07W/FI5CtdSymgQ4FhEOaUsJvbtzt7SxMH+pM19IENuPXH X-Received: by 2002:a05:6e02:20c2:: with SMTP id 2mr12701283ilq.120.1620440838789; Fri, 07 May 2021 19:27:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620440838; cv=none; d=google.com; s=arc-20160816; b=su69rHIZ3I0jRwEnp7ki3o9WhideVfDBRIAkovEufyMMIoep63zew7CsCVibAMzWzq w7Ts8vkJK1wNyaclFL+Fh/NTOFFio998nJH0cw1/Lwxw3iesyAzXQ9btE3iNiHn73Q54 qM0j0Rmo/LeIb3xHXev4LgBvsDGeYZHOQDcjO94p3mH5bS3GBkAiCYJEdtL9Ibx3ltno RSIs5fcOJce3XRAUXrtEcHPQGRpctmGWeS/dLXQKBdjtL1PKq1J55o0CX43O07yDan1K 0Upctz/ENoIhjCJ9AYT7ZD29dLTZN3HuF3aQ0a+V+n6Q2HkQbf10jVDydaasQNtmK84V 7UIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YFLKka0iYCXD41zHCVcvWrqgkoEzdfWn73QZrRjsYNY=; b=Wjf7w8F7nLPzrzjKMQnQXp02dNTQGBU50t/ZJ7W4foX3SSjA9NuxcKeaIBC+Q4UDnC 54idM3c0nc5BL8nkxJx/hN43wA7dI/7Cf7oCJTk5onEmPbZKY8YkNyWgBN+IRgJ5jhlP cx3Pr659e0h+YmVtqwI9lBHmVx8r/nlhfEexgBi+MaYpy8jbkhzyDpO1OCl00czV/eoZ rUA4nc44dh6myQO9a6VyySCw2r94qBV/YxsxuScWg6AU85UiBu3w0t200po8i102IK5C EI04x8dfMiVarea7+mgphmCNam3hoXpjhHDEUTZZZ9AlJrTT3wp1kzYC5vYVkkMMWten 7PPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=abEIsfOs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m35si9850712jav.9.2021.05.07.19.27.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:27:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=abEIsfOs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCgY-0004gn-5y for patch@linaro.org; Fri, 07 May 2021 22:27:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41552) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC84-00031y-A9 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:40 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:56035) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC81-0005TG-Pc for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:40 -0400 Received: by mail-pj1-x1030.google.com with SMTP id gj14so6202079pjb.5 for ; Fri, 07 May 2021 18:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YFLKka0iYCXD41zHCVcvWrqgkoEzdfWn73QZrRjsYNY=; b=abEIsfOsqPKfS2cbgywp1cLBCn0g/xw6dRoNcSHBMQ8I8O8NUaej+enLAQQdq7Sxe2 K8ix1ndNL6XTeuDaApFfum7VCUaX4r24ZW+h37LMxd5e/BzNm5I1Py78JuICII+Lm7y5 AEh60pTbtcVvrcneXA220DLWAZMtvj8iySc0FgPtyEyz5wg3xVAl2KFnvy7h+CAGci+a vUZ4NH5CnSMGHY/2nwSfRlS9922bLafgis682snva6SReX3dU92ahIm7jX4vApy97GwO SINbn205Y4SEbkKv0j9SzkFrfPHEGqW1h54lcM/q2r3rVa6Iyb/GTDSnRVv7P4RSb5iv 15oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YFLKka0iYCXD41zHCVcvWrqgkoEzdfWn73QZrRjsYNY=; b=pc+xFa2zHy+M08LGS8S9m2C3qs6JPpnOccZWASoeXPp/LvWnAlCOjB3ztY7dpnFFx/ dmT7P3YcfZU9XJ6kw77GCQA8oJSp/teVC04MyjnAyf/0gqZTGaqUkiIR8ozJ62w0JUbe DPDv5QB76qmagruqUPx0jweeD0veEsR2jK6W01ohuYM+OkpDC5OoBhsqw4uJth3sjt26 8rx0j1nqsrHnUlbGAPzYBpDIJVQtquho/qFIIG8AIu43qfUpXIGJGFDLR47yMF1Hl06Z sVk7FtUaRCrnCEHmLCYZm49KzF0jx1NPkblyYH6+FfvsMeRO4bWPaX0z+IK6bJiKS42t 5CuA== X-Gm-Message-State: AOAM530f4oRvqw/zZ91Wa7Vr1WXH1LQWeK++VIO1rmQ91sDjaK7WwW27 WeA5qNm0T50nLUn7wji43ncAReMwuV5B3A== X-Received: by 2002:a17:90a:9f02:: with SMTP id n2mr26923831pjp.190.1620438696366; Fri, 07 May 2021 18:51:36 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 50/72] softfloat: Move minmax_flags to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:40 -0700 Message-Id: <20210508014802.892561-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_minmax. Combine 3 bool arguments to a bitmask, return a tri-state value to indicate nan vs unchanged operand. Introduce ftype_minmax functions as a common optimization point. Fold bfloat16 expansions into the same macro as the other types. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 216 ++++++++++++++++---------------------- fpu/softfloat-parts.c.inc | 69 ++++++++++++ 2 files changed, 158 insertions(+), 127 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 586ea5d67a..4c04e88a3a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -482,6 +482,15 @@ enum { float_cmask_anynan = float_cmask_qnan | float_cmask_snan, }; +/* Flags for parts_minmax. */ +enum { + /* Set for minimum; clear for maximum. */ + minmax_ismin = 1, + /* Set for the IEEE 754-2008 minNum() and maxNum() operations. */ + minmax_isnum = 2, + /* Set for the IEEE 754-2008 minNumMag() and minNumMag() operations. */ + minmax_ismag = 4 | minmax_isnum +}; /* Simple helpers for checking if, or what kind of, NaN we have */ static inline __attribute__((unused)) bool is_nan(FloatClass c) @@ -864,6 +873,14 @@ static void parts128_uint_to_float(FloatParts128 *p, uint64_t a, #define parts_uint_to_float(P, I, Z, S) \ PARTS_GENERIC_64_128(uint_to_float, P)(P, I, Z, S) +static int parts64_minmax(FloatParts64 *a, FloatParts64 *b, + float_status *s, int flags, const FloatFmt *fmt); +static int parts128_minmax(FloatParts128 *a, FloatParts128 *b, + float_status *s, int flags, const FloatFmt *fmt); + +#define parts_minmax(A, B, S, Z, F) \ + PARTS_GENERIC_64_128(minmax, A)(A, B, S, Z, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3257,145 +3274,90 @@ float128 uint64_to_float128(uint64_t a, float_status *status) return float128_round_pack_canonical(&p, status); } -/* Float Min/Max */ -/* min() and max() functions. These can't be implemented as - * 'compare and pick one input' because that would mishandle - * NaNs and +0 vs -0. - * - * minnum() and maxnum() functions. These are similar to the min() - * and max() functions but if one of the arguments is a QNaN and - * the other is numerical then the numerical argument is returned. - * SNaNs will get quietened before being returned. - * minnum() and maxnum correspond to the IEEE 754-2008 minNum() - * and maxNum() operations. min() and max() are the typical min/max - * semantics provided by many CPUs which predate that specification. - * - * minnummag() and maxnummag() functions correspond to minNumMag() - * and minNumMag() from the IEEE-754 2008. +/* + * Minimum and maximum */ -static FloatParts64 minmax_floats(FloatParts64 a, FloatParts64 b, bool ismin, - bool ieee, bool ismag, float_status *s) + +static float16 float16_minmax(float16 a, float16 b, float_status *s, int flags) { - if (unlikely(is_nan(a.cls) || is_nan(b.cls))) { - if (ieee) { - /* Takes two floating-point values `a' and `b', one of - * which is a NaN, and returns the appropriate NaN - * result. If either `a' or `b' is a signaling NaN, - * the invalid exception is raised. - */ - if (is_snan(a.cls) || is_snan(b.cls)) { - return *parts_pick_nan(&a, &b, s); - } else if (is_nan(a.cls) && !is_nan(b.cls)) { - return b; - } else if (is_nan(b.cls) && !is_nan(a.cls)) { - return a; - } - } - return *parts_pick_nan(&a, &b, s); - } else { - int a_exp, b_exp; + FloatParts64 pa, pb; + int which; - switch (a.cls) { - case float_class_normal: - a_exp = a.exp; - break; - case float_class_inf: - a_exp = INT_MAX; - break; - case float_class_zero: - a_exp = INT_MIN; - break; - default: - g_assert_not_reached(); - break; - } - switch (b.cls) { - case float_class_normal: - b_exp = b.exp; - break; - case float_class_inf: - b_exp = INT_MAX; - break; - case float_class_zero: - b_exp = INT_MIN; - break; - default: - g_assert_not_reached(); - break; - } - - if (ismag && (a_exp != b_exp || a.frac != b.frac)) { - bool a_less = a_exp < b_exp; - if (a_exp == b_exp) { - a_less = a.frac < b.frac; - } - return a_less ^ ismin ? b : a; - } - - if (a.sign == b.sign) { - bool a_less = a_exp < b_exp; - if (a_exp == b_exp) { - a_less = a.frac < b.frac; - } - return a.sign ^ a_less ^ ismin ? b : a; - } else { - return a.sign ^ ismin ? b : a; - } + float16_unpack_canonical(&pa, a, s); + float16_unpack_canonical(&pb, b, s); + which = parts_minmax(&pa, &pb, s, flags, &float16_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return float16_round_pack_canonical(&pa, s); } + return which ? b : a; } -#define MINMAX(sz, name, ismin, isiee, ismag) \ -float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \ - float_status *s) \ -{ \ - FloatParts64 pa, pb, pr; \ - float ## sz ## _unpack_canonical(&pa, a, s); \ - float ## sz ## _unpack_canonical(&pb, b, s); \ - pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return float ## sz ## _round_pack_canonical(&pr, s); \ +static bfloat16 bfloat16_minmax(bfloat16 a, bfloat16 b, + float_status *s, int flags) +{ + FloatParts64 pa, pb; + int which; + + bfloat16_unpack_canonical(&pa, a, s); + bfloat16_unpack_canonical(&pb, b, s); + which = parts_minmax(&pa, &pb, s, flags, &float16_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return bfloat16_round_pack_canonical(&pa, s); + } + return which ? b : a; } -MINMAX(16, min, true, false, false) -MINMAX(16, minnum, true, true, false) -MINMAX(16, minnummag, true, true, true) -MINMAX(16, max, false, false, false) -MINMAX(16, maxnum, false, true, false) -MINMAX(16, maxnummag, false, true, true) +static float32 float32_minmax(float32 a, float32 b, float_status *s, int flags) +{ + FloatParts64 pa, pb; + int which; -MINMAX(32, min, true, false, false) -MINMAX(32, minnum, true, true, false) -MINMAX(32, minnummag, true, true, true) -MINMAX(32, max, false, false, false) -MINMAX(32, maxnum, false, true, false) -MINMAX(32, maxnummag, false, true, true) - -MINMAX(64, min, true, false, false) -MINMAX(64, minnum, true, true, false) -MINMAX(64, minnummag, true, true, true) -MINMAX(64, max, false, false, false) -MINMAX(64, maxnum, false, true, false) -MINMAX(64, maxnummag, false, true, true) - -#undef MINMAX - -#define BF16_MINMAX(name, ismin, isiee, ismag) \ -bfloat16 bfloat16_ ## name(bfloat16 a, bfloat16 b, float_status *s) \ -{ \ - FloatParts64 pa, pb, pr; \ - bfloat16_unpack_canonical(&pa, a, s); \ - bfloat16_unpack_canonical(&pb, b, s); \ - pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \ - return bfloat16_round_pack_canonical(&pr, s); \ + float32_unpack_canonical(&pa, a, s); + float32_unpack_canonical(&pb, b, s); + which = parts_minmax(&pa, &pb, s, flags, &float32_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return float32_round_pack_canonical(&pa, s); + } + return which ? b : a; } -BF16_MINMAX(min, true, false, false) -BF16_MINMAX(minnum, true, true, false) -BF16_MINMAX(minnummag, true, true, true) -BF16_MINMAX(max, false, false, false) -BF16_MINMAX(maxnum, false, true, false) -BF16_MINMAX(maxnummag, false, true, true) +static float64 float64_minmax(float64 a, float64 b, float_status *s, int flags) +{ + FloatParts64 pa, pb; + int which; -#undef BF16_MINMAX + float64_unpack_canonical(&pa, a, s); + float64_unpack_canonical(&pb, b, s); + which = parts_minmax(&pa, &pb, s, flags, &float64_params); + if (unlikely(which < 0)) { + /* Some sort of nan, need to repack default and silenced nans. */ + return float64_round_pack_canonical(&pa, s); + } + return which ? b : a; +} + +#define MINMAX_1(type, name, flags) \ + type type##_##name(type a, type b, float_status *s) \ + { return type##_minmax(a, b, s, flags); } + +#define MINMAX_2(type) \ + MINMAX_1(type, max, 0) \ + MINMAX_1(type, maxnum, minmax_isnum) \ + MINMAX_1(type, maxnummag, minmax_ismag) \ + MINMAX_1(type, min, minmax_ismin) \ + MINMAX_1(type, minnum, minmax_ismin | minmax_isnum) \ + MINMAX_1(type, minnummag, minmax_ismin | minmax_ismag) + +MINMAX_2(float16) +MINMAX_2(bfloat16) +MINMAX_2(float32) +MINMAX_2(float64) + +#undef MINMAX_1 +#undef MINMAX_2 /* Floating point compare */ static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool is_quiet, diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index f3c4f8c8d2..4d91ef0d32 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -936,3 +936,72 @@ static void partsN(uint_to_float)(FloatPartsN *p, uint64_t a, p->frac_hi = a << shift; } } + +/* + * Float min/max. + * + * Return -1 to return the chosen nan in *a; + * return 0 to use the a input unchanged; 1 to use the b input unchanged. + */ +static int partsN(minmax)(FloatPartsN *a, FloatPartsN *b, + float_status *s, int flags, const FloatFmt *fmt) +{ + int ab_mask = float_cmask(a->cls) | float_cmask(b->cls); + int a_exp, b_exp; + bool a_less; + + if (unlikely(ab_mask & float_cmask_anynan)) { + /* + * For minnum/maxnum, if one operand is a QNaN, and the other + * operand is numerical, then return numerical argument. + */ + if ((flags & minmax_isnum) + && !(ab_mask & float_cmask_snan) + && (ab_mask & ~float_cmask_qnan)) { + return is_nan(a->cls); + } + *a = *parts_pick_nan(a, b, s); + return -1; + } + + a_exp = a->exp; + b_exp = b->exp; + + if (unlikely(ab_mask != float_cmask_normal)) { + switch (a->cls) { + case float_class_normal: + break; + case float_class_inf: + a_exp = INT_MAX; + break; + case float_class_zero: + a_exp = INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + switch (b->cls) { + case float_class_normal: + break; + case float_class_inf: + b_exp = INT_MAX; + break; + case float_class_zero: + b_exp = INT_MIN; + break; + default: + g_assert_not_reached(); + break; + } + } + + if (a->sign != b->sign && !(flags & minmax_ismag)) { + a_less = a->sign; + } else if (a_exp != b_exp) { + a_less = a_exp < b_exp; + } else { + a_less = frac_cmp(a, b) < 0; + } + return a_less ^ !!(flags & minmax_ismin); +} From patchwork Sat May 8 01:47:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432578 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp865011jao; Fri, 7 May 2021 19:35:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYZExcJHqlzQdemPsyYb5r1OkpTjvQE3pc3fv4bXAkLIWrgDCozcrd6Ers/NtA/hjrOikP X-Received: by 2002:a05:6e02:20e8:: with SMTP id q8mr12026149ilv.90.1620441338557; Fri, 07 May 2021 19:35:38 -0700 (PDT) ARC-Seal: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id l17si12290917iow.32.2021.05.07.19.35.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:35:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rQTg9BLN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCob-0006bv-QP for patch@linaro.org; Fri, 07 May 2021 22:35:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC84-00034Y-T8 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:40 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:35776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC82-0005Tr-Do for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:40 -0400 Received: by mail-pg1-x52b.google.com with SMTP id m190so8682026pga.2 for ; Fri, 07 May 2021 18:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=btOAZwJbwmIfoIZyo9x/MIEWhS9Tw3gK+69H5Ryqe74=; b=rQTg9BLNQPs3Bm0GSJAYbtKEIQkd1uty1OD2E2myr+qMKn+CNt9iXS69fP6xuYlExt bE4UYr/fqXQxHlHHJhsP2ToxVKVW9fGw9jFJN9TIuhjrfAw7UlVCdhi/d1F+zDitEqLi kdWVLEM6n7WRDl7GOi8qhxIygFVHisXc5TrcZ9mVeshIZNiSomX4kxGJoyU/oK6wWJ+s rBMH67S/GmZQCub5G/5uBsyiFpayQmiWV4SK+6tH2Jo8V8twNqe/eYhTBLnBa+oHrQLg jG+cV7KKtbm8XVgq+PKkaDfp5L2wfwTvYRqG8f4Mf3czkhp3IVxgRJARgDnW87qlAncv QgNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=btOAZwJbwmIfoIZyo9x/MIEWhS9Tw3gK+69H5Ryqe74=; b=UNP79GjscD6gSSYCnl5+/8AOl6kHT/76mwVLC2HdfufFYLjhN5RGVYt01FdQPr2V2R idoLq6lEdgbXiMWxrsqTMPt2Ocm3oWXjvF5ejXF5cD5MmaCfyfZROVH4UW5LRPSGZgSF DTv/5FMaNUlHBp1e7wgT4CBWYMyYLOyy/ExHSXUuUC1anuOBfvpYsdPmfeu9NArIDnoh z8EFGyEPxBFFajv9EqguIJYtrZ7SIYnWMe880xc6HNaIQ1jxyS2Fw3bXqCwirC67x9KT 21iLi/QzbhX+Xvh6SmBPsMGJXysZ/LcMYvZ5j3QNRc+XjwtY92TOaccc7S0TDSlHbebe l4ag== X-Gm-Message-State: AOAM531VdaeuvX+jD8egcEAgR9dZ6FRU2LI8bD/yO6ScEcjIAYWMYAHQ XhYovFWM4ovj9OSVgHQ1jz5yz9cM16kyzQ== X-Received: by 2002:a62:b609:0:b029:28e:af60:60f5 with SMTP id j9-20020a62b6090000b029028eaf6060f5mr13000409pff.43.1620438697004; Fri, 07 May 2021 18:51:37 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 51/72] softfloat: Move compare_floats to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:41 -0700 Message-Id: <20210508014802.892561-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_compare. Rename all of the intermediate functions to ftype_do_compare. Rename the hard-float functions to ftype_hs_compare. Convert float128 to FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 208 ++++++++++++++------------------------ fpu/softfloat-parts.c.inc | 57 +++++++++++ 2 files changed, 133 insertions(+), 132 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4c04e88a3a..2faceadf8b 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -881,6 +881,14 @@ static int parts128_minmax(FloatParts128 *a, FloatParts128 *b, #define parts_minmax(A, B, S, Z, F) \ PARTS_GENERIC_64_128(minmax, A)(A, B, S, Z, F) +static int parts64_compare(FloatParts64 *a, FloatParts64 *b, + float_status *s, bool q); +static int parts128_compare(FloatParts128 *a, FloatParts128 *b, + float_status *s, bool q); + +#define parts_compare(A, B, S, Q) \ + PARTS_GENERIC_64_128(compare, A)(A, B, S, Q) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3359,92 +3367,42 @@ MINMAX_2(float64) #undef MINMAX_1 #undef MINMAX_2 -/* Floating point compare */ -static FloatRelation compare_floats(FloatParts64 a, FloatParts64 b, bool is_quiet, - float_status *s) +/* + * Floating point compare + */ + +static FloatRelation QEMU_FLATTEN +float16_do_compare(float16 a, float16 b, float_status *s, bool is_quiet) { - if (is_nan(a.cls) || is_nan(b.cls)) { - if (!is_quiet || - a.cls == float_class_snan || - b.cls == float_class_snan) { - float_raise(float_flag_invalid, s); - } - return float_relation_unordered; - } + FloatParts64 pa, pb; - if (a.cls == float_class_zero) { - if (b.cls == float_class_zero) { - return float_relation_equal; - } - return b.sign ? float_relation_greater : float_relation_less; - } else if (b.cls == float_class_zero) { - return a.sign ? float_relation_less : float_relation_greater; - } - - /* The only really important thing about infinity is its sign. If - * both are infinities the sign marks the smallest of the two. - */ - if (a.cls == float_class_inf) { - if ((b.cls == float_class_inf) && (a.sign == b.sign)) { - return float_relation_equal; - } - return a.sign ? float_relation_less : float_relation_greater; - } else if (b.cls == float_class_inf) { - return b.sign ? float_relation_greater : float_relation_less; - } - - if (a.sign != b.sign) { - return a.sign ? float_relation_less : float_relation_greater; - } - - if (a.exp == b.exp) { - if (a.frac == b.frac) { - return float_relation_equal; - } - if (a.sign) { - return a.frac > b.frac ? - float_relation_less : float_relation_greater; - } else { - return a.frac > b.frac ? - float_relation_greater : float_relation_less; - } - } else { - if (a.sign) { - return a.exp > b.exp ? float_relation_less : float_relation_greater; - } else { - return a.exp > b.exp ? float_relation_greater : float_relation_less; - } - } + float16_unpack_canonical(&pa, a, s); + float16_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); } -#define COMPARE(name, attr, sz) \ -static int attr \ -name(float ## sz a, float ## sz b, bool is_quiet, float_status *s) \ -{ \ - FloatParts64 pa, pb; \ - float ## sz ## _unpack_canonical(&pa, a, s); \ - float ## sz ## _unpack_canonical(&pb, b, s); \ - return compare_floats(pa, pb, is_quiet, s); \ -} - -COMPARE(soft_f16_compare, QEMU_FLATTEN, 16) -COMPARE(soft_f32_compare, QEMU_SOFTFLOAT_ATTR, 32) -COMPARE(soft_f64_compare, QEMU_SOFTFLOAT_ATTR, 64) - -#undef COMPARE - FloatRelation float16_compare(float16 a, float16 b, float_status *s) { - return soft_f16_compare(a, b, false, s); + return float16_do_compare(a, b, s, false); } FloatRelation float16_compare_quiet(float16 a, float16 b, float_status *s) { - return soft_f16_compare(a, b, true, s); + return float16_do_compare(a, b, s, true); +} + +static FloatRelation QEMU_SOFTFLOAT_ATTR +float32_do_compare(float32 a, float32 b, float_status *s, bool is_quiet) +{ + FloatParts64 pa, pb; + + float32_unpack_canonical(&pa, a, s); + float32_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); } static FloatRelation QEMU_FLATTEN -f32_compare(float32 xa, float32 xb, bool is_quiet, float_status *s) +float32_hs_compare(float32 xa, float32 xb, float_status *s, bool is_quiet) { union_float32 ua, ub; @@ -3465,25 +3423,36 @@ f32_compare(float32 xa, float32 xb, bool is_quiet, float_status *s) if (likely(isless(ua.h, ub.h))) { return float_relation_less; } - /* The only condition remaining is unordered. + /* + * The only condition remaining is unordered. * Fall through to set flags. */ soft: - return soft_f32_compare(ua.s, ub.s, is_quiet, s); + return float32_do_compare(ua.s, ub.s, s, is_quiet); } FloatRelation float32_compare(float32 a, float32 b, float_status *s) { - return f32_compare(a, b, false, s); + return float32_hs_compare(a, b, s, false); } FloatRelation float32_compare_quiet(float32 a, float32 b, float_status *s) { - return f32_compare(a, b, true, s); + return float32_hs_compare(a, b, s, true); +} + +static FloatRelation QEMU_SOFTFLOAT_ATTR +float64_do_compare(float64 a, float64 b, float_status *s, bool is_quiet) +{ + FloatParts64 pa, pb; + + float64_unpack_canonical(&pa, a, s); + float64_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); } static FloatRelation QEMU_FLATTEN -f64_compare(float64 xa, float64 xb, bool is_quiet, float_status *s) +float64_hs_compare(float64 xa, float64 xb, float_status *s, bool is_quiet) { union_float64 ua, ub; @@ -3504,41 +3473,62 @@ f64_compare(float64 xa, float64 xb, bool is_quiet, float_status *s) if (likely(isless(ua.h, ub.h))) { return float_relation_less; } - /* The only condition remaining is unordered. + /* + * The only condition remaining is unordered. * Fall through to set flags. */ soft: - return soft_f64_compare(ua.s, ub.s, is_quiet, s); + return float64_do_compare(ua.s, ub.s, s, is_quiet); } FloatRelation float64_compare(float64 a, float64 b, float_status *s) { - return f64_compare(a, b, false, s); + return float64_hs_compare(a, b, s, false); } FloatRelation float64_compare_quiet(float64 a, float64 b, float_status *s) { - return f64_compare(a, b, true, s); + return float64_hs_compare(a, b, s, true); } static FloatRelation QEMU_FLATTEN -soft_bf16_compare(bfloat16 a, bfloat16 b, bool is_quiet, float_status *s) +bfloat16_do_compare(bfloat16 a, bfloat16 b, float_status *s, bool is_quiet) { FloatParts64 pa, pb; bfloat16_unpack_canonical(&pa, a, s); bfloat16_unpack_canonical(&pb, b, s); - return compare_floats(pa, pb, is_quiet, s); + return parts_compare(&pa, &pb, s, is_quiet); } FloatRelation bfloat16_compare(bfloat16 a, bfloat16 b, float_status *s) { - return soft_bf16_compare(a, b, false, s); + return bfloat16_do_compare(a, b, s, false); } FloatRelation bfloat16_compare_quiet(bfloat16 a, bfloat16 b, float_status *s) { - return soft_bf16_compare(a, b, true, s); + return bfloat16_do_compare(a, b, s, true); +} + +static FloatRelation QEMU_FLATTEN +float128_do_compare(float128 a, float128 b, float_status *s, bool is_quiet) +{ + FloatParts128 pa, pb; + + float128_unpack_canonical(&pa, a, s); + float128_unpack_canonical(&pb, b, s); + return parts_compare(&pa, &pb, s, is_quiet); +} + +FloatRelation float128_compare(float128 a, float128 b, float_status *s) +{ + return float128_do_compare(a, b, s, false); +} + +FloatRelation float128_compare_quiet(float128 a, float128 b, float_status *s) +{ + return float128_do_compare(a, b, s, true); } /* Multiply A by 2 raised to the power N. */ @@ -6611,52 +6601,6 @@ FloatRelation floatx80_compare_quiet(floatx80 a, floatx80 b, return floatx80_compare_internal(a, b, 1, status); } -static inline FloatRelation -float128_compare_internal(float128 a, float128 b, bool is_quiet, - float_status *status) -{ - bool aSign, bSign; - - if (( ( extractFloat128Exp( a ) == 0x7fff ) && - ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) ) || - ( ( extractFloat128Exp( b ) == 0x7fff ) && - ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )) { - if (!is_quiet || - float128_is_signaling_nan(a, status) || - float128_is_signaling_nan(b, status)) { - float_raise(float_flag_invalid, status); - } - return float_relation_unordered; - } - aSign = extractFloat128Sign( a ); - bSign = extractFloat128Sign( b ); - if ( aSign != bSign ) { - if ( ( ( ( a.high | b.high )<<1 ) | a.low | b.low ) == 0 ) { - /* zero case */ - return float_relation_equal; - } else { - return 1 - (2 * aSign); - } - } else { - if (a.low == b.low && a.high == b.high) { - return float_relation_equal; - } else { - return 1 - 2 * (aSign ^ ( lt128( a.high, a.low, b.high, b.low ) )); - } - } -} - -FloatRelation float128_compare(float128 a, float128 b, float_status *status) -{ - return float128_compare_internal(a, b, 0, status); -} - -FloatRelation float128_compare_quiet(float128 a, float128 b, - float_status *status) -{ - return float128_compare_internal(a, b, 1, status); -} - floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) { bool aSign; diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 4d91ef0d32..4e11aa8b3b 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1005,3 +1005,60 @@ static int partsN(minmax)(FloatPartsN *a, FloatPartsN *b, } return a_less ^ !!(flags & minmax_ismin); } + +/* + * Floating point compare + */ +static FloatRelation partsN(compare)(FloatPartsN *a, FloatPartsN *b, + float_status *s, bool is_quiet) +{ + int ab_mask = float_cmask(a->cls) | float_cmask(b->cls); + int cmp; + + if (likely(ab_mask == float_cmask_normal)) { + if (a->sign != b->sign) { + goto a_sign; + } + if (a->exp != b->exp) { + cmp = a->exp < b->exp ? -1 : 1; + } else { + cmp = frac_cmp(a, b); + } + if (a->sign) { + cmp = -cmp; + } + return cmp; + } + + if (unlikely(ab_mask & float_cmask_anynan)) { + if (!is_quiet || (ab_mask & float_cmask_snan)) { + float_raise(float_flag_invalid, s); + } + return float_relation_unordered; + } + + if (ab_mask & float_cmask_zero) { + if (ab_mask == float_cmask_zero) { + return float_relation_equal; + } else if (a->cls == float_class_zero) { + goto b_sign; + } else { + goto a_sign; + } + } + + if (ab_mask == float_cmask_inf) { + if (a->sign == b->sign) { + return float_relation_equal; + } + } else if (b->cls == float_class_inf) { + goto b_sign; + } else { + g_assert(a->cls == float_class_inf); + } + + a_sign: + return a->sign ? float_relation_less : float_relation_greater; + b_sign: + return b->sign ? float_relation_greater : float_relation_less; +} From patchwork Sat May 8 01:47:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432571 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp862916jao; Fri, 7 May 2021 19:31:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwuv/C9yEmERS+FA38qE6g7+uFltuld3cvf6csxYo7OVZ4yYpYjNxtLYD0nx1YzGVn69z8v X-Received: by 2002:a5d:878e:: with SMTP id f14mr10049732ion.176.1620441098298; Fri, 07 May 2021 19:31:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441098; cv=none; d=google.com; s=arc-20160816; b=UmcclPRW7tsTnLaj32vtak07iu1uW1W27Y4P/WX0QD0k6nKtAs2T/D4jX8UVnrqW/m D3QmyZHdnIxRVlln46tkyoN4glP/2i9L1XRV1hykoIvQEKdOPZyiW3LTXMQIyvU0QB++ ufP8sPGsHestV3Nj1MzO1e5A3kO+B7uXkYzDL4wo1fvc6JdXKbdk1tE+wsQcJ5BiSdhv GqHMI8K9JKnKAgbwoJhKZ1Pee6WYu5fsfbGuo0qLLWeg7gA9VM0rJG/AvcAfvRcBI7qK 68UjjBSiRrg9Zgc/0IpDOqBeBq9VK9mQzmMdEwuhaWNnA21rHu2wKU9laRiS9z3XDKla g8OQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id k11si7784741jap.38.2021.05.07.19.31.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:31:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WB2XNQ1y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCkj-0005yY-Ob for patch@linaro.org; Fri, 07 May 2021 22:31:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC86-0003Bl-Pu for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:42 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:45657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC82-0005UC-V7 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:42 -0400 Received: by mail-pf1-x42c.google.com with SMTP id i190so9084664pfc.12 for ; Fri, 07 May 2021 18:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eMIJGqBzed5Gqno92wb2fBBiT03MKVRcpl3Hpjjr9sA=; b=WB2XNQ1yGN4oLJb3r3tnLj+wjaa/nwWP8mPVhL+0H2oONQ722gMg4ATft46RjusWdl A34AN/izQw1MtDrY4oeITQLY56A1Zgw8XeIb8BcSoGIWxCry7pJQO+QnrOfz9TfOP57L CqpNwpo6u+MkELA2Mk4iwvv3jRMcn05OTjIYuPpa6Y8g5EvjkuQQQxyNfsHddsHQozwA GCvH1D02moeuVnWt5l8ew0shbMwh4JN8fCK7Qf6VZSPqNJsBKI5xnWKYprf7yUkUHM/9 W3WU/KcfQAPB8l7qx0JJoZo9rgsF1FF/dcm5zDR44nLcPw2MfjVUHt0zEbUmHorV30RC Gb5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eMIJGqBzed5Gqno92wb2fBBiT03MKVRcpl3Hpjjr9sA=; b=QPXYZsbRLyjkAAKkPb0FOaV+OXx1ON0h1etmF2AtXGWYA2DHqlJ3DuJHbsLLwwO5J6 FKNSH2xi9Wg3OPiJviocgS1Hk0agVdVHeuxUkotwJkfMuO2nuc9QdyPEnyiC5wGf+Esf 12zSUJQF84T/V5hhPUAkRFP4a9Vt8BOQ5Na3dl5upPL76jS/Cisf5/vRZW1q184OFhKz 2DiqY4ZCvmIETbn/LjeMwQ+Dj4chl1tpPqJi7neeVIap80atVR4caXcOA4u9U8xFf6sY 9wy13MUEFT2sX6v+aZfb3c/N3A0kN08EeVzifLK4M//X4130YtOGxSYr7U0kMyLVi7PQ 9V1A== X-Gm-Message-State: AOAM533i04Jay2J1sriMuWI0IBL7R5Dh/6WsZ/2czPTkGPMm3wo7UaHC OCRVfZRRr/Jbm87FaAWYb7SylAhtQD1uIg== X-Received: by 2002:aa7:87d9:0:b029:28e:af66:d71d with SMTP id i25-20020aa787d90000b029028eaf66d71dmr13658492pfo.28.1620438697557; Fri, 07 May 2021 18:51:37 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 52/72] softfloat: Move scalbn_decomposed to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:42 -0700 Message-Id: <20210508014802.892561-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_scalbn. Reimplement float128_scalbn with FloatParts128. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 103 +++++++++++++------------------------- fpu/softfloat-parts.c.inc | 21 ++++++++ 2 files changed, 55 insertions(+), 69 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 2faceadf8b..f83ca20000 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -889,6 +889,12 @@ static int parts128_compare(FloatParts128 *a, FloatParts128 *b, #define parts_compare(A, B, S, Q) \ PARTS_GENERIC_64_128(compare, A)(A, B, S, Q) +static void parts64_scalbn(FloatParts64 *a, int n, float_status *s); +static void parts128_scalbn(FloatParts128 *a, int n, float_status *s); + +#define parts_scalbn(A, N, S) \ + PARTS_GENERIC_64_128(scalbn, A)(A, N, S) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -3531,58 +3537,53 @@ FloatRelation float128_compare_quiet(float128 a, float128 b, float_status *s) return float128_do_compare(a, b, s, true); } -/* Multiply A by 2 raised to the power N. */ -static FloatParts64 scalbn_decomposed(FloatParts64 a, int n, float_status *s) -{ - if (unlikely(is_nan(a.cls))) { - parts_return_nan(&a, s); - } - if (a.cls == float_class_normal) { - /* The largest float type (even though not supported by FloatParts64) - * is float128, which has a 15 bit exponent. Bounding N to 16 bits - * still allows rounding to infinity, without allowing overflow - * within the int32_t that backs FloatParts64.exp. - */ - n = MIN(MAX(n, -0x10000), 0x10000); - a.exp += n; - } - return a; -} +/* + * Scale by 2**N + */ float16 float16_scalbn(float16 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - float16_unpack_canonical(&pa, a, status); - pr = scalbn_decomposed(pa, n, status); - return float16_round_pack_canonical(&pr, status); + float16_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float16_round_pack_canonical(&p, status); } float32 float32_scalbn(float32 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - float32_unpack_canonical(&pa, a, status); - pr = scalbn_decomposed(pa, n, status); - return float32_round_pack_canonical(&pr, status); + float32_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float32_round_pack_canonical(&p, status); } float64 float64_scalbn(float64 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - float64_unpack_canonical(&pa, a, status); - pr = scalbn_decomposed(pa, n, status); - return float64_round_pack_canonical(&pr, status); + float64_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float64_round_pack_canonical(&p, status); } bfloat16 bfloat16_scalbn(bfloat16 a, int n, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - bfloat16_unpack_canonical(&pa, a, status); - pr = scalbn_decomposed(pa, n, status); - return bfloat16_round_pack_canonical(&pr, status); + bfloat16_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return bfloat16_round_pack_canonical(&p, status); +} + +float128 float128_scalbn(float128 a, int n, float_status *status) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, status); + parts_scalbn(&p, n, status); + return float128_round_pack_canonical(&p, status); } /* @@ -6640,42 +6641,6 @@ floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) aSign, aExp, aSig, 0, status); } -float128 float128_scalbn(float128 a, int n, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) { - return propagateFloat128NaN(a, a, status); - } - return a; - } - if (aExp != 0) { - aSig0 |= UINT64_C(0x0001000000000000); - } else if (aSig0 == 0 && aSig1 == 0) { - return a; - } else { - aExp++; - } - - if (n > 0x10000) { - n = 0x10000; - } else if (n < -0x10000) { - n = -0x10000; - } - - aExp += n - 1; - return normalizeRoundAndPackFloat128( aSign, aExp, aSig0, aSig1 - , status); - -} - static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 4e11aa8b3b..9749c11a6b 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1062,3 +1062,24 @@ static FloatRelation partsN(compare)(FloatPartsN *a, FloatPartsN *b, b_sign: return b->sign ? float_relation_greater : float_relation_less; } + +/* + * Multiply A by 2 raised to the power N. + */ +static void partsN(scalbn)(FloatPartsN *a, int n, float_status *s) +{ + switch (a->cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(a, s); + break; + case float_class_zero: + case float_class_inf: + break; + case float_class_normal: + a->exp += MIN(MAX(n, -0x10000), 0x10000); + break; + default: + g_assert_not_reached(); + } +} From patchwork Sat May 8 01:47:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432575 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp864367jao; Fri, 7 May 2021 19:34:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJywDb0/lBisN/XhXzGKFomxDABDFYIwqXAzOCWrdfF6dCCvlHo0a5xujw8y7PfGD5xCTBj1 X-Received: by 2002:a5e:a902:: with SMTP id c2mr7102485iod.80.1620441260594; Fri, 07 May 2021 19:34:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441260; cv=none; d=google.com; s=arc-20160816; b=LKsbO5va0FHKDgsqUQjjr1tpLotfkhQ7JeQOHiVQlm5iOtNDOGfhuElx2ZBbVngk6H oy9ZSy/yxBFrqVYau5sI92N3Xx3hkegaI20CjHPBGem1jPOzY2JNPIxsi/5Z05F//l0v o94DTIP92V4tVnOhJ7oxZQ3Up3fQWRpMavSXxXHhy2Yn71TLhhA8Jtg5bPTuKxJpSUiX 9AA5See9R/1Q1lbqIpnMCKo1iRT5D+XIv+VgFmBrPApZE+scjqevaPitCGBe8XSsHa8H cMbgmoF629qIFbZZDLHl4XMMs9zLMx68Ho02Z1AJsYmeUE7milTZFCxjViL9ric0ZoaF ODPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vX4LKvyYIDcCSlAmcHQYpRFHW+uxfOceE/Raw8onmTE=; b=vbX+xhq6f5ZN2sO9BbGc3yGSD2LU/jxt/Hz9kBp5sg6qjWAvH1Oy2IYJEvbFwYvb/9 WHIyotJ31C3shltGbAv+GRD3bmtl+AeEVa+1a2ty5EqXcqH87ubinXVVJWtshO8m/Z0N yxHG9MCCmREcXO5JFUh8f+qdiu/qG6OUoV+XF1l2g/zhWA/LqXpTU8pMwqo7H+yyr44K OQsZWSTfHbG6TsEzc6dWE8jQOUnEui2gsC2nPClsg3JJRI74g/faXx9qgEFeKnrb6eGy CKr8IURxyq9FjY7X3Mjr7U6fagh9GZAxYIFsvlgkG9O64HP4reLuiWym6ri+rj9bPlHI og6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ec42+a+n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k5si8155297ils.114.2021.05.07.19.34.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:34:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ec42+a+n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCnL-0003Bd-Vu for patch@linaro.org; Fri, 07 May 2021 22:34:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC88-0003IR-JW for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:44 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:42952) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC84-0005US-1O for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:44 -0400 Received: by mail-pg1-x52d.google.com with SMTP id m12so8627274pgr.9 for ; Fri, 07 May 2021 18:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vX4LKvyYIDcCSlAmcHQYpRFHW+uxfOceE/Raw8onmTE=; b=Ec42+a+nqkzm6WmFPLp0gs1+KxvCtwhc/kEAtoTAWZJqfNf39pL4a0xDkJ/1F9bfm+ rzzFYJAfOYeRoPfJLP21LXnzTQk71Trp3nQoxU/DvK3ZTs8Hj/5MkjyVGkv54gKZvOd5 TMt0H+ciE8coUn1c2m/Ni352icSPHmI/bTkU/hW75q963of8m+57nJQbOG56b1odMK0J iRnIeicyad5ODIS3TOVus/fm7rFF67Fi/W/lrq9ivH7Trowt6yhK9byMv7+l5ogtEd7x 0db1sk66fl4lLILBvbw3RjS+I9It7WZoUQvYNeWYrbXFUzelZYrAEC726amBzmIiOePR /rMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vX4LKvyYIDcCSlAmcHQYpRFHW+uxfOceE/Raw8onmTE=; b=Ngy64TwtaINu/neWy7lalocSKkPUCn2GVkJqMRiaaD0z2m/ynwPSsmxrP/PjR841b/ JnBDxY74upV0TG4Z023ilRo9yAfqFbeWn302IimyEX8WuNE8abNWQ7dd4/+LN7JMUYmy fmjHgOCBHLHS+ke08JhR3+YTynq0mcC5xa27DqmhOQxy/MlCGNZkjVJSfgDJA1v0fB3+ RmsbLo6m+Q0CND8u6XiC3Tp7QVFAlUbfufDBTEyPA/BKU4xppAWHMkn9FB0gYrvomSWm bYqpXjQaFGvrdS1maAV7LVe6kRJPbom7ge4evpIv4xylzCdsQAQ02jKFTflSSYj7jcTA FdNA== X-Gm-Message-State: AOAM533HP4ZIXZf362LzwwjlMjR8FJRxB9W7R6/A2FvBsMD3WfmynsgW 0P8USec8lguqBVBOcp2kKPFn8Z7vTiQqrg== X-Received: by 2002:aa7:96ea:0:b029:28c:e131:f0f with SMTP id i10-20020aa796ea0000b029028ce1310f0fmr13509190pfq.11.1620438698453; Fri, 07 May 2021 18:51:38 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 53/72] softfloat: Move sqrt_float to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:47:43 -0700 Message-Id: <20210508014802.892561-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_sqrt. Reimplement float128_sqrt with FloatParts128. Reimplement with the inverse sqrt newton-raphson algorithm from musl. This is significantly faster than even the berkeley sqrt n-r algorithm, because it does not use division instructions, only multiplication. Ordinarily, changing algorithms at the same time as migrating code is a bad idea, but this is the only way I found that didn't break one of the routines at the same time. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 207 ++++++++++---------------------------- fpu/softfloat-parts.c.inc | 206 +++++++++++++++++++++++++++++++++++++ 2 files changed, 261 insertions(+), 152 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f83ca20000..75a3bb881d 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -819,6 +819,12 @@ static FloatParts128 *parts128_div(FloatParts128 *a, FloatParts128 *b, #define parts_div(A, B, S) \ PARTS_GENERIC_64_128(div, A)(A, B, S) +static void parts64_sqrt(FloatParts64 *a, float_status *s, const FloatFmt *f); +static void parts128_sqrt(FloatParts128 *a, float_status *s, const FloatFmt *f); + +#define parts_sqrt(A, S, F) \ + PARTS_GENERIC_64_128(sqrt, A)(A, S, F) + static bool parts64_round_to_int_normal(FloatParts64 *a, FloatRoundMode rm, int scale, int frac_size); static bool parts128_round_to_int_normal(FloatParts128 *a, FloatRoundMode r, @@ -1385,6 +1391,30 @@ static void frac128_widen(FloatParts256 *r, FloatParts128 *a) #define frac_widen(A, B) FRAC_GENERIC_64_128(widen, B)(A, B) +/* + * Reciprocal sqrt table. 1 bit of exponent, 6-bits of mantessa. + * From https://git.musl-libc.org/cgit/musl/tree/src/math/sqrt_data.c + * and thus MIT licenced. + */ +static const uint16_t rsqrt_tab[128] = { + 0xb451, 0xb2f0, 0xb196, 0xb044, 0xaef9, 0xadb6, 0xac79, 0xab43, + 0xaa14, 0xa8eb, 0xa7c8, 0xa6aa, 0xa592, 0xa480, 0xa373, 0xa26b, + 0xa168, 0xa06a, 0x9f70, 0x9e7b, 0x9d8a, 0x9c9d, 0x9bb5, 0x9ad1, + 0x99f0, 0x9913, 0x983a, 0x9765, 0x9693, 0x95c4, 0x94f8, 0x9430, + 0x936b, 0x92a9, 0x91ea, 0x912e, 0x9075, 0x8fbe, 0x8f0a, 0x8e59, + 0x8daa, 0x8cfe, 0x8c54, 0x8bac, 0x8b07, 0x8a64, 0x89c4, 0x8925, + 0x8889, 0x87ee, 0x8756, 0x86c0, 0x862b, 0x8599, 0x8508, 0x8479, + 0x83ec, 0x8361, 0x82d8, 0x8250, 0x81c9, 0x8145, 0x80c2, 0x8040, + 0xff02, 0xfd0e, 0xfb25, 0xf947, 0xf773, 0xf5aa, 0xf3ea, 0xf234, + 0xf087, 0xeee3, 0xed47, 0xebb3, 0xea27, 0xe8a3, 0xe727, 0xe5b2, + 0xe443, 0xe2dc, 0xe17a, 0xe020, 0xdecb, 0xdd7d, 0xdc34, 0xdaf1, + 0xd9b3, 0xd87b, 0xd748, 0xd61a, 0xd4f1, 0xd3cd, 0xd2ad, 0xd192, + 0xd07b, 0xcf69, 0xce5b, 0xcd51, 0xcc4a, 0xcb48, 0xca4a, 0xc94f, + 0xc858, 0xc764, 0xc674, 0xc587, 0xc49d, 0xc3b7, 0xc2d4, 0xc1f4, + 0xc116, 0xc03c, 0xbf65, 0xbe90, 0xbdbe, 0xbcef, 0xbc23, 0xbb59, + 0xba91, 0xb9cc, 0xb90a, 0xb84a, 0xb78c, 0xb6d0, 0xb617, 0xb560, +}; + #define partsN(NAME) glue(glue(glue(parts,N),_),NAME) #define FloatPartsN glue(FloatParts,N) #define FloatPartsW glue(FloatParts,W) @@ -3588,103 +3618,35 @@ float128 float128_scalbn(float128 a, int n, float_status *status) /* * Square Root - * - * The old softfloat code did an approximation step before zeroing in - * on the final result. However for simpleness we just compute the - * square root by iterating down from the implicit bit to enough extra - * bits to ensure we get a correctly rounded result. - * - * This does mean however the calculation is slower than before, - * especially for 64 bit floats. */ -static FloatParts64 sqrt_float(FloatParts64 a, float_status *s, const FloatFmt *p) -{ - uint64_t a_frac, r_frac, s_frac; - int bit, last_bit; - - if (is_nan(a.cls)) { - parts_return_nan(&a, s); - return a; - } - if (a.cls == float_class_zero) { - return a; /* sqrt(+-0) = +-0 */ - } - if (a.sign) { - float_raise(float_flag_invalid, s); - parts_default_nan(&a, s); - return a; - } - if (a.cls == float_class_inf) { - return a; /* sqrt(+inf) = +inf */ - } - - assert(a.cls == float_class_normal); - - /* We need two overflow bits at the top. Adding room for that is a - * right shift. If the exponent is odd, we can discard the low bit - * by multiplying the fraction by 2; that's a left shift. Combine - * those and we shift right by 1 if the exponent is odd, otherwise 2. - */ - a_frac = a.frac >> (2 - (a.exp & 1)); - a.exp >>= 1; - - /* Bit-by-bit computation of sqrt. */ - r_frac = 0; - s_frac = 0; - - /* Iterate from implicit bit down to the 3 extra bits to compute a - * properly rounded result. Remember we've inserted two more bits - * at the top, so these positions are two less. - */ - bit = DECOMPOSED_BINARY_POINT - 2; - last_bit = MAX(p->frac_shift - 4, 0); - do { - uint64_t q = 1ULL << bit; - uint64_t t_frac = s_frac + q; - if (t_frac <= a_frac) { - s_frac = t_frac + q; - a_frac -= t_frac; - r_frac += q; - } - a_frac <<= 1; - } while (--bit >= last_bit); - - /* Undo the right shift done above. If there is any remaining - * fraction, the result is inexact. Set the sticky bit. - */ - a.frac = (r_frac << 2) + (a_frac != 0); - - return a; -} - float16 QEMU_FLATTEN float16_sqrt(float16 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - float16_unpack_canonical(&pa, a, status); - pr = sqrt_float(pa, status, &float16_params); - return float16_round_pack_canonical(&pr, status); + float16_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float16_params); + return float16_round_pack_canonical(&p, status); } static float32 QEMU_SOFTFLOAT_ATTR soft_f32_sqrt(float32 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - float32_unpack_canonical(&pa, a, status); - pr = sqrt_float(pa, status, &float32_params); - return float32_round_pack_canonical(&pr, status); + float32_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float32_params); + return float32_round_pack_canonical(&p, status); } static float64 QEMU_SOFTFLOAT_ATTR soft_f64_sqrt(float64 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - float64_unpack_canonical(&pa, a, status); - pr = sqrt_float(pa, status, &float64_params); - return float64_round_pack_canonical(&pr, status); + float64_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float64_params); + return float64_round_pack_canonical(&p, status); } float32 QEMU_FLATTEN float32_sqrt(float32 xa, float_status *s) @@ -3743,11 +3705,20 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_status *s) bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { - FloatParts64 pa, pr; + FloatParts64 p; - bfloat16_unpack_canonical(&pa, a, status); - pr = sqrt_float(pa, status, &bfloat16_params); - return bfloat16_round_pack_canonical(&pr, status); + bfloat16_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &bfloat16_params); + return bfloat16_round_pack_canonical(&p, status); +} + +float128 QEMU_FLATTEN float128_sqrt(float128 a, float_status *status) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float128_params); + return float128_round_pack_canonical(&p, status); } /*---------------------------------------------------------------------------- @@ -6475,74 +6446,6 @@ float128 float128_rem(float128 a, float128 b, float_status *status) status); } -/*---------------------------------------------------------------------------- -| Returns the square root of the quadruple-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_sqrt(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp, zExp; - uint64_t aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0; - uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if (aSig0 | aSig1) { - return propagateFloat128NaN(a, a, status); - } - if ( ! aSign ) return a; - goto invalid; - } - if ( aSign ) { - if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a; - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE; - aSig0 |= UINT64_C(0x0001000000000000); - zSig0 = estimateSqrt32( aExp, aSig0>>17 ); - shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 ); - zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 ); - doubleZSig0 = zSig0<<1; - mul64To128( zSig0, zSig0, &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - doubleZSig0 -= 2; - add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 ); - } - zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 ); - if ( ( zSig1 & 0x1FFF ) <= 5 ) { - if ( zSig1 == 0 ) zSig1 = 1; - mul64To128( doubleZSig0, zSig1, &term1, &term2 ); - sub128( rem1, 0, term1, term2, &rem1, &rem2 ); - mul64To128( zSig1, zSig1, &term2, &term3 ); - sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - shortShift128Left( 0, zSig1, 1, &term2, &term3 ); - term3 |= 1; - term2 |= doubleZSig0; - add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 ); - } - zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 ); - } - shift128ExtraRightJamming( zSig0, zSig1, 0, 14, &zSig0, &zSig1, &zSig2 ); - return roundAndPackFloat128(0, zExp, zSig0, zSig1, zSig2, status); - -} - static inline FloatRelation floatx80_compare_internal(floatx80 a, floatx80 b, bool is_quiet, float_status *status) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 9749c11a6b..293029711c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -595,6 +595,212 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, return a; } +/* + * Square Root + * + * The base algorithm is lifted from + * https://git.musl-libc.org/cgit/musl/tree/src/math/sqrtf.c + * https://git.musl-libc.org/cgit/musl/tree/src/math/sqrt.c + * https://git.musl-libc.org/cgit/musl/tree/src/math/sqrtl.c + * and is thus MIT licenced. + */ +static void partsN(sqrt)(FloatPartsN *a, float_status *status, + const FloatFmt *fmt) +{ + const uint32_t three32 = 3u << 30; + const uint64_t three64 = 3ull << 62; + uint32_t d32, m32, r32, s32, u32; /* 32-bit computation */ + uint64_t d64, m64, r64, s64, u64; /* 64-bit computation */ + uint64_t dh, dl, rh, rl, sh, sl, uh, ul; /* 128-bit computation */ + uint64_t d0h, d0l, d1h, d1l, d2h, d2l; + uint64_t discard; + bool exp_odd; + size_t index; + + if (unlikely(a->cls != float_class_normal)) { + switch (a->cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(a, status); + return; + case float_class_zero: + return; + case float_class_inf: + if (unlikely(a->sign)) { + goto d_nan; + } + return; + default: + g_assert_not_reached(); + } + } + + if (unlikely(a->sign)) { + goto d_nan; + } + + /* + * Argument reduction. + * x = 4^e frac; with integer e, and frac in [1, 4) + * m = frac fixed point at bit 62, since we're in base 4. + * If base-2 exponent is odd, exchange that for multiply by 2, + * which results in no shift. + */ + exp_odd = a->exp & 1; + index = extract64(a->frac_hi, 57, 6) | (!exp_odd << 6); + if (!exp_odd) { + frac_shr(a, 1); + } + + /* + * Approximate r ~= 1/sqrt(m) and s ~= sqrt(m) when m in [1, 4). + * + * Initial estimate: + * 7-bit lookup table (1-bit exponent and 6-bit significand). + * + * The relative error (e = r0*sqrt(m)-1) of a linear estimate + * (r0 = a*m + b) is |e| < 0.085955 ~ 0x1.6p-4 at best; + * a table lookup is faster and needs one less iteration. + * The 7-bit table gives |e| < 0x1.fdp-9. + * + * A Newton-Raphson iteration for r is + * s = m*r + * d = s*r + * u = 3 - d + * r = r*u/2 + * + * Fixed point representations: + * m, s, d, u, three are all 2.30; r is 0.32 + */ + m64 = a->frac_hi; + m32 = m64 >> 32; + + r32 = rsqrt_tab[index] << 16; + /* |r*sqrt(m) - 1| < 0x1.FDp-9 */ + + s32 = ((uint64_t)m32 * r32) >> 32; + d32 = ((uint64_t)s32 * r32) >> 32; + u32 = three32 - d32; + + if (N == 64) { + /* float64 or smaller */ + + r32 = ((uint64_t)r32 * u32) >> 31; + /* |r*sqrt(m) - 1| < 0x1.7Bp-16 */ + + s32 = ((uint64_t)m32 * r32) >> 32; + d32 = ((uint64_t)s32 * r32) >> 32; + u32 = three32 - d32; + + if (fmt->frac_size <= 23) { + /* float32 or smaller */ + + s32 = ((uint64_t)s32 * u32) >> 32; /* 3.29 */ + s32 = (s32 - 1) >> 6; /* 9.23 */ + /* s < sqrt(m) < s + 0x1.08p-23 */ + + /* compute nearest rounded result to 2.23 bits */ + uint32_t d0 = (m32 << 16) - s32 * s32; + uint32_t d1 = s32 - d0; + uint32_t d2 = d1 + s32 + 1; + s32 += d1 >> 31; + a->frac_hi = (uint64_t)s32 << (64 - 25); + + /* increment or decrement for inexact */ + if (d2 != 0) { + a->frac_hi += ((int32_t)(d1 ^ d2) < 0 ? -1 : 1); + } + goto done; + } + + /* float64 */ + + r64 = (uint64_t)r32 * u32 * 2; + /* |r*sqrt(m) - 1| < 0x1.37-p29; convert to 64-bit arithmetic */ + mul64To128(m64, r64, &s64, &discard); + mul64To128(s64, r64, &d64, &discard); + u64 = three64 - d64; + + mul64To128(s64, u64, &s64, &discard); /* 3.61 */ + s64 = (s64 - 2) >> 9; /* 12.52 */ + + /* Compute nearest rounded result */ + uint64_t d0 = (m64 << 42) - s64 * s64; + uint64_t d1 = s64 - d0; + uint64_t d2 = d1 + s64 + 1; + s64 += d1 >> 63; + a->frac_hi = s64 << (64 - 54); + + /* increment or decrement for inexact */ + if (d2 != 0) { + a->frac_hi += ((int64_t)(d1 ^ d2) < 0 ? -1 : 1); + } + goto done; + } + + r64 = (uint64_t)r32 * u32 * 2; + /* |r*sqrt(m) - 1| < 0x1.7Bp-16; convert to 64-bit arithmetic */ + + mul64To128(m64, r64, &s64, &discard); + mul64To128(s64, r64, &d64, &discard); + u64 = three64 - d64; + mul64To128(u64, r64, &r64, &discard); + r64 <<= 1; + /* |r*sqrt(m) - 1| < 0x1.a5p-31 */ + + mul64To128(m64, r64, &s64, &discard); + mul64To128(s64, r64, &d64, &discard); + u64 = three64 - d64; + mul64To128(u64, r64, &rh, &rl); + add128(rh, rl, rh, rl, &rh, &rl); + /* |r*sqrt(m) - 1| < 0x1.c001p-59; change to 128-bit arithmetic */ + + mul128To256(a->frac_hi, a->frac_lo, rh, rl, &sh, &sl, &discard, &discard); + mul128To256(sh, sl, rh, rl, &dh, &dl, &discard, &discard); + sub128(three64, 0, dh, dl, &uh, &ul); + mul128To256(uh, ul, sh, sl, &sh, &sl, &discard, &discard); /* 3.125 */ + /* -0x1p-116 < s - sqrt(m) < 0x3.8001p-125 */ + + sub128(sh, sl, 0, 4, &sh, &sl); + shift128Right(sh, sl, 13, &sh, &sl); /* 16.112 */ + /* s < sqrt(m) < s + 1ulp */ + + /* Compute nearest rounded result */ + mul64To128(sl, sl, &d0h, &d0l); + d0h += 2 * sh * sl; + sub128(a->frac_lo << 34, 0, d0h, d0l, &d0h, &d0l); + sub128(sh, sl, d0h, d0l, &d1h, &d1l); + add128(sh, sl, 0, 1, &d2h, &d2l); + add128(d2h, d2l, d1h, d1l, &d2h, &d2l); + add128(sh, sl, 0, d1h >> 63, &sh, &sl); + shift128Left(sh, sl, 128 - 114, &sh, &sl); + + /* increment or decrement for inexact */ + if (d2h | d2l) { + if ((int64_t)(d1h ^ d2h) < 0) { + sub128(sh, sl, 0, 1, &sh, &sl); + } else { + add128(sh, sl, 0, 1, &sh, &sl); + } + } + a->frac_lo = sl; + a->frac_hi = sh; + + done: + /* Convert back from base 4 to base 2. */ + a->exp >>= 1; + if (!(a->frac_hi & DECOMPOSED_IMPLICIT_BIT)) { + frac_add(a, a, a); + } else { + a->exp += 1; + } + return; + + d_nan: + float_raise(float_flag_invalid, status); + parts_default_nan(a, status); +} + /* * Rounds the floating-point value `a' to an integer, and returns the * result as a floating-point value. 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[209.51.188.17]) by mx.google.com with ESMTPS id g1si9248439ila.101.2021.05.07.19.37.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:37:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Xey1+YXB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCqe-00040s-VT for patch@linaro.org; Fri, 07 May 2021 22:37:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC86-00039V-70 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:42 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:44903) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC84-0005VH-D5 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:41 -0400 Received: by mail-pg1-x535.google.com with SMTP id y32so8617369pga.11 for ; Fri, 07 May 2021 18:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zL439EHx3BPOhexd35s+Xkdi6C28utf2wKmRbPR2CBI=; b=Xey1+YXBlzvQ+XRKDOTSi4J19G9eWajaJyQTd4PukhpSnIX9gaxXRNme2bKqp7za1o CAEcAZ5ihkqzT/CwcSjMNGMM2STzyNwO2cuUsrk3ln+peKvBum3Mx7xt0yNEC2uIgRYw 49cptIz+sBVEcVj5nGjTV4+4EItUWu5qhRmVCxPAJDd931TmowV5OA8CYEcD90vjbAGZ pdWu+56H44gIspc0AMnkkc9HC2NEFB+Fabv/wloG42kDTJh/u4f2gy04q2M0mgdEqurU Sla3L64Boa/gdK9YgNpwo1yNjYVpe6G11ge20RA42/EG/x3iork8waEeNDqah3O9lINq B+aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zL439EHx3BPOhexd35s+Xkdi6C28utf2wKmRbPR2CBI=; b=qOVgiHUfxbNQabcHBxFG5JEZlkGtQ017CmfM/3rNYMk5pc14U/gCa23ZKw2F61jF0n qYIQRwKPJalxyIiAXW2rgQ/TnGrm6CkRoc3BzSyl6T0/U9Mo27QPnVeKbm1Y+HyadG4H 6pGV5mg9dpNrIfC44AxXdl/gnVDISVzRQHrHytSxMKWlil8dHaQuWS1p5rRn+doKrMJq tDMHGv7z822y2zOPURhM9lbKdW+cPlp4Af15JaAEpysv3kru8OSdvUNBiUvB7N6yFzbX 5R77UutSViOOZ60dNhLqEStLjMoNIFp9rOdolUMbfqUCo34P3yGHWY6HLmwjDR//vsXJ ylhw== X-Gm-Message-State: AOAM533SWh6a6iL2/xYG/j7o3Hko+EUdy7j+t54mGaelGtSW0vrN5lx8 Ho0ZhDlR1uWdyasMWK3zrbTa49oXle37EQ== X-Received: by 2002:aa7:9104:0:b029:279:e897:2825 with SMTP id 4-20020aa791040000b0290279e8972825mr13447797pfh.51.1620438699041; Fri, 07 May 2021 18:51:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 54/72] softfloat: Split out parts_uncanon_normal Date: Fri, 7 May 2021 18:47:44 -0700 Message-Id: <20210508014802.892561-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will need to treat the non-normal cases of floatx80 specially, so split out the normal case that we can reuse. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 8 ++++++ fpu/softfloat-parts.c.inc | 56 ++++++++++++++++++++++----------------- 2 files changed, 39 insertions(+), 25 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 75a3bb881d..4df69029ec 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -763,6 +763,14 @@ static void parts128_canonicalize(FloatParts128 *p, float_status *status, #define parts_canonicalize(A, S, F) \ PARTS_GENERIC_64_128(canonicalize, A)(A, S, F) +static void parts64_uncanon_normal(FloatParts64 *p, float_status *status, + const FloatFmt *fmt); +static void parts128_uncanon_normal(FloatParts128 *p, float_status *status, + const FloatFmt *fmt); + +#define parts_uncanon_normal(A, S, F) \ + PARTS_GENERIC_64_128(uncanon_normal, A)(A, S, F) + static void parts64_uncanon(FloatParts64 *p, float_status *status, const FloatFmt *fmt); static void parts128_uncanon(FloatParts128 *p, float_status *status, diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 293029711c..65462bf6cb 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -140,8 +140,8 @@ static void partsN(canonicalize)(FloatPartsN *p, float_status *status, * fraction; these bits will be removed. The exponent will be biased * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. */ -static void partsN(uncanon)(FloatPartsN *p, float_status *s, - const FloatFmt *fmt) +static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt) { const int exp_max = fmt->exp_max; const int frac_shift = fmt->frac_shift; @@ -153,29 +153,6 @@ static void partsN(uncanon)(FloatPartsN *p, float_status *s, bool overflow_norm; int exp, flags = 0; - if (unlikely(p->cls != float_class_normal)) { - switch (p->cls) { - case float_class_zero: - p->exp = 0; - frac_clear(p); - return; - case float_class_inf: - g_assert(!fmt->arm_althp); - p->exp = fmt->exp_max; - frac_clear(p); - return; - case float_class_qnan: - case float_class_snan: - g_assert(!fmt->arm_althp); - p->exp = fmt->exp_max; - frac_shr(p, fmt->frac_shift); - return; - default: - break; - } - g_assert_not_reached(); - } - switch (s->float_rounding_mode) { case float_round_nearest_even: overflow_norm = false; @@ -282,6 +259,35 @@ static void partsN(uncanon)(FloatPartsN *p, float_status *s, float_raise(flags, s); } +static void partsN(uncanon)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt) +{ + if (likely(p->cls == float_class_normal)) { + parts_uncanon_normal(p, s, fmt); + } else { + switch (p->cls) { + case float_class_zero: + p->exp = 0; + frac_clear(p); + return; + case float_class_inf: + g_assert(!fmt->arm_althp); + p->exp = fmt->exp_max; + frac_clear(p); + return; + case float_class_qnan: + case float_class_snan: + g_assert(!fmt->arm_althp); + p->exp = fmt->exp_max; + frac_shr(p, fmt->frac_shift); + return; + default: + break; + } + g_assert_not_reached(); + } +} + /* * Returns the result of adding or subtracting the values of the * floating-point values `a' and `b'. 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[209.51.188.17]) by mx.google.com with ESMTPS id r5si9122204ilg.18.2021.05.07.19.28.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:28:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jzx+hLB9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfChl-0004w2-IZ for patch@linaro.org; Fri, 07 May 2021 22:28:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC88-0003Gz-6J for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:44 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:47040) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC84-0005Vp-Uf for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:43 -0400 Received: by mail-pj1-x1033.google.com with SMTP id fa21-20020a17090af0d5b0290157eb6b590fso6554012pjb.5 for ; Fri, 07 May 2021 18:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JS8tZ6x51imi92atbxTjzW0YkjZEJbOn/9U4cbpj3JE=; b=Jzx+hLB96tOM3ip4mAYtlxwCUdA5jv8aSxM/7533rNlGuuudI25kMLvmb00hmFgwMp uFrFu2Ywl6M3ZIt9y3ZqQwiFlroQyQ0HB/+5Fp/jkqIN9E5yc7ePAkhfqDohDMs4ABLn DIvjrjQEUl3XMQewrH6qOxRMo07C1vJIDKZnLcYQxe4Hc/C4Y7IAsvLUvbQZ8/oaq1op 14XbLOB4NeZYJONrL1XwCKgpgAAWIU+ixDbvBi5daBXdwLiXwnX+6X/+XOdi5fO43xd5 y9qT2rI6soW1WhuewUOtgLwpLaHzW24W6xGOSQjkU4U6uefeWimfSVB0rRyMN0hom0JK ylbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JS8tZ6x51imi92atbxTjzW0YkjZEJbOn/9U4cbpj3JE=; b=a9QvkLfjwJbgxac3KYwf/LeGQgF+sjcNNIZ+MPeN8wpeiju5BSHWP1tariZzw07PEI QT3MtfgE+9/cHlfHLP9qGm9T71huP0Wg28IEU4BSXakUKuJTetFvxxv2v9zNOPfnAa4r EJ/vGGqG1zd0sHlLx2XrDDlmfKz/McaRtgDjH6XLytMARDzwx8VxhTQPGoy7ccH173fb +zvcqZKqQYOH/a9q+MgQPhlC/psM7rUNxYtHTWufRxjViXFHg37R6/+07MmfBx3AtlQT EtzOQCK7Vx8exBylunL66eb93/iDnZ9FURlu7s8fi0pqmi7tqrtkOnV/dOzDMIdPbZq+ 1c3Q== X-Gm-Message-State: AOAM531Ww4PeVtO7cr56HVsYOwVC7eZGECtQVmsHAVsOHSBgEmiITHKe pDWeUGnaMEPN7LHzauWrTs1fFG0JtmQlWA== X-Received: by 2002:a17:90a:4588:: with SMTP id v8mr26156047pjg.195.1620438699612; Fri, 07 May 2021 18:51:39 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 55/72] softfloat: Reduce FloatFmt Date: Fri, 7 May 2021 18:47:45 -0700 Message-Id: <20210508014802.892561-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove frac_lsb, frac_lsbm1, roundeven_mask. Compute these from round_mask in parts$N_uncanon_normal. With floatx80, round_mask will not be tied to frac_shift. Everything else is easily computable. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 29 ++++++++++++----------------- fpu/softfloat-parts.c.inc | 6 +++--- 2 files changed, 15 insertions(+), 20 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4df69029ec..6a77e35663 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -562,9 +562,7 @@ typedef struct { * frac_size: the size of the fraction field * frac_shift: shift to normalise the fraction with DECOMPOSED_BINARY_POINT * The following are computed based the size of fraction - * frac_lsb: least significant bit of fraction - * frac_lsbm1: the bit below the least significant bit (for rounding) - * round_mask/roundeven_mask: masks used for rounding + * round_mask: bits below lsb which must be rounded * The following optional modifiers are available: * arm_althp: handle ARM Alternative Half Precision */ @@ -574,24 +572,21 @@ typedef struct { int exp_max; int frac_size; int frac_shift; - uint64_t frac_lsb; - uint64_t frac_lsbm1; - uint64_t round_mask; - uint64_t roundeven_mask; bool arm_althp; + uint64_t round_mask; } FloatFmt; /* Expand fields based on the size of exponent and fraction */ -#define FLOAT_PARAMS(E, F) \ - .exp_size = E, \ - .exp_bias = ((1 << E) - 1) >> 1, \ - .exp_max = (1 << E) - 1, \ - .frac_size = F, \ - .frac_shift = (-F - 1) & 63, \ - .frac_lsb = 1ull << ((-F - 1) & 63), \ - .frac_lsbm1 = 1ull << ((-F - 2) & 63), \ - .round_mask = (1ull << ((-F - 1) & 63)) - 1, \ - .roundeven_mask = (2ull << ((-F - 1) & 63)) - 1 +#define FLOAT_PARAMS_(E, F) \ + .exp_size = E, \ + .exp_bias = ((1 << E) - 1) >> 1, \ + .exp_max = (1 << E) - 1, \ + .frac_size = F + +#define FLOAT_PARAMS(E, F) \ + FLOAT_PARAMS_(E, F), \ + .frac_shift = (-F - 1) & 63, \ + .round_mask = (1ull << ((-F - 1) & 63)) - 1 static const FloatFmt float16_params = { FLOAT_PARAMS(5, 10) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 65462bf6cb..3ee6552d5a 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -145,10 +145,10 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, { const int exp_max = fmt->exp_max; const int frac_shift = fmt->frac_shift; - const uint64_t frac_lsb = fmt->frac_lsb; - const uint64_t frac_lsbm1 = fmt->frac_lsbm1; const uint64_t round_mask = fmt->round_mask; - const uint64_t roundeven_mask = fmt->roundeven_mask; + const uint64_t frac_lsb = round_mask + 1; + const uint64_t frac_lsbm1 = round_mask ^ (round_mask >> 1); + const uint64_t roundeven_mask = round_mask | frac_lsb; uint64_t inc; bool overflow_norm; int exp, flags = 0; From patchwork Sat May 8 01:47:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432589 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp869203jao; Fri, 7 May 2021 19:43:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxvCr54gasJSNE3a4sY8upq3PFUXyxXTPRuxuxpCbDIXRJ/B6zWAyjovGI0tTS2RXIhu0OA X-Received: by 2002:a92:d3c4:: with SMTP id c4mr11235559ilh.50.1620441821266; Fri, 07 May 2021 19:43:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441821; cv=none; d=google.com; s=arc-20160816; b=OUUvgRq86D245tFOAxAuMshaDvf4uNsnbyzTfhPa9hgrWbmBdQI8MMkChFnh5hwVBW K/ALzVhJelNsaIcQqvjFzvz+VDjHL0FbTelzKGz5JMYSVHTVQoEFv6OmpjXB/8UcJ1YM CvuEIIlOHlKICL1mJgejiVovBXNkecQ6hCNQ3zL6CukY+vOFNzbGm1zTjLLg9DLlcToD DmeF+CRauevVl36dviY1VIqIQEHK9ov04ThdoldomvYre9NfSZsCT0AzONuyIgOImsDB pGAo6p2+2O+uUUhQmA/gXlRH6yXNTw2LQQwVBoVxT2gVWLV3HMNFxMLFdoubj5Wrz0j6 6b1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Hiam3qpkLAIJqjlYkVn2YRf+JYbyJaD15I/9lQ8LGfg=; b=U7BW0sReM03CwT/aaO5bVPW6PCuUe1F4C9A1m+DAhnho25Fw3g4NHunBMoDKrq0ydz 5PI0PbsUB2J+PEyGKCACCb747golrmWLHBn003Zs1OUmMg+zKrlZ0tco5ja0FIl2hHNk YCshLZO6vNBX70dLxgOFadl33ElUE6zqYYR2rXl8iot344/99snpATl//UmeZ8ni9la1 lyLwMR3EQ/YR6WK3b1xmExxnSsb6N7H+xF6fu1NiSFVUuUzGzIyeGdHNEzhM5+QtBe4f yzAMjU5LUMr+lQZmpNUyit9d5mvfY26VHCHoEygsJhHQL7L6YfcvOOCyEwIi7bTVcLr/ WOxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pwF35ETW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 5 +- include/fpu/softfloat-types.h | 10 +++- include/fpu/softfloat.h | 4 +- fpu/softfloat.c | 32 ++++++------ linux-user/arm/nwfpe/fpa11.c | 41 +++++++-------- target/i386/tcg/fpu_helper.c | 79 +++++++++++++++++------------ target/m68k/fpu_helper.c | 50 +++++++++--------- target/m68k/softfloat.c | 90 ++++++++++++++++++++------------- tests/fp/fp-test.c | 5 +- 9 files changed, 182 insertions(+), 134 deletions(-) -- 2.25.1 diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 2f0674fbdd..34f4cf92ae 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -69,7 +69,7 @@ static inline void set_float_exception_flags(int val, float_status *status) status->float_exception_flags = val; } -static inline void set_floatx80_rounding_precision(int val, +static inline void set_floatx80_rounding_precision(FloatX80RoundPrec val, float_status *status) { status->floatx80_rounding_precision = val; @@ -120,7 +120,8 @@ static inline int get_float_exception_flags(float_status *status) return status->float_exception_flags; } -static inline int get_floatx80_rounding_precision(float_status *status) +static inline FloatX80RoundPrec +get_floatx80_rounding_precision(float_status *status) { return status->floatx80_rounding_precision; } diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8a3f20fae9..1f83378c20 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -152,6 +152,14 @@ enum { float_flag_output_denormal = 128 }; +/* + * Rounding precision for floatx80. + */ +typedef enum __attribute__((__packed__)) { + floatx80_precision_x, + floatx80_precision_d, + floatx80_precision_s, +} FloatX80RoundPrec; /* * Floating Point Status. Individual architectures may maintain @@ -163,7 +171,7 @@ enum { typedef struct float_status { FloatRoundMode float_rounding_mode; uint8_t float_exception_flags; - signed char floatx80_rounding_precision; + FloatX80RoundPrec floatx80_rounding_precision; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 53f2c2ea3c..94f7841b9f 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1152,7 +1152,7 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status); | Floating-Point Arithmetic. *----------------------------------------------------------------------------*/ -floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, +floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status); @@ -1165,7 +1165,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, | normalized. *----------------------------------------------------------------------------*/ -floatx80 normalizeRoundAndPackFloatx80(int8_t roundingPrecision, +floatx80 normalizeRoundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6a77e35663..441b8f9dc1 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -4344,10 +4344,10 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, | a subnormal number, and the underflow and inexact exceptions are raised if | the abstract input cannot be represented exactly as a subnormal extended | double-precision floating-point number. -| If `roundingPrecision' is 32 or 64, the result is rounded to the same -| number of bits as single or double precision, respectively. Otherwise, the -| result is rounded to the full precision of the extended double-precision -| format. +| If `roundingPrecision' is floatx80_precision_s or floatx80_precision_d, +| the result is rounded to the same number of bits as single or double +| precision, respectively. Otherwise, the result is rounded to the full +| precision of the extended double-precision format. | The input significand must be normalized or smaller. If the input | significand is not normalized, `zExp' must be 0; in that case, the result | returned is a subnormal number, and it must not require rounding. The @@ -4355,27 +4355,29 @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, | Floating-Point Arithmetic. *----------------------------------------------------------------------------*/ -floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, +floatx80 roundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status) { - int8_t roundingMode; + FloatRoundMode roundingMode; bool roundNearestEven, increment, isTiny; int64_t roundIncrement, roundMask, roundBits; roundingMode = status->float_rounding_mode; roundNearestEven = ( roundingMode == float_round_nearest_even ); - if ( roundingPrecision == 80 ) goto precision80; - if ( roundingPrecision == 64 ) { + switch (roundingPrecision) { + case floatx80_precision_x: + goto precision80; + case floatx80_precision_d: roundIncrement = UINT64_C(0x0000000000000400); roundMask = UINT64_C(0x00000000000007FF); - } - else if ( roundingPrecision == 32 ) { + break; + case floatx80_precision_s: roundIncrement = UINT64_C(0x0000008000000000); roundMask = UINT64_C(0x000000FFFFFFFFFF); - } - else { - goto precision80; + break; + default: + g_assert_not_reached(); } zSig0 |= ( zSig1 != 0 ); switch (roundingMode) { @@ -4552,7 +4554,7 @@ floatx80 roundAndPackFloatx80(int8_t roundingPrecision, bool zSign, | normalized. *----------------------------------------------------------------------------*/ -floatx80 normalizeRoundAndPackFloatx80(int8_t roundingPrecision, +floatx80 normalizeRoundAndPackFloatx80(FloatX80RoundPrec roundingPrecision, bool zSign, int32_t zExp, uint64_t zSig0, uint64_t zSig1, float_status *status) @@ -6205,7 +6207,7 @@ floatx80 floatx80_modrem(floatx80 a, floatx80 b, bool mod, uint64_t *quotient, } return normalizeRoundAndPackFloatx80( - 80, zSign, bExp + expDiff, aSig0, aSig1, status); + floatx80_precision_x, zSign, bExp + expDiff, aSig0, aSig1, status); } diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index f6f8163eab..9a93610d24 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -97,37 +97,38 @@ void SetRoundingMode(const unsigned int opcode) void SetRoundingPrecision(const unsigned int opcode) { - int rounding_precision; - FPA11 *fpa11 = GET_FPA11(); + FloatX80RoundPrec rounding_precision; + FPA11 *fpa11 = GET_FPA11(); #ifdef MAINTAIN_FPCR - fpa11->fpcr &= ~MASK_ROUNDING_PRECISION; + fpa11->fpcr &= ~MASK_ROUNDING_PRECISION; #endif - switch (opcode & MASK_ROUNDING_PRECISION) - { - case ROUND_SINGLE: - rounding_precision = 32; + switch (opcode & MASK_ROUNDING_PRECISION) { + case ROUND_SINGLE: + rounding_precision = floatx80_precision_s; #ifdef MAINTAIN_FPCR - fpa11->fpcr |= ROUND_SINGLE; + fpa11->fpcr |= ROUND_SINGLE; #endif - break; + break; - case ROUND_DOUBLE: - rounding_precision = 64; + case ROUND_DOUBLE: + rounding_precision = floatx80_precision_d; #ifdef MAINTAIN_FPCR - fpa11->fpcr |= ROUND_DOUBLE; + fpa11->fpcr |= ROUND_DOUBLE; #endif - break; + break; - case ROUND_EXTENDED: - rounding_precision = 80; + case ROUND_EXTENDED: + rounding_precision = floatx80_precision_x; #ifdef MAINTAIN_FPCR - fpa11->fpcr |= ROUND_EXTENDED; + fpa11->fpcr |= ROUND_EXTENDED; #endif - break; + break; - default: rounding_precision = 80; - } - set_floatx80_rounding_precision(rounding_precision, &fpa11->fp_status); + default: + rounding_precision = floatx80_precision_x; + break; + } + set_floatx80_rounding_precision(rounding_precision, &fpa11->fp_status); } /* Emulate the instruction in the opcode. */ diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 60ed93520a..e495ddf1aa 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -711,38 +711,40 @@ uint32_t helper_fnstcw(CPUX86State *env) void update_fp_status(CPUX86State *env) { - int rnd_type; + FloatRoundMode rnd_mode; + FloatX80RoundPrec rnd_prec; /* set rounding mode */ switch (env->fpuc & FPU_RC_MASK) { default: case FPU_RC_NEAR: - rnd_type = float_round_nearest_even; + rnd_mode = float_round_nearest_even; break; case FPU_RC_DOWN: - rnd_type = float_round_down; + rnd_mode = float_round_down; break; case FPU_RC_UP: - rnd_type = float_round_up; + rnd_mode = float_round_up; break; case FPU_RC_CHOP: - rnd_type = float_round_to_zero; + rnd_mode = float_round_to_zero; break; } - set_float_rounding_mode(rnd_type, &env->fp_status); + set_float_rounding_mode(rnd_mode, &env->fp_status); + switch ((env->fpuc >> 8) & 3) { case 0: - rnd_type = 32; + rnd_prec = floatx80_precision_s; break; case 2: - rnd_type = 64; + rnd_prec = floatx80_precision_d; break; case 3: default: - rnd_type = 80; + rnd_prec = floatx80_precision_x; break; } - set_floatx80_rounding_precision(rnd_type, &env->fp_status); + set_floatx80_rounding_precision(rnd_prec, &env->fp_status); } void helper_fldcw(CPUX86State *env, uint32_t val) @@ -1112,7 +1114,8 @@ void helper_f2xm1(CPUX86State *env) &sig2); /* This result is inexact. */ sig1 |= 1; - ST0 = normalizeRoundAndPackFloatx80(80, sign, exp, sig0, sig1, + ST0 = normalizeRoundAndPackFloatx80(floatx80_precision_x, + sign, exp, sig0, sig1, &env->fp_status); } } else { @@ -1121,9 +1124,10 @@ void helper_f2xm1(CPUX86State *env) int32_t n, aexp, bexp; uint64_t asig0, asig1, asig2, bsig0, bsig1; FloatRoundMode save_mode = env->fp_status.float_rounding_mode; - signed char save_prec = env->fp_status.floatx80_rounding_precision; + FloatX80RoundPrec save_prec = + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode = float_round_nearest_even; - env->fp_status.floatx80_rounding_precision = 80; + env->fp_status.floatx80_rounding_precision = floatx80_precision_x; /* Find the nearest multiple of 1/32 to the argument. */ tmp = floatx80_scalbn(ST0, 5, &env->fp_status); @@ -1221,7 +1225,8 @@ void helper_f2xm1(CPUX86State *env) env->fp_status.float_rounding_mode = save_mode; /* This result is inexact. */ asig1 |= 1; - ST0 = normalizeRoundAndPackFloatx80(80, asign, aexp, asig0, asig1, + ST0 = normalizeRoundAndPackFloatx80(floatx80_precision_x, + asign, aexp, asig0, asig1, &env->fp_status); } @@ -1339,8 +1344,9 @@ void helper_fpatan(CPUX86State *env) * division is exact, the result of fpatan is still inexact * (and underflowing where appropriate). */ - signed char save_prec = env->fp_status.floatx80_rounding_precision; - env->fp_status.floatx80_rounding_precision = 80; + FloatX80RoundPrec save_prec = + env->fp_status.floatx80_rounding_precision; + env->fp_status.floatx80_rounding_precision = floatx80_precision_x; ST1 = floatx80_div(ST1, ST0, &env->fp_status); env->fp_status.floatx80_rounding_precision = save_prec; if (!floatx80_is_zero(ST1) && @@ -1359,7 +1365,8 @@ void helper_fpatan(CPUX86State *env) if (exp == 0) { normalizeFloatx80Subnormal(sig, &exp, &sig); } - ST1 = normalizeRoundAndPackFloatx80(80, sign, exp, sig - 1, + ST1 = normalizeRoundAndPackFloatx80(floatx80_precision_x, + sign, exp, sig - 1, -1, &env->fp_status); } } else { @@ -1415,9 +1422,10 @@ void helper_fpatan(CPUX86State *env) uint64_t azsig2, azsig3, axsig0, axsig1; floatx80 x8; FloatRoundMode save_mode = env->fp_status.float_rounding_mode; - signed char save_prec = env->fp_status.floatx80_rounding_precision; + FloatX80RoundPrec save_prec = + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode = float_round_nearest_even; - env->fp_status.floatx80_rounding_precision = 80; + env->fp_status.floatx80_rounding_precision = floatx80_precision_x; if (arg0_exp == 0) { normalizeFloatx80Subnormal(arg0_sig, &arg0_exp, &arg0_sig); @@ -1486,7 +1494,8 @@ void helper_fpatan(CPUX86State *env) * Split x as x = t + y, where t = n/8 is the nearest * multiple of 1/8 to x. */ - x8 = normalizeRoundAndPackFloatx80(80, false, xexp + 3, xsig0, + x8 = normalizeRoundAndPackFloatx80(floatx80_precision_x, + false, xexp + 3, xsig0, xsig1, &env->fp_status); n = floatx80_to_int32(x8, &env->fp_status); if (n == 0) { @@ -1607,7 +1616,7 @@ void helper_fpatan(CPUX86State *env) /* Compute z^2. */ mul128To256(zsig0, zsig1, zsig0, zsig1, &z2sig0, &z2sig1, &z2sig2, &z2sig3); - z2 = normalizeRoundAndPackFloatx80(80, false, + z2 = normalizeRoundAndPackFloatx80(floatx80_precision_x, false, zexp + zexp - 0x3ffe, z2sig0, z2sig1, &env->fp_status); @@ -1727,7 +1736,7 @@ void helper_fpatan(CPUX86State *env) } /* This result is inexact. */ rsig1 |= 1; - ST1 = normalizeRoundAndPackFloatx80(80, rsign, rexp, + ST1 = normalizeRoundAndPackFloatx80(floatx80_precision_x, rsign, rexp, rsig0, rsig1, &env->fp_status); } @@ -1928,7 +1937,8 @@ static void helper_fyl2x_common(CPUX86State *env, floatx80 arg, int32_t *exp, */ mul128To256(tsig0, tsig1, tsig0, tsig1, &t2sig0, &t2sig1, &t2sig2, &t2sig3); - t2 = normalizeRoundAndPackFloatx80(80, false, texp + texp - 0x3ffe, + t2 = normalizeRoundAndPackFloatx80(floatx80_precision_x, false, + texp + texp - 0x3ffe, t2sig0, t2sig1, &env->fp_status); /* Compute the lower parts of the polynomial expansion. */ @@ -2042,15 +2052,17 @@ void helper_fyl2xp1(CPUX86State *env) exp += arg1_exp - 0x3ffe; /* This result is inexact. */ sig1 |= 1; - ST1 = normalizeRoundAndPackFloatx80(80, arg0_sign ^ arg1_sign, exp, + ST1 = normalizeRoundAndPackFloatx80(floatx80_precision_x, + arg0_sign ^ arg1_sign, exp, sig0, sig1, &env->fp_status); } else { int32_t aexp; uint64_t asig0, asig1, asig2; FloatRoundMode save_mode = env->fp_status.float_rounding_mode; - signed char save_prec = env->fp_status.floatx80_rounding_precision; + FloatX80RoundPrec save_prec = + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode = float_round_nearest_even; - env->fp_status.floatx80_rounding_precision = 80; + env->fp_status.floatx80_rounding_precision = floatx80_precision_x; helper_fyl2x_common(env, ST0, &aexp, &asig0, &asig1); /* @@ -2065,7 +2077,8 @@ void helper_fyl2xp1(CPUX86State *env) /* This result is inexact. */ asig1 |= 1; env->fp_status.float_rounding_mode = save_mode; - ST1 = normalizeRoundAndPackFloatx80(80, arg0_sign ^ arg1_sign, aexp, + ST1 = normalizeRoundAndPackFloatx80(floatx80_precision_x, + arg0_sign ^ arg1_sign, aexp, asig0, asig1, &env->fp_status); env->fp_status.floatx80_rounding_precision = save_prec; } @@ -2149,9 +2162,10 @@ void helper_fyl2x(CPUX86State *env) int32_t int_exp; floatx80 arg0_m1; FloatRoundMode save_mode = env->fp_status.float_rounding_mode; - signed char save_prec = env->fp_status.floatx80_rounding_precision; + FloatX80RoundPrec save_prec = + env->fp_status.floatx80_rounding_precision; env->fp_status.float_rounding_mode = float_round_nearest_even; - env->fp_status.floatx80_rounding_precision = 80; + env->fp_status.floatx80_rounding_precision = floatx80_precision_x; if (arg0_exp == 0) { normalizeFloatx80Subnormal(arg0_sig, &arg0_exp, &arg0_sig); @@ -2208,7 +2222,8 @@ void helper_fyl2x(CPUX86State *env) /* This result is inexact. */ asig1 |= 1; env->fp_status.float_rounding_mode = save_mode; - ST1 = normalizeRoundAndPackFloatx80(80, asign ^ arg1_sign, aexp, + ST1 = normalizeRoundAndPackFloatx80(floatx80_precision_x, + asign ^ arg1_sign, aexp, asig0, asig1, &env->fp_status); } @@ -2290,12 +2305,12 @@ void helper_fscale(CPUX86State *env) } } else { int n; - signed char save = env->fp_status.floatx80_rounding_precision; + FloatX80RoundPrec save = env->fp_status.floatx80_rounding_precision; uint8_t save_flags = get_float_exception_flags(&env->fp_status); set_float_exception_flags(0, &env->fp_status); n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status); set_float_exception_flags(save_flags, &env->fp_status); - env->fp_status.floatx80_rounding_precision = 80; + env->fp_status.floatx80_rounding_precision = floatx80_precision_x; ST0 = floatx80_scalbn(ST0, n, &env->fp_status); env->fp_status.floatx80_rounding_precision = save; } diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 797000e748..fdc4937e29 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -94,13 +94,13 @@ static void m68k_restore_precision_mode(CPUM68KState *env) { switch (env->fpcr & FPCR_PREC_MASK) { case FPCR_PREC_X: /* extended */ - set_floatx80_rounding_precision(80, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_x, &env->fp_status); break; case FPCR_PREC_S: /* single */ - set_floatx80_rounding_precision(32, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_s, &env->fp_status); break; case FPCR_PREC_D: /* double */ - set_floatx80_rounding_precision(64, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_d, &env->fp_status); break; case FPCR_PREC_U: /* undefined */ default: @@ -111,9 +111,9 @@ static void m68k_restore_precision_mode(CPUM68KState *env) static void cf_restore_precision_mode(CPUM68KState *env) { if (env->fpcr & FPCR_PREC_S) { /* single */ - set_floatx80_rounding_precision(32, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_s, &env->fp_status); } else { /* double */ - set_floatx80_rounding_precision(64, &env->fp_status); + set_floatx80_rounding_precision(floatx80_precision_d, &env->fp_status); } } @@ -166,8 +166,8 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val) #define PREC_BEGIN(prec) \ do { \ - int old; \ - old = get_floatx80_rounding_precision(&env->fp_status); \ + FloatX80RoundPrec old = \ + get_floatx80_rounding_precision(&env->fp_status); \ set_floatx80_rounding_precision(prec, &env->fp_status) \ #define PREC_END() \ @@ -176,14 +176,14 @@ void HELPER(set_fpcr)(CPUM68KState *env, uint32_t val) void HELPER(fsround)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_round(val->d, &env->fp_status); PREC_END(); } void HELPER(fdround)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_round(val->d, &env->fp_status); PREC_END(); } @@ -195,14 +195,14 @@ void HELPER(fsqrt)(CPUM68KState *env, FPReg *res, FPReg *val) void HELPER(fssqrt)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_sqrt(val->d, &env->fp_status); PREC_END(); } void HELPER(fdsqrt)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_sqrt(val->d, &env->fp_status); PREC_END(); } @@ -214,14 +214,14 @@ void HELPER(fabs)(CPUM68KState *env, FPReg *res, FPReg *val) void HELPER(fsabs)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_round(floatx80_abs(val->d), &env->fp_status); PREC_END(); } void HELPER(fdabs)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_round(floatx80_abs(val->d), &env->fp_status); PREC_END(); } @@ -233,14 +233,14 @@ void HELPER(fneg)(CPUM68KState *env, FPReg *res, FPReg *val) void HELPER(fsneg)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_round(floatx80_chs(val->d), &env->fp_status); PREC_END(); } void HELPER(fdneg)(CPUM68KState *env, FPReg *res, FPReg *val) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_round(floatx80_chs(val->d), &env->fp_status); PREC_END(); } @@ -252,14 +252,14 @@ void HELPER(fadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) void HELPER(fsadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_add(val0->d, val1->d, &env->fp_status); PREC_END(); } void HELPER(fdadd)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_add(val0->d, val1->d, &env->fp_status); PREC_END(); } @@ -271,14 +271,14 @@ void HELPER(fsub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) void HELPER(fssub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_sub(val1->d, val0->d, &env->fp_status); PREC_END(); } void HELPER(fdsub)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_sub(val1->d, val0->d, &env->fp_status); PREC_END(); } @@ -290,14 +290,14 @@ void HELPER(fmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) void HELPER(fsmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_mul(val0->d, val1->d, &env->fp_status); PREC_END(); } void HELPER(fdmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_mul(val0->d, val1->d, &env->fp_status); PREC_END(); } @@ -307,7 +307,7 @@ void HELPER(fsglmul)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) FloatRoundMode rounding_mode = get_float_rounding_mode(&env->fp_status); floatx80 a, b; - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); set_float_rounding_mode(float_round_to_zero, &env->fp_status); a = floatx80_round(val0->d, &env->fp_status); b = floatx80_round(val1->d, &env->fp_status); @@ -323,14 +323,14 @@ void HELPER(fdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) void HELPER(fsdiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); res->d = floatx80_div(val1->d, val0->d, &env->fp_status); PREC_END(); } void HELPER(fddiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) { - PREC_BEGIN(64); + PREC_BEGIN(floatx80_precision_d); res->d = floatx80_div(val1->d, val0->d, &env->fp_status); PREC_END(); } @@ -340,7 +340,7 @@ void HELPER(fsgldiv)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) FloatRoundMode rounding_mode = get_float_rounding_mode(&env->fp_status); floatx80 a, b; - PREC_BEGIN(32); + PREC_BEGIN(floatx80_precision_s); set_float_rounding_mode(float_round_to_zero, &env->fp_status); a = floatx80_round(val1->d, &env->fp_status); b = floatx80_round(val0->d, &env->fp_status); diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index b6d0ed7acf..02dcc03d15 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -227,7 +227,8 @@ floatx80 floatx80_lognp1(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig, fSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, j, k; floatx80 fp0, fp1, fp2, fp3, f, logof2, klog2, saveu; @@ -270,7 +271,7 @@ floatx80 floatx80_lognp1(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); @@ -426,7 +427,8 @@ floatx80 floatx80_logn(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig, fSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, j, k, adjk; floatx80 fp0, fp1, fp2, fp3, f, logof2, klog2, saveu; @@ -469,7 +471,7 @@ floatx80 floatx80_logn(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); @@ -594,7 +596,8 @@ floatx80 floatx80_log10(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; floatx80 fp0, fp1; @@ -626,7 +629,7 @@ floatx80 floatx80_log10(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; fp0 = floatx80_logn(a, status); fp1 = packFloatx80(0, 0x3FFD, UINT64_C(0xDE5BD8A937287195)); /* INV_L10 */ @@ -651,7 +654,8 @@ floatx80 floatx80_log2(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; floatx80 fp0, fp1; @@ -686,7 +690,7 @@ floatx80 floatx80_log2(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; if (aSig == one_sig) { /* X is 2^k */ status->float_rounding_mode = user_rnd_mode; @@ -718,7 +722,8 @@ floatx80 floatx80_etox(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, n, j, k, m, m1; floatx80 fp0, fp1, fp2, fp3, l2, scale, adjscale; @@ -746,7 +751,7 @@ floatx80 floatx80_etox(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; adjflag = 0; @@ -902,7 +907,8 @@ floatx80 floatx80_twotox(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, n, j, l, m, m1; floatx80 fp0, fp1, fp2, fp3, adjfact, fact1, fact2; @@ -929,7 +935,7 @@ floatx80 floatx80_twotox(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; fp0 = a; @@ -1052,7 +1058,8 @@ floatx80 floatx80_tentox(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, n, j, l, m, m1; floatx80 fp0, fp1, fp2, fp3, adjfact, fact1, fact2; @@ -1079,7 +1086,7 @@ floatx80 floatx80_tentox(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; fp0 = a; @@ -1207,7 +1214,8 @@ floatx80 floatx80_tan(floatx80 a, float_status *status) int32_t aExp, xExp; uint64_t aSig, xSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, l, n, j; floatx80 fp0, fp1, fp2, fp3, fp4, fp5, invtwopi, twopi1, twopi2; @@ -1233,7 +1241,7 @@ floatx80 floatx80_tan(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); @@ -1417,7 +1425,8 @@ floatx80 floatx80_sin(floatx80 a, float_status *status) int32_t aExp, xExp; uint64_t aSig, xSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, l, n, j; floatx80 fp0, fp1, fp2, fp3, fp4, fp5, x, invtwopi, twopi1, twopi2; @@ -1443,7 +1452,7 @@ floatx80 floatx80_sin(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); @@ -1656,7 +1665,8 @@ floatx80 floatx80_cos(floatx80 a, float_status *status) int32_t aExp, xExp; uint64_t aSig, xSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, l, n, j; floatx80 fp0, fp1, fp2, fp3, fp4, fp5, x, invtwopi, twopi1, twopi2; @@ -1682,7 +1692,7 @@ floatx80 floatx80_cos(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); @@ -1893,7 +1903,8 @@ floatx80 floatx80_atan(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, tbl_index; floatx80 fp0, fp1, fp2, fp3, xsave; @@ -1920,7 +1931,7 @@ floatx80 floatx80_atan(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; if (compact < 0x3FFB8000 || compact > 0x4002FFFF) { /* |X| >= 16 or |X| < 1/16 */ @@ -2090,7 +2101,8 @@ floatx80 floatx80_asin(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact; floatx80 fp0, fp1, fp2, one; @@ -2124,7 +2136,7 @@ floatx80 floatx80_asin(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; one = packFloatx80(0, one_exp, one_sig); fp0 = a; @@ -2155,7 +2167,8 @@ floatx80 floatx80_acos(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact; floatx80 fp0, fp1, one; @@ -2193,7 +2206,7 @@ floatx80 floatx80_acos(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; one = packFloatx80(0, one_exp, one_sig); fp0 = a; @@ -2224,7 +2237,8 @@ floatx80 floatx80_atanh(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact; floatx80 fp0, fp1, fp2, one; @@ -2257,7 +2271,7 @@ floatx80 floatx80_atanh(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; one = packFloatx80(0, one_exp, one_sig); fp2 = packFloatx80(aSign, 0x3FFE, one_sig); /* SIGN(X) * (1/2) */ @@ -2289,7 +2303,8 @@ floatx80 floatx80_etoxm1(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact, n, j, m, m1; floatx80 fp0, fp1, fp2, fp3, l2, sc, onebysc; @@ -2316,7 +2331,7 @@ floatx80 floatx80_etoxm1(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; if (aExp >= 0x3FFD) { /* |X| >= 1/4 */ compact = floatx80_make_compact(aExp, aSig); @@ -2541,7 +2556,8 @@ floatx80 floatx80_tanh(floatx80 a, float_status *status) int32_t aExp, vExp; uint64_t aSig, vSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact; floatx80 fp0, fp1; @@ -2565,7 +2581,7 @@ floatx80 floatx80_tanh(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); @@ -2656,7 +2672,8 @@ floatx80 floatx80_sinh(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact; floatx80 fp0, fp1, fp2; @@ -2681,7 +2698,7 @@ floatx80 floatx80_sinh(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); @@ -2744,7 +2761,8 @@ floatx80 floatx80_cosh(floatx80 a, float_status *status) int32_t aExp; uint64_t aSig; - int8_t user_rnd_mode, user_rnd_prec; + FloatRoundMode user_rnd_mode; + FloatX80RoundPrec user_rnd_prec; int32_t compact; floatx80 fp0, fp1; @@ -2767,7 +2785,7 @@ floatx80 floatx80_cosh(floatx80 a, float_status *status) user_rnd_mode = status->float_rounding_mode; user_rnd_prec = status->floatx80_rounding_precision; status->float_rounding_mode = float_round_nearest_even; - status->floatx80_rounding_precision = 80; + status->floatx80_rounding_precision = floatx80_precision_x; compact = floatx80_make_compact(aExp, aSig); diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index ff131afbde..1be3a9788a 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -963,18 +963,21 @@ static void QEMU_NORETURN run_test(void) verCases_usesExact = !!(attrs & FUNC_ARG_EXACT); for (k = 0; k < 3; k++) { + FloatX80RoundPrec qsf_prec80 = floatx80_precision_s; int prec80 = 32; int l; if (k == 1) { prec80 = 64; + qsf_prec80 = floatx80_precision_d; } else if (k == 2) { prec80 = 80; + qsf_prec80 = floatx80_precision_x; } verCases_roundingPrecision = 0; slow_extF80_roundingPrecision = prec80; - qsf.floatx80_rounding_precision = prec80; + qsf.floatx80_rounding_precision = qsf_prec80; if (attrs & FUNC_EFF_ROUNDINGPRECISION) { verCases_roundingPrecision = prec80; From patchwork Sat May 8 01:47:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432583 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp867004jao; 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[209.51.188.17]) by mx.google.com with ESMTPS id k13si9398986jav.44.2021.05.07.19.39.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:39:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MLzGjO4a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCsL-0008Gr-GE for patch@linaro.org; Fri, 07 May 2021 22:39:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC8F-0003U6-N6 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:52 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:37557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC86-0005WB-Bp for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:51 -0400 Received: by mail-pf1-x431.google.com with SMTP id b15so9156311pfl.4 for ; Fri, 07 May 2021 18:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LZ3EVpA+stFdeEBoSATKDS13Onp/VeKXwMPd01vcHvM=; b=MLzGjO4a0NXTWKyzbgVeKknWmmPhCJ5AnX4t979Rdmtlf74ekRu8shyfCi9IGu2wqK 9coqGBUCa9/fpwBV1yvbbNaFdNhqskGsMR6fmgyLMvMpEvb/ic/j2JXsAvN2rhvAd+2/ +UlIbNzJwbuMbJB3c7haMLAiBGQB2qD9olF8lH2dIBq4/Mjc8gghK4jG0/bL/f3LuElb jRj/QyGJlvoHAcNHSOmi/9aV6bbpWGyzn2/3xd7bav2l0nBg9WnNVOclNn4ii2eOspoX N8OwoTklzK4ZL5f9EO3FMazQh0mjC2H9dTOeaaQjF480nQHpkq3bwvLYnyAUP+usGfxg /qBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LZ3EVpA+stFdeEBoSATKDS13Onp/VeKXwMPd01vcHvM=; b=jvLGCpPYY0LQgF4nl+H5NCYEC0jNzMne0OCGry3oEbkAa1zzV8Q6yALr4daf2H9VCs mJYvVDQniYR13MYXl9hPuTrEvJjqSIdiXZEcsRra+nj96Jg6C3JKwtYbZy7dmAmrObzy twyV7kgQKfMMPLcerCm/3dJLDescb5ikjwpAW00IygyCkdF5IxJF1D5vrf7vuvshAb+u f9iIMjs8qov4siZQGcTbvzRZ5CNYhnBO6lP/Q20/m8qEB8WxjvmPnSoY7kVQTwhtxVrJ RMyjD8W/YPYJT3WFOPDsUHE+DicgCBRDcrMZmi/ed55Kwi0jgnVhhYQyaGeesT2zSzx2 OC4A== X-Gm-Message-State: AOAM531fUptlNiHJ4RLZ76UB3OKaUYXZtwlGCsVMh6ai5in9/KoirycF nRs17D/hwxjYxyR0w3M1OzUBv8zZCvI32A== X-Received: by 2002:a63:2115:: with SMTP id h21mr13288716pgh.191.1620438701044; Fri, 07 May 2021 18:51:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 57/72] softfloat: Adjust parts_uncanon_normal for floatx80 Date: Fri, 7 May 2021 18:47:47 -0700 Message-Id: <20210508014802.892561-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With floatx80_precision_x, the rounding happens across the break between words. Notice this case with frac_lsb = round_mask + 1 -> 0 and check the bits in frac_hi as needed. In addition, since frac_shift == 0, we won't implicitly clear round_mask via the right-shift, so explicitly clear those bits. This fixes rounding for floatx80_precision_[sd]. Signed-off-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3ee6552d5a..c18f77f2cf 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -156,7 +156,13 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, switch (s->float_rounding_mode) { case float_round_nearest_even: overflow_norm = false; - inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0); + if (N > 64 && frac_lsb == 0) { + inc = ((p->frac_hi & 1) || (p->frac_lo & round_mask) != frac_lsbm1 + ? frac_lsbm1 : 0); + } else { + inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 + ? frac_lsbm1 : 0); + } break; case float_round_ties_away: overflow_norm = false; @@ -176,7 +182,11 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, break; case float_round_to_odd: overflow_norm = true; - inc = p->frac_lo & frac_lsb ? 0 : round_mask; + if (N > 64 && frac_lsb == 0) { + inc = p->frac_hi & 1 ? 0 : round_mask; + } else { + inc = p->frac_lo & frac_lsb ? 0 : round_mask; + } break; default: g_assert_not_reached(); @@ -191,8 +201,8 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, p->frac_hi |= DECOMPOSED_IMPLICIT_BIT; exp++; } + p->frac_lo &= ~round_mask; } - frac_shr(p, frac_shift); if (fmt->arm_althp) { /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ @@ -201,18 +211,21 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, flags = float_flag_invalid; exp = exp_max; frac_allones(p); + p->frac_lo &= ~round_mask; } } else if (unlikely(exp >= exp_max)) { flags |= float_flag_overflow | float_flag_inexact; if (overflow_norm) { exp = exp_max - 1; frac_allones(p); + p->frac_lo &= ~round_mask; } else { p->cls = float_class_inf; exp = exp_max; frac_clear(p); } } + frac_shr(p, frac_shift); } else if (s->flush_to_zero) { flags |= float_flag_output_denormal; p->cls = float_class_zero; @@ -232,17 +245,28 @@ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, /* Need to recompute round-to-even/round-to-odd. */ switch (s->float_rounding_mode) { case float_round_nearest_even: - inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 - ? frac_lsbm1 : 0); + if (N > 64 && frac_lsb == 0) { + inc = ((p->frac_hi & 1) || + (p->frac_lo & round_mask) != frac_lsbm1 + ? frac_lsbm1 : 0); + } else { + inc = ((p->frac_lo & roundeven_mask) != frac_lsbm1 + ? frac_lsbm1 : 0); + } break; case float_round_to_odd: - inc = p->frac_lo & frac_lsb ? 0 : round_mask; + if (N > 64 && frac_lsb == 0) { + inc = p->frac_hi & 1 ? 0 : round_mask; + } else { + inc = p->frac_lo & frac_lsb ? 0 : round_mask; + } break; default: break; } flags |= float_flag_inexact; frac_addi(p, p, inc); + p->frac_lo &= ~round_mask; } exp = (p->frac_hi & DECOMPOSED_IMPLICIT_BIT) != 0; From patchwork Sat May 8 01:47:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432579 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp865188jao; Fri, 7 May 2021 19:35:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyI6d3zG9T7SdJNimpuqSw7hQBAttf2auQbu+P6ZK07YEuCoT26fd8bv5YoJrDjpL00z9dM X-Received: by 2002:a6b:cb03:: with SMTP id b3mr9976699iog.33.1620441357767; Fri, 07 May 2021 19:35:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441357; cv=none; d=google.com; s=arc-20160816; b=pwqnG9MUvHtlYsjXNGj4Saw9oGEWiqbEdFxnaMd1JK0IcGGlucf0WkPxyaSoGtBZHJ 9DwavczM75htZqHj5YEiomNF6Q2mvLSodZwrkyRizD+xMZBvpz4cojM+/SgfhVmdqtEx m+WfPoRrabaHzavjDa+gof922DWWD9X7dstXFDxJ1uB9bhl5GNQX50d1kYERFGT3K7zh Rm57MDcbTwVPS+VWF6s7XWNZGnZUQ8Fw0gLoVZf67w5PzOd2A0+fBt7N5y7oOEJn9tDN hSkE/iJ2ydsebUzg/hVFFzRqB+9dJc8eDsWj8CQsl8zq7M/M62uUbUPZbXLYy93hw59Y mjyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6KUP9zZZiYCu3ns+jhQ4RQON8DkfJ2QZjQiuE1cSrWY=; b=e+5oFwpvvgHpRmcTYmyJOoqjZ5UyCxdZke7OuK9GhUnLUmCMOKkbgb80IEQItM11yI 3xfKCd0FSRXsMXFw09Z5jU5CJ7vF9ve3aLV8Jc15fGB3BqMyLs4w6O7JNnoGO9M3Um4b obKIxDUftOnlcp9ZWUzP7YnsY2up8zYOxxrQJ4oyG320zQYwOEDb5IP3C64Ixaz4v/O3 fa5h+DuGKyD862N3lw6w3VEGF8TYew8DbjQR0klFpeNIu72UftBJxV/ORXK5YPPkix8J 3SBo+Rd3WkX1nhBqdGaTFgQzRZ2bi7q96peawKYd4mWxQpB/hJq1ekqiPv6wvAQcPYaM BGtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ss4xeaF+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y18si7991345jak.36.2021.05.07.19.35.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:35:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ss4xeaF+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCov-0000W6-8f for patch@linaro.org; Fri, 07 May 2021 22:35:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC89-0003KS-2u for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:45 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:33468) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC86-0005Wf-Rj for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:44 -0400 Received: by mail-pf1-x42c.google.com with SMTP id h11so9339716pfn.0 for ; Fri, 07 May 2021 18:51:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6KUP9zZZiYCu3ns+jhQ4RQON8DkfJ2QZjQiuE1cSrWY=; b=Ss4xeaF+/BGl3rm5UvEvcjgRmwCJyZNvOEJeVazMVFKlny2Z36qgv9DClMvt34Qnkc panLzq7/upMJGTNNaBn4F9B2WwR6NfW8jIIDX9215HdHDxHO+p1zH+zLHQGbg070CP5F MZguCGlZ6lpN2OJsGdNtO6jkCrsyI1/DRT1zh8Q3ldyfDStmcqHPX1AI9VT15kx33NkV VLMzd9MkLcolCxYWzYuvxVPsDAzDHAe+gcGn6HkN6eVHweuhqekXjdBTZAXbq1liJcEg Uc6OvYpgaIoTbwYDl3JuM1E8VvSbCMCGUKVHYpbkzJLBapIHMWcw9ukt/na0K2o8iYUw Wv6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6KUP9zZZiYCu3ns+jhQ4RQON8DkfJ2QZjQiuE1cSrWY=; b=rk38BzWwPTlLS/+d4xA9XwVLz/KSd55pXoJ90vxwkmbS90sJbTx9wNVWYUtUyXVNB0 xfUK6CW6mcZRAay+rF0S5ytMlnIIK4Duwot1T2WZKeZ5sCvIu7dLWuOpg5RTQ4yyElLd JNuDoDWX6OkeZOncoErJWCHrLD73akZkkmv0SlZXsECPrCLuAI/YYRfFd+C4QcFqw2sB /VXHf9jdCi73ief3v1X5LphcxqT1cFvRpxDsA4uEirFReVNm/+PW7qrFWfbgjMwUD39m HpF+i1Oc35fCAdOhd9w/LKHYPo7DXgD0G/CvOiwkTk/1v38BZQ4PSCjb6SeesTYP01vA Z6vQ== X-Gm-Message-State: AOAM533k8xaRa8TAFkNmoXCuY95E6IkldMsxG9IAOeU3IpfEQfOLH8e7 ATk695jGR26H0KgtoMjtTcZSko23AsCBIw== X-Received: by 2002:a63:bf0d:: with SMTP id v13mr5160532pgf.303.1620438701644; Fri, 07 May 2021 18:51:41 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 58/72] tests/fp/fp-test: Reverse order of floatx80 precision tests Date: Fri, 7 May 2021 18:47:48 -0700 Message-Id: <20210508014802.892561-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Many qemu softfloat will check floatx80_rounding_precision even when berkeley testfloat will not. So begin with floatx80_precision_x, so that's the one we use when !FUNC_EFF_ROUNDINGPRECISION. Signed-off-by: Richard Henderson --- tests/fp/fp-test.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 1be3a9788a..352dd71c44 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -963,16 +963,16 @@ static void QEMU_NORETURN run_test(void) verCases_usesExact = !!(attrs & FUNC_ARG_EXACT); for (k = 0; k < 3; k++) { - FloatX80RoundPrec qsf_prec80 = floatx80_precision_s; - int prec80 = 32; + FloatX80RoundPrec qsf_prec80 = floatx80_precision_x; + int prec80 = 80; int l; if (k == 1) { prec80 = 64; qsf_prec80 = floatx80_precision_d; } else if (k == 2) { - prec80 = 80; - qsf_prec80 = floatx80_precision_x; + prec80 = 32; + qsf_prec80 = floatx80_precision_s; } verCases_roundingPrecision = 0; From patchwork Sat May 8 01:47:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432587 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp868828jao; Fri, 7 May 2021 19:43:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyOmhuIyxvjuxW72Gq+wdx0F4VwuTLlfcmXDvA0gO9jW+xqul7faeruFCeubcI+vbAV/By6 X-Received: by 2002:a05:6e02:eac:: with SMTP id u12mr12351781ilj.177.1620441786283; Fri, 07 May 2021 19:43:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441786; cv=none; d=google.com; s=arc-20160816; b=X59kmTUcpKjmuUGmcMIs7f1vabTLzcjhx9ASFzLu8hqXS5vUvUuuaAfLpF/zQCJstA /TMlsRurDAADvhid0kg+znxOYwLdc5ggBPMvOixTbbC6vn7vefMNniSsF51mLJbo/LiI ii3KJkfQw5eRXUaFNqH3CrNPU7jMD/yLN+VzAGzyXjNlU5rA6xJHLqJUXkSyEgJ+KM8I aQj0nQTCSP7vZWqEpmKEwvhOIXBlXH8JeZpeHAmkB6r7ejIiwFk2IqfUGDVhyqEeS77C rkBRlqAuqfpmnLHnufhDjD87Xk66ORrH2bXwtptXgKqHI7GEO4+pzTThKsvyngsPpuss /Ikg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WgYCwPvh5My93odn7SHxHn9PhuRLyEzfRYFAgcYen7A=; b=yaR5foZbkKTqJA+bID80JwEEHD82K9qR2v6GY0kA/BoKOpICFZGluCVBy8+CqpTmib 1ldgnIak+G3JdkgCmAGQ+twSG29FcZKYIp7MltGS5eOYToft+O7p8R6CZV0NU0Wychv6 YwHUEe5So7VMDgm4DYF2MrIAsHB2kgVFJyf/PwFwQrwiqB9JW0PE0VQThmX+QEv+MKEE ydi333yzr7nIjcMMl3mQx0CldcQaExqwOzdcfuq7N+pGyYX4U35Xxpves6SOUFzCq1x0 FPlKocGhZ+CD6akQQqkR3Qtac0PlMbdRJCa0VXWYX4Xiqx/Vb1Oky5YdwnWa3/6Cfi7+ HtKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jXechgJw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s9si7927541ioa.96.2021.05.07.19.43.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:43:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jXechgJw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCvp-0005QF-MP for patch@linaro.org; Fri, 07 May 2021 22:43:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC8H-0003V2-Hl for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:54 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:39563) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC87-0005XX-Kc for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:53 -0400 Received: by mail-pl1-x62c.google.com with SMTP id t4so6147284plc.6 for ; Fri, 07 May 2021 18:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WgYCwPvh5My93odn7SHxHn9PhuRLyEzfRYFAgcYen7A=; b=jXechgJwtehhJeIZED74Mozp6a0EamovWsC8DS9Pmhis8Hfw0+kGbSdMhTVZe6jgQ6 +v2KedTdHuA1hxEAQPtiic8bLJ25yTOtk5m+f4Epjf7NVzKaMfOzvRBQqEuMD23DpsB1 08NzDqBybEoQ0+kg72MSOJA97Lm4OOI3dKahWszpfYn3jEzymiI+uf7E4zD6yyB1kJiG +ayQ8OSSmg+aohZEEQ8dtsVlEW7SayLC98Iyd4ZMPNwswn95g/hiL5eaNqB7NUKb98Za JiHsVEx7HWfY2XK4d5nl7XoDz+QcrMcizQCtcYyD7m18GKBTZ9EfiQMZ2ADA+OlrraUb CNvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WgYCwPvh5My93odn7SHxHn9PhuRLyEzfRYFAgcYen7A=; b=sr7Jq8xbywcXnxj0kvvIqDGE1UMnEpDyaSZMuA8jJFs3r3wvpfOplCzN2vevKIqx/1 oxIBGWdnDoIGpTxaBYeB60DHyxhiewfEZgL6eVYRPNwrACpS3sJYMu/eKtTcIMyfdElm U+qCAv3oxAe+fbihYA82EUxNrUZApNzujWIlqioadfhGAUY0vR1UkoOVYt9xLQWVjnC2 +TfxQqCpzh+HuG5Jes8dFvRK5wBkYqgexCw340HpvZXBHrATNSrS92UQDIQX6Ez+JJMk kpAPfgPelWnsOd79D7gkUrDarexpUeyVZLY7IKsYO4EzVrhLsQp4PTcak8XT2GF7TvAY ME2A== X-Gm-Message-State: AOAM531KXfT5+4FiGcA1U9p8u9ZJBY2swmZcu7+fkf08T+jJDbxbS7mj bRi76IKH/unoYGHrH4ppRBJJW6ILBbkhMg== X-Received: by 2002:a17:90a:1382:: with SMTP id i2mr26470687pja.83.1620438702294; Fri, 07 May 2021 18:51:42 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 59/72] softfloat: Convert floatx80_add/sub to FloatParts Date: Fri, 7 May 2021 18:47:49 -0700 Message-Id: <20210508014802.892561-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since this is the first such, this includes all of the packing and unpacking routines as well. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 339 +++++++++++++++++++----------------------------- 1 file changed, 136 insertions(+), 203 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 441b8f9dc1..3c6751e4d0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -577,14 +577,14 @@ typedef struct { } FloatFmt; /* Expand fields based on the size of exponent and fraction */ -#define FLOAT_PARAMS_(E, F) \ +#define FLOAT_PARAMS_(E) \ .exp_size = E, \ .exp_bias = ((1 << E) - 1) >> 1, \ - .exp_max = (1 << E) - 1, \ - .frac_size = F + .exp_max = (1 << E) - 1 #define FLOAT_PARAMS(E, F) \ - FLOAT_PARAMS_(E, F), \ + FLOAT_PARAMS_(E), \ + .frac_size = F, \ .frac_shift = (-F - 1) & 63, \ .round_mask = (1ull << ((-F - 1) & 63)) - 1 @@ -613,6 +613,18 @@ static const FloatFmt float128_params = { FLOAT_PARAMS(15, 112) }; +#define FLOATX80_PARAMS(R) \ + FLOAT_PARAMS_(15), \ + .frac_size = R == 64 ? 63 : R, \ + .frac_shift = 0, \ + .round_mask = R == 64 ? -1 : (1ull << ((-R - 1) & 63)) - 1 + +static const FloatFmt floatx80_params[3] = { + [floatx80_precision_s] = { FLOATX80_PARAMS(23) }, + [floatx80_precision_d] = { FLOATX80_PARAMS(52) }, + [floatx80_precision_x] = { FLOATX80_PARAMS(64) }, +}; + /* Unpack a float to parts, but do not canonicalize. */ static void unpack_raw64(FloatParts64 *r, const FloatFmt *fmt, uint64_t raw) { @@ -647,6 +659,16 @@ static inline void float64_unpack_raw(FloatParts64 *p, float64 f) unpack_raw64(p, &float64_params, f); } +static void floatx80_unpack_raw(FloatParts128 *p, floatx80 f) +{ + *p = (FloatParts128) { + .cls = float_class_unclassified, + .sign = extract32(f.high, 15, 1), + .exp = extract32(f.high, 0, 15), + .frac_hi = f.low + }; +} + static void float128_unpack_raw(FloatParts128 *p, float128 f) { const int f_size = float128_params.frac_size - 64; @@ -1535,6 +1557,92 @@ static float128 float128_round_pack_canonical(FloatParts128 *p, return float128_pack_raw(p); } +/* Returns false if the encoding is invalid. */ +static bool floatx80_unpack_canonical(FloatParts128 *p, floatx80 f, + float_status *s) +{ + /* Ensure rounding precision is set before beginning. */ + switch (s->floatx80_rounding_precision) { + case floatx80_precision_x: + case floatx80_precision_d: + case floatx80_precision_s: + break; + default: + g_assert_not_reached(); + } + + if (unlikely(floatx80_invalid_encoding(f))) { + float_raise(float_flag_invalid, s); + return false; + } + + floatx80_unpack_raw(p, f); + + if (likely(p->exp != floatx80_params[floatx80_precision_x].exp_max)) { + parts_canonicalize(p, s, &floatx80_params[floatx80_precision_x]); + } else { + /* The explicit integer bit is ignored, after invalid checks. */ + p->frac_hi &= MAKE_64BIT_MASK(0, 63); + p->cls = (p->frac_hi == 0 ? float_class_inf + : parts_is_snan_frac(p->frac_hi, s) + ? float_class_snan : float_class_qnan); + } + return true; +} + +static floatx80 floatx80_round_pack_canonical(FloatParts128 *p, + float_status *s) +{ + const FloatFmt *fmt = &floatx80_params[s->floatx80_rounding_precision]; + uint64_t frac; + int exp; + + switch (p->cls) { + case float_class_normal: + if (s->floatx80_rounding_precision == floatx80_precision_x) { + parts_uncanon_normal(p, s, fmt); + frac = p->frac_hi; + exp = p->exp; + } else { + FloatParts64 p64; + + p64.sign = p->sign; + p64.exp = p->exp; + frac_truncjam(&p64, p); + parts_uncanon_normal(&p64, s, fmt); + frac = p64.frac; + exp = p64.exp; + } + if (exp != fmt->exp_max) { + break; + } + /* rounded to inf -- fall through to set frac correctly */ + + case float_class_inf: + /* x86 and m68k differ in the setting of the integer bit. */ + frac = floatx80_infinity_low; + exp = fmt->exp_max; + break; + + case float_class_zero: + frac = 0; + exp = 0; + break; + + case float_class_snan: + case float_class_qnan: + /* NaNs have the integer bit set. */ + frac = p->frac_hi | (1ull << 63); + exp = fmt->exp_max; + break; + + default: + g_assert_not_reached(); + } + + return packFloatx80(p->sign, exp, frac); +} + /* * Addition and subtraction */ @@ -1724,6 +1832,30 @@ float128 float128_sub(float128 a, float128 b, float_status *status) return float128_addsub(a, b, status, true); } +static floatx80 QEMU_FLATTEN +floatx80_addsub(floatx80 a, floatx80 b, float_status *status, bool subtract) +{ + FloatParts128 pa, pb, *pr; + + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + + pr = parts_addsub(&pa, &pb, status, subtract); + return floatx80_round_pack_canonical(pr, status); +} + +floatx80 floatx80_add(floatx80 a, floatx80 b, float_status *status) +{ + return floatx80_addsub(a, b, status, false); +} + +floatx80 floatx80_sub(floatx80 a, floatx80 b, float_status *status) +{ + return floatx80_addsub(a, b, status, true); +} + /* * Multiplication */ @@ -5733,205 +5865,6 @@ floatx80 floatx80_round_to_int(floatx80 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of adding the absolute values of the extended double- -| precision floating-point values `a' and `b'. If `zSign' is 1, the sum is -| negated before being returned. `zSign' is ignored if the result is a NaN. -| The addition is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static floatx80 addFloatx80Sigs(floatx80 a, floatx80 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - int32_t expDiff; - - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - bSig = extractFloatx80Frac( b ); - bExp = extractFloatx80Exp( b ); - expDiff = aExp - bExp; - if ( 0 < expDiff ) { - if ( aExp == 0x7FFF ) { - if ((uint64_t)(aSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return a; - } - if ( bExp == 0 ) --expDiff; - shift64ExtraRightJamming( bSig, 0, expDiff, &bSig, &zSig1 ); - zExp = aExp; - } - else if ( expDiff < 0 ) { - if ( bExp == 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return packFloatx80(zSign, - floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp == 0 ) ++expDiff; - shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); - zExp = bExp; - } - else { - if ( aExp == 0x7FFF ) { - if ( (uint64_t) ( ( aSig | bSig )<<1 ) ) { - return propagateFloatx80NaN(a, b, status); - } - return a; - } - zSig1 = 0; - zSig0 = aSig + bSig; - if ( aExp == 0 ) { - if ((aSig | bSig) & UINT64_C(0x8000000000000000) && zSig0 < aSig) { - /* At least one of the values is a pseudo-denormal, - * and there is a carry out of the result. */ - zExp = 1; - goto shiftRight1; - } - if (zSig0 == 0) { - return packFloatx80(zSign, 0, 0); - } - normalizeFloatx80Subnormal( zSig0, &zExp, &zSig0 ); - goto roundAndPack; - } - zExp = aExp; - goto shiftRight1; - } - zSig0 = aSig + bSig; - if ( (int64_t) zSig0 < 0 ) goto roundAndPack; - shiftRight1: - shift64ExtraRightJamming( zSig0, zSig1, 1, &zSig0, &zSig1 ); - zSig0 |= UINT64_C(0x8000000000000000); - ++zExp; - roundAndPack: - return roundAndPackFloatx80(status->floatx80_rounding_precision, - zSign, zExp, zSig0, zSig1, status); -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the absolute values of the extended -| double-precision floating-point values `a' and `b'. If `zSign' is 1, the -| difference is negated before being returned. `zSign' is ignored if the -| result is a NaN. The subtraction is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -static floatx80 subFloatx80Sigs(floatx80 a, floatx80 b, bool zSign, - float_status *status) -{ - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - int32_t expDiff; - - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - bSig = extractFloatx80Frac( b ); - bExp = extractFloatx80Exp( b ); - expDiff = aExp - bExp; - if ( 0 < expDiff ) goto aExpBigger; - if ( expDiff < 0 ) goto bExpBigger; - if ( aExp == 0x7FFF ) { - if ( (uint64_t) ( ( aSig | bSig )<<1 ) ) { - return propagateFloatx80NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - if ( aExp == 0 ) { - aExp = 1; - bExp = 1; - } - zSig1 = 0; - if ( bSig < aSig ) goto aBigger; - if ( aSig < bSig ) goto bBigger; - return packFloatx80(status->float_rounding_mode == float_round_down, 0, 0); - bExpBigger: - if ( bExp == 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return packFloatx80(zSign ^ 1, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp == 0 ) ++expDiff; - shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 ); - bBigger: - sub128( bSig, 0, aSig, zSig1, &zSig0, &zSig1 ); - zExp = bExp; - zSign ^= 1; - goto normalizeRoundAndPack; - aExpBigger: - if ( aExp == 0x7FFF ) { - if ((uint64_t)(aSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return a; - } - if ( bExp == 0 ) --expDiff; - shift128RightJamming( bSig, 0, expDiff, &bSig, &zSig1 ); - aBigger: - sub128( aSig, 0, bSig, zSig1, &zSig0, &zSig1 ); - zExp = aExp; - normalizeRoundAndPack: - return normalizeRoundAndPackFloatx80(status->floatx80_rounding_precision, - zSign, zExp, zSig0, zSig1, status); -} - -/*---------------------------------------------------------------------------- -| Returns the result of adding the extended double-precision floating-point -| values `a' and `b'. The operation is performed according to the IEC/IEEE -| Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_add(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSign = extractFloatx80Sign( a ); - bSign = extractFloatx80Sign( b ); - if ( aSign == bSign ) { - return addFloatx80Sigs(a, b, aSign, status); - } - else { - return subFloatx80Sigs(a, b, aSign, status); - } - -} - -/*---------------------------------------------------------------------------- -| Returns the result of subtracting the extended double-precision floating- -| point values `a' and `b'. The operation is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_sub(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSign = extractFloatx80Sign( a ); - bSign = extractFloatx80Sign( b ); - if ( aSign == bSign ) { - return subFloatx80Sigs(a, b, aSign, status); - } - else { - return addFloatx80Sigs(a, b, aSign, status); - } - -} - /*---------------------------------------------------------------------------- | Returns the result of multiplying the extended double-precision floating- | point values `a' and `b'. The operation is performed according to the From patchwork Sat May 8 01:47:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432584 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp867443jao; Fri, 7 May 2021 19:40:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw8L4DA3klQjUcOQHdYMl+/QgMg5935MF/UtsxfES/xQMaqJ8Snd454JWXjaLfBrovbmjiw X-Received: by 2002:a6b:7d4c:: with SMTP id d12mr9560749ioq.29.1620441614552; Fri, 07 May 2021 19:40:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441614; cv=none; d=google.com; s=arc-20160816; b=immzbcCd8ROuupxCPep+HjhZUuJEQPSfjDuTvvnEKQNCKIcPW75vQTR0rHkzWElHMV GpNwfsBctuK4a87JBF3QHqPcYyj6K9T7r9JgUnOYX9B2nE6gKBhd2R+qPA20lW2tohAJ YtsfJqMxuDh8xUdTISvl7hCGMhxRHU+Fp1RBXNBF9/YXD3ybPWem9p5DMHh0nsKdZjkH OC3Gl5QqvYZVi1AAsvT3PCHTXD1Na3Ve7cjFiU3qRmxfsxU0xw164Wcmg2+WmeLfD1tX nm5ZgbkQgTuyMMiARTrIPeMNWIpYxWIIIHfQv6ah7YEFvnsX9MzFjcb1QX8y3ff1mbUA pvkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jj12YuLJHh6Oh0IVnZb6UWCqmTi7ol2b4RGLMuxGRMs=; b=Ygzaj39bAzRaHb8RsM6vySjIeReTANPz14NUVgJOhNNbaFmP5wfJ2kJ/wGTgsEkA9B weQBrFiGdlyjHZ7mM5Lx3M1ARLThRr3x0LX8wyBZxXH5+2YhajN1864i6wFoyv9it0TD hZFxjBM00Kp5pL8rQ7CuipjV5pp8+YAFCb0xh52khH6fWqv6q+mXDuWs3knwFmWLpSvs n3QNV8UfOqrshq3yWsSj3q0v3/nT/lml25n/d1OQinOQyt6VdiKd0SJHYKctudI/+hLp UTN7VCUCuy/SDpR6lWaZwoQzj0ESmZQeJX72p7g8PbarbZoXPeT24f5LomOaTUZMKkIO CBoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RycazAL0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:51:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 60/72] softfloat: Convert floatx80_mul to FloatParts Date: Fri, 7 May 2021 18:47:50 -0700 Message-Id: <20210508014802.892561-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 76 +++++++++---------------------------------------- 1 file changed, 14 insertions(+), 62 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 3c6751e4d0..4454219f8a 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1943,6 +1943,20 @@ float128_mul(float128 a, float128 b, float_status *status) return float128_round_pack_canonical(pr, status); } +floatx80 QEMU_FLATTEN +floatx80_mul(floatx80 a, floatx80 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + + pr = parts_mul(&pa, &pb, status); + return floatx80_round_pack_canonical(pr, status); +} + /* * Fused multiply-add */ @@ -5865,68 +5879,6 @@ floatx80 floatx80_round_to_int(floatx80 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of multiplying the extended double-precision floating- -| point values `a' and `b'. The operation is performed according to the -| IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_mul(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - bSig = extractFloatx80Frac( b ); - bExp = extractFloatx80Exp( b ); - bSign = extractFloatx80Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FFF ) { - if ( (uint64_t) ( aSig<<1 ) - || ( ( bExp == 0x7FFF ) && (uint64_t) ( bSig<<1 ) ) ) { - return propagateFloatx80NaN(a, b, status); - } - if ( ( bExp | bSig ) == 0 ) goto invalid; - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( bExp == 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - if ( ( aExp | aSig ) == 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 ); - normalizeFloatx80Subnormal( aSig, &aExp, &aSig ); - } - if ( bExp == 0 ) { - if ( bSig == 0 ) return packFloatx80( zSign, 0, 0 ); - normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); - } - zExp = aExp + bExp - 0x3FFE; - mul64To128( aSig, bSig, &zSig0, &zSig1 ); - if ( 0 < (int64_t) zSig0 ) { - shortShift128Left( zSig0, zSig1, 1, &zSig0, &zSig1 ); - --zExp; - } - return roundAndPackFloatx80(status->floatx80_rounding_precision, - zSign, zExp, zSig0, zSig1, status); -} - /*---------------------------------------------------------------------------- | Returns the result of dividing the extended double-precision floating-point | value `a' by the corresponding value `b'. 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Fri, 07 May 2021 18:51:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 61/72] softfloat: Convert floatx80_div to FloatParts Date: Fri, 7 May 2021 18:47:51 -0700 Message-Id: <20210508014802.892561-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 100 +++++++----------------------------------------- 1 file changed, 13 insertions(+), 87 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 4454219f8a..352f359bc5 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2293,6 +2293,19 @@ float128_div(float128 a, float128 b, float_status *status) return float128_round_pack_canonical(pr, status); } +floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + + pr = parts_div(&pa, &pb, status); + return floatx80_round_pack_canonical(pr, status); +} + /* * Float to Float conversions * @@ -5879,93 +5892,6 @@ floatx80 floatx80_round_to_int(floatx80 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of dividing the extended double-precision floating-point -| value `a' by the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status) -{ - bool aSign, bSign, zSign; - int32_t aExp, bExp, zExp; - uint64_t aSig, bSig, zSig0, zSig1; - uint64_t rem0, rem1, rem2, term0, term1, term2; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - bSig = extractFloatx80Frac( b ); - bExp = extractFloatx80Exp( b ); - bSign = extractFloatx80Sign( b ); - zSign = aSign ^ bSign; - if ( aExp == 0x7FFF ) { - if ((uint64_t)(aSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - if ( bExp == 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - goto invalid; - } - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( bExp == 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - return packFloatx80( zSign, 0, 0 ); - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - if ( ( aExp | aSig ) == 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - float_raise(float_flag_divbyzero, status); - return packFloatx80(zSign, floatx80_infinity_high, - floatx80_infinity_low); - } - normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 ); - normalizeFloatx80Subnormal( aSig, &aExp, &aSig ); - } - zExp = aExp - bExp + 0x3FFE; - rem1 = 0; - if ( bSig <= aSig ) { - shift128Right( aSig, 0, 1, &aSig, &rem1 ); - ++zExp; - } - zSig0 = estimateDiv128To64( aSig, rem1, bSig ); - mul64To128( bSig, zSig0, &term0, &term1 ); - sub128( aSig, rem1, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - add128( rem0, rem1, 0, bSig, &rem0, &rem1 ); - } - zSig1 = estimateDiv128To64( rem1, 0, bSig ); - if ( (uint64_t) ( zSig1<<1 ) <= 8 ) { - mul64To128( bSig, zSig1, &term1, &term2 ); - sub128( rem1, 0, term1, term2, &rem1, &rem2 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - add128( rem1, rem2, 0, bSig, &rem1, &rem2 ); - } - zSig1 |= ( ( rem1 | rem2 ) != 0 ); - } - return roundAndPackFloatx80(status->floatx80_rounding_precision, - zSign, zExp, zSig0, zSig1, status); -} - /*---------------------------------------------------------------------------- | Returns the remainder of the extended double-precision floating-point value | `a' with respect to the corresponding value `b'. The operation is performed From patchwork Sat May 8 01:47:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432568 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp862307jao; Fri, 7 May 2021 19:30:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz7q3s8Xy/iHFLbkGnTjuCTKps4wCw2rZHpqIifMYf3Oq9pLYgPT8+h09VRG5ev+pG+2QNo X-Received: by 2002:a05:6e02:1ba5:: with SMTP id n5mr11660749ili.45.1620441028071; Fri, 07 May 2021 19:30:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441028; cv=none; d=google.com; s=arc-20160816; b=Puh15rSLeBrhk+HoQBkGGa7wPSMRPS7CCsFLQXjHAO2mNCvjyt4Aiv8uJSIPHvAq+S 3wGBqYWa+qUw7p3FurPa2yiOkgUAN7DhK5YlrTQB9l049LNAWE4WyZ2uZ3SyxvSeWhxJ lgY88XqtQmWfK391uA/JfWG8P3IE7VqfQBtRijW4WwtuAKh90XoSeO6F+I5BckmJFT7u gHt/2Ro2bGGKHzQ7MEJXqMXqAM8QTRc9U1tHEi6YaZw7T4Idd9JoJnCLaRoPmSwRpKNZ bjKydpoQHo/wCzoIr0lFRbIHUibqOQjYcRhj9Yx/iGYlu4NaW5NpMwvIffzGRuG517E+ /A3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=t3Jy5CANfNVfC3/a+h+EOADacahyzwCmvSWB6DnAZSc=; b=XrYHPbG5P9VAxVfeYhmMkSC69rIieBS2FXmfZTcDG77ov2vBOd5RWwho6IvRE1udds 0DHXiH//Qz1rIMWWWeylAiKxc1SjK9klwkCy4Tj5b0cxDaUhVkGOOkB8HPcD7rnC9CTB CMUaGA15Qi2x3hoSiUaTgJSf6dViAfXx1RBznZf8GQAkBd1xrSKJ85HsGTth6pS+DjFo q/QxdRa7JcFCR6wbmOz6MXy/2OsAE3OMK78gNcztPOFsJPS9Yt3rsJRL8H3zDx7ODaTV c7/mnUoDI9O0O4Z9f2VJlOJMekiHB0ayVA7eUgRhBVWmd/aVAo0yRf4RxkOchEk0FmaX 014Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fbM6omQO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:51:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 62/72] softfloat: Convert floatx80_sqrt to FloatParts Date: Fri, 7 May 2021 18:47:52 -0700 Message-Id: <20210508014802.892561-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 82 +++++++------------------------------------------ 1 file changed, 11 insertions(+), 71 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 352f359bc5..7050d8f012 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3883,6 +3883,17 @@ float128 QEMU_FLATTEN float128_sqrt(float128 a, float_status *status) return float128_round_pack_canonical(&p, status); } +floatx80 floatx80_sqrt(floatx80 a, float_status *s) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, s)) { + return floatx80_default_nan(s); + } + parts_sqrt(&p, s, &floatx80_params[s->floatx80_rounding_precision]); + return floatx80_round_pack_canonical(&p, s); +} + /*---------------------------------------------------------------------------- | The pattern for a default generated NaN. *----------------------------------------------------------------------------*/ @@ -6046,77 +6057,6 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) return floatx80_modrem(a, b, true, "ient, status); } -/*---------------------------------------------------------------------------- -| Returns the square root of the extended double-precision floating-point -| value `a'. The operation is performed according to the IEC/IEEE Standard -| for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_sqrt(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp, zExp; - uint64_t aSig0, aSig1, zSig0, zSig1, doubleZSig0; - uint64_t rem0, rem1, rem2, rem3, term0, term1, term2, term3; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig0 = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - if ( aExp == 0x7FFF ) { - if ((uint64_t)(aSig0 << 1)) { - return propagateFloatx80NaN(a, a, status); - } - if ( ! aSign ) return a; - goto invalid; - } - if ( aSign ) { - if ( ( aExp | aSig0 ) == 0 ) return a; - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - if ( aExp == 0 ) { - if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 ); - normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 ); - } - zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFF; - zSig0 = estimateSqrt32( aExp, aSig0>>32 ); - shift128Right( aSig0, 0, 2 + ( aExp & 1 ), &aSig0, &aSig1 ); - zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 ); - doubleZSig0 = zSig0<<1; - mul64To128( zSig0, zSig0, &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 ); - while ( (int64_t) rem0 < 0 ) { - --zSig0; - doubleZSig0 -= 2; - add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 ); - } - zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 ); - if ( ( zSig1 & UINT64_C(0x3FFFFFFFFFFFFFFF) ) <= 5 ) { - if ( zSig1 == 0 ) zSig1 = 1; - mul64To128( doubleZSig0, zSig1, &term1, &term2 ); - sub128( rem1, 0, term1, term2, &rem1, &rem2 ); - mul64To128( zSig1, zSig1, &term2, &term3 ); - sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 ); - while ( (int64_t) rem1 < 0 ) { - --zSig1; - shortShift128Left( 0, zSig1, 1, &term2, &term3 ); - term3 |= 1; - term2 |= doubleZSig0; - add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 ); - } - zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 ); - } - shortShift128Left( 0, zSig1, 1, &zSig0, &zSig1 ); - zSig0 |= doubleZSig0; - return roundAndPackFloatx80(status->floatx80_rounding_precision, - 0, zExp, zSig0, zSig1, status); -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point | value `a' to the extended double-precision floating-point format. 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Fri, 07 May 2021 18:51:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 63/72] softfloat: Convert floatx80_round to FloatParts Date: Fri, 7 May 2021 18:47:53 -0700 Message-Id: <20210508014802.892561-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 7050d8f012..faccc8df41 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -5794,10 +5794,12 @@ float128 floatx80_to_float128(floatx80 a, float_status *status) floatx80 floatx80_round(floatx80 a, float_status *status) { - return roundAndPackFloatx80(status->floatx80_rounding_precision, - extractFloatx80Sign(a), - extractFloatx80Exp(a), - extractFloatx80Frac(a), 0, status); + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, status)) { + return floatx80_default_nan(status); + } + return floatx80_round_pack_canonical(&p, status); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:47:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432580 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp866005jao; Fri, 7 May 2021 19:37:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxXz8K0Dntlajo646YvHO7kdp2z/ewPcAGyAobdxfFUvOf929cRQPO6KsjcFDKUMFz+cgnd X-Received: by 2002:a02:37c9:: with SMTP id r192mr11494650jar.88.1620441464479; Fri, 07 May 2021 19:37:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441464; cv=none; d=google.com; s=arc-20160816; b=Q0DfQP2bkbJVvy1jgIWh2Jb4aaue5Ci3PgL6MuCbTIhKOePresXXAkI9siocjueyE3 le/DQmTrEs3Z22g74zJQ5VCbr+odMZ2SJrxl7llBpwBooEBvhyY+25rvHuysgKE1DzRT i2QSsHhXOPC19ZQlPZsjwuyRPd6KBeYtsCVscmz+W46zcKWyPu7BwetpIQh4e5+JLrPp 2wJcvQOk1B0OItztcwfspDmzu0nRtPrJ9WuXGk415sGJ8lJSUnHw1TS2J1gIqJORfAVP UR/plME4XVrlWEmwkpBA1SQBkSb6w0hEXpzYH6Jrix3eIKdSuavO0sm/PUyEPAqvvZDp RvJA== ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 64/72] softfloat: Convert floatx80_round_to_int to FloatParts Date: Fri, 7 May 2021 18:47:54 -0700 Message-Id: <20210508014802.892561-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 116 ++++++------------------------------------------ 1 file changed, 13 insertions(+), 103 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index faccc8df41..914cf2688c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2609,6 +2609,19 @@ float128 float128_round_to_int(float128 a, float_status *s) return float128_round_pack_canonical(&p, s); } +floatx80 floatx80_round_to_int(floatx80 a, float_status *status) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, status)) { + return floatx80_default_nan(status); + } + + parts_round_to_int(&p, status->float_rounding_mode, 0, status, + &floatx80_params[status->floatx80_rounding_precision]); + return floatx80_round_pack_canonical(&p, status); +} + /* * Floating-point to signed integer conversions */ @@ -5802,109 +5815,6 @@ floatx80 floatx80_round(floatx80 a, float_status *status) return floatx80_round_pack_canonical(&p, status); } -/*---------------------------------------------------------------------------- -| Rounds the extended double-precision floating-point value `a' to an integer, -| and returns the result as an extended quadruple-precision floating-point -| value. The operation is performed according to the IEC/IEEE Standard for -| Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_round_to_int(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t lastBitMask, roundBitsMask; - floatx80 z; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aExp = extractFloatx80Exp( a ); - if ( 0x403E <= aExp ) { - if ( ( aExp == 0x7FFF ) && (uint64_t) ( extractFloatx80Frac( a )<<1 ) ) { - return propagateFloatx80NaN(a, a, status); - } - return a; - } - if ( aExp < 0x3FFF ) { - if ( ( aExp == 0 ) - && ( (uint64_t) ( extractFloatx80Frac( a ) ) == 0 ) ) { - return a; - } - float_raise(float_flag_inexact, status); - aSign = extractFloatx80Sign( a ); - switch (status->float_rounding_mode) { - case float_round_nearest_even: - if ( ( aExp == 0x3FFE ) && (uint64_t) ( extractFloatx80Frac( a )<<1 ) - ) { - return - packFloatx80( aSign, 0x3FFF, UINT64_C(0x8000000000000000)); - } - break; - case float_round_ties_away: - if (aExp == 0x3FFE) { - return packFloatx80(aSign, 0x3FFF, UINT64_C(0x8000000000000000)); - } - break; - case float_round_down: - return - aSign ? - packFloatx80( 1, 0x3FFF, UINT64_C(0x8000000000000000)) - : packFloatx80( 0, 0, 0 ); - case float_round_up: - return - aSign ? packFloatx80( 1, 0, 0 ) - : packFloatx80( 0, 0x3FFF, UINT64_C(0x8000000000000000)); - - case float_round_to_zero: - break; - default: - g_assert_not_reached(); - } - return packFloatx80( aSign, 0, 0 ); - } - lastBitMask = 1; - lastBitMask <<= 0x403E - aExp; - roundBitsMask = lastBitMask - 1; - z = a; - switch (status->float_rounding_mode) { - case float_round_nearest_even: - z.low += lastBitMask>>1; - if ((z.low & roundBitsMask) == 0) { - z.low &= ~lastBitMask; - } - break; - case float_round_ties_away: - z.low += lastBitMask >> 1; - break; - case float_round_to_zero: - break; - case float_round_up: - if (!extractFloatx80Sign(z)) { - z.low += roundBitsMask; - } - break; - case float_round_down: - if (extractFloatx80Sign(z)) { - z.low += roundBitsMask; - } - break; - default: - abort(); - } - z.low &= ~ roundBitsMask; - if ( z.low == 0 ) { - ++z.high; - z.low = UINT64_C(0x8000000000000000); - } - if (z.low != a.low) { - float_raise(float_flag_inexact, status); - } - return z; - -} - /*---------------------------------------------------------------------------- | Returns the remainder of the extended double-precision floating-point value | `a' with respect to the corresponding value `b'. The operation is performed From patchwork Sat May 8 01:47:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432573 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp863337jao; Fri, 7 May 2021 19:32:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy8nu1PBQj6/7HozQ9siqD4Sm2nejlpR15hDodqD+eVQlE7ygPs8bR1UmH2UrX2EW1hLhVl X-Received: by 2002:a92:d5cd:: with SMTP id d13mr11829689ilq.133.1620441150002; Fri, 07 May 2021 19:32:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441149; cv=none; d=google.com; s=arc-20160816; b=0vHeZHq5bTbNPvC1jfniaizKlTADtD3kHCGZWJ0zlLd9uAWmDc9Q0hgP50/PWCofBQ LfYstvMzWxQihlZsyGy7JiCPoagZHi5iDsmHCj7/JBkPHQNHgXrwGZSYvc2ByfHG+rpI g+uBSj5hErghp7jmSripWvew8ourj57KvahSJ/eSdJNRJuBhX2d5VKNm43Upw0MFfiZn D9KrNukuFIMTgEkkBkhVaZK1OXrFnSJR0SLjGNp1uMfZPV8uitmeRjw2m6ZUlhDAqsus muMsvy/WhG+Ik7VrF/f4MKszbwWqsJ0JbL8K+y+k7UP8i1yx9q9+fc0YdTlquOavJNKN Rk7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=j0n+VHMEDjMKtgDcOQxDeJHVUUgoF67rvW1U9FdzS+U=; b=bCVaP4us2oz7qtedEebcp8UXm0//XbjSKtqkxHeOlbasLi8k3KwNKScYlhaAn1lnXJ QWwvyGvuulfucru5txkBLQ5fiar/FkyQWp41VIDS5PR2I+xcmAc8f6FhlQQtAEEkt4lh p9fcAHLkANeHJNgUvJSjmMKFSMfKfyDbPFsLpdKdcmBs8+3nfM/+m/se0qDVbbeOHnhh M2Zn0Ftfn6axAh7BXnkjgkYor1AXZAGb1xxVxoisQcgK+pXf86mxWtQuKzBTFEWQj4Vg RvI4uHGqUQilz0n++UVZtiv822VsoQlBkhj+FP5YLlUurft2rhanZDfO8bmd2Xp1rSYk O5pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pYXZ4Idr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:51:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 65/72] softfloat: Convert integer to floatx80 to FloatParts Date: Fri, 7 May 2021 18:47:55 -0700 Message-Id: <20210508014802.892561-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 58 +++++++++++-------------------------------------- 1 file changed, 13 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 914cf2688c..82f71896ac 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3344,6 +3344,19 @@ float128 int32_to_float128(int32_t a, float_status *status) return int64_to_float128(a, status); } +floatx80 int64_to_floatx80(int64_t a, float_status *status) +{ + FloatParts128 p; + + parts_sint_to_float(&p, a, 0, status); + return floatx80_round_pack_canonical(&p, status); +} + +floatx80 int32_to_floatx80(int32_t a, float_status *status) +{ + return int64_to_floatx80(a, status); +} + /* * Unsigned Integer to floating-point conversions */ @@ -5035,51 +5048,6 @@ static float128 normalizeRoundAndPackFloat128(bool zSign, int32_t zExp, } - -/*---------------------------------------------------------------------------- -| Returns the result of converting the 32-bit two's complement integer `a' -| to the extended double-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 int32_to_floatx80(int32_t a, float_status *status) -{ - bool zSign; - uint32_t absA; - int8_t shiftCount; - uint64_t zSig; - - if ( a == 0 ) return packFloatx80( 0, 0, 0 ); - zSign = ( a < 0 ); - absA = zSign ? - a : a; - shiftCount = clz32(absA) + 32; - zSig = absA; - return packFloatx80( zSign, 0x403E - shiftCount, zSig< X-Patchwork-Id: 432577 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp864649jao; Fri, 7 May 2021 19:34:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGQcimwCTVfmo4MkKXX4ztMOBhS4UhiKhOLTDzRtB2R2QpZGFGlD1Jj5XX1mU0KiYxNRAM X-Received: by 2002:a92:c649:: with SMTP id 9mr12302450ill.79.1620441289076; Fri, 07 May 2021 19:34:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441289; cv=none; d=google.com; s=arc-20160816; b=B7fhnx2gGLDszV+6MAoTMTW7mqhzIT7xgLLb1KeH39+O0HTjxUnS0q49VBpfu+Y7I1 DbKi2p2f4JjUoSnBIt12PdTH6+8X1UPOFsDRpIDsz5FOlLBjUfT3iEJ3MSPicycaDVu6 FSIYOpm3CGptRKr3BzG9el7XunMrgS+2IPFrftYXFhJhzyM2hfhnsajGzJsK5LezEsKI 7BNO7H36AsIYHa2H5CfMjm4xAvEKj8+98gjhi/KdJTue8Er825iZDVG3w7dZtGmOiQ5I IdcrGYsHV7cZOo6RCaVHcMbYkIvEg++XS4uHZBbSqjsqKZl47LVGwZVojHn/v9EQ8llD 8xiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=krbccElr6YBGv/dTDG8O6hv4U6UMSoNxQsDJQmD9EcE=; b=Oad5RJU7CK+JOInRaOPQdzUmdQ4HMTHD005PSHFfsC2v1H8aOMIevWlhxBDl8LSXcB cuA2KqSuYv8vYE0WPSF10LHVdCRSAzqbJTAzbPZ1scoHZPyn4NzHtTAoe+NVJhN/IkMF 42jLPYlBMym4TNUHzdz3DGGUd+ajtRwg5yaE+AkDOKsJ1NiLPyo2/VyZ9OZENNoEid4t jA7R2WIM0PPKq92qr/m97ItO+oi5w2khZ0m+1j4u+5PL0A7RxWJNx6kT+dHDNjXvmbZE DB9F+BoIMDJwWRQunKVduzS6nMP612Z3e+QpVhk1DDXtK+6eDF8lEH4KvXhkJXAcLE0J gZaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gYq0cjMv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z25si8878770ior.21.2021.05.07.19.34.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:34:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gYq0cjMv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56512 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCno-0004uR-Gi for patch@linaro.org; Fri, 07 May 2021 22:34:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC8M-0003Wk-LM for qemu-devel@nongnu.org; Fri, 07 May 2021 21:52:00 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:33294) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC8B-0005Zs-UM for qemu-devel@nongnu.org; Fri, 07 May 2021 21:51:57 -0400 Received: by mail-pj1-x102a.google.com with SMTP id b14-20020a17090a6e0eb0290155c7f6a356so5542382pjk.0 for ; Fri, 07 May 2021 18:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=krbccElr6YBGv/dTDG8O6hv4U6UMSoNxQsDJQmD9EcE=; b=gYq0cjMvPMbh0vFKsUhAveW1xnYBWLRtdjRjiud7ZdJZdL44RKnXpE/+SSMCP7E+pL +g4t1a5avnqdtBfgrUtAli9YOl5KxF7CR5phwb/q/V6LhPBtJKM4fM6Nux78XQSLFq6p NKbFSnId+/zMPNMvjEMZML+aBsE6q0A9YTEzMERolaWYhaj5zYggovW1ydyKJtFogC20 SWDFP5aPEB6VB8+rGKu8284EmUQlkj2j6faTWbo1v7b+TAEKpVbzZgPqY7wgnewougB1 bFRgamlytLAUQ024d9dMQAo/n/VPqZ2w1w2PMmB8N9o4SVhec1t6dbZLnWwSya1K0BYc TOug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=krbccElr6YBGv/dTDG8O6hv4U6UMSoNxQsDJQmD9EcE=; b=N49FvzB0HL8/ZAbSMcMOrH6LlOFq+5DeOZ1zoCEroTl05aygGS8DnTi1XDFEX6KVYq gG8DE+vmGhhPzNVFQG/tn/oBQsWs9vuG/RRPt/VFx+ePjGBz9RnBpx2om6x1yXx1Tqjd Atu4KDFUGyDU9Fp3mD2DqdGe5ATBQa0nQEnqR4zCZ9D9fgzSNJ84iot8k4v6Yg9gNXZO m6vtMrgyEwYcEEGtGAIiKj9yiSVaFjs+zmVfbMFp42Pecx01sasOVSUyGasojoZvLC/f 2ph+zLIJXBaYqWhAqxq+XRBicJTQ6XvED46W2G1rpmsCHbybRWfmAmaCB/qBL9InWesI JAEw== X-Gm-Message-State: AOAM533eyRH1WFMjrtKBOifxF1rgzgMYLNF6CZdJY+e6g2ETsP5MQ2GZ Af5xAtjMJemnTPOpnfMfIRoGXHFokkDfaA== X-Received: by 2002:a17:90a:744e:: with SMTP id o14mr1621318pjk.96.1620438706637; Fri, 07 May 2021 18:51:46 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 66/72] softfloat: Convert floatx80 float conversions to FloatParts Date: Fri, 7 May 2021 18:47:56 -0700 Message-Id: <20210508014802.892561-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the last use of commonNaNT and all of the routines that use it, so remove all of them for Werror. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 276 ++++++++------------------------- fpu/softfloat-specialize.c.inc | 175 --------------------- 2 files changed, 67 insertions(+), 384 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 82f71896ac..d7c6c37d99 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2560,6 +2560,73 @@ float128 float64_to_float128(float64 a, float_status *s) return float128_round_pack_canonical(&p128, s); } +float32 floatx80_to_float32(floatx80 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + if (floatx80_unpack_canonical(&p128, a, s)) { + parts_float_to_float_narrow(&p64, &p128, s); + } else { + parts_default_nan(&p64, s); + } + return float32_round_pack_canonical(&p64, s); +} + +float64 floatx80_to_float64(floatx80 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + if (floatx80_unpack_canonical(&p128, a, s)) { + parts_float_to_float_narrow(&p64, &p128, s); + } else { + parts_default_nan(&p64, s); + } + return float64_round_pack_canonical(&p64, s); +} + +float128 floatx80_to_float128(floatx80 a, float_status *s) +{ + FloatParts128 p; + + if (floatx80_unpack_canonical(&p, a, s)) { + parts_float_to_float(&p, s); + } else { + parts_default_nan(&p, s); + } + return float128_round_pack_canonical(&p, s); +} + +floatx80 float32_to_floatx80(float32 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float32_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return floatx80_round_pack_canonical(&p128, s); +} + +floatx80 float64_to_floatx80(float64 a, float_status *s) +{ + FloatParts64 p64; + FloatParts128 p128; + + float64_unpack_canonical(&p64, a, s); + parts_float_to_float_widen(&p128, &p64, s); + return floatx80_round_pack_canonical(&p128, s); +} + +floatx80 float128_to_floatx80(float128 a, float_status *s) +{ + FloatParts128 p; + + float128_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return floatx80_round_pack_canonical(&p, s); +} + /* * Round to integral value */ @@ -5048,42 +5115,6 @@ static float128 normalizeRoundAndPackFloat128(bool zSign, int32_t zExp, } -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point value -| `a' to the extended double-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 float32_to_floatx80(float32 a, float_status *status) -{ - bool aSign; - int aExp; - uint32_t aSig; - - a = float32_squash_input_denormal(a, status); - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - if ( aExp == 0xFF ) { - if (aSig) { - floatx80 res = commonNaNToFloatx80(float32ToCommonNaN(a, status), - status); - return floatx80_silence_nan(res, status); - } - return packFloatx80(aSign, - floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - aSig |= 0x00800000; - return packFloatx80( aSign, aExp + 0x3F80, ( (uint64_t) aSig )<<40 ); - -} - /*---------------------------------------------------------------------------- | Returns the remainder of the single-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5320,43 +5351,6 @@ float32 float32_log2(float32 a, float_status *status) return normalizeRoundAndPackFloat32(zSign, 0x85, zSig, status); } -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point value -| `a' to the extended double-precision floating-point format. The conversion -| is performed according to the IEC/IEEE Standard for Binary Floating-Point -| Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 float64_to_floatx80(float64 a, float_status *status) -{ - bool aSign; - int aExp; - uint64_t aSig; - - a = float64_squash_input_denormal(a, status); - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - if ( aExp == 0x7FF ) { - if (aSig) { - floatx80 res = commonNaNToFloatx80(float64ToCommonNaN(a, status), - status); - return floatx80_silence_nan(res, status); - } - return packFloatx80(aSign, - floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - return - packFloatx80( - aSign, aExp + 0x3C00, (aSig | UINT64_C(0x0010000000000000)) << 11); - -} - /*---------------------------------------------------------------------------- | Returns the remainder of the double-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5667,104 +5661,6 @@ int64_t floatx80_to_int64_round_to_zero(floatx80 a, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the single-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 floatx80_to_float32(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - if ( aExp == 0x7FFF ) { - if ( (uint64_t) ( aSig<<1 ) ) { - float32 res = commonNaNToFloat32(floatx80ToCommonNaN(a, status), - status); - return float32_silence_nan(res, status); - } - return packFloat32( aSign, 0xFF, 0 ); - } - shift64RightJamming( aSig, 33, &aSig ); - if ( aExp || aSig ) aExp -= 0x3F81; - return roundAndPackFloat32(aSign, aExp, aSig, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the double-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 floatx80_to_float64(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig, zSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - if ( aExp == 0x7FFF ) { - if ( (uint64_t) ( aSig<<1 ) ) { - float64 res = commonNaNToFloat64(floatx80ToCommonNaN(a, status), - status); - return float64_silence_nan(res, status); - } - return packFloat64( aSign, 0x7FF, 0 ); - } - shift64RightJamming( aSig, 1, &zSig ); - if ( aExp || aSig ) aExp -= 0x3C01; - return roundAndPackFloat64(aSign, aExp, zSig, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the quadruple-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 floatx80_to_float128(floatx80 a, float_status *status) -{ - bool aSign; - int aExp; - uint64_t aSig, zSig0, zSig1; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - if ( ( aExp == 0x7FFF ) && (uint64_t) ( aSig<<1 ) ) { - float128 res = commonNaNToFloat128(floatx80ToCommonNaN(a, status), - status); - return float128_silence_nan(res, status); - } - shift128Right( aSig<<1, 0, 16, &zSig0, &zSig1 ); - return packFloat128( aSign, aExp, zSig0, zSig1 ); - -} - /*---------------------------------------------------------------------------- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the @@ -5937,44 +5833,6 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) return floatx80_modrem(a, b, true, "ient, status); } -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point -| value `a' to the extended double-precision floating-point format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 float128_to_floatx80(float128 a, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig0, aSig1; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - if ( aExp == 0x7FFF ) { - if ( aSig0 | aSig1 ) { - floatx80 res = commonNaNToFloatx80(float128ToCommonNaN(a, status), - status); - return floatx80_silence_nan(res, status); - } - return packFloatx80(aSign, floatx80_infinity_high, - floatx80_infinity_low); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return packFloatx80( aSign, 0, 0 ); - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - else { - aSig0 |= UINT64_C(0x0001000000000000); - } - shortShift128Left( aSig0, aSig1, 15, &aSig0, &aSig1 ); - return roundAndPackFloatx80(80, aSign, aExp, aSig0, aSig1, status); - -} - /*---------------------------------------------------------------------------- | Returns the remainder of the quadruple-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a0cf016b4f..88eab344df 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -257,14 +257,6 @@ floatx80 floatx80_default_nan(float_status *status) const floatx80 floatx80_infinity = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low); -/*---------------------------------------------------------------------------- -| Internal canonical NaN format. -*----------------------------------------------------------------------------*/ -typedef struct { - bool sign; - uint64_t high, low; -} commonNaNT; - /*---------------------------------------------------------------------------- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -380,46 +372,6 @@ bool float32_is_signaling_nan(float32 a_, float_status *status) } } -/*---------------------------------------------------------------------------- -| Returns the result of converting the single-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float32ToCommonNaN(float32 a, float_status *status) -{ - commonNaNT z; - - if (float32_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = float32_val(a) >> 31; - z.low = 0; - z.high = ((uint64_t)float32_val(a)) << 41; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the single- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float32 commonNaNToFloat32(commonNaNT a, float_status *status) -{ - uint32_t mantissa = a.high >> 41; - - if (status->default_nan_mode) { - return float32_default_nan(status); - } - - if (mantissa) { - return make_float32( - (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41)); - } else { - return float32_default_nan(status); - } -} - /*---------------------------------------------------------------------------- | Select which NaN to propagate for a two-input operation. | IEEE754 doesn't specify all the details of this, so the @@ -780,48 +732,6 @@ bool float64_is_signaling_nan(float64 a_, float_status *status) } } -/*---------------------------------------------------------------------------- -| Returns the result of converting the double-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float64ToCommonNaN(float64 a, float_status *status) -{ - commonNaNT z; - - if (float64_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = float64_val(a) >> 63; - z.low = 0; - z.high = float64_val(a) << 12; - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the double- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float64 commonNaNToFloat64(commonNaNT a, float_status *status) -{ - uint64_t mantissa = a.high >> 12; - - if (status->default_nan_mode) { - return float64_default_nan(status); - } - - if (mantissa) { - return make_float64( - (((uint64_t) a.sign) << 63) - | UINT64_C(0x7FF0000000000000) - | (a.high >> 12)); - } else { - return float64_default_nan(status); - } -} - /*---------------------------------------------------------------------------- | Takes two double-precision floating-point values `a' and `b', one of which | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a @@ -941,55 +851,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Returns the result of converting the extended double-precision floating- -| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the -| invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status) -{ - floatx80 dflt; - commonNaNT z; - - if (floatx80_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - if (a.low >> 63) { - z.sign = a.high >> 15; - z.low = 0; - z.high = a.low << 1; - } else { - dflt = floatx80_default_nan(status); - z.sign = dflt.high >> 15; - z.low = 0; - z.high = dflt.low << 1; - } - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the extended -| double-precision floating-point format. -*----------------------------------------------------------------------------*/ - -static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) -{ - floatx80 z; - - if (status->default_nan_mode) { - return floatx80_default_nan(status); - } - - if (a.high >> 1) { - z.low = UINT64_C(0x8000000000000000) | a.high >> 1; - z.high = (((uint16_t)a.sign) << 15) | 0x7FFF; - } else { - z = floatx80_default_nan(status); - } - return z; -} - /*---------------------------------------------------------------------------- | Takes two extended double-precision floating-point values `a' and `b', one | of which is a NaN, and returns the appropriate NaN result. If either `a' or @@ -1082,42 +943,6 @@ bool float128_is_signaling_nan(float128 a, float_status *status) } } -/*---------------------------------------------------------------------------- -| Returns the result of converting the quadruple-precision floating-point NaN -| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid -| exception is raised. -*----------------------------------------------------------------------------*/ - -static commonNaNT float128ToCommonNaN(float128 a, float_status *status) -{ - commonNaNT z; - - if (float128_is_signaling_nan(a, status)) { - float_raise(float_flag_invalid, status); - } - z.sign = a.high >> 63; - shortShift128Left(a.high, a.low, 16, &z.high, &z.low); - return z; -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the canonical NaN `a' to the quadruple- -| precision floating-point format. -*----------------------------------------------------------------------------*/ - -static float128 commonNaNToFloat128(commonNaNT a, float_status *status) -{ - float128 z; - - if (status->default_nan_mode) { - return float128_default_nan(status); - } - - shift128Right(a.high, a.low, 16, &z.high, &z.low); - z.high |= (((uint64_t)a.sign) << 63) | UINT64_C(0x7FFF000000000000); - return z; -} - /*---------------------------------------------------------------------------- | Takes two quadruple-precision floating-point values `a' and `b', one of | which is a NaN, and returns the appropriate NaN result. If either `a' or From patchwork Sat May 8 01:47:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432582 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp866020jao; Fri, 7 May 2021 19:37:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeHRmKKpFhCC+LjM+h5Xs4c7R8a4drjxAOcdK8Ijrtk/blE8NKNqkcKM9ojGZPPFR8w5ib X-Received: by 2002:a05:6602:181:: with SMTP id m1mr10520468ioo.153.1620441466242; Fri, 07 May 2021 19:37:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441466; cv=none; d=google.com; s=arc-20160816; b=EFcRyngGS83pnKppVTDv4Fekvb5dpntH57VFsPwCNrD9wp7bXG5Cc/HAANKPgc+z1d m9eGDBiYyvBfx885NwAX/epr4MKLCOcGrywxgAX5GN1u7XlrPqAzFusjBRy3ZMkq4LCy yBfCs9SLb1Re/xAlNenwSEzJb7uK28HUaG4PQY5Nzj9LYe1klF1FeHFs4JoyuHQINfvn NfinOpMhYX/ceQ3ki7A4qs7GSvc5OWahW1DLMi+sWwWyCAa2I5zeMBUrJBV1AFvWylAL DwDKH+foUekpy7xVKKo2725EJLcjfEYpsWfRL80VxVlat9GlPe75JNdlx0cqMD58ueNO iQfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FAQ0+Arx3hcf96RReOfO4wuHa+U02gZo3qBKfpYs2sk=; b=B4N4tYi/hweI/TfJoPUhiCZeiHcCfvR4qyi6VlQYop+aOJME+ws235HEq2bPTDT1uy ANdaWipP/UyamdSKb5rK44qpxxCXtB3i1BYR6qx8LPgFak4dPVZjkmXMzZ8Tc+vJgqbQ LTS/2nroNEBTbVbXyutm7Ej/5KvCidFEGX+LIZ4W1q9T5uj7lyEtj2Z3lPc3ArcKw6wt fbp5WDUfiJ6niPhlKseyCJJiNkVHfK1oFX60InZbAZTMRcX3DU2sihIo0zqZvwLtIq02 I9e/7H+4meG+8PYLDp+2mlEdCvOaUYVlqYnm0FRkpBA+15xxiUUY7iWbFiJ/c+7imR3I Xfdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yC4xlohb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:51:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 67/72] softfloat: Convert floatx80 to integer to FloatParts Date: Fri, 7 May 2021 18:47:57 -0700 Message-Id: <20210508014802.892561-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 336 ++++++------------------------------------------ 1 file changed, 42 insertions(+), 294 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index d7c6c37d99..9f28c5c058 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2828,6 +2828,28 @@ static int64_t float128_to_int64_scalbn(float128 a, FloatRoundMode rmode, return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); } +static int32_t floatx80_to_int32_scalbn(floatx80 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, s)) { + parts_default_nan(&p, s); + } + return parts_float_to_sint(&p, rmode, scale, INT32_MIN, INT32_MAX, s); +} + +static int64_t floatx80_to_int64_scalbn(floatx80 a, FloatRoundMode rmode, + int scale, float_status *s) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, s)) { + parts_default_nan(&p, s); + } + return parts_float_to_sint(&p, rmode, scale, INT64_MIN, INT64_MAX, s); +} + int8_t float16_to_int8(float16 a, float_status *s) { return float16_to_int8_scalbn(a, s->float_rounding_mode, 0, s); @@ -2888,6 +2910,16 @@ int64_t float128_to_int64(float128 a, float_status *s) return float128_to_int64_scalbn(a, s->float_rounding_mode, 0, s); } +int32_t floatx80_to_int32(floatx80 a, float_status *s) +{ + return floatx80_to_int32_scalbn(a, s->float_rounding_mode, 0, s); +} + +int64_t floatx80_to_int64(floatx80 a, float_status *s) +{ + return floatx80_to_int64_scalbn(a, s->float_rounding_mode, 0, s); +} + int16_t float16_to_int16_round_to_zero(float16 a, float_status *s) { return float16_to_int16_scalbn(a, float_round_to_zero, 0, s); @@ -2943,6 +2975,16 @@ int64_t float128_to_int64_round_to_zero(float128 a, float_status *s) return float128_to_int64_scalbn(a, float_round_to_zero, 0, s); } +int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *s) +{ + return floatx80_to_int32_scalbn(a, float_round_to_zero, 0, s); +} + +int64_t floatx80_to_int64_round_to_zero(floatx80 a, float_status *s) +{ + return floatx80_to_int64_scalbn(a, float_round_to_zero, 0, s); +} + int16_t bfloat16_to_int16(bfloat16 a, float_status *s) { return bfloat16_to_int16_scalbn(a, s->float_rounding_mode, 0, s); @@ -4162,127 +4204,6 @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 -| and 7, and returns the properly rounded 32-bit integer corresponding to the -| input. If `zSign' is 1, the input is negated before being converted to an -| integer. Bit 63 of `absZ' must be zero. Ordinarily, the fixed-point input -| is simply rounded to an integer, with the inexact exception raised if the -| input cannot be represented exactly as an integer. However, if the fixed- -| point input is too large, the invalid exception is raised and the largest -| positive or negative integer is returned. -*----------------------------------------------------------------------------*/ - -static int32_t roundAndPackInt32(bool zSign, uint64_t absZ, - float_status *status) -{ - int8_t roundingMode; - bool roundNearestEven; - int8_t roundIncrement, roundBits; - int32_t z; - - roundingMode = status->float_rounding_mode; - roundNearestEven = ( roundingMode == float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - roundIncrement = 0x40; - break; - case float_round_to_zero: - roundIncrement = 0; - break; - case float_round_up: - roundIncrement = zSign ? 0 : 0x7f; - break; - case float_round_down: - roundIncrement = zSign ? 0x7f : 0; - break; - case float_round_to_odd: - roundIncrement = absZ & 0x80 ? 0 : 0x7f; - break; - default: - abort(); - } - roundBits = absZ & 0x7F; - absZ = ( absZ + roundIncrement )>>7; - if (!(roundBits ^ 0x40) && roundNearestEven) { - absZ &= ~1; - } - z = absZ; - if ( zSign ) z = - z; - if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) { - float_raise(float_flag_invalid, status); - return zSign ? INT32_MIN : INT32_MAX; - } - if (roundBits) { - float_raise(float_flag_inexact, status); - } - return z; - -} - -/*---------------------------------------------------------------------------- -| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and -| `absZ1', with binary point between bits 63 and 64 (between the input words), -| and returns the properly rounded 64-bit integer corresponding to the input. -| If `zSign' is 1, the input is negated before being converted to an integer. -| Ordinarily, the fixed-point input is simply rounded to an integer, with -| the inexact exception raised if the input cannot be represented exactly as -| an integer. However, if the fixed-point input is too large, the invalid -| exception is raised and the largest positive or negative integer is -| returned. -*----------------------------------------------------------------------------*/ - -static int64_t roundAndPackInt64(bool zSign, uint64_t absZ0, uint64_t absZ1, - float_status *status) -{ - int8_t roundingMode; - bool roundNearestEven, increment; - int64_t z; - - roundingMode = status->float_rounding_mode; - roundNearestEven = ( roundingMode == float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment = ((int64_t) absZ1 < 0); - break; - case float_round_to_zero: - increment = 0; - break; - case float_round_up: - increment = !zSign && absZ1; - break; - case float_round_down: - increment = zSign && absZ1; - break; - case float_round_to_odd: - increment = !(absZ0 & 1) && absZ1; - break; - default: - abort(); - } - if ( increment ) { - ++absZ0; - if ( absZ0 == 0 ) goto overflow; - if (!(absZ1 << 1) && roundNearestEven) { - absZ0 &= ~1; - } - } - z = absZ0; - if ( zSign ) z = - z; - if ( z && ( ( z < 0 ) ^ zSign ) ) { - overflow: - float_raise(float_flag_invalid, status); - return zSign ? INT64_MIN : INT64_MAX; - } - if (absZ1) { - float_raise(float_flag_inexact, status); - } - return z; - -} - /*---------------------------------------------------------------------------- | Normalizes the subnormal single-precision floating-point value represented | by the denormalized significand `aSig'. The normalized exponent and @@ -5488,179 +5409,6 @@ float64 float64_log2(float64 a, float_status *status) return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status); } -/*---------------------------------------------------------------------------- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the 32-bit two's complement integer format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic---which means in particular that the conversion -| is rounded according to the current rounding mode. If `a' is a NaN, the -| largest positive integer is returned. Otherwise, if the conversion -| overflows, the largest integer with the same sign as `a' is returned. -*----------------------------------------------------------------------------*/ - -int32_t floatx80_to_int32(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return 1 << 31; - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - if ( ( aExp == 0x7FFF ) && (uint64_t) ( aSig<<1 ) ) aSign = 0; - shiftCount = 0x4037 - aExp; - if ( shiftCount <= 0 ) shiftCount = 1; - shift64RightJamming( aSig, shiftCount, &aSig ); - return roundAndPackInt32(aSign, aSig, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the result of converting the extended double-precision floating- -| point value `a' to the 32-bit two's complement integer format. The -| conversion is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic, except that the conversion is always rounded -| toward zero. If `a' is a NaN, the largest positive integer is returned. -| Otherwise, if the conversion overflows, the largest integer with the same -| sign as `a' is returned. -*----------------------------------------------------------------------------*/ - -int32_t floatx80_to_int32_round_to_zero(floatx80 a, float_status *status) -{ - bool aSign; - int32_t aExp, shiftCount; - uint64_t aSig, savedASig; - int32_t z; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return 1 << 31; - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - if ( 0x401E < aExp ) { - if ( ( aExp == 0x7FFF ) && (uint64_t) ( aSig<<1 ) ) aSign = 0; - goto invalid; - } - else if ( aExp < 0x3FFF ) { - if (aExp || aSig) { - float_raise(float_flag_inexact, status); - } - return 0; - } - shiftCount = 0x403E - aExp; - savedASig = aSig; - aSig >>= shiftCount; - z = aSig; - if ( aSign ) z = - z; - if ( ( z < 0 ) ^ aSign ) { - invalid: - float_raise(float_flag_invalid, status); - return aSign ? (int32_t) 0x80000000 : 0x7FFFFFFF; - } - if ( ( aSig<>( - shiftCount ); - if ( (uint64_t) ( aSig<<( shiftCount & 63 ) ) ) { - float_raise(float_flag_inexact, status); - } - if ( aSign ) z = - z; - return z; - -} - /*---------------------------------------------------------------------------- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the From patchwork Sat May 8 01:47:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432576 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp864400jao; Fri, 7 May 2021 19:34:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzPw1wfqyfdKvGcIKrd29ymKWfZQbeBpRtTJcVuWDmzQqr3+QvIN+LiYGC12k8DDrKLwGm6 X-Received: by 2002:a02:8787:: with SMTP id t7mr2309368jai.53.1620441264207; Fri, 07 May 2021 19:34:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441264; cv=none; d=google.com; s=arc-20160816; b=oJKZ8sOYXztcEdUCRaLvZQOzqKhzA4yJF5F2HUj95JjuZM5CLkT/2scjN2bahKMkry FGlu3hgCLrAs4VhwNJj+QjuCm9qS2Fg2tIVYBH74Qp2/nOSo2cPqC3y72XyVF9Uynhfo KuyDekrgXIyD5+gbYO0y4i1VDDJioyaN0NXPzoN++Ii38QClmauDgkZnbyAIpCokVZUi PCAfGzku+jRccjGaUJ1VLo4pJjiP0Wh/N283eNZUQq2YAzmm2imdXFn9uMZxlKQeFiMk Y8P2ihnHzSgnrCnNZhicw1Rk582C6pnC4WmYDjCskCIyW2Um1c4c+ElXFlVzfxiNIdKy HgwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xRrqi4bmOzILqgbF3ktlxWwTxarrZ6yzbdF4Z3f3EcY=; b=bat00UuuSzbiuWHCFLFymZkNxLouMAZXtR0UM5HPwLi1yI3dARaRgAKHvARsnLW59m kw0MxY4uUpwHBYdTvadS7LHSgn+Ua7tC3vscePCjshrKfowASsWzE53u6x+9lx/ijYaF V+/yzQwgbeGzVui/1unOia2YEUNozZ/XPLYuLcztpYvPQ3KfyB2Z2/eMd9ZJgkHiUeX3 JyRnCzQKMzdOq9AjmXj+EHQUGd5Hu0gYHVhs/n8pnTMsaANmabGC9ZkvNRB3JWjjRoSQ /NnLowXmlMg7IMCtkjW6+38dznoLbJcBWTAqNpdChRrou2aGjy8ERuppLrMvr19yo0tH Jd8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R0VdEcuY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 07 May 2021 18:51:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 68/72] softfloat: Convert floatx80_scalbn to FloatParts Date: Fri, 7 May 2021 18:47:58 -0700 Message-Id: <20210508014802.892561-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 50 +++++++++++-------------------------------------- 1 file changed, 11 insertions(+), 39 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9f28c5c058..81ff563dc0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3913,6 +3913,17 @@ float128 float128_scalbn(float128 a, int n, float_status *status) return float128_round_pack_canonical(&p, status); } +floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) +{ + FloatParts128 p; + + if (!floatx80_unpack_canonical(&p, a, status)) { + return floatx80_default_nan(status); + } + parts_scalbn(&p, n, status); + return floatx80_round_pack_canonical(&p, status); +} + /* * Square Root */ @@ -5747,45 +5758,6 @@ FloatRelation floatx80_compare_quiet(floatx80 a, floatx80 b, return floatx80_compare_internal(a, b, 1, status); } -floatx80 floatx80_scalbn(floatx80 a, int n, float_status *status) -{ - bool aSign; - int32_t aExp; - uint64_t aSig; - - if (floatx80_invalid_encoding(a)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig = extractFloatx80Frac( a ); - aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - - if ( aExp == 0x7FFF ) { - if ( aSig<<1 ) { - return propagateFloatx80NaN(a, a, status); - } - return a; - } - - if (aExp == 0) { - if (aSig == 0) { - return a; - } - aExp++; - } - - if (n > 0x10000) { - n = 0x10000; - } else if (n < -0x10000) { - n = -0x10000; - } - - aExp += n; - return normalizeRoundAndPackFloatx80(status->floatx80_rounding_precision, - aSign, aExp, aSig, 0, status); -} - static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; From patchwork Sat May 8 01:47:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432591 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp869942jao; Fri, 7 May 2021 19:45:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRF6r4r2EW08XQMg8LWULwxXkHn9goMT+BT76BZIkKt95APyMay9Or0kCbjtFmmOgnzHKq X-Received: by 2002:a02:b398:: with SMTP id p24mr11875360jan.74.1620441903665; Fri, 07 May 2021 19:45:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441903; cv=none; d=google.com; s=arc-20160816; b=GTxGj3GzzBwcHCpB7dWQe1GaPjh2/UtoNko3IIQ17r+EnV7Ai9LZRrRduuTCWAT7WZ sXiOpEgJv8Tr8MKpc7qt6H1gw81dT55gAva/gpQPYn/X9++CxyZDiIRNMv/8PfKBu/25 g0ADZHOhSnf3NjfUudfoURGFs6QL2LtEz/3N2yaMa6XLPvtK8BS9njVusAEuLE48eNwA OHy6JK2aCvQqKChFdpGkzURtmICArO63I5sReEU2tGZoKaV3zddmjkh1v0S0ZEIvkiiq bpVdXBWf7zDHVDsDKbvSdxE7rqPaeqcXAtqQqCsxInAz4qxeqn4cFjpDvv/QBz2dPhyU 6Pgw== ARC-Message-Signature: i=1; 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Fri, 07 May 2021 18:51:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 69/72] softfloat: Convert floatx80 compare to FloatParts Date: Fri, 7 May 2021 18:47:59 -0700 Message-Id: <20210508014802.892561-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat.c | 82 +++++++++++++------------------------------------ 1 file changed, 22 insertions(+), 60 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 81ff563dc0..b89ec4b832 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3864,6 +3864,28 @@ FloatRelation float128_compare_quiet(float128 a, float128 b, float_status *s) return float128_do_compare(a, b, s, true); } +static FloatRelation QEMU_FLATTEN +floatx80_do_compare(floatx80 a, floatx80 b, float_status *s, bool is_quiet) +{ + FloatParts128 pa, pb; + + if (!floatx80_unpack_canonical(&pa, a, s) || + !floatx80_unpack_canonical(&pb, b, s)) { + return float_relation_unordered; + } + return parts_compare(&pa, &pb, s, is_quiet); +} + +FloatRelation floatx80_compare(floatx80 a, floatx80 b, float_status *s) +{ + return floatx80_do_compare(a, b, s, false); +} + +FloatRelation floatx80_compare_quiet(floatx80 a, floatx80 b, float_status *s) +{ + return floatx80_do_compare(a, b, s, true); +} + /* * Scale by 2**N */ @@ -5698,66 +5720,6 @@ float128 float128_rem(float128 a, float128 b, float_status *status) return normalizeRoundAndPackFloat128(aSign ^ zSign, bExp - 4, aSig0, aSig1, status); } - -static inline FloatRelation -floatx80_compare_internal(floatx80 a, floatx80 b, bool is_quiet, - float_status *status) -{ - bool aSign, bSign; - - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return float_relation_unordered; - } - if (( ( extractFloatx80Exp( a ) == 0x7fff ) && - ( extractFloatx80Frac( a )<<1 ) ) || - ( ( extractFloatx80Exp( b ) == 0x7fff ) && - ( extractFloatx80Frac( b )<<1 ) )) { - if (!is_quiet || - floatx80_is_signaling_nan(a, status) || - floatx80_is_signaling_nan(b, status)) { - float_raise(float_flag_invalid, status); - } - return float_relation_unordered; - } - aSign = extractFloatx80Sign( a ); - bSign = extractFloatx80Sign( b ); - if ( aSign != bSign ) { - - if ( ( ( (uint16_t) ( ( a.high | b.high ) << 1 ) ) == 0) && - ( ( a.low | b.low ) == 0 ) ) { - /* zero case */ - return float_relation_equal; - } else { - return 1 - (2 * aSign); - } - } else { - /* Normalize pseudo-denormals before comparison. */ - if ((a.high & 0x7fff) == 0 && a.low & UINT64_C(0x8000000000000000)) { - ++a.high; - } - if ((b.high & 0x7fff) == 0 && b.low & UINT64_C(0x8000000000000000)) { - ++b.high; - } - if (a.low == b.low && a.high == b.high) { - return float_relation_equal; - } else { - return 1 - 2 * (aSign ^ ( lt128( a.high, a.low, b.high, b.low ) )); - } - } -} - -FloatRelation floatx80_compare(floatx80 a, floatx80 b, float_status *status) -{ - return floatx80_compare_internal(a, b, 0, status); -} - -FloatRelation floatx80_compare_quiet(floatx80 a, floatx80 b, - float_status *status) -{ - return floatx80_compare_internal(a, b, 1, status); -} - static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; From patchwork Sat May 8 01:48:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432590 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp869883jao; Fri, 7 May 2021 19:44:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJqXNeszi3dCnBpdP7UvBaoroV71dUOkvj6YyvVkT0p25+mduehwr6kFlkrJvV6ox8aHr2 X-Received: by 2002:a05:6638:2643:: with SMTP id n3mr11606184jat.104.1620441897509; Fri, 07 May 2021 19:44:57 -0700 (PDT) ARC-Seal: i=1; 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Use muladd instead of separate mul+add. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 53 +++++++++++++++++++++---------------------------- 1 file changed, 23 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index b89ec4b832..906bb427ae 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -5212,47 +5212,40 @@ static const float64 float32_exp2_coefficients[15] = float32 float32_exp2(float32 a, float_status *status) { - bool aSign; - int aExp; - uint32_t aSig; - float64 r, x, xn; + FloatParts64 xp, xnp, tp, rp; int i; - a = float32_squash_input_denormal(a, status); - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - - if ( aExp == 0xFF) { - if (aSig) { - return propagateFloat32NaN(a, float32_zero, status); + float32_unpack_canonical(&xp, a, status); + if (unlikely(xp.cls != float_class_normal)) { + switch (xp.cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(&xp, status); + return float32_round_pack_canonical(&xp, status); + case float_class_inf: + return xp.sign ? float32_zero : a; + case float_class_zero: + return float32_one; + default: + break; } - return (aSign) ? float32_zero : a; - } - if (aExp == 0) { - if (aSig == 0) return float32_one; + g_assert_not_reached(); } float_raise(float_flag_inexact, status); - /* ******************************* */ - /* using float64 for approximation */ - /* ******************************* */ - x = float32_to_float64(a, status); - x = float64_mul(x, float64_ln2, status); + float64_unpack_canonical(&xnp, float64_ln2, status); + xp = *parts_mul(&xp, &tp, status); + xnp = xp; - xn = x; - r = float64_one; + float64_unpack_canonical(&rp, float64_one, status); for (i = 0 ; i < 15 ; i++) { - float64 f; - - f = float64_mul(xn, float32_exp2_coefficients[i], status); - r = float64_add(r, f, status); - - xn = float64_mul(xn, x, status); + float64_unpack_canonical(&tp, float32_exp2_coefficients[i], status); + rp = *parts_muladd(&tp, &xp, &rp, 0, status); + xnp = *parts_mul(&xnp, &xp, status); } - return float64_to_float32(r, status); + return float32_round_pack_canonical(&rp, status); } /*---------------------------------------------------------------------------- From patchwork Sat May 8 01:48:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432585 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp867474jao; Fri, 7 May 2021 19:40:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqXO0c+BYq0ACTF3sXDT938Mf4hTCVhxNDOUMBKYGEJDJLPIB3LaVuODIsR9zJ7hxk6Z+B X-Received: by 2002:a5d:960d:: with SMTP id w13mr9664802iol.126.1620441618707; Fri, 07 May 2021 19:40:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441618; cv=none; d=google.com; s=arc-20160816; b=vkBZFTJC4jj++OYHGq2nOtcOLerXSJ/y7cS1arJ9BteEnqDBgNuisU1y3rQotTzz4b jLhpxHgHwzPrhnPJshK6AEniBtpDc5IyaT5F4dyauIwURghHHV3wRZMMIg1LrkwgO8IA yxEJ84aXBHul1py8QGwb0qO7hadnrcsqHzeFcZ0ZaRwvw8e8NENEJwgzX0l8eklrpHCb Jzl2JefiWwQv5I617+KL2FvLaQI06Sb6dIGNJQ1c/gJwcPIXepyGcJd454obwVjKPVrG Begm/tLGjuFfqifCQTWyd5k4ghXTRqXCm3AKpqrX757zkCLBh5EjW/Efrvox2H2jNRer /ORg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HKpES++YzydctcZZ/K52SO5JvpywviZhDsWevoMxn68=; b=zpYE5ZQ6EtPi+6/9k/2rSvQWeqff7E9oy51Wm+ehT9lTpfwv9kWu7f8CIrRmLAsciC IK1csgo2fvvZgBmFEzCc3R/2tc/h9RccZ90T35Cv7TTLGrlKZKZRyhkJ8ak5T6UvZWrC x8cBwu9w6tNEzDIEPq6XohNous0ePiDjHHkBb9VUNj3xBsf4BA+VhySMOVh+k6aupzDY 6qZivtbTaIxwDheXYxJ07f69lFh39t7nfuy+lJIcuAKp3KrE34LNCFAWiYke/wRVjmIX 4nx+vImAR6bhzAZGT1/cI2IuEHalvGX6LvFfVOCgqNOFQJS1pJc3DpB+LXj4MsWPyH3I Vwzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dhbsNS2p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r9si7958622ilo.79.2021.05.07.19.40.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 May 2021 19:40:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dhbsNS2p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lfCt8-00081f-1O for patch@linaro.org; Fri, 07 May 2021 22:40:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lfC8S-0003YA-C5 for qemu-devel@nongnu.org; Fri, 07 May 2021 21:52:04 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:37594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lfC8F-0005bT-5E for qemu-devel@nongnu.org; Fri, 07 May 2021 21:52:04 -0400 Received: by mail-pg1-x535.google.com with SMTP id d29so8636759pgd.4 for ; Fri, 07 May 2021 18:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HKpES++YzydctcZZ/K52SO5JvpywviZhDsWevoMxn68=; b=dhbsNS2pnUX+XkgIxVOtkVOcYTqsAfl19HlAuHSweUEzo4iEhXW80iETDALkH1ppFG vVSo8ZBzmfzA98wcjn80c2KEMy65Zx5iOkbqcTdoMhPpeROLGLrqdRXqUUuWCdbcSREw PwhmlCtTyKLTOIKvwCdTViGbgSa2Bt2MTY+yGe44tJflm1SQZTzpnGJMkfEIZuQf/3L3 a/Lul1riH/MAcICyogAi+r5ZKvlRtnfumvmCXHEVncpc+Idh7sZ0hIIx01RFRMsXyioj k0vRFkq/9Aci8x360cdIYE0EQhxFTWK0nQ656jH66vZMza4w0YMDxZl2QdyDv6O+amEo SgiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HKpES++YzydctcZZ/K52SO5JvpywviZhDsWevoMxn68=; b=nQ85beENOLuH/cd4ZcCM1fOp2RD944UoEICnLKtZ0DKbgeQj3B/LsgmQ3iu9nXD37c 1wykb71krO5ePsguPpJTbqXe3iKYc27GtlTUmT1XOkZPYSX2pu8gDhDcN5svD58RtNii 00v6ICw8ZzvNuV6n2y7W39odeV0T3iUID/bbidFsTmqYtoj8RBv4OI3ZEzECtXohJo/j 0OJjqaKThcQ+NdaKgUlY86HccGmKE2fXfSYJYBtyRzoQNdDk6ReqfkakqWLWIW2vVm64 7mqn64n6+nImF6vZYMoiUy+RXIYKJYvUW5yoIFB6PhAtTeSv5RP9ILysi17/kDSZnCdx HpSQ== X-Gm-Message-State: AOAM531IRjAs9C7pJd+MHUjgegryjFFoYG3SLZOwOolW+qoXnhvq13SC HpztjtFulNYlscXT/HsE95ZniDH7VFDGQg== X-Received: by 2002:a63:e515:: with SMTP id r21mr13014531pgh.412.1620438709678; Fri, 07 May 2021 18:51:49 -0700 (PDT) Received: from localhost.localdomain ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id 204sm5861396pfw.158.2021.05.07.18.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 May 2021 18:51:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 71/72] softfloat: Move floatN_log2 to softfloat-parts.c.inc Date: Fri, 7 May 2021 18:48:01 -0700 Message-Id: <20210508014802.892561-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210508014802.892561-1-richard.henderson@linaro.org> References: <20210508014802.892561-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename to parts$N_log2. Though this is partly a ruse, since I do not believe the code will succeed for float128 without work. Which is ok for now, because we do not need this for more than float32 and float64. Since berkeley-testfloat-3 doesn't support log2, compare float64_log2 vs the system log2. Fix the errors for inputs near 1.0: test: 3ff00000000000b0 +0x1.00000000000b0p+0 sf: 3d2fa00000000000 +0x1.fa00000000000p-45 libm: 3d2fbd422b1bd36f +0x1.fbd422b1bd36fp-45 Error in fraction: 32170028290927 ulp test: 3feec24f6770b100 +0x1.ec24f6770b100p-1 sf: bfad3740d13c9ec0 -0x1.d3740d13c9ec0p-5 libm: bfad3740d13c9e98 -0x1.d3740d13c9e98p-5 Error in fraction: 40 ulp Signed-off-by: Richard Henderson --- fpu/softfloat.c | 126 ++++++++------------------------------ tests/fp/fp-test-log2.c | 118 +++++++++++++++++++++++++++++++++++ fpu/softfloat-parts.c.inc | 125 +++++++++++++++++++++++++++++++++++++ tests/fp/meson.build | 11 ++++ 4 files changed, 281 insertions(+), 99 deletions(-) create mode 100644 tests/fp/fp-test-log2.c -- 2.25.1 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 906bb427ae..3823a7ec6f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -926,6 +926,12 @@ static void parts128_scalbn(FloatParts128 *a, int n, float_status *s); #define parts_scalbn(A, N, S) \ PARTS_GENERIC_64_128(scalbn, A)(A, N, S) +static void parts64_log2(FloatParts64 *a, float_status *s, const FloatFmt *f); +static void parts128_log2(FloatParts128 *a, float_status *s, const FloatFmt *f); + +#define parts_log2(A, S, F) \ + PARTS_GENERIC_64_128(log2, A)(A, S, F) + /* * Helper functions for softfloat-parts.c.inc, per-size operations. */ @@ -4062,6 +4068,27 @@ floatx80 floatx80_sqrt(floatx80 a, float_status *s) return floatx80_round_pack_canonical(&p, s); } +/* + * log2 + */ +float32 float32_log2(float32 a, float_status *status) +{ + FloatParts64 p; + + float32_unpack_canonical(&p, a, status); + parts_log2(&p, status, &float32_params); + return float32_round_pack_canonical(&p, status); +} + +float64 float64_log2(float64 a, float_status *status) +{ + FloatParts64 p; + + float64_unpack_canonical(&p, a, status); + parts_log2(&p, status, &float64_params); + return float64_round_pack_canonical(&p, status); +} + /*---------------------------------------------------------------------------- | The pattern for a default generated NaN. *----------------------------------------------------------------------------*/ @@ -5248,56 +5275,6 @@ float32 float32_exp2(float32 a, float_status *status) return float32_round_pack_canonical(&rp, status); } -/*---------------------------------------------------------------------------- -| Returns the binary log of the single-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ -float32 float32_log2(float32 a, float_status *status) -{ - bool aSign, zSign; - int aExp; - uint32_t aSig, zSig, i; - - a = float32_squash_input_denormal(a, status); - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat32( 1, 0xFF, 0 ); - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - if ( aSign ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - if ( aExp == 0xFF ) { - if (aSig) { - return propagateFloat32NaN(a, float32_zero, status); - } - return a; - } - - aExp -= 0x7F; - aSig |= 0x00800000; - zSign = aExp < 0; - zSig = aExp << 23; - - for (i = 1 << 22; i > 0; i >>= 1) { - aSig = ( (uint64_t)aSig * aSig ) >> 23; - if ( aSig & 0x01000000 ) { - aSig >>= 1; - zSig |= i; - } - } - - if ( zSign ) - zSig = -zSig; - - return normalizeRoundAndPackFloat32(zSign, 0x85, zSig, status); -} - /*---------------------------------------------------------------------------- | Returns the remainder of the double-precision floating-point value `a' | with respect to the corresponding value `b'. The operation is performed @@ -5386,55 +5363,6 @@ float64 float64_rem(float64 a, float64 b, float_status *status) } -/*---------------------------------------------------------------------------- -| Returns the binary log of the double-precision floating-point value `a'. -| The operation is performed according to the IEC/IEEE Standard for Binary -| Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ -float64 float64_log2(float64 a, float_status *status) -{ - bool aSign, zSign; - int aExp; - uint64_t aSig, aSig0, aSig1, zSig, i; - a = float64_squash_input_denormal(a, status); - - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - - if ( aExp == 0 ) { - if ( aSig == 0 ) return packFloat64( 1, 0x7FF, 0 ); - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - if ( aSign ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - if ( aExp == 0x7FF ) { - if (aSig) { - return propagateFloat64NaN(a, float64_zero, status); - } - return a; - } - - aExp -= 0x3FF; - aSig |= UINT64_C(0x0010000000000000); - zSign = aExp < 0; - zSig = (uint64_t)aExp << 52; - for (i = 1LL << 51; i > 0; i >>= 1) { - mul64To128( aSig, aSig, &aSig0, &aSig1 ); - aSig = ( aSig0 << 12 ) | ( aSig1 >> 52 ); - if ( aSig & UINT64_C(0x0020000000000000) ) { - aSig >>= 1; - zSig |= i; - } - } - - if ( zSign ) - zSig = -zSig; - return normalizeRoundAndPackFloat64(zSign, 0x408, zSig, status); -} - /*---------------------------------------------------------------------------- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c new file mode 100644 index 0000000000..8ad856509b --- /dev/null +++ b/tests/fp/fp-test-log2.c @@ -0,0 +1,118 @@ +/* + * fp-test-log2.c - test QEMU's softfloat log2 + * + * Copyright (C) 2020, Linaro, Ltd. + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef HW_POISON_H +#error Must define HW_POISON_H to work around TARGET_* poisoning +#endif + +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include +#include "fpu/softfloat.h" + +typedef union { + double d; + float64 i; +} ufloat64; + +static int errors; + +static void compare(ufloat64 test, ufloat64 real, ufloat64 soft, bool exact) +{ + int msb; + uint64_t ulp = UINT64_MAX; + + if (real.i == soft.i) { + return; + } + msb = 63 - __builtin_clzll(real.i ^ soft.i); + + if (msb < 52) { + if (real.i > soft.i) { + ulp = real.i - soft.i; + } else { + ulp = soft.i - real.i; + } + } + + /* glibc allows 3 ulp error in its libm-test-ulps; allow 4 here */ + if (!exact && ulp <= 4) { + return; + } + + printf("test: %016" PRIx64 " %+.13a\n" + " sf: %016" PRIx64 " %+.13a\n" + "libm: %016" PRIx64 " %+.13a\n", + test.i, test.d, soft.i, soft.d, real.i, real.d); + + if (msb == 63) { + printf("Error in sign!\n\n"); + } else if (msb >= 52) { + printf("Error in exponent: %d\n\n", + (int)(soft.i >> 52) - (int)(real.i >> 52)); + } else { + printf("Error in fraction: %" PRIu64 " ulp\n\n", ulp); + } + + if (++errors == 20) { + exit(1); + } +} + +int main(int ac, char **av) +{ + ufloat64 test, real, soft; + float_status qsf = {0}; + int i; + + set_float_rounding_mode(float_round_nearest_even, &qsf); + + test.d = 0.0; + real.d = -__builtin_inf(); + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d = 1.0; + real.d = 0.0; + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d = 2.0; + real.d = 1.0; + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d = 4.0; + real.d = 2.0; + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d = 0x1p64; + real.d = 64.0; + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + test.d = __builtin_inf(); + real.d = __builtin_inf(); + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, true); + + for (i = 0; i < 10000; ++i) { + test.d = drand48() + 1.0; /* [1.0, 2.0) */ + real.d = log2(test.d); + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, false); + + test.d = drand48() * 100; /* [0.0, 100) */ + real.d = log2(test.d); + soft.i = float64_log2(test.i, &qsf); + compare(test, real, soft, false); + } + + return 0; +} diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index c18f77f2cf..3659c6a4c0 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1319,3 +1319,128 @@ static void partsN(scalbn)(FloatPartsN *a, int n, float_status *s) g_assert_not_reached(); } } + +/* + * Return log2(A) + */ +static void partsN(log2)(FloatPartsN *a, float_status *s, const FloatFmt *fmt) +{ + uint64_t a0, a1, r, t, ign; + FloatPartsN f; + int i, n, a_exp, f_exp; + + if (unlikely(a->cls != float_class_normal)) { + switch (a->cls) { + case float_class_snan: + case float_class_qnan: + parts_return_nan(a, s); + return; + case float_class_zero: + /* log2(0) = -inf */ + a->cls = float_class_inf; + a->sign = 1; + return; + case float_class_inf: + if (unlikely(a->sign)) { + goto d_nan; + } + return; + default: + break; + } + g_assert_not_reached(); + } + if (unlikely(a->sign)) { + goto d_nan; + } + + /* TODO: This algorithm looses bits too quickly for float128. */ + g_assert(N == 64); + + a_exp = a->exp; + f_exp = -1; + + r = 0; + t = DECOMPOSED_IMPLICIT_BIT; + a0 = a->frac_hi; + a1 = 0; + + n = fmt->frac_size + 2; + if (unlikely(a_exp == -1)) { + /* + * When a_exp == -1, we're computing the log2 of a value [0.5,1.0). + * When the value is very close to 1.0, there are lots of 1's in + * the msb parts of the fraction. At the end, when we subtract + * this value from -1.0, we can see a catastrophic loss of precision, + * as 0x800..000 - 0x7ff..ffx becomes 0x000..00y, leaving only the + * bits of y in the final result. To minimize this, compute as many + * digits as we can. + * ??? This case needs another algorithm to avoid this. + */ + n = fmt->frac_size * 2 + 2; + /* Don't compute a value overlapping the sticky bit */ + n = MIN(n, 62); + } + + for (i = 0; i < n; i++) { + if (a1) { + mul128To256(a0, a1, a0, a1, &a0, &a1, &ign, &ign); + } else if (a0 & 0xffffffffull) { + mul64To128(a0, a0, &a0, &a1); + } else if (a0 & ~DECOMPOSED_IMPLICIT_BIT) { + a0 >>= 32; + a0 *= a0; + } else { + goto exact; + } + + if (a0 & DECOMPOSED_IMPLICIT_BIT) { + if (unlikely(a_exp == 0 && r == 0)) { + /* + * When a_exp == 0, we're computing the log2 of a value + * [1.0,2.0). When the value is very close to 1.0, there + * are lots of 0's in the msb parts of the fraction. + * We need to compute more digits to produce a correct + * result -- restart at the top of the fraction. + * ??? This is likely to lose precision quickly, as for + * float128; we may need another method. + */ + f_exp -= i; + t = r = DECOMPOSED_IMPLICIT_BIT; + i = 0; + } else { + r |= t; + } + } else { + add128(a0, a1, a0, a1, &a0, &a1); + } + t >>= 1; + } + + /* Set sticky for inexact. */ + r |= (a1 || a0 & ~DECOMPOSED_IMPLICIT_BIT); + + exact: + parts_sint_to_float(a, a_exp, 0, s); + if (r == 0) { + return; + } + + memset(&f, 0, sizeof(f)); + f.cls = float_class_normal; + f.frac_hi = r; + f.exp = f_exp - frac_normalize(&f); + + if (a_exp < 0) { + parts_sub_normal(a, &f); + } else if (a_exp > 0) { + parts_add_normal(a, &f); + } else { + *a = f; + } + return; + + d_nan: + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); +} diff --git a/tests/fp/meson.build b/tests/fp/meson.build index 1c3eee9955..9218bfd3b0 100644 --- a/tests/fp/meson.build +++ b/tests/fp/meson.build @@ -634,3 +634,14 @@ fpbench = executable( include_directories: [sfinc, include_directories(tfdir)], c_args: fpcflags, ) + +fptestlog2 = executable( + 'fp-test-log2', + ['fp-test-log2.c', '../../fpu/softfloat.c'], + link_with: [libsoftfloat], + dependencies: [qemuutil], + include_directories: [sfinc], + c_args: fpcflags, +) +test('fp-test-log2', fptestlog2, + suite: ['softfloat', 'softfloat-ops']) From patchwork Sat May 8 01:48:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 432586 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp868490jao; Fri, 7 May 2021 19:42:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx3WI8CaMonMtO2Iws8KG1Dp+GzFRojW7bM3pwq/Ix8T0ndVwFkAUeGrLayJNZUZlMYArS2 X-Received: by 2002:a05:6638:37a6:: with SMTP id w38mr11515390jal.106.1620441747563; Fri, 07 May 2021 19:42:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620441747; cv=none; d=google.com; s=arc-20160816; b=PK91WUadgvTAV2pnjNRQYOK1/DX5WX/Ww4N5/Fmi7XzKfusI9LYAg4uFgYOwTQmHMb qRyy4Gqv7dWz38BjU/MLYBea8T28uq3kFX0MOUTN+TQ4JoQnMcYeDyQVSBpISjpIGnww 0Pa60qDmqZ9/LB+XxUqZ55uMW8HULJiGenMBYGLtUqcr1+OpHp0oN5tYPj8duGw87jaj 6Pwc8FiD+QE/YUpT+DlAXYTKUPrt3khn65XWWPqpVuQZ7AOc1ag5ZE+nO96ybZeWNGuj nC9lVnHAxW9iKjlyFd/zHAcSEFw/MzmXEQoBQS/TDQHqYVcIljWO6w5IDdGugLFEtfsz X5qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jyFTCsiIz4vQ/b29mHqKyxCY82vLhUnZ9Ckfj2MLd9w=; b=EC/0be4Tr+78jzC09MWLQpCRAPYo4OiT1hrv2mD7jBysMJRRj9eXV91OM9imOw0j4H dCD0uSSB7nLXfSS8PGXgN38vAhNemUxKylT9NhWrBFxWvi5TVSybKMoxS1filsUhNSOg WuFWSRRe1XZk/R6s0XhhKVp4uoXIQMTVX1+myIX7RScQRZFVRYJe4sEqfNdLGtbq3cJ7 8zQBCr2fJYth25FSIZ6cIbbFSy/O6k3lqYEH1Kih8JCJSCHvfJxQ7NgdGXeP8g2GOlpj S6GHUEYYGnt0YMQqyNlNd0FoRQM4tG1BIaLRjRQierBCqbmR0QSiRlwcrnCDEA+q774b fA+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=K5Ouhzh5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This was the last use of a lot of the legacy infrastructure, so remove it as required. Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 34 + fpu/softfloat.c | 1339 +++++++------------------------- fpu/softfloat-parts.c.inc | 34 + fpu/softfloat-specialize.c.inc | 165 ---- 4 files changed, 329 insertions(+), 1243 deletions(-) -- 2.25.1 diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index ec4e27a595..81c3fe8256 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -745,4 +745,38 @@ static inline bool ne128(uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1) return a0 != b0 || a1 != b1; } +/* + * Similarly, comparisons of 192-bit values. + */ + +static inline bool eq192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2) +{ + return ((a0 ^ b0) | (a1 ^ b1) | (a2 ^ b2)) == 0; +} + +static inline bool le192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2) +{ + if (a0 != b0) { + return a0 < b0; + } + if (a1 != b1) { + return a1 < b1; + } + return a2 <= b2; +} + +static inline bool lt192(uint64_t a0, uint64_t a1, uint64_t a2, + uint64_t b0, uint64_t b1, uint64_t b2) +{ + if (a0 != b0) { + return a0 < b0; + } + if (a1 != b1) { + return a1 < b1; + } + return a2 < b2; +} + #endif diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 3823a7ec6f..7376b3470c 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -401,60 +401,6 @@ float64_gen2(float64 xa, float64 xb, float_status *s, return soft(ua.s, ub.s, s); } -/*---------------------------------------------------------------------------- -| Returns the fraction bits of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline uint32_t extractFloat32Frac(float32 a) -{ - return float32_val(a) & 0x007FFFFF; -} - -/*---------------------------------------------------------------------------- -| Returns the exponent bits of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline int extractFloat32Exp(float32 a) -{ - return (float32_val(a) >> 23) & 0xFF; -} - -/*---------------------------------------------------------------------------- -| Returns the sign bit of the single-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline bool extractFloat32Sign(float32 a) -{ - return float32_val(a) >> 31; -} - -/*---------------------------------------------------------------------------- -| Returns the fraction bits of the double-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline uint64_t extractFloat64Frac(float64 a) -{ - return float64_val(a) & UINT64_C(0x000FFFFFFFFFFFFF); -} - -/*---------------------------------------------------------------------------- -| Returns the exponent bits of the double-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline int extractFloat64Exp(float64 a) -{ - return (float64_val(a) >> 52) & 0x7FF; -} - -/*---------------------------------------------------------------------------- -| Returns the sign bit of the double-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline bool extractFloat64Sign(float64 a) -{ - return float64_val(a) >> 63; -} - /* * Classify a floating point number. Everything above float_class_qnan * is a NaN so cls >= float_class_qnan is any NaN. @@ -844,6 +790,14 @@ static FloatParts128 *parts128_div(FloatParts128 *a, FloatParts128 *b, #define parts_div(A, B, S) \ PARTS_GENERIC_64_128(div, A)(A, B, S) +static FloatParts64 *parts64_modrem(FloatParts64 *a, FloatParts64 *b, + uint64_t *mod_quot, float_status *s); +static FloatParts128 *parts128_modrem(FloatParts128 *a, FloatParts128 *b, + uint64_t *mod_quot, float_status *s); + +#define parts_modrem(A, B, Q, S) \ + PARTS_GENERIC_64_128(modrem, A)(A, B, Q, S) + static void parts64_sqrt(FloatParts64 *a, float_status *s, const FloatFmt *f); static void parts128_sqrt(FloatParts128 *a, float_status *s, const FloatFmt *f); @@ -1228,6 +1182,186 @@ static int frac256_normalize(FloatParts256 *a) #define frac_normalize(A) FRAC_GENERIC_64_128_256(normalize, A)(A) +static void frac64_modrem(FloatParts64 *a, FloatParts64 *b, uint64_t *mod_quot) +{ + uint64_t a0, a1, b0, t0, t1, q, quot; + int exp_diff = a->exp - b->exp; + int shift; + + a0 = a->frac; + a1 = 0; + + if (exp_diff < -1) { + if (mod_quot) { + *mod_quot = 0; + } + return; + } + if (exp_diff == -1) { + a0 >>= 1; + exp_diff = 0; + } + + b0 = b->frac; + quot = q = b0 <= a0; + if (q) { + a0 -= b0; + } + + exp_diff -= 64; + while (exp_diff > 0) { + q = estimateDiv128To64(a0, a1, b0); + q = q > 2 ? q - 2 : 0; + mul64To128(b0, q, &t0, &t1); + sub128(a0, a1, t0, t1, &a0, &a1); + shortShift128Left(a0, a1, 62, &a0, &a1); + exp_diff -= 62; + quot = (quot << 62) + q; + } + + exp_diff += 64; + if (exp_diff > 0) { + q = estimateDiv128To64(a0, a1, b0); + q = q > 2 ? (q - 2) >> (64 - exp_diff) : 0; + mul64To128(b0, q << (64 - exp_diff), &t0, &t1); + sub128(a0, a1, t0, t1, &a0, &a1); + shortShift128Left(0, b0, 64 - exp_diff, &t0, &t1); + while (le128(t0, t1, a0, a1)) { + ++q; + sub128(a0, a1, t0, t1, &a0, &a1); + } + quot = (exp_diff < 64 ? quot << exp_diff : 0) + q; + } else { + t0 = b0; + t1 = 0; + } + + if (mod_quot) { + *mod_quot = quot; + } else { + sub128(t0, t1, a0, a1, &t0, &t1); + if (lt128(t0, t1, a0, a1) || + (eq128(t0, t1, a0, a1) && (q & 1))) { + a0 = t0; + a1 = t1; + a->sign = !a->sign; + } + } + + if (likely(a0)) { + shift = clz64(a0); + shortShift128Left(a0, a1, shift, &a0, &a1); + } else if (likely(a1)) { + shift = clz64(a1); + a0 = a1 << shift; + a1 = 0; + shift += 64; + } else { + a->cls = float_class_zero; + return; + } + + a->exp = b->exp + exp_diff - shift; + a->frac = a0 | (a1 != 0); +} + +static void frac128_modrem(FloatParts128 *a, FloatParts128 *b, + uint64_t *mod_quot) +{ + uint64_t a0, a1, a2, b0, b1, t0, t1, t2, q, quot; + int exp_diff = a->exp - b->exp; + int shift; + + a0 = a->frac_hi; + a1 = a->frac_lo; + a2 = 0; + + if (exp_diff < -1) { + if (mod_quot) { + *mod_quot = 0; + } + return; + } + if (exp_diff == -1) { + shift128Right(a0, a1, 1, &a0, &a1); + exp_diff = 0; + } + + b0 = b->frac_hi; + b1 = b->frac_lo; + + quot = q = le128(b0, b1, a0, a1); + if (q) { + sub128(a0, a1, b0, b1, &a0, &a1); + } + + exp_diff -= 64; + while (exp_diff > 0) { + q = estimateDiv128To64(a0, a1, b0); + q = q > 4 ? q - 4 : 0; + mul128By64To192(b0, b1, q, &t0, &t1, &t2); + sub192(a0, a1, a2, t0, t1, t2, &a0, &a1, &a2); + shortShift192Left(a0, a1, a2, 61, &a0, &a1, &a2); + exp_diff -= 61; + quot = (quot << 61) + q; + } + + exp_diff += 64; + if (exp_diff > 0) { + q = estimateDiv128To64(a0, a1, b0); + q = q > 4 ? (q - 4) >> (64 - exp_diff) : 0; + mul128By64To192(b0, b1, q << (64 - exp_diff), &t0, &t1, &t2); + sub192(a0, a1, a2, t0, t1, t2, &a0, &a1, &a2); + shortShift192Left(0, b0, b1, 64 - exp_diff, &t0, &t1, &t2); + while (le192(t0, t1, t2, a0, a1, a2)) { + ++q; + sub192(a0, a1, a2, t0, t1, t2, &a0, &a1, &a2); + } + quot = (exp_diff < 64 ? quot << exp_diff : 0) + q; + } else { + t0 = b0; + t1 = b1; + t2 = 0; + } + + if (mod_quot) { + *mod_quot = quot; + } else { + sub192(t0, t1, t2, a0, a1, a2, &t0, &t1, &t2); + if (lt192(t0, t1, t2, a0, a1, a2) || + (eq192(t0, t1, t2, a0, a1, a2) && (q & 1))) { + a0 = t0; + a1 = t1; + a2 = t2; + a->sign = !a->sign; + } + } + + if (likely(a0)) { + shift = clz64(a0); + shortShift192Left(a0, a1, a2, shift, &a0, &a1, &a2); + } else if (likely(a1)) { + shift = clz64(a1); + shortShift128Left(a1, a2, shift, &a0, &a1); + a2 = 0; + shift += 64; + } else if (likely(a2)) { + shift = clz64(a2); + a0 = a2 << shift; + a1 = a2 = 0; + shift += 128; + } else { + a->cls = float_class_zero; + return; + } + + a->exp = b->exp + exp_diff - shift; + a->frac_hi = a0; + a->frac_lo = a1 | (a2 != 0); +} + +#define frac_modrem(A, B, Q) FRAC_GENERIC_64_128(modrem, A)(A, B, Q) + static void frac64_shl(FloatParts64 *a, int c) { a->frac <<= c; @@ -2312,6 +2446,79 @@ floatx80 floatx80_div(floatx80 a, floatx80 b, float_status *status) return floatx80_round_pack_canonical(pr, status); } +/* + * Remainder + */ + +float32 float32_rem(float32 a, float32 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float32_unpack_canonical(&pa, a, status); + float32_unpack_canonical(&pb, b, status); + pr = parts_modrem(&pa, &pb, NULL, status); + + return float32_round_pack_canonical(pr, status); +} + +float64 float64_rem(float64 a, float64 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = parts_modrem(&pa, &pb, NULL, status); + + return float64_round_pack_canonical(pr, status); +} + +float128 float128_rem(float128 a, float128 b, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + float128_unpack_canonical(&pa, a, status); + float128_unpack_canonical(&pb, b, status); + pr = parts_modrem(&pa, &pb, NULL, status); + + return float128_round_pack_canonical(pr, status); +} + +/* + * Returns the remainder of the extended double-precision floating-point value + * `a' with respect to the corresponding value `b'. + * If 'mod' is false, the operation is performed according to the IEC/IEEE + * Standard for Binary Floating-Point Arithmetic. If 'mod' is true, return + * the remainder based on truncating the quotient toward zero instead and + * *quotient is set to the low 64 bits of the absolute value of the integer + * quotient. + */ +floatx80 floatx80_modrem(floatx80 a, floatx80 b, bool mod, + uint64_t *quotient, float_status *status) +{ + FloatParts128 pa, pb, *pr; + + *quotient = 0; + if (!floatx80_unpack_canonical(&pa, a, status) || + !floatx80_unpack_canonical(&pb, b, status)) { + return floatx80_default_nan(status); + } + pr = parts_modrem(&pa, &pb, mod ? quotient : NULL, status); + + return floatx80_round_pack_canonical(pr, status); +} + +floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status) +{ + uint64_t quotient; + return floatx80_modrem(a, b, false, "ient, status); +} + +floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) +{ + uint64_t quotient; + return floatx80_modrem(a, b, true, "ient, status); +} + /* * Float to Float conversions * @@ -4264,300 +4471,6 @@ bfloat16 bfloat16_squash_input_denormal(bfloat16 a, float_status *status) return a; } -/*---------------------------------------------------------------------------- -| Normalizes the subnormal single-precision floating-point value represented -| by the denormalized significand `aSig'. The normalized exponent and -| significand are stored at the locations pointed to by `zExpPtr' and -| `zSigPtr', respectively. -*----------------------------------------------------------------------------*/ - -static void - normalizeFloat32Subnormal(uint32_t aSig, int *zExpPtr, uint32_t *zSigPtr) -{ - int8_t shiftCount; - - shiftCount = clz32(aSig) - 8; - *zSigPtr = aSig<float_rounding_mode; - roundNearestEven = ( roundingMode == float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - roundIncrement = 0x40; - break; - case float_round_to_zero: - roundIncrement = 0; - break; - case float_round_up: - roundIncrement = zSign ? 0 : 0x7f; - break; - case float_round_down: - roundIncrement = zSign ? 0x7f : 0; - break; - case float_round_to_odd: - roundIncrement = zSig & 0x80 ? 0 : 0x7f; - break; - default: - abort(); - break; - } - roundBits = zSig & 0x7F; - if ( 0xFD <= (uint16_t) zExp ) { - if ( ( 0xFD < zExp ) - || ( ( zExp == 0xFD ) - && ( (int32_t) ( zSig + roundIncrement ) < 0 ) ) - ) { - bool overflow_to_inf = roundingMode != float_round_to_odd && - roundIncrement != 0; - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat32(zSign, 0xFF, -!overflow_to_inf); - } - if ( zExp < 0 ) { - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat32(zSign, 0, 0); - } - isTiny = status->tininess_before_rounding - || (zExp < -1) - || (zSig + roundIncrement < 0x80000000); - shift32RightJamming( zSig, - zExp, &zSig ); - zExp = 0; - roundBits = zSig & 0x7F; - if (isTiny && roundBits) { - float_raise(float_flag_underflow, status); - } - if (roundingMode == float_round_to_odd) { - /* - * For round-to-odd case, the roundIncrement depends on - * zSig which just changed. - */ - roundIncrement = zSig & 0x80 ? 0 : 0x7f; - } - } - } - if (roundBits) { - float_raise(float_flag_inexact, status); - } - zSig = ( zSig + roundIncrement )>>7; - if (!(roundBits ^ 0x40) && roundNearestEven) { - zSig &= ~1; - } - if ( zSig == 0 ) zExp = 0; - return packFloat32( zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Takes an abstract floating-point value having sign `zSign', exponent `zExp', -| and significand `zSig', and returns the proper single-precision floating- -| point value corresponding to the abstract input. This routine is just like -| `roundAndPackFloat32' except that `zSig' does not have to be normalized. -| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true'' -| floating-point exponent. -*----------------------------------------------------------------------------*/ - -static float32 - normalizeRoundAndPackFloat32(bool zSign, int zExp, uint32_t zSig, - float_status *status) -{ - int8_t shiftCount; - - shiftCount = clz32(zSig) - 1; - return roundAndPackFloat32(zSign, zExp - shiftCount, zSig<float_rounding_mode; - roundNearestEven = ( roundingMode == float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - roundIncrement = 0x200; - break; - case float_round_to_zero: - roundIncrement = 0; - break; - case float_round_up: - roundIncrement = zSign ? 0 : 0x3ff; - break; - case float_round_down: - roundIncrement = zSign ? 0x3ff : 0; - break; - case float_round_to_odd: - roundIncrement = (zSig & 0x400) ? 0 : 0x3ff; - break; - default: - abort(); - } - roundBits = zSig & 0x3FF; - if ( 0x7FD <= (uint16_t) zExp ) { - if ( ( 0x7FD < zExp ) - || ( ( zExp == 0x7FD ) - && ( (int64_t) ( zSig + roundIncrement ) < 0 ) ) - ) { - bool overflow_to_inf = roundingMode != float_round_to_odd && - roundIncrement != 0; - float_raise(float_flag_overflow | float_flag_inexact, status); - return packFloat64(zSign, 0x7FF, -(!overflow_to_inf)); - } - if ( zExp < 0 ) { - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat64(zSign, 0, 0); - } - isTiny = status->tininess_before_rounding - || (zExp < -1) - || (zSig + roundIncrement < UINT64_C(0x8000000000000000)); - shift64RightJamming( zSig, - zExp, &zSig ); - zExp = 0; - roundBits = zSig & 0x3FF; - if (isTiny && roundBits) { - float_raise(float_flag_underflow, status); - } - if (roundingMode == float_round_to_odd) { - /* - * For round-to-odd case, the roundIncrement depends on - * zSig which just changed. - */ - roundIncrement = (zSig & 0x400) ? 0 : 0x3ff; - } - } - } - if (roundBits) { - float_raise(float_flag_inexact, status); - } - zSig = ( zSig + roundIncrement )>>10; - if (!(roundBits ^ 0x200) && roundNearestEven) { - zSig &= ~1; - } - if ( zSig == 0 ) zExp = 0; - return packFloat64( zSign, zExp, zSig ); - -} - -/*---------------------------------------------------------------------------- -| Takes an abstract floating-point value having sign `zSign', exponent `zExp', -| and significand `zSig', and returns the proper double-precision floating- -| point value corresponding to the abstract input. This routine is just like -| `roundAndPackFloat64' except that `zSig' does not have to be normalized. -| Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true'' -| floating-point exponent. -*----------------------------------------------------------------------------*/ - -static float64 - normalizeRoundAndPackFloat64(bool zSign, int zExp, uint64_t zSig, - float_status *status) -{ - int8_t shiftCount; - - shiftCount = clz64(zSig) - 1; - return roundAndPackFloat64(zSign, zExp - shiftCount, zSig<>48 ) & 0x7FFF; - -} - -/*---------------------------------------------------------------------------- -| Returns the sign bit of the quadruple-precision floating-point value `a'. -*----------------------------------------------------------------------------*/ - -static inline bool extractFloat128Sign(float128 a) -{ - return a.high >> 63; -} - -/*---------------------------------------------------------------------------- -| Normalizes the subnormal quadruple-precision floating-point value -| represented by the denormalized significand formed by the concatenation of -| `aSig0' and `aSig1'. The normalized exponent is stored at the location -| pointed to by `zExpPtr'. The most significant 49 bits of the normalized -| significand are stored at the location pointed to by `zSig0Ptr', and the -| least significant 64 bits of the normalized significand are stored at the -| location pointed to by `zSig1Ptr'. -*----------------------------------------------------------------------------*/ - -static void - normalizeFloat128Subnormal( - uint64_t aSig0, - uint64_t aSig1, - int32_t *zExpPtr, - uint64_t *zSig0Ptr, - uint64_t *zSig1Ptr - ) -{ - int8_t shiftCount; - - if ( aSig0 == 0 ) { - shiftCount = clz64(aSig1) - 15; - if ( shiftCount < 0 ) { - *zSig0Ptr = aSig1>>( - shiftCount ); - *zSig1Ptr = aSig1<<( shiftCount & 63 ); - } - else { - *zSig0Ptr = aSig1<float_rounding_mode; - roundNearestEven = ( roundingMode == float_round_nearest_even ); - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment = ((int64_t)zSig2 < 0); - break; - case float_round_to_zero: - increment = 0; - break; - case float_round_up: - increment = !zSign && zSig2; - break; - case float_round_down: - increment = zSign && zSig2; - break; - case float_round_to_odd: - increment = !(zSig1 & 0x1) && zSig2; - break; - default: - abort(); - } - if ( 0x7FFD <= (uint32_t) zExp ) { - if ( ( 0x7FFD < zExp ) - || ( ( zExp == 0x7FFD ) - && eq128( - UINT64_C(0x0001FFFFFFFFFFFF), - UINT64_C(0xFFFFFFFFFFFFFFFF), - zSig0, - zSig1 - ) - && increment - ) - ) { - float_raise(float_flag_overflow | float_flag_inexact, status); - if ( ( roundingMode == float_round_to_zero ) - || ( zSign && ( roundingMode == float_round_up ) ) - || ( ! zSign && ( roundingMode == float_round_down ) ) - || (roundingMode == float_round_to_odd) - ) { - return - packFloat128( - zSign, - 0x7FFE, - UINT64_C(0x0000FFFFFFFFFFFF), - UINT64_C(0xFFFFFFFFFFFFFFFF) - ); - } - return packFloat128( zSign, 0x7FFF, 0, 0 ); - } - if ( zExp < 0 ) { - if (status->flush_to_zero) { - float_raise(float_flag_output_denormal, status); - return packFloat128(zSign, 0, 0, 0); - } - isTiny = status->tininess_before_rounding - || (zExp < -1) - || !increment - || lt128(zSig0, zSig1, - UINT64_C(0x0001FFFFFFFFFFFF), - UINT64_C(0xFFFFFFFFFFFFFFFF)); - shift128ExtraRightJamming( - zSig0, zSig1, zSig2, - zExp, &zSig0, &zSig1, &zSig2 ); - zExp = 0; - if (isTiny && zSig2) { - float_raise(float_flag_underflow, status); - } - switch (roundingMode) { - case float_round_nearest_even: - case float_round_ties_away: - increment = ((int64_t)zSig2 < 0); - break; - case float_round_to_zero: - increment = 0; - break; - case float_round_up: - increment = !zSign && zSig2; - break; - case float_round_down: - increment = zSign && zSig2; - break; - case float_round_to_odd: - increment = !(zSig1 & 0x1) && zSig2; - break; - default: - abort(); - } - } - } - if (zSig2) { - float_raise(float_flag_inexact, status); - } - if ( increment ) { - add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 ); - if ((zSig2 + zSig2 == 0) && roundNearestEven) { - zSig1 &= ~1; - } - } - else { - if ( ( zSig0 | zSig1 ) == 0 ) zExp = 0; - } - return packFloat128( zSign, zExp, zSig0, zSig1 ); - -} - -/*---------------------------------------------------------------------------- -| Takes an abstract floating-point value having sign `zSign', exponent `zExp', -| and significand formed by the concatenation of `zSig0' and `zSig1', and -| returns the proper quadruple-precision floating-point value corresponding -| to the abstract input. This routine is just like `roundAndPackFloat128' -| except that the input significand has fewer bits and does not have to be -| normalized. In all cases, `zExp' must be 1 less than the ``true'' floating- -| point exponent. -*----------------------------------------------------------------------------*/ - -static float128 normalizeRoundAndPackFloat128(bool zSign, int32_t zExp, - uint64_t zSig0, uint64_t zSig1, - float_status *status) -{ - int8_t shiftCount; - uint64_t zSig2; - - if ( zSig0 == 0 ) { - zSig0 = zSig1; - zSig1 = 0; - zExp -= 64; - } - shiftCount = clz64(zSig0) - 15; - if ( 0 <= shiftCount ) { - zSig2 = 0; - shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 ); - } - else { - shift128ExtraRightJamming( - zSig0, zSig1, 0, - shiftCount, &zSig0, &zSig1, &zSig2 ); - } - zExp -= shiftCount; - return roundAndPackFloat128(zSign, zExp, zSig0, zSig1, zSig2, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the remainder of the single-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float32 float32_rem(float32 a, float32 b, float_status *status) -{ - bool aSign, zSign; - int aExp, bExp, expDiff; - uint32_t aSig, bSig; - uint32_t q; - uint64_t aSig64, bSig64, q64; - uint32_t alternateASig; - int32_t sigMean; - a = float32_squash_input_denormal(a, status); - b = float32_squash_input_denormal(b, status); - - aSig = extractFloat32Frac( a ); - aExp = extractFloat32Exp( a ); - aSign = extractFloat32Sign( a ); - bSig = extractFloat32Frac( b ); - bExp = extractFloat32Exp( b ); - if ( aExp == 0xFF ) { - if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) { - return propagateFloat32NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - if ( bExp == 0xFF ) { - if (bSig) { - return propagateFloat32NaN(a, b, status); - } - return a; - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - float_raise(float_flag_invalid, status); - return float32_default_nan(status); - } - normalizeFloat32Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return a; - normalizeFloat32Subnormal( aSig, &aExp, &aSig ); - } - expDiff = aExp - bExp; - aSig |= 0x00800000; - bSig |= 0x00800000; - if ( expDiff < 32 ) { - aSig <<= 8; - bSig <<= 8; - if ( expDiff < 0 ) { - if ( expDiff < -1 ) return a; - aSig >>= 1; - } - q = ( bSig <= aSig ); - if ( q ) aSig -= bSig; - if ( 0 < expDiff ) { - q = ( ( (uint64_t) aSig )<<32 ) / bSig; - q >>= 32 - expDiff; - bSig >>= 2; - aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; - } - else { - aSig >>= 2; - bSig >>= 2; - } - } - else { - if ( bSig <= aSig ) aSig -= bSig; - aSig64 = ( (uint64_t) aSig )<<40; - bSig64 = ( (uint64_t) bSig )<<40; - expDiff -= 64; - while ( 0 < expDiff ) { - q64 = estimateDiv128To64( aSig64, 0, bSig64 ); - q64 = ( 2 < q64 ) ? q64 - 2 : 0; - aSig64 = - ( ( bSig * q64 )<<38 ); - expDiff -= 62; - } - expDiff += 64; - q64 = estimateDiv128To64( aSig64, 0, bSig64 ); - q64 = ( 2 < q64 ) ? q64 - 2 : 0; - q = q64>>( 64 - expDiff ); - bSig <<= 6; - aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q; - } - do { - alternateASig = aSig; - ++q; - aSig -= bSig; - } while ( 0 <= (int32_t) aSig ); - sigMean = aSig + alternateASig; - if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) { - aSig = alternateASig; - } - zSign = ( (int32_t) aSig < 0 ); - if ( zSign ) aSig = - aSig; - return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status); -} - - - /*---------------------------------------------------------------------------- | Returns the binary exponential of the single-precision floating-point value | `a'. The operation is performed according to the IEC/IEEE Standard for @@ -5275,94 +4806,6 @@ float32 float32_exp2(float32 a, float_status *status) return float32_round_pack_canonical(&rp, status); } -/*---------------------------------------------------------------------------- -| Returns the remainder of the double-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float64 float64_rem(float64 a, float64 b, float_status *status) -{ - bool aSign, zSign; - int aExp, bExp, expDiff; - uint64_t aSig, bSig; - uint64_t q, alternateASig; - int64_t sigMean; - - a = float64_squash_input_denormal(a, status); - b = float64_squash_input_denormal(b, status); - aSig = extractFloat64Frac( a ); - aExp = extractFloat64Exp( a ); - aSign = extractFloat64Sign( a ); - bSig = extractFloat64Frac( b ); - bExp = extractFloat64Exp( b ); - if ( aExp == 0x7FF ) { - if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) { - return propagateFloat64NaN(a, b, status); - } - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - if ( bExp == 0x7FF ) { - if (bSig) { - return propagateFloat64NaN(a, b, status); - } - return a; - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - float_raise(float_flag_invalid, status); - return float64_default_nan(status); - } - normalizeFloat64Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig == 0 ) return a; - normalizeFloat64Subnormal( aSig, &aExp, &aSig ); - } - expDiff = aExp - bExp; - aSig = (aSig | UINT64_C(0x0010000000000000)) << 11; - bSig = (bSig | UINT64_C(0x0010000000000000)) << 11; - if ( expDiff < 0 ) { - if ( expDiff < -1 ) return a; - aSig >>= 1; - } - q = ( bSig <= aSig ); - if ( q ) aSig -= bSig; - expDiff -= 64; - while ( 0 < expDiff ) { - q = estimateDiv128To64( aSig, 0, bSig ); - q = ( 2 < q ) ? q - 2 : 0; - aSig = - ( ( bSig>>2 ) * q ); - expDiff -= 62; - } - expDiff += 64; - if ( 0 < expDiff ) { - q = estimateDiv128To64( aSig, 0, bSig ); - q = ( 2 < q ) ? q - 2 : 0; - q >>= 64 - expDiff; - bSig >>= 2; - aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; - } - else { - aSig >>= 2; - bSig >>= 2; - } - do { - alternateASig = aSig; - ++q; - aSig -= bSig; - } while ( 0 <= (int64_t) aSig ); - sigMean = aSig + alternateASig; - if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) { - aSig = alternateASig; - } - zSign = ( (int64_t) aSig < 0 ); - if ( zSign ) aSig = - aSig; - return normalizeRoundAndPackFloat64(aSign ^ zSign, bExp, aSig, status); - -} - /*---------------------------------------------------------------------------- | Rounds the extended double-precision floating-point value `a' | to the precision provided by floatx80_rounding_precision and returns the @@ -5381,266 +4824,6 @@ floatx80 floatx80_round(floatx80 a, float_status *status) return floatx80_round_pack_canonical(&p, status); } -/*---------------------------------------------------------------------------- -| Returns the remainder of the extended double-precision floating-point value -| `a' with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic, -| if 'mod' is false; if 'mod' is true, return the remainder based on truncating -| the quotient toward zero instead. '*quotient' is set to the low 64 bits of -| the absolute value of the integer quotient. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_modrem(floatx80 a, floatx80 b, bool mod, uint64_t *quotient, - float_status *status) -{ - bool aSign, zSign; - int32_t aExp, bExp, expDiff, aExpOrig; - uint64_t aSig0, aSig1, bSig; - uint64_t q, term0, term1, alternateASig0, alternateASig1; - - *quotient = 0; - if (floatx80_invalid_encoding(a) || floatx80_invalid_encoding(b)) { - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - aSig0 = extractFloatx80Frac( a ); - aExpOrig = aExp = extractFloatx80Exp( a ); - aSign = extractFloatx80Sign( a ); - bSig = extractFloatx80Frac( b ); - bExp = extractFloatx80Exp( b ); - if ( aExp == 0x7FFF ) { - if ( (uint64_t) ( aSig0<<1 ) - || ( ( bExp == 0x7FFF ) && (uint64_t) ( bSig<<1 ) ) ) { - return propagateFloatx80NaN(a, b, status); - } - goto invalid; - } - if ( bExp == 0x7FFF ) { - if ((uint64_t)(bSig << 1)) { - return propagateFloatx80NaN(a, b, status); - } - if (aExp == 0 && aSig0 >> 63) { - /* - * Pseudo-denormal argument must be returned in normalized - * form. - */ - return packFloatx80(aSign, 1, aSig0); - } - return a; - } - if ( bExp == 0 ) { - if ( bSig == 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return floatx80_default_nan(status); - } - normalizeFloatx80Subnormal( bSig, &bExp, &bSig ); - } - if ( aExp == 0 ) { - if ( aSig0 == 0 ) return a; - normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 ); - } - zSign = aSign; - expDiff = aExp - bExp; - aSig1 = 0; - if ( expDiff < 0 ) { - if ( mod || expDiff < -1 ) { - if (aExp == 1 && aExpOrig == 0) { - /* - * Pseudo-denormal argument must be returned in - * normalized form. - */ - return packFloatx80(aSign, aExp, aSig0); - } - return a; - } - shift128Right( aSig0, 0, 1, &aSig0, &aSig1 ); - expDiff = 0; - } - *quotient = q = ( bSig <= aSig0 ); - if ( q ) aSig0 -= bSig; - expDiff -= 64; - while ( 0 < expDiff ) { - q = estimateDiv128To64( aSig0, aSig1, bSig ); - q = ( 2 < q ) ? q - 2 : 0; - mul64To128( bSig, q, &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 ); - shortShift128Left( aSig0, aSig1, 62, &aSig0, &aSig1 ); - expDiff -= 62; - *quotient <<= 62; - *quotient += q; - } - expDiff += 64; - if ( 0 < expDiff ) { - q = estimateDiv128To64( aSig0, aSig1, bSig ); - q = ( 2 < q ) ? q - 2 : 0; - q >>= 64 - expDiff; - mul64To128( bSig, q<<( 64 - expDiff ), &term0, &term1 ); - sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 ); - shortShift128Left( 0, bSig, 64 - expDiff, &term0, &term1 ); - while ( le128( term0, term1, aSig0, aSig1 ) ) { - ++q; - sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 ); - } - if (expDiff < 64) { - *quotient <<= expDiff; - } else { - *quotient = 0; - } - *quotient += q; - } - else { - term1 = 0; - term0 = bSig; - } - if (!mod) { - sub128( term0, term1, aSig0, aSig1, &alternateASig0, &alternateASig1 ); - if ( lt128( alternateASig0, alternateASig1, aSig0, aSig1 ) - || ( eq128( alternateASig0, alternateASig1, aSig0, aSig1 ) - && ( q & 1 ) ) - ) { - aSig0 = alternateASig0; - aSig1 = alternateASig1; - zSign = ! zSign; - ++*quotient; - } - } - return - normalizeRoundAndPackFloatx80( - floatx80_precision_x, zSign, bExp + expDiff, aSig0, aSig1, status); - -} - -/*---------------------------------------------------------------------------- -| Returns the remainder of the extended double-precision floating-point value -| `a' with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_rem(floatx80 a, floatx80 b, float_status *status) -{ - uint64_t quotient; - return floatx80_modrem(a, b, false, "ient, status); -} - -/*---------------------------------------------------------------------------- -| Returns the remainder of the extended double-precision floating-point value -| `a' with respect to the corresponding value `b', with the quotient truncated -| toward zero. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) -{ - uint64_t quotient; - return floatx80_modrem(a, b, true, "ient, status); -} - -/*---------------------------------------------------------------------------- -| Returns the remainder of the quadruple-precision floating-point value `a' -| with respect to the corresponding value `b'. The operation is performed -| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. -*----------------------------------------------------------------------------*/ - -float128 float128_rem(float128 a, float128 b, float_status *status) -{ - bool aSign, zSign; - int32_t aExp, bExp, expDiff; - uint64_t aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2; - uint64_t allZero, alternateASig0, alternateASig1, sigMean1; - int64_t sigMean0; - - aSig1 = extractFloat128Frac1( a ); - aSig0 = extractFloat128Frac0( a ); - aExp = extractFloat128Exp( a ); - aSign = extractFloat128Sign( a ); - bSig1 = extractFloat128Frac1( b ); - bSig0 = extractFloat128Frac0( b ); - bExp = extractFloat128Exp( b ); - if ( aExp == 0x7FFF ) { - if ( ( aSig0 | aSig1 ) - || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) { - return propagateFloat128NaN(a, b, status); - } - goto invalid; - } - if ( bExp == 0x7FFF ) { - if (bSig0 | bSig1) { - return propagateFloat128NaN(a, b, status); - } - return a; - } - if ( bExp == 0 ) { - if ( ( bSig0 | bSig1 ) == 0 ) { - invalid: - float_raise(float_flag_invalid, status); - return float128_default_nan(status); - } - normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 ); - } - if ( aExp == 0 ) { - if ( ( aSig0 | aSig1 ) == 0 ) return a; - normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 ); - } - expDiff = aExp - bExp; - if ( expDiff < -1 ) return a; - shortShift128Left( - aSig0 | UINT64_C(0x0001000000000000), - aSig1, - 15 - ( expDiff < 0 ), - &aSig0, - &aSig1 - ); - shortShift128Left( - bSig0 | UINT64_C(0x0001000000000000), bSig1, 15, &bSig0, &bSig1 ); - q = le128( bSig0, bSig1, aSig0, aSig1 ); - if ( q ) sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 ); - expDiff -= 64; - while ( 0 < expDiff ) { - q = estimateDiv128To64( aSig0, aSig1, bSig0 ); - q = ( 4 < q ) ? q - 4 : 0; - mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 ); - shortShift192Left( term0, term1, term2, 61, &term1, &term2, &allZero ); - shortShift128Left( aSig0, aSig1, 61, &aSig0, &allZero ); - sub128( aSig0, 0, term1, term2, &aSig0, &aSig1 ); - expDiff -= 61; - } - if ( -64 < expDiff ) { - q = estimateDiv128To64( aSig0, aSig1, bSig0 ); - q = ( 4 < q ) ? q - 4 : 0; - q >>= - expDiff; - shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 ); - expDiff += 52; - if ( expDiff < 0 ) { - shift128Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 ); - } - else { - shortShift128Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 ); - } - mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 ); - sub128( aSig0, aSig1, term1, term2, &aSig0, &aSig1 ); - } - else { - shift128Right( aSig0, aSig1, 12, &aSig0, &aSig1 ); - shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 ); - } - do { - alternateASig0 = aSig0; - alternateASig1 = aSig1; - ++q; - sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 ); - } while ( 0 <= (int64_t) aSig0 ); - add128( - aSig0, aSig1, alternateASig0, alternateASig1, (uint64_t *)&sigMean0, &sigMean1 ); - if ( ( sigMean0 < 0 ) - || ( ( ( sigMean0 | sigMean1 ) == 0 ) && ( q & 1 ) ) ) { - aSig0 = alternateASig0; - aSig1 = alternateASig1; - } - zSign = ( (int64_t) aSig0 < 0 ); - if ( zSign ) sub128( 0, 0, aSig0, aSig1, &aSig0, &aSig1 ); - return normalizeRoundAndPackFloat128(aSign ^ zSign, bExp - 4, aSig0, aSig1, - status); -} static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3659c6a4c0..1bc8db4cf1 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -625,6 +625,40 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, return a; } +/* + * Floating point remainder, per IEC/IEEE, or modulus. + */ +static FloatPartsN *partsN(modrem)(FloatPartsN *a, FloatPartsN *b, + uint64_t *mod_quot, float_status *s) +{ + int ab_mask = float_cmask(a->cls) | float_cmask(b->cls); + + if (likely(ab_mask == float_cmask_normal)) { + frac_modrem(a, b, mod_quot); + return a; + } + + if (mod_quot) { + *mod_quot = 0; + } + + /* All the NaN cases */ + if (unlikely(ab_mask & float_cmask_anynan)) { + return parts_pick_nan(a, b, s); + } + + /* Inf % N; N % 0 */ + if (a->cls == float_class_inf || b->cls == float_class_zero) { + float_raise(float_flag_invalid, s); + parts_default_nan(a, s); + return a; + } + + /* N % Inf; 0 % N */ + g_assert(b->cls == float_class_inf || a->cls == float_class_zero); + return a; +} + /* * Square Root * diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 88eab344df..6754a94afc 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -636,62 +636,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, #endif } -/*---------------------------------------------------------------------------- -| Takes two single-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) -{ - bool aIsLargerSignificand; - uint32_t av, bv; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!float32_is_any_nan(a) - ? float_class_normal - : float32_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!float32_is_any_nan(b) - ? float_class_normal - : float32_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - av = float32_val(a); - bv = float32_val(b); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float32_default_nan(status); - } - - if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) { - aIsLargerSignificand = 0; - } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (av < bv) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return float32_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float32_silence_nan(a, status); - } - return a; - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -732,62 +676,6 @@ bool float64_is_signaling_nan(float64 a_, float_status *status) } } -/*---------------------------------------------------------------------------- -| Takes two double-precision floating-point values `a' and `b', one of which -| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a -| signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) -{ - bool aIsLargerSignificand; - uint64_t av, bv; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!float64_is_any_nan(a) - ? float_class_normal - : float64_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!float64_is_any_nan(b) - ? float_class_normal - : float64_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - av = float64_val(a); - bv = float64_val(b); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float64_default_nan(status); - } - - if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) { - aIsLargerSignificand = 0; - } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (av < bv) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return float64_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float64_silence_nan(a, status); - } - return a; - } -} - /*---------------------------------------------------------------------------- | Returns 1 if the extended double-precision floating-point value `a' is a | quiet NaN; otherwise returns 0. This slightly differs from the same @@ -942,56 +830,3 @@ bool float128_is_signaling_nan(float128 a, float_status *status) } } } - -/*---------------------------------------------------------------------------- -| Takes two quadruple-precision floating-point values `a' and `b', one of -| which is a NaN, and returns the appropriate NaN result. If either `a' or -| `b' is a signaling NaN, the invalid exception is raised. -*----------------------------------------------------------------------------*/ - -static float128 propagateFloat128NaN(float128 a, float128 b, - float_status *status) -{ - bool aIsLargerSignificand; - FloatClass a_cls, b_cls; - - /* This is not complete, but is good enough for pickNaN. */ - a_cls = (!float128_is_any_nan(a) - ? float_class_normal - : float128_is_signaling_nan(a, status) - ? float_class_snan - : float_class_qnan); - b_cls = (!float128_is_any_nan(b) - ? float_class_normal - : float128_is_signaling_nan(b, status) - ? float_class_snan - : float_class_qnan); - - if (is_snan(a_cls) || is_snan(b_cls)) { - float_raise(float_flag_invalid, status); - } - - if (status->default_nan_mode) { - return float128_default_nan(status); - } - - if (lt128(a.high << 1, a.low, b.high << 1, b.low)) { - aIsLargerSignificand = 0; - } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) { - aIsLargerSignificand = 1; - } else { - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; - } - - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { - if (is_snan(b_cls)) { - return float128_silence_nan(b, status); - } - return b; - } else { - if (is_snan(a_cls)) { - return float128_silence_nan(a, status); - } - return a; - } -}