From patchwork Mon May 10 06:31:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433031 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2564387jao; Sun, 9 May 2021 23:31:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz1IEFSsoNp6FSBH7iIDLucHyRl7npNIjtoa1l4+ATvBDmNnnSpVXrtE2drOf29JdPclVnb X-Received: by 2002:aa7:d40e:: with SMTP id z14mr22520426edq.73.1620628279013; Sun, 09 May 2021 23:31:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628279; cv=none; d=google.com; s=arc-20160816; b=ZcUD8Bu6DBCTuXsSNJtt6Avs9aO1MRLbL3bc+Z7hLMhn9D82o42vO4lZ9Sz0K1e8oC ih49MSLRcikUOsc7UKVi3VJhmQI255tnc34uIaaWvRA12orjrljS0B1IJ5cTTiZ54m/t pPjQob+IqSInwUM7QVi89XF6NlQO1+2f84hUZf9Qsw6OyzI1WGFp+EPz0RUiYeUKmzzQ 8DAr9ZMvj1qSRYWEiuO8oiQ9gI7xF7GCYY+FK1QyeNkcbY6YmXfUMDWKHf2zO+cjek0U KKxiLRNJ+6dE+NJaeug6sA3bc4ljYskpjD06EIMkjYnbDqXChT8RezlMBtmyA/tv065N z/Dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=8JuwnyjUQoQmG+UhiM4SlX663SBaUpMiztf2nxsYscA=; b=MATbUJr8HRi79WafM50Rfa2qYYOpw2KZIzdyNS9KJAf8N1Szbxik0aN1+SoE6yCPzE IfuvudKW/A79+r4pROcwiJsRImL6v4VQC7L6gC5Zx2fs3uys8mFsX9jpGgYi8P7Ln6mF lhVpR6DoJMxq5O6z1worw2aLXOWgOZyd2xA6cfolQNTWSu349AY1k6ukgyU5IKpH6IBv kufIOQxUGxhTKe++3PFTxaWv/j/OLQOTzst/KzK8oMBPdZzWt83kwWVeO/XhaDqRUVyf ijtV7CFFrRzC/rQhDZWCBsaYw+H5aL8n7bGHBBp9iqZTat34WZLQh/SnggCxt/kAZZQF E1zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KkUKyr53; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id gr23si12513444ejb.87.2021.05.09.23.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:18 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KkUKyr53; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EAEA582B71; Mon, 10 May 2021 08:31:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="KkUKyr53"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AC35882EB1; Mon, 10 May 2021 08:31:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EB51E82B41 for ; Mon, 10 May 2021 08:31:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pj1-x102e.google.com with SMTP id l10-20020a17090a850ab0290155b06f6267so9456341pjn.5 for ; Sun, 09 May 2021 23:31:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=8JuwnyjUQoQmG+UhiM4SlX663SBaUpMiztf2nxsYscA=; b=KkUKyr53r76kmMzDzX7+UAdcBhsguYhsrOHQmpKOBLVeUZJUNMLKCeJYaYXSDsfC8u n3tShBhMj+fvSoIFrHsO4WzQmmQ9ZpqviiwnSy0NvzuFR2FCFA77JipdwNMWzloutunT h+14xHEdWfU9/CSGtGhVsPHXEOhFUs4+sVEzsjcARfB+1VL5ppHWNJReNr+cxXtA4rwT C6q/bbs2l+tXEGQbKNx+Hv4RrofEo5QUONfv1PCn9ojtAQb730gdzlmCgdzTr8CXSjrW it6garDfg+wDwy9fpvTvz7VYZEw9dKe2S7rYlbKNTwmvMY4dYWZFLNzI9aaty2CjxipR z0Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=8JuwnyjUQoQmG+UhiM4SlX663SBaUpMiztf2nxsYscA=; b=q+BrncMJ4iJl/Dp8FSYtsh3zn8SxVnqVoHfmSXzQcQGJegHT4LALd3dlJbeDODjJb7 d1UwXYtqGCXhqF7tWgrEyM4TeVkr1WTYlk9wfpI0WnKER/4df16EYe46yn5ur8W42Fp3 eFSvlVIouyVjephLMhpukci/Nu2ZnbElx60lM8PJMZcBA+W6E378u1Jpc17lBX5UQOhW E6SkM+JLFdY3581YZgiaeWHdpyQUSZEoemvoZdDk0kfH9crIdBaJDtnKw7w6DFWghVfb fo5mhfzK+5hI6tr0zH6Zm+k8wF8hrSe0b7xuLHMn+4bDmZmwcxbp6or5VLSbMwGMypjj 0Q2A== X-Gm-Message-State: AOAM532AY+xtugrrMao4RH3mdDX9vg+zqXPZdZ1xRh5xFftbbvvVJ6GF ZdUrku1RYCE323CJYhXzHkT2rw== X-Received: by 2002:a17:90a:20b:: with SMTP id c11mr25176622pjc.44.1620628270251; Sun, 09 May 2021 23:31:10 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id d3sm17914103pjw.35.2021.05.09.23.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:09 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 01/14] pci: Update the highest subordinate bus number for bridge setup Date: Mon, 10 May 2021 15:31:05 +0900 Message-Id: <162062826490.501222.2760653538005920634.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Update the highest subordinate bus number after probing the devices under the bus for setting up the bridge correctly. The commit 42f3663a3f67 ("pci: Update to use new sequence numbers") removed this but it is required if a PCIe bridge is under the bus. Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers") Signed-off-by: Masami Hiramatsu Reviewed-by: Simon Glass Tested-by: Tim Harvey --- drivers/pci/pci-uclass.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index dfd54b339f..f463ef3550 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -646,6 +646,9 @@ int dm_pci_hose_probe_bus(struct udevice *bus) return log_msg_ret("probe", ret); } + if (!ea_pos) + sub_bus = pci_get_bus_max(); + dm_pciauto_postscan_setup_bridge(bus, sub_bus); return sub_bus; From patchwork Mon May 10 06:31:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433032 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2564546jao; Sun, 9 May 2021 23:31:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhH3uPTXdkQF0rzDA/hc21k95gUv0QIri7BOqAqp5iviwfZ4lDSUXtgZ9vPReOEdk4YPAI X-Received: by 2002:a17:906:63d2:: with SMTP id u18mr24221452ejk.186.1620628291832; Sun, 09 May 2021 23:31:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628291; cv=none; d=google.com; s=arc-20160816; b=zweWP77L2vqj7tMs7ycOWTlAClR7j/bmDFmRb/YnhQFCH5a6Qvu/yGbjXPi8X2KC+v 9jlq3AE83+aDSRlpP+ZskxK5wEfXxD+gFMpAXt04L3Tj6cpGaoIs+vfijWecf1XdBT7i byq+T+8ZSfg4rHlY0KhIdiwNH3raMjKO53LLQTGjtHHhtLi6skrNSqIrekOBzKrqGNEQ LyqbKD0bJCKjcQOsX6C5tpdSjjVBHRaKdrgtOz0AW0xbDulRg29Bcd8j4NzWTe+uIGVO SxmizGb0zKVy0x9OHh/co0HjVwX5Det8AhkoemxK1DzgM47WD5e0b5z1xt+FBDH5Nsy/ r70Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=UJp7+95mtEq8MBJE+R/DZyh+k8I4LvQpS2znz6umB8A=; b=T5CnsP8XOVp5Q5hpG1vXhNb24EXCwXfAzVt67uTpLEDbyz0LTXBcv1XhiRwed6jIVF qYLJhObreQGyMV1Uqagrza0hCP8BOC02ZTUHPpNo6wFH5SVjz3wwFoFwu99+5LmyofIB jgBmMNq5eTt+z47Bp7nHghcHQIjbVQRlfZSXsYxNTqZEImQo4olHJH+cbdj2Z70hSxiO W3IKb8tblQoDNhZwBlTHHSOeTX+mALVmvDszFEZ7844US5pa8Z9EgFnwEDV+xeimRZZL +QUlI2iWOF0+EMiWkDUn9iRdrmLqlZNYVqDvqIIFux9u/QmKm8fzK/uY8S6bth0zOJIV yRhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HTry4LFB; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id v26si13130690edx.196.2021.05.09.23.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:31 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HTry4LFB; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E7D5582B41; Mon, 10 May 2021 08:31:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="HTry4LFB"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 564CC82B41; Mon, 10 May 2021 08:31:26 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2B7CE82EB2 for ; Mon, 10 May 2021 08:31:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pg1-x535.google.com with SMTP id i14so12578207pgk.5 for ; Sun, 09 May 2021 23:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=UJp7+95mtEq8MBJE+R/DZyh+k8I4LvQpS2znz6umB8A=; b=HTry4LFBy2pMOiZQJ+9RynJVYt1v7s7MeHzNQkoX+kQ3z0kZbyZx2ydq2AD57WJczl b890YrIeH2zZnnvBfUrXwcOgOXFpQaHCpf1PysGPX8sT7ju+bFef5RU7xEjfmlbPMrse INdOoRAxe5Fq7XY+AlaACfxUni+SypJ5b1rM5cyirPd1gY6sVjokRKKm1i6eQLTiy2V9 uLbiiChDRcBww7T21/DY2Hd61bprJ3QggoDPJyiek0GqPtUQmwF0PgwLVoklba33saj5 WiyQE6NiWiTQemKuWdlSZTlUyr1YP44WJr8WisBRSek5zBeBrsWB5KtxiMg1dZ803urC zdWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=UJp7+95mtEq8MBJE+R/DZyh+k8I4LvQpS2znz6umB8A=; b=J3N589DNdIt5yPAgB0gUCI50GJRpAKhHT6WlZnOFVYq50/G6tiAUvnf0woscE9M84X SixgpW4bRixwYVSqmD4oIQaExgJ0WKxNc2BBsTJVi6QxNM2VFmZ6c7aduclzYK5uk+S6 EEkdqXv58nUn3bVylLkMiS60iFWUWY9IJkzGvrYfVi7vhrO8PkWcDc/2xmih83XhFs4V VHVP3ToJXs5GP7JAKSVbM4lJ1hljqu4+IKLrQIxvFW3nLR2iVC4bd/iQOrW1HoX9b5lp 6ihK4HRkE83ihrR5/7cRnyPb4VVswpoQ3vd2UXKNLJFwwvkNpqH/yIMII6HrcOIkLKea Cw1Q== X-Gm-Message-State: AOAM532C5CXP7rLmS4wL1oOaoPED61XuQsnu02NqVNVH2XrWqlVItTAv Y8NsCFVUWlT9H1xfZCBykvuzzw== X-Received: by 2002:a63:1921:: with SMTP id z33mr23872486pgl.211.1620628280663; Sun, 09 May 2021 23:31:20 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id u12sm18686857pji.45.2021.05.09.23.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:20 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 02/14] ata: ahci-pci: Use scsi_ops to initialize ops Date: Mon, 10 May 2021 15:31:15 +0900 Message-Id: <162062827563.501222.14010796212514133274.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Without this fix, scsi-scan will cause a synchronous abort when accessing ops->scan. Signed-off-by: Masami Hiramatsu Reviewed-by: Simon Glass --- drivers/ata/ahci-pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 11ec98b56f..b1d231e0f9 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -5,6 +5,7 @@ #include #include +#include #include #include @@ -28,6 +29,7 @@ static const struct udevice_id ahci_pci_ids[] = { U_BOOT_DRIVER(ahci_pci) = { .name = "ahci_pci", .id = UCLASS_AHCI, + .ops = &scsi_ops, .of_match = ahci_pci_ids, .bind = ahci_pci_bind, .probe = ahci_pci_probe, From patchwork Mon May 10 06:31:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433033 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2564634jao; Sun, 9 May 2021 23:31:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwpezjiIhtZpRsE2vQOdEQrqqRAlqp4v0iPrw6QjBBrnaa1dmTVbskzRkR9PEDVBw6VEPiU X-Received: by 2002:a17:906:49c1:: with SMTP id w1mr24664506ejv.178.1620628299773; Sun, 09 May 2021 23:31:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628299; cv=none; d=google.com; s=arc-20160816; b=nUhwjiWf2MKflrY3LE0/S3ChHCdbQSlRoLyg0W+4en2BZWYU8zt5z15rPG09lGTwt4 bO/pDbnUMd2gemyrmIMvGALhdy8ZkN8aF3azbeF6dxykVYySCbcPZD+FvKFsSRaqRyqM GHgKoOakSwS3/w3hqd1/2h8z2F5G11WGtmhzzbEHN/CsxUuGJG0sST1YK8zjZFunjUHB gFcRm3Zf3n6Jbwhv86pDwDuvJ8arf+C5NyPVnivSFolpcTLsOpkbBOvbFD7DZvTihPTe vr7nXbh/ion+7LA+yOYye6xO0+hoKOQioIaHYWJrNJyB3N3j3485dgvEXD7YlhabgsYT H0gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=HUeuKptVZl+AyYfhXDPh4WDXeiyXxCHn77aqz5aRYGQ=; b=04f7YhlAxk0/UXzfAggEmA0IuwAyAXSe/L04rEiKjWfghj2A7igBXSUZF4zkMwRy+V KA0s4oeddJavhdU8w4yjPspcHRjV51GbdGf1784it5182KrD5jATTwd68S5iboxnOid7 9pOvXegpV3lPRy+Ygy4uLtH471+XgBJTnwCIXJNEH1o2mkd1BkPB2+m+u32ikTL4PRZS TDW2oYCZ+9d4xWmsQ5TSB0kI6pLgAVF+rJI/GnjtPzgKmv8uuKy1uELix/ij3cJaRNKF JtXxfK/fZwqp7x8ebjzA4nbbh3ABceFQGKzB7PqTtNlKI9OAYWZhVs+VHyL3WCzOZ5ZJ vPJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rZfPXM1A; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id r27si7095015ejc.437.2021.05.09.23.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:39 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rZfPXM1A; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1731282EB7; Mon, 10 May 2021 08:31:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="rZfPXM1A"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1F2F182EB5; Mon, 10 May 2021 08:31:37 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F0DAA82EBC for ; Mon, 10 May 2021 08:31:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pj1-x1036.google.com with SMTP id ge1so9168025pjb.2 for ; Sun, 09 May 2021 23:31:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=HUeuKptVZl+AyYfhXDPh4WDXeiyXxCHn77aqz5aRYGQ=; b=rZfPXM1AiZEaAaKl4HmdXGCdjeusyDGmt0i36C6tMwRWnDdQuRZVi7Qr/NXYl0XtJU 6FZRyN9BTIrPot0lVtxCCM5Cvl1HlpS9uO/75iqdEhu+jQGG1kiKxBcFEzmJ5UiDAyjZ TGjG8DARFNnoCXBNx0Dfst4KF/hdzTGpchmPXvQBB21eYwWj3qyp25iTPuLDe7eLb6Lo TNeqFHASgZMe+SzUW+FWcbF3YmGdeF7VZSZAgW4a1bdzcZ+OQPnMru3PB4RoGpRqd9Xl 4qOwyj2cMGjMLjttkOqubKok4Z5hCkd/DKxJAO5kfOScFQEC509UIOrI96Kl2dU4zdQg Zvsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=HUeuKptVZl+AyYfhXDPh4WDXeiyXxCHn77aqz5aRYGQ=; b=Pno3oBT2SRSFn0XGcOoX3Nqiu5RDXP8Fn+CRmF+ZC4+0F+c017Tiwru+rJo7iKOdnl jr6JjcpWK8CZ0cYXNhB7ysdh4zpdj9O31Zsvu5UUApuKZoHOCnh1UkZW29oBei/6HVfm tg+VVwKO5mBJ+wZLa+lPdVyMj0c9/HcZo5rHhykTR6kIXMaeGweL7srl+GCST9jJ+LoL ullQgzsxazrmD+NbPZGBpAgbQ3W6Dg3aFd42r7gGPoI6T3WpbZhKQtMSJPZT0Bq+ir0S ShYA539zNNeQf/7WREXup01KldcDCXu983EZ9ppevsaYGXXCNc1foKJ28Mpw27LWsamS KOiw== X-Gm-Message-State: AOAM5316BcAKDyTSaaJO+hGol5oEyViQE+ztHoyI8Yy1snWO6ljlL7Yw NDJdZTpW5pN0/qwN1Oiek/WHMySFFPZZc7Mm X-Received: by 2002:a17:902:b109:b029:ef:1ee:9d02 with SMTP id q9-20020a170902b109b02900ef01ee9d02mr18786846plr.85.1620628291506; Sun, 09 May 2021 23:31:31 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id 79sm10347598pfz.202.2021.05.09.23.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:31 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 03/14] dm: pci: Skip setting VGA bridge bits if parent device is the host bus Date: Mon, 10 May 2021 15:31:26 +0900 Message-Id: <162062828602.501222.16973646108770784279.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Commit bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges") sets the VGA bridge bits by checking pplat->class, but if the parent device is the pci host bus device, it can be skipped. Moreover, it shouldn't access the pplat because the parent has different plat data. Without this fix, "pci enum" command cause a synchronous abort. pci_auto_config_devices: start PCI Autoconfig: Bus Memory region: [78000000-7fffffff], Physical Memory [78000000-7fffffffx] PCI Autoconfig: Bus I/O region: [0-ffff], Physical Memory [77f00000-77f0ffffx] pci_auto_config_devices: device pci_6:0.0 PCI Autoconfig: BAR 0, Mem, size=0x1000000, address=0x78000000 bus_lower=0x79000000 PCI Autoconfig: BAR 1, Mem, size=0x8000000, No room in resource, avail start=79000000 / size=8000000, need=8000000 PCI: Failed autoconfig bar 14 PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004 PCI Autoconfig: BAR 3, Mem, size=0x2000000, address=0x7a000000 bus_lower=0x7c000000 PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100 PCI Autoconfig: ROM, size=0x80000, address=0x7c000000 bus_lower=0x7c080000 "Synchronous Abort" handler, esr 0x96000006 elr: 00000000e002bd28 lr : 00000000e002bce8 (reloc) elr: 00000000fff6fd28 lr : 00000000fff6fce8 x0 : 0000000000001041 x1 : 000000000000003e x2 : 00000000ffb0f8c8 x3 : 0000000000000001 x4 : 0000000000000080 x5 : 0000000000000000 x6 : 00000000fff718fc x7 : 000000000000000f x8 : 00000000ffb0f238 x9 : 0000000000000008 x10: 0000000000000000 x11: 0000000000000010 x12: 0000000000000006 x13: 000000000001869f x14: 00000000ffb0fcd0 x15: 0000000000000020 x16: 00000000fff71cc4 x17: 0000000000000000 x18: 00000000ffb13d90 x19: 00000000ffb14320 x20: 0000000000000000 x21: 00000000ffb14090 x22: 00000000ffb0f8c8 x23: 0000000000000001 x24: 00000000ffb14c10 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 00000000ffb14c70 x29: 00000000ffb0f830 Code: 52800843 52800061 52800e00 97ffcf65 (b9400280) Resetting CPU ... Signed-off-by: Masami Hiramatsu Reviewed-by: Simon Glass --- drivers/pci/pci-uclass.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index f463ef3550..e9baa34e74 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -550,6 +550,9 @@ int pci_auto_config_devices(struct udevice *bus) max_bus = ret; sub_bus = max(sub_bus, max_bus); + if (dev_get_parent(dev) == bus) + continue; + pplat = dev_get_parent_plat(dev); if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8)) set_vga_bridge_bits(dev); From patchwork Mon May 10 06:31:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433034 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2564730jao; Sun, 9 May 2021 23:31:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1ukSGq2Q+UGJGUjCL9PjpJTS5L702zU+i7mBvwvoX/Q0NOwntDyVml0wDnmOOeJ7FRWM5 X-Received: by 2002:aa7:cf12:: with SMTP id a18mr27547059edy.160.1620628310400; Sun, 09 May 2021 23:31:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628310; cv=none; d=google.com; s=arc-20160816; b=lvo3KRUfN77QBnnCrl1O0Xfet47ZFlAprQhFIyMBcZaYzQSXM2z2LRLbBmD5dZ5fdU jgKe9KaW5sZ8+c7qkhfjwQZfWUZYAEQ8MF5tgXT3h9hLSUdUJzTlRtyzkWf/f6GUmkFQ wBPI19DfDj2olKlGKo+QVu3CNBUkpZbG9Gv82ijcLxaHwVV1eJbc5rXFhjbjAIMRfk5G 7JlFon5jL5kLdbsB2frMf9FpPIjDUeR6W37q/8W/WyG+hJZ7MYAk+0TlQw6wO8cmPc2j wUlI3jR6Zx7gLrdP7uqldbDYsuMVjdBRRpoqWK/a/7shwcistPKvvwdI9JZQHvbwZQkE SmUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=PMLjaHX0yNu4Vt2+2+BRUy44Cz7XPGdIquySHnGbOJY=; b=M1uMhG1Txkr2ogaugxIoXuWJrVaQVKgri+3vsjtXyj5DRKWveVbfecDco7/SzT5QaH 1dED6xJWaqn0AT1yA3KBA+t6iAP2rhbVXHSGUud0qcSP1VRv95uNRszjMW6fxBi78k6L it5xAoy9aVcKDY/4JWUM7HzukI6n3hUGRd2lJ4VC46V0gMT24VPasXlNFP0iiCx0eDMx v8PINUS551L1+E8UEpHawXRCLwV87BV2lYCHC4yK7XEcBxWD/8r4tAJWl+7pCApxBJCv eGy9LolZnkZ8QvD6A6nYG5WTspx5sbFbjaCgPJmJHBVh0aJo9JBh/e8kqJwCS4e1DYI7 xSPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k5ZjMniA; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id n9si12479282edy.573.2021.05.09.23.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:50 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k5ZjMniA; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 29BA982D34; Mon, 10 May 2021 08:31:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="k5ZjMniA"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CADAA82EB8; Mon, 10 May 2021 08:31:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 967CC82EC3 for ; Mon, 10 May 2021 08:31:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pl1-x632.google.com with SMTP id h7so8635469plt.1 for ; Sun, 09 May 2021 23:31:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=PMLjaHX0yNu4Vt2+2+BRUy44Cz7XPGdIquySHnGbOJY=; b=k5ZjMniAhMyCAyeg8lSCaaN/qmOE8dAoLbC6WS4Iuy4cictsB+QrRpjCAnyMFXysTb O89zl+4CZZS379vp/qQSDtlaSiiZqCPjss/SDEZlbhDe2EP2yStIC/LVzRNQZ78b88K3 vbnTv6bxLxsvk/GJdQ6XjsD5yvHDEjx92qi3E7LO6xr2dSWbhbYBmQAjGLJMlsHjlTUh r//qFYkWcYEvg1W5z2mb6L1okT7aSrtypnFhdbwO8dnRj8tCvc4adRBC3c7xMCP6thSb SbJXaHwgEMo24A6Ud53DMT4vJT9HW/1N3xvp13OhSrG/3yO7EI5wQUDQXGe574pYaBcd 2Q1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=PMLjaHX0yNu4Vt2+2+BRUy44Cz7XPGdIquySHnGbOJY=; b=nRkvY5RD2BEa7R0FtzMsTCZhgGJvLExRRp2PhCPMEkTmpu7i26TAKgjBdWIbVYqku7 y0Z64yyqkGS5GwUOYsgSTOPIqeH5mrkLvKPu6d/yqOkGbt4dTLbzQahSbrTdki3/dzeA 6mRgiFKJgdyvgt7l9otmJuvMCTd/7qSvbpdxS7b8UPiEgYbmN2aaTLIzkCW9Ef8KjdLA URNNPDd0h1NzlVBPLyU7b+KFGdWBg1vAgOQZQCMZnWpS4D0F51GUAAo+hgJ+/BGMS/BV 8+Sc4GWHQPP9LP2+3ME6DTY/taJtR4jYFYEEBfayhd/7jfXezYV53pesUxagQGI6wdY2 +VGQ== X-Gm-Message-State: AOAM533BKqgcm+h/fwr+q5BGKd6HGiLqyNjp/oXZyekyxulVkFGikM+Y Ttc8112LINP5VzaXwrHxH5qtSQ== X-Received: by 2002:a17:90b:1d8f:: with SMTP id pf15mr25802114pjb.36.1620628302025; Sun, 09 May 2021 23:31:42 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id o140sm10219688pfd.65.2021.05.09.23.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:41 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 04/14] efi: Fix to use null handle to create new handle for efi_fmp_raw Date: Mon, 10 May 2021 15:31:37 +0900 Message-Id: <162062829690.501222.2649388175245001703.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean When running the efidebug capsule disk-update command, the efi_fmp_raw protocol installation is failed with 2 (EFI_INVALID_PARAMETER) as below. This is because the code passes efi_root instaed of handle. => efidebug capsule disk-update EFI: Call: efi_install_multiple_protocol_interfaces( &handle, &efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL) EFI: Entry efi_install_multiple_protocol_interfaces(00000000fbaf5988) EFI: Call: efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Entry efi_install_protocol_interface(00000000fbaf5988, 86c77a67-0b97-4633-a187-49104d0685c7, 0, 00000000fbfa6ee8) EFI: new handle 00000000fbb37520 EFI: Exit: efi_install_protocol_interface: 0 EFI: 0 returned by efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Exit: efi_install_multiple_protocol_interfaces: 0 EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle, &efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL) EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL) EFI: Entry efi_install_multiple_protocol_interfaces(00000000fbfec648) EFI: Call: efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Entry efi_install_protocol_interface(00000000fbfec648, 86c77a67-0b97-4633-a187-49104d0685c7, 0, 00000000fbfa6f18) EFI: handle 00000000fbaf8520 EFI: Exit: efi_install_protocol_interface: 2 EFI: 2 returned by efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Exit: efi_install_multiple_protocol_interfaces: 2 EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL) Command failed, result=1 To fix this issue, pass the handle variable as same as the efi_fmp_fit installation. Signed-off-by: Masami Hiramatsu --- lib/efi_loader/efi_capsule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 6ee883d5b1..f038245c93 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -949,7 +949,7 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void) if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) { handle = NULL; ret = EFI_CALL(efi_install_multiple_protocol_interfaces( - &efi_root, + &handle, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)); } From patchwork Mon May 10 06:31:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433035 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2564828jao; Sun, 9 May 2021 23:32:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1J9DI2jgj9y4MkF74WA1vs5h46vBkDMKybtrkyR3iEWNpDFh2UDRx2YxYWsCuZsSiqsH6 X-Received: by 2002:a17:906:15c7:: with SMTP id l7mr2017111ejd.167.1620628322563; Sun, 09 May 2021 23:32:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628322; cv=none; d=google.com; s=arc-20160816; b=WfNJDVUqJ7r/r2ypSwKkcpBOU0TQXaxiX/jtvpH4a6RHK04n5gbPqpr5LZ0iy07Yso zh+l+zFgfugiBPmwxUct9IYw46Lb+FEqmwRZnEn+C27WjmvtSVHCYr/F2AIrKcL+D5sX 5NHZkWeZQs2S2YrtcHr1a6//9N3TwcNj/euMKjrkW9J+TfeXjnquse+f99A0kFet6dwp edzn639x6yruPgbb00K2KsraELosH4cFHkgGnsDLHEi2AVNbvmaYaICuIX7kDxY8cG1e 8W7hOT6C7K3TFC+6hpeR8dc4skCajtB5MaoJj5lHyKjNHGua6LKK0ZTNxGU4CqvjpoL+ EpZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kNMvCq5NSLUhOWBROkv/ngQG1SNtYOXkbhnsI12D2E8=; b=FWv2+uzeIJpkiYSqK5sH1fP/tJFum+iyF2Z/tCxT+VYRsT/fxTyy3zxco1tHKmeD2R 3S4VdoM0xQoxMA2LkZbXSgEP8lT33lcSPi4Z1GRoyfG49jEp+zo8BI4Rj5KzP4yanwIB gOVauF5h+Z1ozhPoFIGvNrUJmaTmptuWugd+VZfMQ9pNkX/erCsnaKhdFx6NxsNrcj3l zozM5NNIyUu2swMR9wWbfNz+u6HoZObRL7dVhc4wTk7/me4Z6/iaEvJA8wDnBxasXe5k hHZd4eeKKcvT+U+GSLz0GrRemPseZ+y/kG6twn+ybsGsS6+P+2ARJA2S6GZnid69jAoY tEZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r8j/UZbe"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id do16si12326360ejc.105.2021.05.09.23.32.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:02 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="r8j/UZbe"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 35A2182EAE; Mon, 10 May 2021 08:32:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="r8j/UZbe"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B6D4782EAE; Mon, 10 May 2021 08:31:59 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 68EFF82EC8 for ; Mon, 10 May 2021 08:31:54 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pl1-x629.google.com with SMTP id t21so8633323plo.2 for ; Sun, 09 May 2021 23:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=kNMvCq5NSLUhOWBROkv/ngQG1SNtYOXkbhnsI12D2E8=; b=r8j/UZbedc7nk9p+F+wIk/79qHUuOYztamA7YpZpGd3sagEPWyZe7A4qym35dq0P3n JBD1yUfYjfA2JYg+F+9QYaAR7V2cK9cX9WbUBHqiwjqB2G6bf6bzRUcUT/Meevk5Unzu KiHbJFSNQxNwM/WYDuWjoKHDcBuPOISP+Er5mL64zNCa8Qfa+CIneocM+pjzewaH2GfS 6xFwAJf391XeEWle0C7BabFq5rkbHwgMTMPFwCj+5hM23V4w7dFk+cnBA45lPy1zdotc CFWDyH8JtrjwQc8qLjmcg1ZR36XD8zhiMEAUDnWWa1doFyr04dNKRBbdjaznsJ7xRKYO htRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=kNMvCq5NSLUhOWBROkv/ngQG1SNtYOXkbhnsI12D2E8=; b=KrKoywGDFsQn9HzYZzWRVaACKaOUfhS1tH0oGPkUmUI1gZnBVQ+xHn64jiz0NfSfQ/ 40N+e68r+wDeAwmad7pqmw9hFLNpr6gZ8lz0ZYfQLyoTUSqGZGY+an9H+1Nndb80GPQ/ 10I3ZtOI1y4XvXlFHzMyXVPEbojHJomTVxDiJ8xEjBYNcuwb87WaY2mvcl+5SUXyTA8K 7dFnINpPDU8IBAnSyCGP1st7MT/cBpdtoUOFIu2Vl6GUJMqoNbLl3hKZdx17rQrfTjFs zXOmZUF3obIbgX3D6OV0f/jFTmVrUHnTNUDNBvwfQIUL1sW2JmFGowE8YmBby+ob2nGV y8NQ== X-Gm-Message-State: AOAM53135Us5lLtP+kM9QWW1qrN56R4WkIY+qM/LVk+VURamn84WbD7n 0UEpXDo5OjKiiglTh+3UvQZ/YQ== X-Received: by 2002:a17:90b:703:: with SMTP id s3mr27090429pjz.69.1620628312686; Sun, 09 May 2021 23:31:52 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id i24sm10091406pfd.35.2021.05.09.23.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:31:52 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 05/14] gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs Date: Mon, 10 May 2021 15:31:47 +0900 Message-Id: <162062830744.501222.5764354502088824981.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Since some SoCs and boards do not hae extra asm/arch/gpio.h, introduce CONFIG_GPIO_EXTRA_HEADER instead of adding !define(CONFIG_ARCH_XXXX) in asm/gpio.h. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Change the config name to positive and selected by the opposite CONFIG_ARCH_*. (Build checked by Github CI) --- arch/arm/Kconfig | 94 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/gpio.h | 8 ---- 2 files changed, 95 insertions(+), 7 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..023824df77 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -90,6 +90,9 @@ config HAS_VBAR config HAS_THUMB2 bool +config GPIO_EXTRA_HEADER + bool + # Used for compatibility with asm files copied from the kernel config ARM_ASM_UNIFIED bool @@ -518,25 +521,30 @@ choice config ARCH_AT91 bool "Atmel AT91" + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" select CPU_ARM920T + select GPIO_EXTRA_HEADER select PL010_SERIAL config TARGET_ASPENITE bool "Support aspenite" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_GPLUGD bool "Support gplugd" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL imply CMD_SAVES help @@ -547,6 +555,7 @@ config ARCH_KIRKWOOD select ARCH_MISC_INIT select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" @@ -555,6 +564,7 @@ config ARCH_MVEBU select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL select OF_CONTROL @@ -565,11 +575,13 @@ config ARCH_MVEBU config ARCH_ORION5X bool "Marvell Orion" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER config TARGET_SPEAR300 bool "Support spear300" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -577,6 +589,7 @@ config TARGET_SPEAR310 bool "Support spear310" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -584,6 +597,7 @@ config TARGET_SPEAR320 bool "Support spear320" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -591,6 +605,7 @@ config TARGET_SPEAR600 bool "Support spear600" select BOARD_EARLY_INIT_F select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL imply CMD_SAVES @@ -601,6 +616,7 @@ config TARGET_STV0991 select DM_SERIAL select DM_SPI select DM_SPI_FLASH + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SPI select SPI_FLASH @@ -610,18 +626,21 @@ config TARGET_X600 bool "Support x600" select BOARD_LATE_INIT select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_BCM283X bool "Broadcom BCM283X family" select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SERIAL_SEARCH_ALL @@ -650,6 +669,7 @@ config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select OF_PRIOR_STAGE imply CMD_DM @@ -660,6 +680,7 @@ config ARCH_BCMSTB config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A + select GPIO_EXTRA_HEADER imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH @@ -671,6 +692,7 @@ config TARGET_BCMCYGNUS config TARGET_BCMNS2 bool "Support Broadcom Northstar2" select ARM64 + select GPIO_EXTRA_HEADER help Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit ARMv8 Cortex-A57 processors targeting a broad range of networking @@ -695,6 +717,7 @@ config ARCH_EXYNOS select DM_SPI select DM_SPI_FLASH select SPI + select GPIO_EXTRA_HEADER imply SYS_THUMB_BUILD imply CMD_DM imply FAT_WRITE @@ -706,6 +729,7 @@ config ARCH_S5PC1XX select DM_GPIO select DM_I2C select DM_SERIAL + select GPIO_EXTRA_HEADER imply CMD_DM config ARCH_HIGHBANK @@ -726,6 +750,7 @@ config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select PL01X_SERIAL imply CMD_DM @@ -736,6 +761,7 @@ config ARCH_IPQ40XX select DM_GPIO select DM_SERIAL select DM_RESET + select GPIO_EXTRA_HEADER select MSM_SMEM select PINCTRL select CLK @@ -747,6 +773,7 @@ config ARCH_KEYSTONE bool "TI Keystone" select CMD_POWEROFF select CPU_V7A + select GPIO_EXTRA_HEADER select SUPPORT_SPL select SYS_ARCH_TIMER select SYS_THUMB_BUILD @@ -763,6 +790,7 @@ config ARCH_K3 config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7A + select GPIO_EXTRA_HEADER select SPL_BOARD_INIT if SPL select SPL_STACK_R if SPL select SUPPORT_SPL @@ -771,6 +799,7 @@ config ARCH_OMAP2PLUS config ARCH_MESON bool "Amlogic Meson" + select GPIO_EXTRA_HEADER imply DISTRO_DEFAULTS imply DM_RNG help @@ -781,6 +810,7 @@ config ARCH_MESON config ARCH_MEDIATEK bool "MediaTek SoCs" select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_DM if SPL select SPL_LIBCOMMON_SUPPORT if SPL @@ -797,6 +827,7 @@ config ARCH_LPC32XX select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select SPL_DM if SPL select SUPPORT_SPL imply CMD_DM @@ -805,12 +836,14 @@ config ARCH_IMX8 bool "NXP i.MX8 platform" select ARM64 select DM + select GPIO_EXTRA_HEADER select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -823,33 +856,39 @@ config ARCH_IMXRT select CPU_V7M select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select SUPPORT_SPL imply CMD_DM config ARCH_MX23 bool "NXP i.MX23 family" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER imply MXC_GPIO config ARCH_MX28 bool "NXP i.MX28 family" select CPU_ARM926EJS + select GPIO_EXTRA_HEADER select PL011_SERIAL select SUPPORT_SPL config ARCH_MX31 bool "NXP i.MX31 family" select CPU_ARM1136 + select GPIO_EXTRA_HEADER config ARCH_MX7ULP bool "NXP MX7ULP" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -861,6 +900,7 @@ config ARCH_MX7 bool "Freescale MX7" select ARCH_MISC_INIT select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -871,6 +911,7 @@ config ARCH_MX7 config ARCH_MX6 bool "Freescale MX6" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -886,18 +927,21 @@ config ARCH_MX5 bool "Freescale MX5" select BOARD_EARLY_INIT_F select CPU_V7A + select GPIO_EXTRA_HEADER imply MXC_GPIO config ARCH_NEXELL bool "Nexell S5P4418/S5P6818 SoC" select ENABLE_ARM_SOC_BOOT0_HOOK select DM + select GPIO_EXTRA_HEADER config ARCH_OWL bool "Actions Semi OWL SoCs" select DM select DM_ETH select DM_SERIAL + select GPIO_EXTRA_HEADER select OWL_SERIAL select CLK select CLK_OWL @@ -920,6 +964,7 @@ config ARCH_RMOBILE bool "Renesas ARM SoCs" select DM select DM_SERIAL + select GPIO_EXTRA_HEADER imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE @@ -932,6 +977,7 @@ config ARCH_SNAPDRAGON select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select MSM_SMEM select OF_CONTROL select OF_SEPARATE @@ -947,6 +993,7 @@ config ARCH_SOCFPGA select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL select SPL_DM_RESET if DM_RESET @@ -998,6 +1045,7 @@ config ARCH_SUNXI select DM_SCSI if SCSI select DM_SERIAL select DM_USB if DISTRO_DEFAULTS + select GPIO_EXTRA_HEADER select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE @@ -1057,6 +1105,7 @@ config ARCH_VERSAL select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL imply BOARD_LATE_INIT imply ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -1064,6 +1113,7 @@ config ARCH_VERSAL config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A + select GPIO_EXTRA_HEADER select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS imply MTD_RAW_NAND @@ -1080,6 +1130,7 @@ config ARCH_ZYNQ select DM_SPI select DM_SPI_FLASH select DM_USB if USB + select GPIO_EXTRA_HEADER select OF_CONTROL select SPI select SPL_BOARD_INIT if SPL @@ -1106,6 +1157,7 @@ config ARCH_ZYNQMP_R5 select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL imply CMD_DM imply DM_USB_GADGET @@ -1123,6 +1175,7 @@ config ARCH_ZYNQMP select DM_SPI_FLASH if DM_SPI select DM_USB if USB select FIRMWARE + select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_BOARD_INIT if SPL select SPL_CLK if SPL @@ -1143,23 +1196,27 @@ config ARCH_ZYNQMP config ARCH_TEGRA bool "NVIDIA Tegra" + select GPIO_EXTRA_HEADER imply DISTRO_DEFAULTS imply FAT_WRITE config TARGET_VEXPRESS64_AEMV8A bool "Support vexpress_aemv8a" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL select SEMIHOSTING config TARGET_VEXPRESS64_JUNO bool "Support Versatile Express Juno Development Platform" select ARM64 + select GPIO_EXTRA_HEADER select PL01X_SERIAL select DM select OF_CONTROL @@ -1188,6 +1245,7 @@ config TARGET_LS2080A_EMU select ARM64 select ARMV8_MULTIENTRY select FSL_DDR_SYNC_REFRESH + select GPIO_EXTRA_HEADER help Support for Freescale LS2080A_EMU platform. The LS2080A Development System (EMULATOR) is a pre-silicon @@ -1201,6 +1259,7 @@ config TARGET_LS1088AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT help @@ -1216,6 +1275,7 @@ config TARGET_LS2080AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL imply SCSI imply SCSI_AHCI @@ -1237,6 +1297,7 @@ config TARGET_LS2080ARDB select SUPPORT_SPL select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1251,6 +1312,7 @@ config TARGET_LS2081ARDB select ARM64 select ARMV8_MULTIENTRY select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER select SUPPORT_SPL help Support for Freescale LS2081ARDB platform. @@ -1265,6 +1327,7 @@ config TARGET_LX2160ARDB select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2160ARDB platform. The lx2160ardb (LX2160A Reference design board (RDB) @@ -1278,6 +1341,7 @@ config TARGET_LX2160AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2160AQDS platform. The lx2160aqds (LX2160A QorIQ Development System (QDS) @@ -1292,6 +1356,7 @@ config TARGET_LX2162AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for NXP LX2162AQDS platform. The lx2162aqds support is based on LX2160A Layerscape Architecture processor. @@ -1302,6 +1367,7 @@ config TARGET_HIKEY select DM select DM_GPIO select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SPECIFY_CONSOLE_INDEX @@ -1315,6 +1381,7 @@ config TARGET_HIKEY960 select ARM64 select DM select DM_SERIAL + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL imply CMD_DM @@ -1328,6 +1395,7 @@ config TARGET_POPLAR select DM select DM_SERIAL select DM_USB + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL imply CMD_DM @@ -1343,6 +1411,7 @@ config TARGET_LS1012AQDS select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1012AQDS platform. The LS1012A Development System (QDS) is a high-performance @@ -1355,6 +1424,7 @@ config TARGET_LS1012ARDB select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1369,6 +1439,7 @@ config TARGET_LS1012A2G5RDB select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1012A2G5RDB platform. @@ -1382,6 +1453,7 @@ config TARGET_LS1012AFRWY select ARM64 select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1395,6 +1467,7 @@ config TARGET_LS1012AFRDM select ARCH_LS1012A select ARM64 select ARCH_SUPPORT_TFABOOT + select GPIO_EXTRA_HEADER help Support for Freescale LS1012AFRDM platform. The LS1012A Freedom board (FRDM) is a high-performance @@ -1408,6 +1481,7 @@ config TARGET_LS1028AQDS select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1028AQDS platform The LS1028A Development System (QDS) is a high-performance @@ -1421,6 +1495,7 @@ config TARGET_LS1028ARDB select ARMV8_MULTIENTRY select ARCH_SUPPORT_TFABOOT select BOARD_LATE_INIT + select GPIO_EXTRA_HEADER help Support for Freescale LS1028ARDB platform The LS1028A Development System (RDB) is a high-performance @@ -1436,6 +1511,7 @@ config TARGET_LS1088ARDB select BOARD_LATE_INIT select SUPPORT_SPL select FSL_DDR_INTERACTIVE if !SD_BOOT + select GPIO_EXTRA_HEADER help Support for NXP LS1088ARDB platform. The LS1088A Reference design board (RDB) is a high-performance @@ -1456,6 +1532,7 @@ config TARGET_LS1021AQDS select SYS_FSL_DDR select FSL_DDR_INTERACTIVE select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI imply SCSI @@ -1471,6 +1548,7 @@ config TARGET_LS1021ATWR select LS1_DEEP_SLEEP select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER imply SCSI config TARGET_PG_WCOM_SELI8 @@ -1484,6 +1562,7 @@ config TARGET_PG_WCOM_SELI8 select CPU_V7_HAS_VIRT select SYS_FSL_DDR select FSL_DDR_INTERACTIVE + select GPIO_EXTRA_HEADER select VENDOR_KM imply SCSI help @@ -1502,6 +1581,7 @@ config TARGET_LS1021ATSN select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP select SUPPORT_SPL + select GPIO_EXTRA_HEADER imply SCSI config TARGET_LS1021AIOT @@ -1514,6 +1594,7 @@ config TARGET_LS1021AIOT select CPU_V7_HAS_VIRT select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1021AIOT platform. @@ -1533,6 +1614,7 @@ config TARGET_LS1043AQDS select FSL_DDR_INTERACTIVE if !SPL select FSL_DSPI if !SPL_NO_DSPI select DM_SPI_FLASH if FSL_DSPI + select GPIO_EXTRA_HEADER imply SCSI imply SCSI_AHCI help @@ -1549,6 +1631,7 @@ config TARGET_LS1043ARDB select SUPPORT_SPL select FSL_DSPI if !SPL_NO_DSPI select DM_SPI_FLASH if FSL_DSPI + select GPIO_EXTRA_HEADER help Support for Freescale LS1043ARDB platform. @@ -1565,6 +1648,7 @@ config TARGET_LS1046AQDS select FSL_DDR_BIST if !SPL select FSL_DDR_INTERACTIVE if !SPL select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046AQDS platform. @@ -1585,6 +1669,7 @@ config TARGET_LS1046ARDB select SUPPORT_SPL select FSL_DDR_BIST select FSL_DDR_INTERACTIVE if !SPL + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046ARDB platform. @@ -1601,6 +1686,7 @@ config TARGET_LS1046AFRWY select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM_SPI_FLASH if DM_SPI + select GPIO_EXTRA_HEADER imply SCSI help Support for Freescale LS1046AFRWY platform. @@ -1629,6 +1715,7 @@ config TARGET_SL28 select DM_SERIAL select DM_SPI select DM_USB + select GPIO_EXTRA_HEADER select SPL_DM if SPL select SPL_DM_SPI if SPL select SPL_DM_SPI_FLASH if SPL @@ -1641,6 +1728,7 @@ config TARGET_SL28 config TARGET_COLIBRI_PXA270 bool "Support colibri_pxa270" select CPU_PXA + select GPIO_EXTRA_HEADER config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" @@ -1677,6 +1765,7 @@ config ARCH_STM32 select CPU_V7M select DM select DM_SERIAL + select GPIO_EXTRA_HEADER imply CMD_DM config ARCH_STI @@ -1702,6 +1791,7 @@ config ARCH_STM32MP select DM_GPIO select DM_RESET select DM_SERIAL + select GPIO_EXTRA_HEADER select MISC select OF_CONTROL select OF_LIBFDT @@ -1764,6 +1854,7 @@ config ARCH_OCTEONTX bool "Support OcteonTX SoCs" select CLK select DM + select GPIO_EXTRA_HEADER select ARM64 select OF_CONTROL select OF_LIVE @@ -1774,6 +1865,7 @@ config ARCH_OCTEONTX2 bool "Support OcteonTX2 SoCs" select CLK select DM + select GPIO_EXTRA_HEADER select ARM64 select OF_CONTROL select OF_LIVE @@ -1783,6 +1875,7 @@ config ARCH_OCTEONTX2 config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 + select GPIO_EXTRA_HEADER select OF_CONTROL select PL01X_SERIAL select SYS_CACHE_SHIFT_7 @@ -1796,6 +1889,7 @@ config ARCH_ASPEED config TARGET_DURIAN bool "Support Phytium Durian Platform" select ARM64 + select GPIO_EXTRA_HEADER help Support for durian platform. It has 2GB Sdram, uart and pcie. diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 7609367884..650783ae73 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,10 +1,4 @@ -#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ - !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \ - !defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \ - !defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \ - !defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM) && \ - !defined(CONFIG_TARGET_BCMNS3) && !defined(CONFIG_TARGET_TOTAL_COMPUTE) && \ - !defined(CONFIG_ARCH_QEMU) +#ifdef CONFIG_GPIO_EXTRA_HEADER #include #endif #include From patchwork Mon May 10 06:31:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433036 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2564929jao; Sun, 9 May 2021 23:32:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxDuTaAqJFY0PJ522U2wShVxSH+xO8doMA5z6knLLUFK5NeiWnp6Zk/pMPc99Ai1RIPRDQz X-Received: by 2002:a05:6402:1281:: with SMTP id w1mr23608582edv.148.1620628333615; Sun, 09 May 2021 23:32:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628333; cv=none; d=google.com; s=arc-20160816; b=XgUBj2AXVe0y7tZ1VVFV3xrxGd7oJG7yXPBGlpNWnGkXXfnsoS2vGnTUMLLBRW0aXw MdBp4NhqjeQB08MCUWCFjrQLYj6SnWu9IckuTxcXUYLOl3GcIrVL17GIfREi8u8ZNEGZ deFKBEXo7j2Tg/9/VxMho/RIjKrgVy79bC0gCxsKv0sHZEi7Psh3I53Ocu3xlxxYwWXd KEQzlo/3xx1q6CGIGB13Ho/Oi8qGQfUrze8XlCpDc8hmGQ+VRmH0OFz7yWqWQYKhGA8J 06MTdOsM3hT0yZ4lJcLvj73UC6w8WOF6hC4ckL3PVt1pNq/EPgSa6CpXEGENG/Sm1t+D Zluw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=PXmN9guEUKyUVJnJ5VdpDHMXobmlcN2VlQCUc+QQ+DM=; b=F//11EyWgpSH9EG+oIOECYKFheLWBRV1pR45t+YfljFKaVomUtgLEdDVVyzKBaRj5E dQZC4Xz0gqTXsochoOvj8YudBcpTC8CPjWMequ4nJWoWlBxB4WtEa6afqCmABDvYk45M 8MFxBWnxxyF39VpVhEgdtTV33k/ctb2EvLCHwIzO7HQFATU2YaJ08DUG2UgSY6LawEDp 6ZjtJNKaZYoKXuQszqsFyYu8fQW5ZffpXK3DxGA/HwBOLhJtFFDep6XeAubxJDS+9lrq ytOnt1m5hUY4qRW7CtG3eRHS9uVY4Alw2K+znc1EOkTNEQR8cnvO9/9mzy5k6GFnuRIo UAZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b6wQFubZ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id gx23si11390603ejb.47.2021.05.09.23.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:13 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b6wQFubZ; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 06A0D82ED2; Mon, 10 May 2021 08:32:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="b6wQFubZ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CAF9B82ED1; Mon, 10 May 2021 08:32:09 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D47B482B71 for ; Mon, 10 May 2021 08:32:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pj1-x1030.google.com with SMTP id cl24-20020a17090af698b0290157efd14899so9691564pjb.2 for ; Sun, 09 May 2021 23:32:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=PXmN9guEUKyUVJnJ5VdpDHMXobmlcN2VlQCUc+QQ+DM=; b=b6wQFubZESwd1HIf82IEOIjyQ2EpYagEmQs2Ipe2CyfXa9sWHOrzx8EE1S9nCZV77r uJ3KFhLGZC1aLyskkPlIrEdbBgCvYZCj7gsju9b/kX5LQwZp7JMZKB3XHt5LBHavBS+s i57Cix3MhaPGMVUNwcWWaMn3q85P79ULXVbspurxdF/yEFpVc4ZvwLi+mAcBvjUxFnk5 KaT51K+mKmipl+vArSm8e1DOpNlcCn2KYPsXR6TK0wxOFzHlAc5jDQvIEUVWH/xJN278 3SoHIC1d6txS4i1WMCzGHGZdKTteDqrDhDmoj2los8oh2eq8eO2UKp4MdfTUKc6ZJgXA rVgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=PXmN9guEUKyUVJnJ5VdpDHMXobmlcN2VlQCUc+QQ+DM=; b=cYoS9K4hOD4ZRmpyeHFj+is/EEO2ydOBxf/x0uR88JvuUXqpsSxgPZrEAvB7DzUQ+E 1BJO4M4Isy3MGOMrddkhKQgXJ/WItCYaAVo0MY2RfGZrvSFTa/+W7D8FAGWqdcy8BNxQ aBnPlJjP9OCNgT0LQQiX68y3z0yGLmvpOms3W4PCIU9Ip7PAMA0jqw329eQ0H5JxGKNa kzfqKa2K3yQOyUhT+ErWY5xP1HkuGtGQ4Wkbqym1sDHJ+z1kCPi8t2vjXSk/Y/lyQltp MJPchZJXR9u1xgfmTmsYLyGzWRkdX3HPd4f0ZgP5nxQejf4RXoghi3egcQkop9US9J2D +vxw== X-Gm-Message-State: AOAM5307Bzaj3Hc02bypD6SaR38BggGXkwKKIjpD68KrYG7cbF0v4VqI guMLRCmytb5UVuQaw62nFkC84uT93d0Z2MAc X-Received: by 2002:a17:90a:b907:: with SMTP id p7mr25064960pjr.79.1620628323248; Sun, 09 May 2021 23:32:03 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id j7sm9675827pfc.164.2021.05.09.23.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:02 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 06/14] pci: synquacer: Add SynQuacer ECAM based PCIe driver Date: Mon, 10 May 2021 15:31:58 +0900 Message-Id: <162062831812.501222.10313303764630216413.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add ECAM based SynQuacer PCIe RC driver. This driver configures the PCIe RC and filter out a ghost pcie config. Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device is configured by firmware (EDK2), it doesn't re-configure in the kernel. So as same as EDK2, U-Boot needs to configure it before boot the kernel. Signed-off-by: Masami Hiramatsu --- drivers/pci/Kconfig | 12 + drivers/pci/Makefile | 1 drivers/pci/pcie_ecam_synquacer.c | 600 +++++++++++++++++++++++++++++++++++++ 3 files changed, 613 insertions(+) create mode 100644 drivers/pci/pcie_ecam_synquacer.c diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index d5b6018b3d..2e6393f25b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -81,6 +81,18 @@ config PCIE_ECAM_GENERIC Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. +config PCIE_ECAM_SYNQUACER + bool "SynQuacer ECAM-based PCI host controller support" + default n + depends on DM_PCI + select PCI_INIT_R + select PCI_REGION_MULTI_ENTRY + help + Say Y here if you want to enable support for Socionext + SynQuacer SoC's ECAM-based PCIe host controllers. + Note that this must be configured when boot because Linux driver + expects the PCIe RC has been configured in the bootloader. + config PCI_PHYTIUM bool "Phytium PCIe support" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 1f741786a0..035e3d3088 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -16,6 +16,7 @@ endif obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o +obj-$(CONFIG_PCIE_ECAM_SYNQUACER) += pcie_ecam_synquacer.o obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o diff --git a/drivers/pci/pcie_ecam_synquacer.c b/drivers/pci/pcie_ecam_synquacer.c new file mode 100644 index 0000000000..c6e7c59f8a --- /dev/null +++ b/drivers/pci/pcie_ecam_synquacer.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SynQuacer PCIE host driver + * + * Based on drivers/pci/pcie_ecam_generic.c + * + * Copyright (C) 2016 Imagination Technologies + * Copyright (C) 2021 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include + +/* iATU registers */ +#define IATU_VIEWPORT_OFF 0x900 +#define IATU_VIEWPORT_INBOUND BIT(31) +#define IATU_VIEWPORT_OUTBOUND 0 +#define IATU_VIEWPORT_REGION_INDEX(idx) ((idx) & 7) + +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT(12) + +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT(31) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT(28) +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF + +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914 +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918 +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C + +/* Clock and resets */ +#define CORE_CONTROL 0x000 +#define APP_LTSSM_ENABLE BIT(4) +#define DEVICE_TYPE (BIT(3) | BIT(2) | BIT(1) | BIT(0)) + +#define AXI_CLK_STOP 0x004 +#define DBI_ACLK_STOP BIT(8) +#define SLV_ACLK_STOP BIT(4) +#define MSTR_ACLK_STOP BIT(0) +#define DBI_CSYSREQ_REG BIT(9) +#define SLV_CSYSREQ_REG BIT(5) +#define MSTR_CSYSREQ_REG BIT(1) + +#define RESET_CONTROL_1 0x00C +#define PERST_N_O_REG BIT(5) +#define PERST_N_I_REG BIT(4) +#define BUTTON_RST_N_REG BIT(1) +#define PWUP_RST_N_REG BIT(0) + +#define RESET_CONTROL_2 0x010 + +#define RESET_SELECT_1 0x014 +#define SQU_RST_SEL BIT(29) +#define PHY_RST_SEL BIT(28) +#define PWR_RST_SEL BIT(24) +#define STI_RST_SEL BIT(20) +#define N_STI_RST_SEL BIT(16) +#define CORE_RST_SEL BIT(12) +#define PERST_SEL BIT(4) +#define BUTTON_RST_SEL BIT(1) +#define PWUP_RST_SEL BIT(0) + +#define RESET_SELECT_2 0x018 +#define DBI_ARST_SEL BIT(8) +#define SLV_ARST_SEL BIT(4) +#define MSTR_ARST_SEL BIT(0) + +#define EM_CONTROL 0x030 +#define PRE_DET_STT_REG BIT(4) + +#define EM_SELECT 0x034 +#define PRE_DET_STT_SEL BIT(4) + +#define PM_CONTROL_2 0x050 +#define SYS_AUX_PWR_DET BIT(8) + +#define PHY_CONFIG_COM_6 0x114 +#define PIPE_PORT_SEL GENMASK(1, 0) + +#define LINK_MONITOR 0x210 +#define SMLH_LINK_UP BIT(0) + +#define LINK_CAPABILITIES_REG 0x07C +#define PCIE_CAP_MAX_LINK_WIDTH GENMASK(7, 4) +#define PCIE_CAP_MAX_LINK_SPEED GENMASK(3, 0) + +#define LINK_CONTROL_LINK_STATUS_REG 0x080 +#define PCIE_CAP_NEGO_LINK_WIDTH GENMASK(23, 20) +#define PCIE_CAP_LINK_SPEED GENMASK(19, 16) + +#define TYPE1_CLASS_CODE_REV_ID_REG 0x008 +#define BASE_CLASS_CODE 0xFF000000 +#define BASE_CLASS_CODE_VALUE 0x06 +#define SUBCLASS_CODE 0x00FF0000 +#define SUBCLASS_CODE_VALUE 0x04 +#define PROGRAM_INTERFACE 0x0000FF00 +#define PROGRAM_INTERFACE_VALUE 0x00 + +#define GEN2_CONTROL_OFF 0x80c +#define DIRECT_SPEED_CHANGE BIT(17) + +#define MISC_CONTROL_1_OFF 0x8BC +#define DBI_RO_WR_EN BIT(0) + +static void or_writel(void *base, u32 offs, u32 val) +{ + writel(readl(base + offs) | val, base + offs); +} + +static void masked_writel(void *base, u32 offs, u32 mask, u32 val) +{ + u32 data; + int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */ + + if (val && shift > 1) + val <<= shift - 1; + + if (mask != ~0) + data = (readl(base + offs) & ~mask) | val; + else + data = val; + + writel(data, base + offs); +} + +static u32 masked_readl(void *base, u32 offs, u32 mask) +{ + u32 data; + int shift = ffs(mask); /* Note that ffs() returns 1 for 0x1 */ + + data = readl(base + offs); + + if (mask != ~0) + data &= mask; + if (shift > 1) + data >>= shift - 1; + + return data; +} + +/* + * Since SynQuacer's PCIe RC is expected to be initialized in the + * firmware (including U-Boot), devicetree doesn't have control + * blocks. + * + * Thus, this will initialize the PCIe RC with fixed addresses. + */ + +#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000 +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000 +#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000 + +#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000 +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000 +#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000 +#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000 + +#define SIZE_16KB 0x00004000 +#define SIZE_64KB 0x00010000 +#define SIZE_1MB 0x00100000 + +#define SYNQUACER_PCI_DBI_SIZE SIZE_16KB +#define SYNQUACER_PCI_EXS_SIZE SIZE_64KB + +#define NUM_SQ_PCI_RC 2 + +static const struct synquacer_pcie_base { + phys_addr_t cfg_base; + phys_addr_t dbi_base; + phys_addr_t exs_base; +} synquacer_pci_bases[NUM_SQ_PCI_RC] = { + { + .cfg_base = SYNQUACER_PCI_SEG0_CONFIG_BASE, + .dbi_base = SYNQUACER_PCI_SEG0_DBI_BASE, + .exs_base = SYNQUACER_PCI_SEG0_EXS_BASE, + }, { + .cfg_base = SYNQUACER_PCI_SEG1_CONFIG_BASE, + .dbi_base = SYNQUACER_PCI_SEG1_DBI_BASE, + .exs_base = SYNQUACER_PCI_SEG1_EXS_BASE, + }, +}; + +/** + * struct synquacer_ecam_pcie - synquacer_ecam PCIe controller state + * @cfg_base: The base address of memory mapped configuration space + */ +struct synquacer_ecam_pcie { + void *cfg_base; + pci_size_t size; + void *dbi_base; + void *exs_base; + int first_busno; + + struct pci_region mem; + struct pci_region io; + struct pci_region mem64; +}; + +DECLARE_GLOBAL_DATA_PTR; + +/** + * pci_synquacer_ecam_conf_address() - Calculate the address of a config access + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @paddress: Pointer to the pointer to write the calculates address to + * + * Calculates the address that should be accessed to perform a PCIe + * configuration space access for a given device identified by the PCIe + * controller device @pcie and the bus, device & function numbers in @bdf. If + * access to the device is not valid then the function will return an error + * code. Otherwise the address to access will be written to the pointer pointed + * to by @paddress. + */ +static int pci_synquacer_ecam_conf_address(const struct udevice *bus, + pci_dev_t bdf, uint offset, + void **paddress) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(bus); + void *addr; + + addr = pcie->cfg_base; + addr += (PCI_BUS(bdf) - pcie->first_busno) << 20; + addr += PCI_DEV(bdf) << 15; + addr += PCI_FUNC(bdf) << 12; + addr += offset; + *paddress = addr; + + return 0; +} + +static bool pci_synquacer_ecam_addr_valid(const struct udevice *bus, + pci_dev_t bdf) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(bus); + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); + + /* + * The Synopsys DesignWare PCIe controller in ECAM mode will not filter + * type 0 config TLPs sent to devices 1 and up on its downstream port, + * resulting in devices appearing multiple times on bus 0 unless we + * filter out those accesses here. + */ + if (PCI_BUS(bdf) == pcie->first_busno && PCI_DEV(bdf) > 0) + return false; + + return (PCI_BUS(bdf) >= pcie->first_busno && + PCI_BUS(bdf) < pcie->first_busno + num_buses); +} + +/** + * pci_synquacer_ecam_read_config() - Read from configuration space + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @valuep: A pointer at which to store the read value + * @size: Indicates the size of access to perform + * + * Read a value of size @size from offset @offset within the configuration + * space of the device identified by the bus, device & function numbers in @bdf + * on the PCI bus @bus. + */ +static int pci_synquacer_ecam_read_config(const struct udevice *bus, + pci_dev_t bdf, uint offset, + ulong *valuep, enum pci_size_t size) +{ + if (!pci_synquacer_ecam_addr_valid(bus, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + + return pci_generic_mmap_read_config(bus, pci_synquacer_ecam_conf_address, + bdf, offset, valuep, size); +} + +/** + * pci_synquacer_ecam_write_config() - Write to configuration space + * @bus: Pointer to the PCI bus + * @bdf: Identifies the PCIe device to access + * @offset: The offset into the device's configuration space + * @value: The value to write + * @size: Indicates the size of access to perform + * + * Write the value @value of size @size from offset @offset within the + * configuration space of the device identified by the bus, device & function + * numbers in @bdf on the PCI bus @bus. + */ +static int pci_synquacer_ecam_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + if (!pci_synquacer_ecam_addr_valid(bus, bdf)) + return 0; + + return pci_generic_mmap_write_config(bus, pci_synquacer_ecam_conf_address, + bdf, offset, value, size); +} + +/** + * pci_synquacer_ecam_of_to_plat() - Translate from DT to device state + * @dev: A pointer to the device being operated on + * + * Translate relevant data from the device tree pertaining to device @dev into + * state that the driver will later make use of. This state is stored in the + * device's private data structure. + * + * Return: 0 on success, else -EINVAL + */ +static int pci_synquacer_ecam_of_to_plat(struct udevice *dev) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(dev); + struct fdt_resource reg_res; + int i, err; + + debug("%s: called for %s\n", __func__, dev->name); + + err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", + 0, ®_res); + if (err < 0) { + pr_err("\"reg\" resource not found\n"); + return err; + } + + /* Find the correct pair of the DBI/EXS base address */ + for (i = 0; i < NUM_SQ_PCI_RC; i++) { + if (synquacer_pci_bases[i].cfg_base == reg_res.start) + break; + } + if (i == NUM_SQ_PCI_RC) { + pr_err("Unknown ECAM base address %lx.\n", + (unsigned long)reg_res.start); + return -ENOENT; + } + pcie->dbi_base = map_physmem(synquacer_pci_bases[i].dbi_base, + SYNQUACER_PCI_DBI_SIZE, MAP_NOCACHE); + if (!pcie->dbi_base) { + pr_err("Failed to map DBI for %s\n", dev->name); + return -ENOMEM; + } + + pcie->exs_base = map_physmem(synquacer_pci_bases[i].exs_base, + SYNQUACER_PCI_EXS_SIZE, MAP_NOCACHE); + if (!pcie->exs_base) { + pr_err("Failed to map EXS for %s\n", dev->name); + return -ENOMEM; + } + + pcie->size = fdt_resource_size(®_res); + pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); + if (!pcie->cfg_base) { + pr_err("Failed to map config space for %s\n", dev->name); + return -ENOMEM; + } + debug("mappings DBI: %p EXS: %p CFG: %p\n", pcie->dbi_base, pcie->exs_base, pcie->cfg_base); + + return 0; +} + +static void pci_synquacer_pre_init(struct synquacer_ecam_pcie *pcie) +{ + void *base = pcie->exs_base; + + masked_writel(base, EM_SELECT, PRE_DET_STT_SEL, 0); + masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 0); + masked_writel(base, EM_CONTROL, PRE_DET_STT_REG, 1); + + /* 1: Assert all PHY / LINK resets */ + masked_writel(base, RESET_SELECT_1, PERST_SEL, 0); + masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 0); + masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 0); + + /* Device Reset(PERST#) is effective afrer Set device_type (RC) */ + masked_writel(base, RESET_SELECT_1, PWUP_RST_SEL, 0); + masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 0); + masked_writel(base, RESET_SELECT_1, BUTTON_RST_SEL, 0); + masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 0); + masked_writel(base, RESET_SELECT_1, PWR_RST_SEL, 1); + masked_writel(base, RESET_SELECT_2, MSTR_ARST_SEL, 1); + masked_writel(base, RESET_SELECT_2, SLV_ARST_SEL, 1); + masked_writel(base, RESET_SELECT_2, DBI_ARST_SEL, 1); + masked_writel(base, RESET_SELECT_1, CORE_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, STI_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, N_STI_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, SQU_RST_SEL, 1); + masked_writel(base, RESET_SELECT_1, PHY_RST_SEL, 1); + + /* 2: Set P_app_ltssm_enable='0' for reprogramming before linkup. */ + masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 0); + + /* 3: Set device_type (RC) */ + masked_writel(base, CORE_CONTROL, DEVICE_TYPE, 4); +} + +static void pci_synquacer_dbi_init(void *dbi_base) +{ + masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 1); + /* 4 Lanes */ + masked_writel(dbi_base, LINK_CAPABILITIES_REG, + PCIE_CAP_MAX_LINK_WIDTH, 4); + /* Gen 2 */ + masked_writel(dbi_base, LINK_CAPABILITIES_REG, + PCIE_CAP_MAX_LINK_SPEED, 2); + + masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG, + BASE_CLASS_CODE, BASE_CLASS_CODE_VALUE); + masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG, + SUBCLASS_CODE, SUBCLASS_CODE_VALUE); + masked_writel(dbi_base, TYPE1_CLASS_CODE_REV_ID_REG, + PROGRAM_INTERFACE, PROGRAM_INTERFACE_VALUE); + + masked_writel(dbi_base, MISC_CONTROL_1_OFF, DBI_RO_WR_EN, 0); +} + +static void pcie_sq_prog_outbound_atu(void *dbi_base, int index, + u64 cpu_base, u64 pci_base, u64 size, + u32 type, u32 flags) +{ + debug("%s: %p, %d, %llx, %llx, %llx, %x, %x\n", __func__, + dbi_base, index, cpu_base, pci_base, size, type, flags); + + writel(IATU_VIEWPORT_OUTBOUND | IATU_VIEWPORT_REGION_INDEX(index), + dbi_base + IATU_VIEWPORT_OFF); + + writel((u32)(cpu_base & 0xffffffff), + dbi_base + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0); + writel((u32)(cpu_base >> 32), + dbi_base + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0); + writel((u32)(cpu_base + size - 1), + dbi_base + IATU_LIMIT_ADDR_OFF_OUTBOUND_0); + + writel((u32)(pci_base & 0xffffffff), + dbi_base + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0); + writel((u32)(pci_base >> 32), + dbi_base + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0); + + writel(type, dbi_base + IATU_REGION_CTRL_1_OFF_OUTBOUND_0); + writel(IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN | flags, + dbi_base + IATU_REGION_CTRL_2_OFF_OUTBOUND_0); +} + +static void pci_synquacer_post_init(struct synquacer_ecam_pcie *pcie) +{ + void *base = pcie->exs_base; + + /* + * 4: Set Bifurcation 1=disable 4=able + * 5: Supply Reference (It has executed) + * 6: Wait for 10usec (Reference Clocks is stable) + * 7: De assert PERST# + */ + masked_writel(base, RESET_CONTROL_1, PERST_N_I_REG, 1); + masked_writel(base, RESET_CONTROL_1, PERST_N_O_REG, 1); + + /* 8: Assert SYS_AUX_PWR_DET */ + masked_writel(base, PM_CONTROL_2, SYS_AUX_PWR_DET, 1); + + /* 9: Supply following clocks */ + masked_writel(base, AXI_CLK_STOP, MSTR_CSYSREQ_REG, 1); + masked_writel(base, AXI_CLK_STOP, MSTR_ACLK_STOP, 0); + masked_writel(base, AXI_CLK_STOP, SLV_CSYSREQ_REG, 1); + masked_writel(base, AXI_CLK_STOP, SLV_ACLK_STOP, 0); + masked_writel(base, AXI_CLK_STOP, DBI_CSYSREQ_REG, 1); + masked_writel(base, AXI_CLK_STOP, DBI_ACLK_STOP, 0); + + /* + * 10: De assert PHY reset + * 11: De assert LINK's PMC reset + */ + masked_writel(base, RESET_CONTROL_1, PWUP_RST_N_REG, 1); + masked_writel(base, RESET_CONTROL_1, BUTTON_RST_N_REG, 1); + + /* 12: PHY auto + * 13: Wrapper auto + * 14-17: PHY auto + * 18: Wrapper auto + * 19: Update registers through DBI AXI Slave interface + */ + pci_synquacer_dbi_init(pcie->dbi_base); + + or_writel(pcie->dbi_base, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Force link speed change to Gen2 at link up */ + or_writel(pcie->dbi_base, GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + + /* Region 0: MMIO32 range */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 0, + pcie->mem.phys_start, + pcie->mem.bus_start, + pcie->mem.size, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); + + /* Region 1: Type 0 config space */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 1, + (u64)pcie->cfg_base, + 0, + SIZE_64KB, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE); + + /* Region 2: Type 1 config space */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 2, + (u64)pcie->cfg_base + SIZE_64KB, + 0, + (u64)pcie->io.phys_start - (u64)pcie->cfg_base - SIZE_64KB, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE); + + /* Region 3: port I/O range */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 3, + pcie->io.phys_start, + pcie->io.bus_start, + pcie->io.size, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, + 0); + + /* Region 4: MMIO64 range */ + pcie_sq_prog_outbound_atu(pcie->dbi_base, 4, + pcie->mem64.phys_start, + pcie->mem64.bus_start, + pcie->mem64.size, + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); + + /* enable link */ + if (masked_readl(base, CORE_CONTROL, APP_LTSSM_ENABLE) == 0) + masked_writel(base, CORE_CONTROL, APP_LTSSM_ENABLE, 1); +} + +static int pci_synquacer_ecam_probe(struct udevice *dev) +{ + struct synquacer_ecam_pcie *pcie = dev_get_priv(dev); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(ctlr); + + debug("Probe synquacer pcie for bus %d\n", dev_seq(dev)); + pcie->first_busno = dev_seq(dev); + + /* Store the IO and MEM windows settings for configuring ATU */ + pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */ + pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */ + pcie->io.size = hose->regions[0].size; /* IO size */ + + pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */ + pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */ + pcie->mem.size = hose->regions[1].size; /* MEM size */ + + pcie->mem64.phys_start = hose->regions[2].phys_start; /* MEM64 base */ + pcie->mem64.bus_start = hose->regions[2].bus_start; /* MEM64_bus_addr */ + pcie->mem64.size = hose->regions[2].size; /* MEM64 size */ + + pci_synquacer_pre_init(pcie); + + mdelay(150); + + pci_synquacer_post_init(pcie); + + /* It takes a while to stabilize the PCIe bus for scanning */ + mdelay(100); + + return 0; +} + +static const struct dm_pci_ops pci_synquacer_ecam_ops = { + .read_config = pci_synquacer_ecam_read_config, + .write_config = pci_synquacer_ecam_write_config, +}; + +static const struct udevice_id pci_synquacer_ecam_ids[] = { + { .compatible = "socionext,synquacer-pcie-ecam" }, + { } +}; + +U_BOOT_DRIVER(pci_synquacer_ecam) = { + .name = "pci_synquacer_ecam", + .id = UCLASS_PCI, + .of_match = pci_synquacer_ecam_ids, + .ops = &pci_synquacer_ecam_ops, + .probe = pci_synquacer_ecam_probe, + .of_to_plat = pci_synquacer_ecam_of_to_plat, + .priv_auto = sizeof(struct synquacer_ecam_pcie), +}; From patchwork Mon May 10 06:32:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433037 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565031jao; Sun, 9 May 2021 23:32:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwjXgzVTBgR7nOPdEKiexQjebQc2X+LRDfkEvFsRXD/wT1PtNdiLgFXan9SL00saVI627sJ X-Received: by 2002:aa7:de99:: with SMTP id j25mr6394574edv.91.1620628345632; Sun, 09 May 2021 23:32:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628345; cv=none; d=google.com; s=arc-20160816; b=Hp3sk28ahlqgfk7kvlR73VlgNxjSDNZuOBD76IRqXUg9RFCwPyMO9fzD68zBnMBSrA JHJ9Z0EqJcIWcFdgmRd4WmanH0iig4cUskyWnYtsMDsTG59CkzbvD+8VfSGiJFKCYy6N JgSmXDD48wHXGwtt7IrEGFebi6PjlC67adSIyVq0+eS7agJPvvnF4Iz5MfnN2aLypgkm tM2T5e9NPg5Invrbg+D3RjGEzvWf3tPzNUBATI38QitmO9qze+1lLW0sov4TiVfMn+Pp TSLnHiLpksb2DGl+JoapXktJHslN4/KpdFpSwARRUw8NbXFWoIcwnIsOQwYrAl0f7KNo ooXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=npvXnpPiP367k1OhBMtAMtri6Gp/DHUlQp4+fs3A9Tk=; b=X2MFNe+/TQj+35FKZlAlNoj1uhqbpbSkZdsNGy6Gce6lSwYEsSaOmLxBc2qVRV4PWk IibkqFsScSb6Zkd1OfNuxijbfODw6/SuxbV3ryEOEmRX7rqRYxtVAhpZFFkaxS+m1dae uU7/1yt3jEvFi8Ic66u/LitCauWfxkf3k185NM5xYPTaUcTvpdb2KZMb2pI0eHFQbMaO Gn/NpQPQ+J/rYcdCa9LlQmSz5QThoz1yFcmSgot5d1b3oWPdgh69cNcyJJ3adYD795ha OHk1Q+yiUEyPvRZenyxj0CgCmtsNvL/2LiT50RTKX9ofTmEw7VKm36vYwfYkYqBSeAm/ iKfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rnCbXnwD; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id y8si9928882edq.378.2021.05.09.23.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:25 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rnCbXnwD; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5F78F82ED4; Mon, 10 May 2021 08:32:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="rnCbXnwD"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5BFE782ED4; Mon, 10 May 2021 08:32:18 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2048682B71 for ; Mon, 10 May 2021 08:32:15 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pg1-x52c.google.com with SMTP id j12so6502522pgh.7 for ; Sun, 09 May 2021 23:32:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=npvXnpPiP367k1OhBMtAMtri6Gp/DHUlQp4+fs3A9Tk=; b=rnCbXnwDmvorqS3fqStcrI2RN33gEph7nQeZBLXnpjf9lN2jaxMohFWmipXe3Bhv5V oN4N6/APxaSq9OJemz6HCcmDWCFJVNXJumXDKbEMtwHP4ms2juZN8qNO26q3MoTgwcn1 DFi7ke97pVqOUfwYRP749Yz3NKVWhEju+e6Yp5k9tue+Ek8pfETEj2o9DenLd/R/rxo1 EdmW3xfUux+2HRvhAyB4OJAEnG1bF5gzt1OmxTgcux4hbBr+RG4G4HuUxP93mt4VF6EY N7Zb+27DATlVfHGMm1NXHl+brY2cIL2N9bS5BrIAjy61NUPTUrSPbQ0hH2ShT1vwsqRj MCkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=npvXnpPiP367k1OhBMtAMtri6Gp/DHUlQp4+fs3A9Tk=; b=FZUsXMd19j9dULrNbQBaDUA1ACIKZ39GLfjYwhoUF8q9s1u1m8ydEg8F2tVGQORdeX VuRcYJsYvMKAl9mJdGH/8TPsgB6HdcUawZ35FYdHVrARUg9YGm+BL17Tux8xZEkAjStw uWgoxYB0SD7rsL0cAaUvvwgmIohMdbqdqyOm8saMhBiEJevpjsTDMe4S6+dYCW7f4BPM 2KWgSCWvyVGtkw3Ryb0Xf7SQ2Ah0bhKILwe8V1ycCmtSMg0MIy4XBKsHs2r0d52N52cK rb1HfivoThY43yyrUffndkJwWyAec1Zw6mwMz3Cod2XHjLj82TR6HQuazUUG6fgsn+m+ UZhQ== X-Gm-Message-State: AOAM532Yd/1NWFD+Q3Io6YTMJFN591MYwMsSLBHRPgstMf/zfcFYXbnD 3xbK+czrXNGGkpG7x9BXwofUWQ== X-Received: by 2002:a65:640f:: with SMTP id a15mr10795517pgv.251.1620628333680; Sun, 09 May 2021 23:32:13 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id 187sm10308993pff.139.2021.05.09.23.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:13 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 07/14] mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver Date: Mon, 10 May 2021 15:32:08 +0900 Message-Id: <162062832864.501222.1041145417453522338.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Jassi Brar Signed-off-by: Jassi Brar Signed-off-by: Masami Hiramatsu --- Changes in v3: - Rename config name to MMC_SDHCI_F_SDH30. - Remove unneeded wait in drivers/mmc/sdhci.c. - Rename probe function to f_sdh30_sdhci_probe. --- drivers/mmc/Kconfig | 10 ++++++ drivers/mmc/Makefile | 1 + drivers/mmc/f_sdh30.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 drivers/mmc/f_sdh30.c Reviewed-by: Jaehoon Chung diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f4ad1db45d..026b6f7d24 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -559,6 +559,16 @@ config MMC_SDHCI_IPROC If unsure, say N. +config MMC_SDHCI_F_SDH30 + bool "SDHCI support for Fujitsu Semiconductor F_SDH30" + depends on BLK && DM_MMC + depends on MMC_SDHCI + help + This selects the Secure Digital Host Controller Interface (SDHCI) + Needed by some Fujitsu SoC for MMC / SD / SDIO support. + If you have a controller with this interface, say Y or M here. + If unsure, say N. + config MMC_SDHCI_KONA bool "SDHCI support on Broadcom KONA platform" depends on MMC_SDHCI diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 89d6af3db3..f5fd59093e 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -76,3 +76,4 @@ obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o obj-$(CONFIG_MMC_MTK) += mtk-sd.o +obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c new file mode 100644 index 0000000000..3a85d9e348 --- /dev/null +++ b/drivers/mmc/f_sdh30.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Socionext F_SDH30 eMMC driver + * Copyright 2021 Linaro Ltd. + * Copyright 2021 Socionext, Inc. + */ + +#include +#include +#include +#include +#include + +struct f_sdh30_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int f_sdh30_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct f_sdh30_plat *plat = dev_get_plat(dev); + struct sdhci_host *host = dev_get_priv(dev); + int ret; + + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; + + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; + + ret = sdhci_setup_cfg(&plat->cfg, host, 200000000, 400000); + if (ret) + return ret; + + upriv->mmc = host->mmc; + + mmc_set_clock(host->mmc, host->mmc->cfg->f_min, MMC_CLK_ENABLE); + + return sdhci_probe(dev); +} + +static int f_sdh30_of_to_plat(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + + host->name = strdup(dev->name); + host->ioaddr = dev_read_addr_ptr(dev); + host->bus_width = dev_read_u32_default(dev, "bus-width", 4); + host->index = dev_read_u32_default(dev, "index", 0); + + return 0; +} + +static int f_sdh30_bind(struct udevice *dev) +{ + struct f_sdh30_plat *plat = dev_get_plat(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id f_sdh30_mmc_ids[] = { + { .compatible = "fujitsu,mb86s70-sdhci-3.0" }, + { } +}; + +U_BOOT_DRIVER(f_sdh30_drv) = { + .name = "f_sdh30_sdhci", + .id = UCLASS_MMC, + .of_match = f_sdh30_mmc_ids, + .of_to_plat = f_sdh30_of_to_plat, + .ops = &sdhci_ops, + .bind = f_sdh30_bind, + .probe = f_sdh30_sdhci_probe, + .priv_auto = sizeof(struct sdhci_host), + .plat_auto = sizeof(struct f_sdh30_plat), +}; From patchwork Mon May 10 06:32:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433038 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565135jao; Sun, 9 May 2021 23:32:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIBwDYUA73rTdMekQN3zaKlD1Abxa9/QsOgqe2dYIw9B/+s0v4wubHl3KyJ+Xjf7uZgRNw X-Received: by 2002:aa7:dd19:: with SMTP id i25mr27761446edv.247.1620628356251; Sun, 09 May 2021 23:32:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628356; cv=none; d=google.com; s=arc-20160816; b=0PRZac4MOT279yaF+QjH247NT9lptYEer0Hq9x229lDdlbfUZmxIzzz7nL43Pbmv7B aG2ciW4AoLmHyV5xhOAiho9KknMUyIxco0Uc5y7Rc0KqxzkwvyFpAqTWQrM1Nt4tOSLR g/JxRXLw9eZBoW+UQW3XdH4BUvq18ThR+6wPc0mSGveYTvDV+Y7GDMQ3mm77CRGmxxeM cNtw2BWsj1PySSD5xCpjwH8RcvPt8VVISUQ4DZ3EFyGv5jjkHFpaNCWX24//jIMWjCiT /s6Nhp60uVZXQA5UwwzbEP2K7Qgxb/XREFx0+wTGFcNU0sGX/p0lgwnWOVM3HB5RLB52 y7oQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ztMh4mDq2LmepDFWWDX2D7aYx7SsicB+NEG/qsKUL3s=; b=d1/xWECVScW1KXIyeQ6WOjpNuhEBlppWxugw4Ch+ie/uQeEmCXZYZxu1zU8HFJzx/5 GrEVJV3no2OR2iCpCxlPrHN3A3a0mcDdrVuTAEteUYeVax5Dx2MR6n74H2dKVQfz0KGQ 5sF7gv7jEdLZ4L+5YyPcuKH712Bd05ecKPOZQsSmHuKlxA0V9yaBTxUJELKq8ZxLoV2W XwyZ/Oca9ZlCz31JtjRwdVjY7rJs2fnVUqrKDQWr/PztrQrIEuRG2yeYbSK2PegHytzT v4BHs/rctqErOuBmd7F96HDXVRI2UH1XgM7DMbPj3KKPJOLx0GfG6IlHfX3UKN19iEUC GfgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HeXCzj6c; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id r14si9368755edy.200.2021.05.09.23.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:36 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HeXCzj6c; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A469382ECF; Mon, 10 May 2021 08:32:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="HeXCzj6c"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 742F282ECF; Mon, 10 May 2021 08:32:30 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4D5D082ECF for ; Mon, 10 May 2021 08:32:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pg1-x52f.google.com with SMTP id t193so32443pgb.4 for ; Sun, 09 May 2021 23:32:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=ztMh4mDq2LmepDFWWDX2D7aYx7SsicB+NEG/qsKUL3s=; b=HeXCzj6c/nForerd2qP7wTGvNV5A36uR/P+98tBOL7AO+S2u2y6RBQhKogGG7o6UA+ WC7AamvXxpuWZzVP+Mm7QHASBpw1mq7WKChiPJNpJECErhciGjwb7jgoBo8gB7nORK8C BVqBNg4Wi9wqZJtk91cmaBQUhTlGARjN8Ybc1y5uoZfm1MbaC07r54i3TulTrNPX3k+m xpxQdKR3/F/XSkVtbQ96XeRLRGAoq4oOnGBUacDxAkwBYojnIHUG9AdEUWREYXwN4fHu YGxwLOrXi5Pp7810ueQrxGD0CxBv2KvdszR2RHTKMp1a789Mflrym00xz79cGdsyh1cz eg6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=ztMh4mDq2LmepDFWWDX2D7aYx7SsicB+NEG/qsKUL3s=; b=dmt9RzR8B5RJIy1b5dyTjnbR3DdPjALuIViGFkcAkSEfShEh2VFNO4wq3UvF5YqnVc rCEQTZm/JlJPBIiPT5R//2L3pl54jKeqb52lGzrSIK/nzXUHkF+dh6uPHOGqRylowGTw ZpNI3zu8NEIcrd5UU+77y3QzTMo7no9pu3DlwyU8JXffswYH0jirrbZFmttqnIT85TMU M3D5FXYZcOxj1KDFCJ4MHGTso1BQ7oBV2nkypjQo6DX1KV3B5FYcO5SgqaUPXp3CNtnx viPY7sZnQqP1zjNYaNjcDlq5hbQfuNkeB8SasFB1dZr6NxlSJhCyM3zvWQB/VB01KRt/ lP2w== X-Gm-Message-State: AOAM5333CFMreigQzfkK9wx9vd9fiUG2CL/56onVqgREn+uc2Mw4O/LX 8gEptiwE33NXBhxCLcbmbJv9Gw== X-Received: by 2002:a63:d49:: with SMTP id 9mr23347126pgn.317.1620628344622; Sun, 09 May 2021 23:32:24 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id y66sm10401515pgb.14.2021.05.09.23.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:24 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 08/14] spi: synquacer: Add HSSPI SPI controller driver for SynQuacer Date: Mon, 10 May 2021 15:32:19 +0900 Message-Id: <162062833903.501222.4763248909232329535.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Jassi Brar This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar Signed-off-by: Masami Hiramatsu --- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 drivers/spi/spi-synquacer.c | 491 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 500 insertions(+) create mode 100644 drivers/spi/spi-synquacer.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1494c91763..62d9676550 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -481,4 +481,12 @@ config MXC_SPI Enable the MXC SPI controller driver. This driver can be used on various i.MX SoCs such as i.MX31/35/51/6/7. +config SYNQUACER_SPI + bool "Socionext SynQuacer HS-SPI driver" + depends on ARCH_SYNQUACER + help + Enable the Socionext HS-SPI driver for SynQuacer. This driver can + be used to access the SPI interface and SPI NOR flash on platforms + embedding this HS-SPI IP core. + endif # menu "SPI Support" diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cfe4fae1d4..98c95323d1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o +obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c new file mode 100644 index 0000000000..ce558c4bc0 --- /dev/null +++ b/drivers/spi/spi-synquacer.c @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * spi-synquacer.c - Socionext Synquacer SPI driver + * Copyright 2021 Linaro Ltd. + * Copyright 2021 Socionext, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MCTRL 0x0 +#define MEN 0 +#define CSEN 1 +#define IPCLK 3 +#define MES 4 +#define SYNCON 5 + +#define PCC0 0x4 +#define PCC(n) (PCC0 + (n) * 4) +#define RTM 3 +#define ACES 2 +#define SAFESYNC 16 +#define CPHA 0 +#define CPOL 1 +#define SSPOL 4 +#define SDIR 7 +#define SS2CD 5 +#define SENDIAN 8 +#define CDRS_SHIFT 9 +#define CDRS_MASK 0x7f + +#define TXF 0x14 +#define TXE 0x18 +#define TXC 0x1c +#define RXF 0x20 +#define RXE 0x24 +#define RXC 0x28 +#define TFLETE 4 +#define RFMTE 5 + +#define FAULTF 0x2c +#define FAULTC 0x30 + +#define DMCFG 0x34 +#define SSDC 1 +#define MSTARTEN 2 + +#define DMSTART 0x38 +#define TRIGGER 0 +#define DMSTOP 8 +#define CS_MASK 3 +#define CS_SHIFT 16 +#define DATA_TXRX 0 +#define DATA_RX 1 +#define DATA_TX 2 +#define DATA_MASK 3 +#define DATA_SHIFT 26 +#define BUS_WIDTH 24 + +#define DMBCC 0x3c +#define DMSTATUS 0x40 +#define RX_DATA_MASK 0x1f +#define RX_DATA_SHIFT 8 +#define TX_DATA_MASK 0x1f +#define TX_DATA_SHIFT 16 + +#define TXBITCNT 0x44 + +#define FIFOCFG 0x4c +#define BPW_MASK 0x3 +#define BPW_SHIFT 8 +#define RX_FLUSH 11 +#define TX_FLUSH 12 +#define RX_TRSHLD_MASK 0xf +#define RX_TRSHLD_SHIFT 0 +#define TX_TRSHLD_MASK 0xf +#define TX_TRSHLD_SHIFT 4 + +#define TXFIFO 0x50 +#define RXFIFO 0x90 +#define MID 0xfc + +#define FIFO_DEPTH 16 +#define TX_TRSHLD 4 +#define RX_TRSHLD (FIFO_DEPTH - TX_TRSHLD) + +#define TXBIT 1 +#define RXBIT 2 + +DECLARE_GLOBAL_DATA_PTR; + +struct synquacer_spi_plat { + void __iomem *base; + bool aces, rtm; +}; + +struct synquacer_spi_priv { + void __iomem *base; + bool aces, rtm; + int speed, cs, mode, rwflag; + void *rx_buf; + const void *tx_buf; + unsigned int tx_words, rx_words; +}; + +static void read_fifo(struct synquacer_spi_priv *priv) +{ + u32 len = readl(priv->base + DMSTATUS); + u8 *buf = priv->rx_buf; + int i; + + len = (len >> RX_DATA_SHIFT) & RX_DATA_MASK; + len = min_t(unsigned int, len, priv->rx_words); + + for (i = 0; i < len; i++) + *buf++ = readb(priv->base + RXFIFO); + + priv->rx_buf = buf; + priv->rx_words -= len; +} + +static void write_fifo(struct synquacer_spi_priv *priv) +{ + u32 len = readl(priv->base + DMSTATUS); + const u8 *buf = priv->tx_buf; + int i; + + len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK; + len = min_t(unsigned int, FIFO_DEPTH - len, priv->tx_words); + + for (i = 0; i < len; i++) + writeb(*buf++, priv->base + TXFIFO); + + priv->tx_buf = buf; + priv->tx_words -= len; +} + +static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active) +{ + u32 val; + + val = readl(priv->base + DMSTART); + val &= ~(CS_MASK << CS_SHIFT); + val |= priv->cs << CS_SHIFT; + + if (active) { + writel(val, priv->base + DMSTART); + + val = readl(priv->base + DMSTART); + val &= ~BIT(DMSTOP); + writel(val, priv->base + DMSTART); + } else { + val |= BIT(DMSTOP); + writel(val, priv->base + DMSTART); + + if (priv->rx_buf) { + u32 buf[16]; + + priv->rx_buf = buf; + priv->rx_words = 16; + read_fifo(priv); + } + } +} + +static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx) +{ + struct udevice *bus = dev->parent; + struct synquacer_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + u32 val, div, bus_width; + int rwflag; + + rwflag = (rx ? 1 : 0) | (tx ? 2 : 0); + + /* if nothing to do */ + if (slave_plat->mode == priv->mode && + rwflag == priv->rwflag && + slave_plat->cs == priv->cs && + slave_plat->max_hz == priv->speed) + return; + + priv->rwflag = rwflag; + priv->cs = slave_plat->cs; + priv->mode = slave_plat->mode; + priv->speed = slave_plat->max_hz; + + if (priv->mode & SPI_TX_BYTE) + bus_width = 1; + else if (priv->mode & SPI_TX_DUAL) + bus_width = 2; + else if (priv->mode & SPI_TX_QUAD) + bus_width = 4; + else if (priv->mode & SPI_TX_OCTAL) + bus_width = 8; + + div = DIV_ROUND_UP(125000000, priv->speed); + + val = readl(priv->base + PCC(priv->cs)); + val &= ~BIT(RTM); + val &= ~BIT(ACES); + val &= ~BIT(SAFESYNC); + if ((priv->mode & (SPI_TX_DUAL | SPI_RX_DUAL)) && div < 3) + val |= BIT(SAFESYNC); + if ((priv->mode & (SPI_TX_QUAD | SPI_RX_QUAD)) && div < 6) + val |= BIT(SAFESYNC); + + if (priv->mode & SPI_CPHA) + val |= BIT(CPHA); + else + val &= ~BIT(CPHA); + + if (priv->mode & SPI_CPOL) + val |= BIT(CPOL); + else + val &= ~BIT(CPOL); + + if (priv->mode & SPI_CS_HIGH) + val |= BIT(SSPOL); + else + val &= ~BIT(SSPOL); + + if (priv->mode & SPI_LSB_FIRST) + val |= BIT(SDIR); + else + val &= ~BIT(SDIR); + + if (priv->aces) + val |= BIT(ACES); + + if (priv->rtm) + val |= BIT(RTM); + + val |= (3 << SS2CD); + val |= BIT(SENDIAN); + + val &= ~(CDRS_MASK << CDRS_SHIFT); + val |= ((div >> 1) << CDRS_SHIFT); + + writel(val, priv->base + PCC(priv->cs)); + + val = readl(priv->base + FIFOCFG); + val &= ~(BPW_MASK << BPW_SHIFT); + val |= (0 << BPW_SHIFT); + writel(val, priv->base + FIFOCFG); + + val = readl(priv->base + DMSTART); + val &= ~(DATA_MASK << DATA_SHIFT); + + if (tx && rx) + val |= (DATA_TXRX << DATA_SHIFT); + else if (rx) + val |= (DATA_RX << DATA_SHIFT); + else + val |= (DATA_TX << DATA_SHIFT); + + val &= ~(3 << BUS_WIDTH); + val |= ((bus_width >> 1) << BUS_WIDTH); + writel(val, priv->base + DMSTART); +} + +static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *tx_buf, void *rx_buf, + unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct synquacer_spi_priv *priv = dev_get_priv(bus); + u32 val, words, busy; + + val = readl(priv->base + FIFOCFG); + val |= (1 << RX_FLUSH); + val |= (1 << TX_FLUSH); + writel(val, priv->base + FIFOCFG); + + synquacer_spi_config(dev, rx_buf, tx_buf); + + priv->tx_buf = tx_buf; + priv->rx_buf = rx_buf; + + words = bitlen / 8; + + if (tx_buf) { + busy |= BIT(TXBIT); + priv->tx_words = words; + } else { + busy &= ~BIT(TXBIT); + priv->tx_words = 0; + } + + if (rx_buf) { + busy |= BIT(RXBIT); + priv->rx_words = words; + } else { + busy &= ~BIT(RXBIT); + priv->rx_words = 0; + } + + if (flags & SPI_XFER_BEGIN) + synquacer_cs_set(priv, true); + + if (tx_buf) + write_fifo(priv); + + if (rx_buf) { + val = readl(priv->base + FIFOCFG); + val &= ~(RX_TRSHLD_MASK << RX_TRSHLD_SHIFT); + val |= ((priv->rx_words > FIFO_DEPTH ? + RX_TRSHLD : priv->rx_words) << RX_TRSHLD_SHIFT); + writel(val, priv->base + FIFOCFG); + } + + writel(~0, priv->base + TXC); + writel(~0, priv->base + RXC); + + /* Trigger */ + val = readl(priv->base + DMSTART); + val |= BIT(TRIGGER); + writel(val, priv->base + DMSTART); + + while (busy & (BIT(RXBIT) | BIT(TXBIT))) { + if (priv->rx_words) + read_fifo(priv); + else + busy &= ~BIT(RXBIT); + + if (priv->tx_words) { + write_fifo(priv); + } else { + u32 len; + + do { /* wait for shifter to empty out */ + cpu_relax(); + len = readl(priv->base + DMSTATUS); + len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK; + } while (tx_buf && len); + busy &= ~BIT(TXBIT); + } + } + + if (flags & SPI_XFER_END) + synquacer_cs_set(priv, false); + + return 0; +} + +static int synquacer_spi_set_speed(struct udevice *bus, uint speed) +{ + return 0; +} + +static int synquacer_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int synquacer_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int synquacer_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static void synquacer_spi_disable_module(struct synquacer_spi_priv *priv) +{ + writel(0, priv->base + MCTRL); + while (readl(priv->base + MCTRL) & BIT(MES)) + cpu_relax(); +} + +static void synquacer_spi_init(struct synquacer_spi_priv *priv) +{ + u32 val; + + synquacer_spi_disable_module(priv); + + writel(0, priv->base + TXE); + writel(0, priv->base + RXE); + val = readl(priv->base + TXF); + writel(val, priv->base + TXC); + val = readl(priv->base + RXF); + writel(val, priv->base + RXC); + val = readl(priv->base + FAULTF); + writel(val, priv->base + FAULTC); + + val = readl(priv->base + DMCFG); + val &= ~BIT(SSDC); + val &= ~BIT(MSTARTEN); + writel(val, priv->base + DMCFG); + + /* Enable module with direct mode */ + val = readl(priv->base + MCTRL); + val &= ~BIT(IPCLK); + val &= ~BIT(CSEN); + val |= BIT(MEN); + val |= BIT(SYNCON); + writel(val, priv->base + MCTRL); +} + +static void synquacer_spi_exit(struct synquacer_spi_priv *priv) +{ + u32 val; + + synquacer_spi_disable_module(priv); + + /* Enable module with command sequence mode */ + val = readl(priv->base + MCTRL); + val &= ~BIT(IPCLK); + val |= BIT(CSEN); + val |= BIT(MEN); + val |= BIT(SYNCON); + writel(val, priv->base + MCTRL); + + while (!(readl(priv->base + MCTRL) & BIT(MES))) + cpu_relax(); +} + +static int synquacer_spi_probe(struct udevice *bus) +{ + struct synquacer_spi_plat *plat = dev_get_plat(bus); + struct synquacer_spi_priv *priv = dev_get_priv(bus); + + priv->base = plat->base; + priv->aces = plat->aces; + priv->rtm = plat->rtm; + + synquacer_spi_init(priv); + return 0; +} + +static int synquacer_spi_remove(struct udevice *bus) +{ + struct synquacer_spi_priv *priv = dev_get_priv(bus); + + synquacer_spi_exit(priv); + return 0; +} + +static int synquacer_spi_of_to_plat(struct udevice *bus) +{ + struct synquacer_spi_plat *plat = dev_get_plat(bus); + struct clk clk; + + plat->base = dev_read_addr_ptr(bus); + + plat->aces = dev_read_bool(bus, "socionext,set-aces"); + plat->rtm = dev_read_bool(bus, "socionext,use-rtm"); + + clk_get_by_name(bus, "iHCLK", &clk); + clk_enable(&clk); + + return 0; +} + +static const struct dm_spi_ops synquacer_spi_ops = { + .claim_bus = synquacer_spi_claim_bus, + .release_bus = synquacer_spi_release_bus, + .xfer = synquacer_spi_xfer, + .set_speed = synquacer_spi_set_speed, + .set_mode = synquacer_spi_set_mode, +}; + +static const struct udevice_id synquacer_spi_ids[] = { + { .compatible = "socionext,synquacer-spi" }, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(synquacer_spi) = { + .name = "synquacer_spi", + .id = UCLASS_SPI, + .of_match = synquacer_spi_ids, + .ops = &synquacer_spi_ops, + .of_to_plat = synquacer_spi_of_to_plat, + .plat_auto = sizeof(struct synquacer_spi_plat), + .priv_auto = sizeof(struct synquacer_spi_priv), + .probe = synquacer_spi_probe, + .flags = DM_FLAG_OS_PREPARE, + .remove = synquacer_spi_remove, +}; From patchwork Mon May 10 06:32:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433039 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565274jao; Sun, 9 May 2021 23:32:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHMeXJ9AJKBLEl7ogB9Bb9t6SJ7gLoI80vy1K/M2LqBQqLtrRhh52JTufDAGxRzld8UJnS X-Received: by 2002:a05:6402:c1:: with SMTP id i1mr27454296edu.315.1620628369310; Sun, 09 May 2021 23:32:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628369; cv=none; d=google.com; s=arc-20160816; b=CgLWgf4PyjZCxbYT5CkNl+dkb1YNLBHzKk3On3OynjaJczvkthVAw8iH6dal4kf5Ha /548fYoLq/5foPBbIHqwyrATA18URn3wEpxpoIdPBV+XyHN71frNaLCYNHB6vIxz9Lf9 FKw5jmg6mzeWTv3V/wKNoHDymb/aKfPBEXL/bn1fg7XCkF64BaZz/bzDJuI+T/h6Nys/ RTjQXLZtpc6rImlS5QxQhY3sM7LpmckKY4wgsBhIimTJthquI+0R89WqIS3JHjKbOyAw Yxo+3G8tZYrZ1IlStz7C56fRMCcE0Ysc+tkoDuvSGLSnaLVbPJJSp+keIfOhqAOvuvo2 mYAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=eMJHVBU8gRaT77SJ1QNHGe0/SCXPlIVrZuoZLC1Iz5E=; b=mtm+lw94wa11bVYaLowYs4DSImDVsF/XfVGBBwIUJrxxRP5i4fmNdQA5f3ffLR3CBQ +nqWf7yekMTl9+vVOGTdeK9MXGDJsP5szCgoXZZoqzUr0tnH4/OW2JZYwqmdsl5m1/t8 G7oYA5hZfOYtLIz4ZRTUTMqoe+oytrH10kUNjUJfF8kqEsF/mecp4dmQcst2laxdFdj0 ceKRNM+3pKWSTRKWKbRvDuKrcJAzIyTnq3xn6IxA4pnpufMxWe9v2PFxnZu3sw27tycg FrN/VBxO0FsinWGNU8/el2nAAX6kDesmIBQ9vfIa5NjwOKy84qW1oZb1DM8lW6PxVrYo oLwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ntD8Ski5; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id gu8si13173211ejb.497.2021.05.09.23.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:49 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ntD8Ski5; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DB0AE81D43; Mon, 10 May 2021 08:32:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ntD8Ski5"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AE7C282EDB; Mon, 10 May 2021 08:32:42 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 261C480050 for ; Mon, 10 May 2021 08:32:37 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pg1-x531.google.com with SMTP id s22so12561756pgk.6 for ; Sun, 09 May 2021 23:32:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=eMJHVBU8gRaT77SJ1QNHGe0/SCXPlIVrZuoZLC1Iz5E=; b=ntD8Ski5YhtuZ48Owy9t5mix9gN3kxJU5x0JSdOuzL/7DffOaCNAZawN2c4rJ7ZNiD ILoQFNbngpWAdXFT1xBNqOg8lxBh6tF7XDZZ+/3eZ5g52bbZfUd1Ybhbd5nfkD3r4jX4 yxiUbrpsfh4I1raY1HT8BU2TlKVpP50342+5H80GHb85xrzeEt5jXIXeMgXP9VLstL7P d/rcx+n6MBmomNPbQeyTsNoI0u4XE+JajkHel0sQij2k/hc5HneSDCI/BJO6ZrelmuNZ VmV5Ai4mCEiw2luV0Ge2vrC72ZIqxvuck5dUnjZhdhrlFEDtCMBhBzWqF7JrxIHUl8EY kETA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=eMJHVBU8gRaT77SJ1QNHGe0/SCXPlIVrZuoZLC1Iz5E=; b=uh6Vsg3/xh1R+Ik6NttR9RzU9q+eWzTdjlabquR/mEcczDLkDxmPlb7jcS/Z3KNxTL kXeC3vyVJPsQ2pnq7KXvkvhzy7SdG9UevY2kQnZY/CeIuWVqZSlJi6Tw4eKdmNI243Gd Ur2BVCu/+iX92Xc9o/NLHiFcXyCWLet2oRK/LTDQ2siZY/LyNxSmWHuSataefX3itJCN Pw9pMo0jEL9lVrYqYCYE1z8lR2ArVFNh2hfgKYNu0ansT5n8pwgwVwuM6UWZOBbngh0h l7v3iBzRmUjVvgME+7d4r91c0yHnIbey/5ptquJY+m1YJ/89CerJwQR26yXmx1pHmML8 jd7A== X-Gm-Message-State: AOAM533oXNOliQZnuYyiSCNiglwBSWa9JQDwer5J/U+E9TfHsAR4gU0K Z8b0iv06VBl4KaW+6wiS1ktMoQ== X-Received: by 2002:a63:cf01:: with SMTP id j1mr23994299pgg.131.1620628355287; Sun, 09 May 2021 23:32:35 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id e24sm7387871pgi.17.2021.05.09.23.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:34 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 09/14] net: synquacer: Add netsec driver Date: Mon, 10 May 2021 15:32:30 +0900 Message-Id: <162062835000.501222.3452378364952217599.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean From: Jassi Brar Add SynQuacer's NETSEC GbE controller driver. Since this driver will load the firmware from SPI NOR flash, this depends on CONFIG_SYNQUACER_SPI=y. Signed-off-by: Jassi Brar --- drivers/net/Kconfig | 8 drivers/net/Makefile | 1 drivers/net/sni_netsec.c | 1134 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1143 insertions(+) create mode 100644 drivers/net/sni_netsec.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 382639044b..9fc28b149d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -673,6 +673,14 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config SNI_NETSEC + bool "Socionext NETSEC Ethernet support" + depends on DM_ETH && SYNQUACER_SPI + select PHYLIB + help + This driver implements support for the Socionext SynQuacer NETSEC + ethernet controller, as found on the Socionext SynQuacer family. + source "drivers/net/mscc_eswitch/Kconfig" config ETHER_ON_FEC1 diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 2ce89f7e3c..c23e828edc 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-y += qe/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o obj-y += ti/ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-y += mscc_eswitch/ diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c new file mode 100644 index 0000000000..a9ebf6af9c --- /dev/null +++ b/drivers/net/sni_netsec.c @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/** + * netsec.c - Socionext Synquacer Netsec driver + * Copyright 2021 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NETSEC_REG_SOFT_RST 0x104 +#define NETSEC_REG_COM_INIT 0x120 + +#define NETSEC_REG_TOP_STATUS 0x200 +#define NETSEC_IRQ_RX BIT(1) +#define NETSEC_IRQ_TX BIT(0) + +#define NETSEC_REG_TOP_INTEN 0x204 +#define NETSEC_REG_INTEN_SET 0x234 +#define NETSEC_REG_INTEN_CLR 0x238 + +#define NETSEC_REG_NRM_TX_STATUS 0x400 +#define NETSEC_REG_NRM_TX_INTEN 0x404 +#define NETSEC_REG_NRM_TX_INTEN_SET 0x428 +#define NETSEC_REG_NRM_TX_INTEN_CLR 0x42c +#define NRM_TX_ST_NTOWNR BIT(17) +#define NRM_TX_ST_TR_ERR BIT(16) +#define NRM_TX_ST_TXDONE BIT(15) +#define NRM_TX_ST_TMREXP BIT(14) + +#define NETSEC_REG_NRM_RX_STATUS 0x440 +#define NETSEC_REG_NRM_RX_INTEN 0x444 +#define NETSEC_REG_NRM_RX_INTEN_SET 0x468 +#define NETSEC_REG_NRM_RX_INTEN_CLR 0x46c +#define NRM_RX_ST_RC_ERR BIT(16) +#define NRM_RX_ST_PKTCNT BIT(15) +#define NRM_RX_ST_TMREXP BIT(14) + +#define NETSEC_REG_PKT_CMD_BUF 0xd0 + +#define NETSEC_REG_CLK_EN 0x100 + +#define NETSEC_REG_PKT_CTRL 0x140 + +#define NETSEC_REG_DMA_TMR_CTRL 0x20c +#define NETSEC_REG_F_TAIKI_MC_VER 0x22c +#define NETSEC_REG_F_TAIKI_VER 0x230 +#define NETSEC_REG_DMA_HM_CTRL 0x214 +#define NETSEC_REG_DMA_MH_CTRL 0x220 +#define NETSEC_REG_ADDR_DIS_CORE 0x218 +#define NETSEC_REG_DMAC_HM_CMD_BUF 0x210 +#define NETSEC_REG_DMAC_MH_CMD_BUF 0x21c + +#define NETSEC_REG_NRM_TX_PKTCNT 0x410 + +#define NETSEC_REG_NRM_TX_DONE_PKTCNT 0x414 +#define NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT 0x418 + +#define NETSEC_REG_NRM_TX_TMR 0x41c + +#define NETSEC_REG_NRM_RX_PKTCNT 0x454 +#define NETSEC_REG_NRM_RX_RXINT_PKTCNT 0x458 +#define NETSEC_REG_NRM_TX_TXINT_TMR 0x420 +#define NETSEC_REG_NRM_RX_RXINT_TMR 0x460 + +#define NETSEC_REG_NRM_RX_TMR 0x45c + +#define NETSEC_REG_NRM_TX_DESC_START_UP 0x434 +#define NETSEC_REG_NRM_TX_DESC_START_LW 0x408 +#define NETSEC_REG_NRM_RX_DESC_START_UP 0x474 +#define NETSEC_REG_NRM_RX_DESC_START_LW 0x448 + +#define NETSEC_REG_NRM_TX_CONFIG 0x430 +#define NETSEC_REG_NRM_RX_CONFIG 0x470 + +#define MAC_REG_STATUS 0x1024 +#define MAC_REG_DATA 0x11c0 +#define MAC_REG_CMD 0x11c4 +#define MAC_REG_FLOW_TH 0x11cc +#define MAC_REG_INTF_SEL 0x11d4 +#define MAC_REG_DESC_INIT 0x11fc +#define MAC_REG_DESC_SOFT_RST 0x1204 +#define NETSEC_REG_MODE_TRANS_COMP_STATUS 0x500 + +#define GMAC_REG_MCR 0x0000 +#define GMAC_REG_MFFR 0x0004 +#define GMAC_REG_GAR 0x0010 +#define GMAC_REG_GDR 0x0014 +#define GMAC_REG_FCR 0x0018 +#define GMAC_REG_BMR 0x1000 +#define GMAC_REG_RDLAR 0x100c +#define GMAC_REG_TDLAR 0x1010 +#define GMAC_REG_OMR 0x1018 + +#define MHZ(n) ((n) * 1000 * 1000) + +#define NETSEC_TX_SHIFT_OWN_FIELD 31 +#define NETSEC_TX_SHIFT_LD_FIELD 30 +#define NETSEC_TX_SHIFT_DRID_FIELD 24 +#define NETSEC_TX_SHIFT_PT_FIELD 21 +#define NETSEC_TX_SHIFT_TDRID_FIELD 16 +#define NETSEC_TX_SHIFT_CC_FIELD 15 +#define NETSEC_TX_SHIFT_FS_FIELD 9 +#define NETSEC_TX_LAST 8 +#define NETSEC_TX_SHIFT_CO 7 +#define NETSEC_TX_SHIFT_SO 6 +#define NETSEC_TX_SHIFT_TRS_FIELD 4 + +#define NETSEC_RX_PKT_OWN_FIELD 31 +#define NETSEC_RX_PKT_LD_FIELD 30 +#define NETSEC_RX_PKT_SDRID_FIELD 24 +#define NETSEC_RX_PKT_FR_FIELD 23 +#define NETSEC_RX_PKT_ER_FIELD 21 +#define NETSEC_RX_PKT_ERR_FIELD 16 +#define NETSEC_RX_PKT_TDRID_FIELD 12 +#define NETSEC_RX_PKT_FS_FIELD 9 +#define NETSEC_RX_PKT_LS_FIELD 8 +#define NETSEC_RX_PKT_CO_FIELD 6 + +#define NETSEC_RX_PKT_ERR_MASK 3 + +#define NETSEC_MAX_TX_PKT_LEN 1518 +#define NETSEC_MAX_TX_JUMBO_PKT_LEN 9018 + +#define NETSEC_RING_GMAC 15 +#define NETSEC_RING_MAX 2 + +#define NETSEC_TCP_SEG_LEN_MAX 1460 +#define NETSEC_TCP_JUMBO_SEG_LEN_MAX 8960 + +#define NETSEC_RX_CKSUM_NOTAVAIL 0 +#define NETSEC_RX_CKSUM_OK 1 +#define NETSEC_RX_CKSUM_NG 2 + +#define NETSEC_TOP_IRQ_REG_ME_START BIT(20) +#define NETSEC_IRQ_TRANSITION_COMPLETE BIT(4) + +#define NETSEC_MODE_TRANS_COMP_IRQ_N2T BIT(20) +#define NETSEC_MODE_TRANS_COMP_IRQ_T2N BIT(19) + +#define NETSEC_INT_PKTCNT_MAX 2047 + +#define NETSEC_FLOW_START_TH_MAX 95 +#define NETSEC_FLOW_STOP_TH_MAX 95 +#define NETSEC_FLOW_PAUSE_TIME_MIN 5 + +#define NETSEC_CLK_EN_REG_DOM_ALL 0x3f + +#define NETSEC_PKT_CTRL_REG_MODE_NRM BIT(28) +#define NETSEC_PKT_CTRL_REG_EN_JUMBO BIT(27) +#define NETSEC_PKT_CTRL_REG_LOG_CHKSUM_ER BIT(3) +#define NETSEC_PKT_CTRL_REG_LOG_HD_INCOMPLETE BIT(2) +#define NETSEC_PKT_CTRL_REG_LOG_HD_ER BIT(1) +#define NETSEC_PKT_CTRL_REG_DRP_NO_MATCH BIT(0) + +#define NETSEC_CLK_EN_REG_DOM_G BIT(5) +#define NETSEC_CLK_EN_REG_DOM_C BIT(1) +#define NETSEC_CLK_EN_REG_DOM_D BIT(0) + +#define NETSEC_COM_INIT_REG_DB BIT(2) +#define NETSEC_COM_INIT_REG_CLS BIT(1) +#define NETSEC_COM_INIT_REG_ALL (NETSEC_COM_INIT_REG_CLS | \ + NETSEC_COM_INIT_REG_DB) + +#define NETSEC_SOFT_RST_REG_RESET 0 +#define NETSEC_SOFT_RST_REG_RUN BIT(31) + +#define NETSEC_DMA_CTRL_REG_STOP 1 +#define MH_CTRL__MODE_TRANS BIT(20) + +#define NETSEC_GMAC_CMD_ST_READ 0 +#define NETSEC_GMAC_CMD_ST_WRITE BIT(28) +#define NETSEC_GMAC_CMD_ST_BUSY BIT(31) + +#define NETSEC_GMAC_BMR_REG_COMMON 0x00412080 +#define NETSEC_GMAC_BMR_REG_RESET 0x00020181 +#define NETSEC_GMAC_BMR_REG_SWR 0x00000001 + +#define NETSEC_GMAC_OMR_REG_ST BIT(13) +#define NETSEC_GMAC_OMR_REG_SR BIT(1) + +#define NETSEC_GMAC_MCR_REG_IBN BIT(30) +#define NETSEC_GMAC_MCR_REG_CST BIT(25) +#define NETSEC_GMAC_MCR_REG_JE BIT(20) +#define NETSEC_MCR_PS BIT(15) +#define NETSEC_GMAC_MCR_REG_FES BIT(14) +#define NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON 0x0000280c +#define NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON 0x0001a00c + +#define NETSEC_FCR_RFE BIT(2) +#define NETSEC_FCR_TFE BIT(1) + +#define NETSEC_GMAC_GAR_REG_GW BIT(1) +#define NETSEC_GMAC_GAR_REG_GB BIT(0) + +#define NETSEC_GMAC_GAR_REG_SHIFT_PA 11 +#define NETSEC_GMAC_GAR_REG_SHIFT_GR 6 +#define GMAC_REG_SHIFT_CR_GAR 2 + +#define NETSEC_GMAC_GAR_REG_CR_25_35_MHZ 2 +#define NETSEC_GMAC_GAR_REG_CR_35_60_MHZ 3 +#define NETSEC_GMAC_GAR_REG_CR_60_100_MHZ 0 +#define NETSEC_GMAC_GAR_REG_CR_100_150_MHZ 1 +#define NETSEC_GMAC_GAR_REG_CR_150_250_MHZ 4 +#define NETSEC_GMAC_GAR_REG_CR_250_300_MHZ 5 + +#define NETSEC_GMAC_RDLAR_REG_COMMON 0x18000 +#define NETSEC_GMAC_TDLAR_REG_COMMON 0x1c000 + +#define NETSEC_REG_NETSEC_VER_F_TAIKI 0x50000 + +#define NETSEC_REG_DESC_RING_CONFIG_CFG_UP BIT(31) +#define NETSEC_REG_DESC_RING_CONFIG_CH_RST BIT(30) +#define NETSEC_REG_DESC_TMR_MODE 4 +#define NETSEC_REG_DESC_ENDIAN 0 + +#define NETSEC_MAC_DESC_SOFT_RST_SOFT_RST 1 +#define NETSEC_MAC_DESC_INIT_REG_INIT 1 + +#define NETSEC_EEPROM_MAC_ADDRESS 0x00 +#define NETSEC_EEPROM_HM_ME_ADDRESS_H 0x08 +#define NETSEC_EEPROM_HM_ME_ADDRESS_L 0x0C +#define NETSEC_EEPROM_HM_ME_SIZE 0x10 +#define NETSEC_EEPROM_MH_ME_ADDRESS_H 0x14 +#define NETSEC_EEPROM_MH_ME_ADDRESS_L 0x18 +#define NETSEC_EEPROM_MH_ME_SIZE 0x1C +#define NETSEC_EEPROM_PKT_ME_ADDRESS 0x20 +#define NETSEC_EEPROM_PKT_ME_SIZE 0x24 + +#define DESC_SZ sizeof(struct netsec_de) + +#define NETSEC_F_NETSEC_VER_MAJOR_NUM(x) ((x) & 0xffff0000) + +#define EERPROM_MAP_OFFSET 0x8000000 +#define NOR_BLOCK 1024 + +struct netsec_de { /* Netsec Descriptor layout */ + u32 attr; + u32 data_buf_addr_up; + u32 data_buf_addr_lw; + u32 buf_len_info; +}; + +struct netsec_priv { + struct netsec_de rxde[PKTBUFSRX]; + struct netsec_de txde[1]; + u16 rxat; + + phys_addr_t eeprom_base; + phys_addr_t ioaddr; + + struct mii_dev *bus; + struct phy_device *phydev; + u32 phy_addr, freq; + int phy_mode; + int max_speed; +}; + +struct netsec_tx_pkt_ctrl { + u16 tcp_seg_len; + bool tcp_seg_offload_flag; + bool cksum_offload_flag; +}; + +struct netsec_rx_pkt_info { + int rx_cksum_result; + int err_code; + bool err_flag; +}; + +static void netsec_write_reg(struct netsec_priv *priv, u32 reg_addr, u32 val) +{ + writel(val, priv->ioaddr + reg_addr); +} + +static u32 netsec_read_reg(struct netsec_priv *priv, u32 reg_addr) +{ + return readl(priv->ioaddr + reg_addr); +} + +/************* MDIO BUS OPS FOLLOW *************/ + +#define TIMEOUT_SPINS_MAC 1000 +#define TIMEOUT_SECONDARY_MS_MAC 100 + +static u32 netsec_clk_type(u32 freq) +{ + if (freq < MHZ(35)) + return NETSEC_GMAC_GAR_REG_CR_25_35_MHZ; + if (freq < MHZ(60)) + return NETSEC_GMAC_GAR_REG_CR_35_60_MHZ; + if (freq < MHZ(100)) + return NETSEC_GMAC_GAR_REG_CR_60_100_MHZ; + if (freq < MHZ(150)) + return NETSEC_GMAC_GAR_REG_CR_100_150_MHZ; + if (freq < MHZ(250)) + return NETSEC_GMAC_GAR_REG_CR_150_250_MHZ; + + return NETSEC_GMAC_GAR_REG_CR_250_300_MHZ; +} + +static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) +{ + u32 timeout = TIMEOUT_SPINS_MAC; + + while (--timeout && netsec_read_reg(priv, addr) & mask) + cpu_relax(); + if (timeout) + return 0; + + timeout = TIMEOUT_SECONDARY_MS_MAC; + while (--timeout && netsec_read_reg(priv, addr) & mask) + udelay(2000); + + if (timeout) + return 0; + + pr_err("%s: timeout\n", __func__); + + return -ETIMEDOUT; +} + +static int netsec_set_mac_reg(struct netsec_priv *priv, u32 addr, u32 value) +{ + netsec_write_reg(priv, MAC_REG_DATA, value); + netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE); + return netsec_wait_while_busy(priv, + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); +} + +static int netsec_get_mac_reg(struct netsec_priv *priv, u32 addr, u32 *read) +{ + int ret; + + netsec_write_reg(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ); + ret = netsec_wait_while_busy(priv, + MAC_REG_CMD, NETSEC_GMAC_CMD_ST_BUSY); + if (ret) + return ret; + + *read = netsec_read_reg(priv, MAC_REG_DATA); + + return 0; +} + +static int netsec_mac_wait_while_busy(struct netsec_priv *priv, + u32 addr, u32 mask) +{ + u32 timeout = TIMEOUT_SPINS_MAC; + u32 data; + int ret; + + do { + ret = netsec_get_mac_reg(priv, addr, &data); + if (ret) + break; + udelay(1); + } while (--timeout && (data & mask)); + + if (timeout) + return 0; + + timeout = TIMEOUT_SECONDARY_MS_MAC; + do { + udelay(2000); + + ret = netsec_get_mac_reg(priv, addr, &data); + if (ret) + break; + cpu_relax(); + } while (--timeout && (data & mask)); + + if (timeout && !ret) + return 0; + + return -ETIMEDOUT; +} + +static void netsec_cache_invalidate(uintptr_t vaddr, int len) +{ + invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), + roundup(vaddr + len, ARCH_DMA_MINALIGN)); +} + +static void netsec_cache_flush(uintptr_t vaddr, int len) +{ + flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), + roundup(vaddr + len, ARCH_DMA_MINALIGN)); +} + +static void netsec_set_rx_de(struct netsec_priv *priv, u16 idx, void *addr) +{ + struct netsec_de *de = &priv->rxde[idx]; + u32 attr = (1 << NETSEC_RX_PKT_OWN_FIELD) | + (1 << NETSEC_RX_PKT_FS_FIELD) | + (1 << NETSEC_RX_PKT_LS_FIELD); + + if (idx == PKTBUFSRX - 1) + attr |= (1 << NETSEC_RX_PKT_LD_FIELD); + + de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr); + de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr); + de->buf_len_info = PKTSIZE; + de->attr = attr; + dmb(); + netsec_cache_flush((uintptr_t)de, sizeof(*de)); +} + +static void netsec_set_tx_de(struct netsec_priv *priv, void *addr, int len) +{ + struct netsec_de *de = &priv->txde[0]; + u32 attr; + + attr = (1 << NETSEC_TX_SHIFT_OWN_FIELD) | + (1 << NETSEC_TX_SHIFT_PT_FIELD) | + (NETSEC_RING_GMAC << NETSEC_TX_SHIFT_TDRID_FIELD) | + (1 << NETSEC_TX_SHIFT_FS_FIELD) | + (1 << NETSEC_TX_LAST) | + (1 << NETSEC_TX_SHIFT_TRS_FIELD) | + (1 << NETSEC_TX_SHIFT_LD_FIELD); + + de->data_buf_addr_up = upper_32_bits((dma_addr_t)addr); + de->data_buf_addr_lw = lower_32_bits((dma_addr_t)addr); + de->buf_len_info = len; + de->attr = attr; + dmb(); + netsec_cache_flush((uintptr_t)de, sizeof(*de)); +} + +static int netsec_get_phy_reg(struct netsec_priv *priv, + int phy_addr, int reg_addr) +{ + u32 data; + int ret; + + if (phy_addr != 7) + return -EINVAL; + + if (netsec_set_mac_reg(priv, GMAC_REG_GAR, NETSEC_GMAC_GAR_REG_GB | + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | + reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | + (netsec_clk_type(priv->freq) << + GMAC_REG_SHIFT_CR_GAR))) + return -ETIMEDOUT; + + ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, + NETSEC_GMAC_GAR_REG_GB); + if (ret) + return ret; + + ret = netsec_get_mac_reg(priv, GMAC_REG_GDR, &data); + if (ret) + return ret; + + return data; +} + +static int netsec_set_phy_reg(struct netsec_priv *priv, + int phy_addr, int reg_addr, u16 val) +{ + int ret; + + if (phy_addr != 7) + return -EINVAL; + if (netsec_set_mac_reg(priv, GMAC_REG_GDR, val)) + return -ETIMEDOUT; + + if (netsec_set_mac_reg(priv, GMAC_REG_GAR, + phy_addr << NETSEC_GMAC_GAR_REG_SHIFT_PA | + reg_addr << NETSEC_GMAC_GAR_REG_SHIFT_GR | + NETSEC_GMAC_GAR_REG_GW | NETSEC_GMAC_GAR_REG_GB | + (netsec_clk_type(priv->freq) << + GMAC_REG_SHIFT_CR_GAR))) + return -ETIMEDOUT; + + ret = netsec_mac_wait_while_busy(priv, GMAC_REG_GAR, + NETSEC_GMAC_GAR_REG_GB); + + /* Developerbox implements RTL8211E PHY and there is + * a compatibility problem with F_GMAC4. + * RTL8211E expects MDC clock must be kept toggling for several + * clock cycle with MDIO high before entering the IDLE state. + * To meet this requirement, netsec driver needs to issue dummy + * read(e.g. read PHYID1(offset 0x2) register) right after write. + */ + netsec_get_phy_reg(priv, phy_addr, MII_PHYSID1); + + return ret; +} + +static int netsec_mac_update_to_phy_state(struct netsec_priv *priv) +{ + struct phy_device *phydev = priv->phydev; + u32 value = 0; + + value = phydev->duplex ? NETSEC_GMAC_MCR_REG_FULL_DUPLEX_COMMON : + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON; + + if (phydev->speed != SPEED_1000) + value |= NETSEC_MCR_PS; + + if (phydev->interface != PHY_INTERFACE_MODE_GMII && + phydev->speed == SPEED_100) + value |= NETSEC_GMAC_MCR_REG_FES; + + value |= NETSEC_GMAC_MCR_REG_CST | NETSEC_GMAC_MCR_REG_JE; + + if (phy_interface_is_rgmii(phydev)) + value |= NETSEC_GMAC_MCR_REG_IBN; + + if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value)) + return -ETIMEDOUT; + + return 0; +} + +static int netsec_start_gmac(struct netsec_priv *priv) +{ + u32 value = 0; + int ret; + + if (priv->max_speed != SPEED_1000) + value = (NETSEC_GMAC_MCR_REG_CST | + NETSEC_GMAC_MCR_REG_HALF_DUPLEX_COMMON); + + if (netsec_set_mac_reg(priv, GMAC_REG_MCR, value)) + return -ETIMEDOUT; + + if (netsec_set_mac_reg(priv, GMAC_REG_BMR, + NETSEC_GMAC_BMR_REG_RESET)) + return -ETIMEDOUT; + + /* Wait soft reset */ + mdelay(5); + + ret = netsec_get_mac_reg(priv, GMAC_REG_BMR, &value); + if (ret) + return ret; + + if (value & NETSEC_GMAC_BMR_REG_SWR) + return -EAGAIN; + + netsec_write_reg(priv, MAC_REG_DESC_SOFT_RST, 1); + if (netsec_wait_while_busy(priv, MAC_REG_DESC_SOFT_RST, 1)) + return -ETIMEDOUT; + + netsec_write_reg(priv, MAC_REG_DESC_INIT, 1); + if (netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1)) + return -ETIMEDOUT; + + if (netsec_set_mac_reg(priv, GMAC_REG_BMR, + NETSEC_GMAC_BMR_REG_COMMON)) + return -ETIMEDOUT; + + if (netsec_set_mac_reg(priv, GMAC_REG_RDLAR, + NETSEC_GMAC_RDLAR_REG_COMMON)) + return -ETIMEDOUT; + + if (netsec_set_mac_reg(priv, GMAC_REG_TDLAR, + NETSEC_GMAC_TDLAR_REG_COMMON)) + return -ETIMEDOUT; + + if (netsec_set_mac_reg(priv, GMAC_REG_MFFR, 0x80000001)) + return -ETIMEDOUT; + + ret = netsec_mac_update_to_phy_state(priv); + if (ret) + return ret; + + ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value); + if (ret) + return ret; + + value |= NETSEC_GMAC_OMR_REG_SR; + value |= NETSEC_GMAC_OMR_REG_ST; + + netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); + netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); + + if (netsec_set_mac_reg(priv, GMAC_REG_OMR, value)) + return -ETIMEDOUT; + + return 0; +} + +static int netsec_stop_gmac(struct netsec_priv *priv) +{ + u32 value; + int ret; + + ret = netsec_get_mac_reg(priv, GMAC_REG_OMR, &value); + if (ret) + return ret; + value &= ~NETSEC_GMAC_OMR_REG_SR; + value &= ~NETSEC_GMAC_OMR_REG_ST; + + /* disable all interrupts */ + netsec_write_reg(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0); + netsec_write_reg(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0); + + return netsec_set_mac_reg(priv, GMAC_REG_OMR, value); +} + +static void netsec_spi_read(char *buf, loff_t len, loff_t offset) +{ + struct udevice *new; + struct spi_flash *flash; + + spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE, &new); + flash = dev_get_uclass_priv(new); + + spi_flash_read(flash, offset, len, buf); +} + +static int netsec_read_rom_hwaddr(struct udevice *dev) +{ + struct netsec_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + char macp[NOR_BLOCK]; + + netsec_spi_read(macp, sizeof(macp), priv->eeprom_base); + + pdata->enetaddr[0] = readb(macp + 3); + pdata->enetaddr[1] = readb(macp + 2); + pdata->enetaddr[2] = readb(macp + 1); + pdata->enetaddr[3] = readb(macp + 0); + pdata->enetaddr[4] = readb(macp + 7); + pdata->enetaddr[5] = readb(macp + 6); + return 0; +} + +static int netsec_send(struct udevice *dev, void *packet, int length) +{ + struct netsec_priv *priv = dev_get_priv(dev); + u32 val, tout; + + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_STATUS); + netsec_cache_flush((uintptr_t)packet, length); + netsec_set_tx_de(priv, packet, length); + netsec_write_reg(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */ + + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT); + + tout = 10000; + do { + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_DONE_PKTCNT); + udelay(2); + } while (--tout && !val); + + if (!tout) { + val = netsec_read_reg(priv, NETSEC_REG_NRM_TX_PKTCNT); + pr_err("%s: ETIMEDOUT: %dpackets\n", __func__, val); + return -ETIMEDOUT; + } + + return 0; +} + +static int netsec_free_packet(struct udevice *dev, uchar *packet, int length) +{ + struct netsec_priv *priv = dev_get_priv(dev); + + netsec_set_rx_de(priv, priv->rxat, net_rx_packets[priv->rxat]); + + priv->rxat++; + if (priv->rxat == PKTBUFSRX) + priv->rxat = 0; + + return 0; +} + +static int netsec_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct netsec_priv *priv = dev_get_priv(dev); + int idx = priv->rxat; + uchar *ptr = net_rx_packets[idx]; + struct netsec_de *de = &priv->rxde[idx]; + int length = 0; + + netsec_cache_invalidate((uintptr_t)de, sizeof(*de)); + + if (de->attr & (1U << NETSEC_RX_PKT_OWN_FIELD)) + return -EAGAIN; + + length = de->buf_len_info >> 16; + + /* invalidate after DMA is done */ + netsec_cache_invalidate((uintptr_t)ptr, length); + *packetp = ptr; + + return length; +} + +static int _netsec_get_phy_reg(struct mii_dev *bus, + int phy_addr, int devad, int reg_addr) +{ + return netsec_get_phy_reg(bus->priv, phy_addr, reg_addr); +} + +static int _netsec_set_phy_reg(struct mii_dev *bus, + int phy_addr, int devad, int reg_addr, u16 val) +{ + return netsec_set_phy_reg(bus->priv, phy_addr, reg_addr, val); +} + +static int netsec_mdiobus_init(struct netsec_priv *priv, const char *name) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) + return -ENOMEM; + + bus->read = _netsec_get_phy_reg; + bus->write = _netsec_set_phy_reg; + snprintf(bus->name, sizeof(bus->name), "%s", name); + bus->priv = priv; + + return mdio_register(bus); +} + +static int netsec_phy_init(struct netsec_priv *priv, void *dev) +{ + struct phy_device *phydev; + int ret; + + phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static int netsec_netdev_load_ucode_region(struct netsec_priv *priv, u32 reg, + u32 addr_h, u32 addr_l, u32 size) +{ + u64 base = ((u64)addr_h << 32 | addr_l) - EERPROM_MAP_OFFSET; + + while (size > 0) { + char buf[NOR_BLOCK]; + u32 *ucode = (u32 *)buf; + u64 off; + int i; + + off = base % NOR_BLOCK; + base -= off; + netsec_spi_read(buf, sizeof(buf), base); + + for (i = off / 4; i < sizeof(buf) / 4 && size > 0; i++, size--) + netsec_write_reg(priv, reg, ucode[i]); + base += NOR_BLOCK; + } + + return 0; +} + +static int netsec_netdev_load_microcode(struct netsec_priv *priv) +{ + u32 addr_h, addr_l, size; + char buf[NOR_BLOCK]; + u32 *ucinfo = (u32 *)buf; + int err; + + netsec_spi_read(buf, sizeof(buf), priv->eeprom_base); + + addr_h = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_H >> 2]; + addr_l = ucinfo[NETSEC_EEPROM_HM_ME_ADDRESS_L >> 2]; + size = ucinfo[NETSEC_EEPROM_HM_ME_SIZE >> 2]; + + err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_HM_CMD_BUF, + addr_h, addr_l, size); + if (err) + return err; + + addr_h = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_H >> 2]; + addr_l = ucinfo[NETSEC_EEPROM_MH_ME_ADDRESS_L >> 2]; + size = ucinfo[NETSEC_EEPROM_MH_ME_SIZE >> 2]; + + err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_DMAC_MH_CMD_BUF, + addr_h, addr_l, size); + if (err) + return err; + + addr_h = 0; + addr_l = ucinfo[NETSEC_EEPROM_PKT_ME_ADDRESS >> 2]; + size = ucinfo[NETSEC_EEPROM_PKT_ME_SIZE >> 2]; + + err = netsec_netdev_load_ucode_region(priv, NETSEC_REG_PKT_CMD_BUF, + addr_h, addr_l, size); + if (err) + return err; + + return 0; +} + +void netsec_pre_init_microengine(struct netsec_priv *priv) +{ + u32 data; + + /* Remove dormant settings */ + data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR); + data &= ~BMCR_PDOWN; + data |= BMCR_ISOLATE; + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data); + mdelay(100); + + /* Put phy in loopback mode to guarantee RXCLK input */ + data |= BMCR_LOOPBACK; + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data); + mdelay(100); +} + +void netsec_post_init_microengine(struct netsec_priv *priv) +{ + u32 data; + + /* Get phy back to normal operation */ + data = netsec_get_phy_reg(priv, priv->phy_addr, MII_BMCR); + data &= ~BMCR_LOOPBACK; + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data); + mdelay(100); + + /* Apply software reset */ + data |= BMCR_RESET; + netsec_set_phy_reg(priv, priv->phy_addr, MII_BMCR, data); + mdelay(100); +} + +static int netsec_reset_hardware(struct netsec_priv *priv, bool load_ucode) +{ + u32 value; + int err; + + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 0x24); + + /* stop DMA engines */ + if (!netsec_read_reg(priv, NETSEC_REG_ADDR_DIS_CORE)) { + netsec_write_reg(priv, NETSEC_REG_DMA_HM_CTRL, + NETSEC_DMA_CTRL_REG_STOP); + netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, + NETSEC_DMA_CTRL_REG_STOP); + + value = 100; + while (netsec_read_reg(priv, NETSEC_REG_DMA_HM_CTRL) & + NETSEC_DMA_CTRL_REG_STOP) { + udelay(1000); + if (--value == 0) { + pr_err("%s:%d timeout!\n", __func__, __LINE__); + break; + } + } + + value = 100; + while (netsec_read_reg(priv, NETSEC_REG_DMA_MH_CTRL) & + NETSEC_DMA_CTRL_REG_STOP) { + udelay(1000); + if (--value == 0) { + pr_err("%s:%d timeout!\n", __func__, __LINE__); + break; + } + } + } + + netsec_set_mac_reg(priv, GMAC_REG_BMR, NETSEC_GMAC_BMR_REG_RESET); + + netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET); + netsec_write_reg(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN); + netsec_write_reg(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL); + + value = 100; + while (netsec_read_reg(priv, NETSEC_REG_COM_INIT) != 0) { + udelay(1000); + if (--value == 0) { + pr_err("%s:%d COM_INIT timeout!\n", __func__, __LINE__); + break; + } + } + + /* MAC desc init */ + netsec_write_reg(priv, MAC_REG_DESC_INIT, 1); + netsec_wait_while_busy(priv, MAC_REG_DESC_INIT, 1); + /* set MAC_INTF_SEL */ + netsec_write_reg(priv, MAC_REG_INTF_SEL, 1); + + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5); + + /* set desc_start addr */ + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP, + upper_32_bits((dma_addr_t)priv->rxde)); + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW, + lower_32_bits((dma_addr_t)priv->rxde)); + + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP, + upper_32_bits((dma_addr_t)priv->txde)); + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW, + lower_32_bits((dma_addr_t)priv->txde)); + + /* set normal tx dring ring config */ + netsec_write_reg(priv, NETSEC_REG_NRM_TX_CONFIG, + 1 << NETSEC_REG_DESC_ENDIAN); + netsec_write_reg(priv, NETSEC_REG_NRM_RX_CONFIG, + 1 << NETSEC_REG_DESC_ENDIAN); + + if (load_ucode) { + err = netsec_netdev_load_microcode(priv); + if (err) { + pr_err("%s: failed to load microcode (%d)\n", + __func__, err); + return err; + } + } + + /* set desc_start addr */ + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_UP, + upper_32_bits((dma_addr_t)priv->rxde)); + netsec_write_reg(priv, NETSEC_REG_NRM_RX_DESC_START_LW, + lower_32_bits((dma_addr_t)priv->rxde)); + + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_UP, + upper_32_bits((dma_addr_t)priv->txde)); + netsec_write_reg(priv, NETSEC_REG_NRM_TX_DESC_START_LW, + lower_32_bits((dma_addr_t)priv->txde)); + + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5); + + /* start DMA engines */ + netsec_write_reg(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1); + + netsec_pre_init_microengine(priv); + + netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 0); + + mdelay(100); + + if (!(netsec_read_reg(priv, NETSEC_REG_TOP_STATUS) & + NETSEC_TOP_IRQ_REG_ME_START)) { + pr_err("microengine start failed\n"); + return -ENXIO; + } + + netsec_post_init_microengine(priv); + + /* clear microcode load end status */ + netsec_write_reg(priv, NETSEC_REG_TOP_STATUS, + NETSEC_TOP_IRQ_REG_ME_START); + + netsec_write_reg(priv, NETSEC_REG_CLK_EN, 1 << 5); + + value = netsec_read_reg(priv, NETSEC_REG_PKT_CTRL); + value |= NETSEC_PKT_CTRL_REG_MODE_NRM; + /* change to normal mode */ + netsec_write_reg(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS); + netsec_write_reg(priv, NETSEC_REG_PKT_CTRL, value); + + value = 100; + while ((netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS) & + NETSEC_MODE_TRANS_COMP_IRQ_T2N) == 0) { + udelay(1000); + if (--value == 0) { + value = netsec_read_reg(priv, NETSEC_REG_MODE_TRANS_COMP_STATUS); + pr_err("%s:%d timeout! val=%x\n", __func__, __LINE__, value); + break; + } + } + + /* clear any pending EMPTY/ERR irq status */ + netsec_write_reg(priv, NETSEC_REG_NRM_TX_STATUS, ~0); + + /* Disable TX & RX intr */ + netsec_write_reg(priv, NETSEC_REG_INTEN_CLR, ~0); + + return 0; +} + +static void netsec_stop(struct udevice *dev) +{ + struct netsec_priv *priv = dev_get_priv(dev); + + netsec_write_reg(priv, NETSEC_REG_ADDR_DIS_CORE, 7); + netsec_stop_gmac(priv); + phy_shutdown(priv->phydev); + netsec_reset_hardware(priv, false); +} + +static int netsec_start(struct udevice *dev) +{ + struct netsec_priv *priv = dev_get_priv(dev); + int i; + + phy_startup(priv->phydev); + netsec_start_gmac(priv); + + priv->rxat = 0; + for (i = 0; i < PKTBUFSRX; i++) + netsec_set_rx_de(priv, i, net_rx_packets[i]); + + return 0; +} + +static int netsec_of_to_plat(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct netsec_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args phandle_args; + const char *phy_mode; + + pdata->iobase = dev_read_addr_index(dev, 0); + priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET; + + pdata->phy_interface = -1; + phy_mode = dev_read_prop(dev, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + pr_err("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) + priv->phy_addr = ofnode_read_u32_default(phandle_args.node, "reg", 7); + else + priv->phy_addr = 7; + + pdata->max_speed = dev_read_u32_default(dev, "max-speed", SPEED_1000); + + priv->ioaddr = pdata->iobase; + priv->phy_mode = pdata->phy_interface; + priv->max_speed = pdata->max_speed; + priv->freq = 250000000UL; + + return 0; +} + +#define SMMU_SCR0_SHCFG_INNER (0x2 << 22) +#define SMMU_SCR0_MTCFG (0x1 << 20) +#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16) + +static int netsec_probe(struct udevice *dev) +{ + struct netsec_priv *priv = dev_get_priv(dev); + int ret; + + writel(SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB, + (phys_addr_t)0x52E00000); + + netsec_reset_hardware(priv, true); + + ret = netsec_mdiobus_init(priv, dev->name); + if (ret) { + pr_err("Failed to initialize mdiobus: %d\n", ret); + return ret; + } + + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = netsec_phy_init(priv, dev); + if (ret) { + pr_err("Failed to initialize phy: %d\n", ret); + goto out_mdiobus_release; + } + + return 0; +out_mdiobus_release: + mdio_unregister(priv->bus); + mdio_free(priv->bus); + return ret; +} + +static int netsec_remove(struct udevice *dev) +{ + struct netsec_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static const struct eth_ops netsec_ops = { + .start = netsec_start, + .stop = netsec_stop, + .send = netsec_send, + .recv = netsec_recv, + .free_pkt = netsec_free_packet, + .read_rom_hwaddr = netsec_read_rom_hwaddr, +}; + +static const struct udevice_id netsec_ids[] = { + { + .compatible = "socionext,synquacer-netsec", + }, + {} +}; + +U_BOOT_DRIVER(ave) = { + .name = "synquacer_netsec", + .id = UCLASS_ETH, + .of_match = netsec_ids, + .probe = netsec_probe, + .remove = netsec_remove, + .of_to_plat = netsec_of_to_plat, + .ops = &netsec_ops, + .priv_auto = sizeof(struct netsec_priv), + .plat_auto = sizeof(struct eth_pdata), +}; From patchwork Mon May 10 06:32:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433040 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565456jao; Sun, 9 May 2021 23:33:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTeaFgOddlzPhNQb2h0DumnSsLRdrzmsqGXjn9I54DYRWD8FuD4Oud3zIQXB1zlHnZegSN X-Received: by 2002:aa7:dc15:: with SMTP id b21mr28105008edu.350.1620628383134; Sun, 09 May 2021 23:33:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628383; cv=none; d=google.com; s=arc-20160816; b=BUCS7F0uvAkTudKFXWiwhat8SeMFnl2g5ylvK/murPuu0JsjKKdzW9DfYI80wCUHmb MFWNBHPeNeJPoOaZDXI029MFnq4V3W1WXm5QGc8TZUD49FdH147dCvM7LkV/yqPnoo+A XZf5aiym7XukfJ8ZbLYwFo/8uemnF7P8YxFaA+06Cqfuyp89Q1Bf1cTXVYbc8HHTYVFE LhrxWvZhwXYJiSpCXOz6FfLUjbjHn85qbbuiUqm71MmpGTKRrZm7/geqQncEtMo29pP6 p7p+pb8c8mOpc2puPx03UHUimxGPiiw0mn/lc3aq3dzcCeSNTmRen5P4qQGfUvt+gPvA l05Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=WvR0YphJLob2nx8zuoPkwKm8nfDJAa/4ICl+1qIuVWs=; b=Kke0hN/wrSgsPWEHWtOPpExnH4w2PLYBEannIhtwLG0RJNs/oQtAxGgf2m8d3GoshS iIui8N7rudOO27+OfgD6wafa7a4AgkljgHhhGt1eKuY3LAkvMR260PGUGQS8oWYQyx9s TSTG3fm/zNBj2DlnxzGokUg38FYxIkk3qiO5QZlvLzgIBtWT5e0aGC5uxttkkxvKMNf8 A/PjhG7NFTVf7rRVH0CEs/fUiunKDA4sCB/sZVmtaC625PMuP5GKDVcnc7tn9iKVeSOD gCXDAGLXpXYlJVTpvlt0C0m9Lsk5ImUWMAq/Tt2Lm2P9OZXiw223R45M2eM9Ae7a+K8+ QY7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ERaHEIra; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id kl4si12464664ejc.648.2021.05.09.23.33.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:33:03 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ERaHEIra; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6DF1E82EDA; Mon, 10 May 2021 08:32:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ERaHEIra"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3163582EDB; Mon, 10 May 2021 08:32:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BEA0C82EDA for ; Mon, 10 May 2021 08:32:47 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pl1-x62b.google.com with SMTP id b21so8658737plz.0 for ; Sun, 09 May 2021 23:32:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=WvR0YphJLob2nx8zuoPkwKm8nfDJAa/4ICl+1qIuVWs=; b=ERaHEIraPpR6PteNaMe7yuniCcKj7MUTPLoxzilkZMI1/mn9+qKwMIR/UMfJFTaxCm CSQXU85/TPbmeMMgO2EfJEY18fYTL4ZfjO8DPMPV+ur/nWQeviwfzViUqtoVNogKGL6i Q9GIAyr7/Vt2rNKZmS75PAPoedhzGuR5X48aEefhPymbXVCWzEaZRFe2RiibjDDvNf3y NDRujBjyL4npj3zXm1c/qS+ImYEay+CIJ2pPRGmuK0LpzfaeQTWhu/l5dHx8yUC6GgLx tNCnaVb2c+f1pujyioDAlGJS7uKPpMGAmVLGpZc4xpE6UxfLx6dAqXX+KmmCyi0LJj3p BE5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=WvR0YphJLob2nx8zuoPkwKm8nfDJAa/4ICl+1qIuVWs=; b=rI4Y0hABDNRRkOn3TxzDeOm3MXYfGFVnN5BRHf5Sp4z5iQe0xZFY9Xm36swgr1N3KH 0zDFQJuzmKJ6b0Vt/9nl4SEuKOn2RrzyQ9qbl7e0R3EBphWPF16ZE0kH8axVsb+xUR8S Q191wROE8BIYS5JKJFQZ7gGGOhYg0Y38nJiq90XYrGW++tLHuKoCcJj6sVs/hYNl5Pxw B6hED+tFjUVv4ySUB1v217NYJfCzTWkhhxlzzuHnxQUXduG/FNbg1QMwCgTgS7p+9/6R 16O8gP7Z8ELLBGTqb8XjKNcefi6CdGgoz1koSr/jZ1+Qj8GtnutbvjHzu/V0/dl/32U7 fg7Q== X-Gm-Message-State: AOAM532moXQFCDRzI9MTZuPX8Kztbv+TBKtx2bVHJ91mhSCsK3xjIpF5 qC+/noqvCXWrY5BOnr5I/xc4+g== X-Received: by 2002:a17:90a:f40f:: with SMTP id ch15mr25493983pjb.113.1620628366198; Sun, 09 May 2021 23:32:46 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id b13sm8712635pfl.140.2021.05.09.23.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:45 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 10/14] ARM: dts: synquacer: Add device trees for DeveloperBox Date: Mon, 10 May 2021 15:32:41 +0900 Message-Id: <162062836082.501222.8408962066728030820.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add device trees for 96boards EE DeveloperBox and basement SynQuacer SoC dtsi. These files are imported from EDK2 commit 83d38b0b4c0f240d4488c600bbe87cea391f3922 as-is (except for the changes #include path and some macros). And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi Signed-off-by: Masami Hiramatsu --- Changes in v3: - Use generic nor flash instead of specific mx25u51245g. (chip parameters will be searched by the register value) Changes in v2: - Add reference commit id of original EDK2 to the comment - Just copy the EDK2 dts files as-is (change #include path) - Split out the u-boot specific changes in -u-boot.dtsi. - Removed unneeded spi-nor flash partition information. --- arch/arm/dts/Makefile | 2 arch/arm/dts/synquacer-sc2a11-caches.dtsi | 73 ++ .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 57 ++ arch/arm/dts/synquacer-sc2a11-developerbox.dts | 56 ++ arch/arm/dts/synquacer-sc2a11.dtsi | 595 ++++++++++++++++++++ 5 files changed, 783 insertions(+) create mode 100644 arch/arm/dts/synquacer-sc2a11-caches.dtsi create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi create mode 100644 arch/arm/dts/synquacer-sc2a11-developerbox.dts create mode 100644 arch/arm/dts/synquacer-sc2a11.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a5cae010c2..92b48e7033 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1083,6 +1083,8 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb +dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/synquacer-sc2a11-caches.dtsi b/arch/arm/dts/synquacer-sc2a11-caches.dtsi new file mode 100644 index 0000000000..177ddf8c2b --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-caches.dtsi @@ -0,0 +1,73 @@ +/** @file + * Copyright (c) 2018, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +#define __L1(cpuref, l2ref) \ +cpuref { \ + i-cache-size = <0x8000>; \ + i-cache-line-size = <64>; \ + i-cache-sets = <256>; \ + d-cache-size = <0x8000>; \ + d-cache-line-size = <64>; \ + d-cache-sets = <128>; \ + l2-cache = ; \ +}; + +#define __L2(idx) \ +L2_##idx: l2-cache##idx { \ + cache-size = <0x40000>; \ + cache-line-size = <64>; \ + cache-sets = <256>; \ + cache-unified; \ + next-level-cache = <&L3>; \ +}; + +/ { + __L2(0) + __L2(1) + __L2(2) + __L2(3) + __L2(4) + __L2(5) + __L2(6) + __L2(7) + __L2(8) + __L2(9) + __L2(10) + __L2(11) + + L3: l3-cache { + cache-level = <3>; + cache-size = <0x400000>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-unified; + }; +}; + +__L1(&CPU0, &L2_0) +__L1(&CPU1, &L2_0) +__L1(&CPU2, &L2_1) +__L1(&CPU3, &L2_1) +__L1(&CPU4, &L2_2) +__L1(&CPU5, &L2_2) +__L1(&CPU6, &L2_3) +__L1(&CPU7, &L2_3) +__L1(&CPU8, &L2_4) +__L1(&CPU9, &L2_4) +__L1(&CPU10, &L2_5) +__L1(&CPU11, &L2_5) +__L1(&CPU12, &L2_6) +__L1(&CPU13, &L2_6) +__L1(&CPU14, &L2_7) +__L1(&CPU15, &L2_7) +__L1(&CPU16, &L2_8) +__L1(&CPU17, &L2_8) +__L1(&CPU18, &L2_9) +__L1(&CPU19, &L2_9) +__L1(&CPU20, &L2_10) +__L1(&CPU21, &L2_10) +__L1(&CPU22, &L2_11) +__L1(&CPU23, &L2_11) diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi new file mode 100644 index 0000000000..2439997753 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// Copyright (c) 2021, Linaro Limited. All rights reserved. +// + +/ { + aliases { + spi_nor = &spi_nor; + }; + + spi_nor: spi@54800000 { + compatible = "socionext,synquacer-spi"; + reg = <0x00 0x54800000 0x00 0x1000>; + interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>; + clocks = <&clk_alw_1_8>; + clock-names = "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + active_clk_edges; + chipselect_num = <1>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <31250000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + }; + }; + + firmware { + optee { + status = "okay"; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&sdhci { + status = "okay"; +}; diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts new file mode 100644 index 0000000000..42b6cbbb82 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts @@ -0,0 +1,56 @@ +/** @file + * Copyright (c) 2017, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +/dts-v1/; + +#include "synquacer-sc2a11.dtsi" + +#define KEY_POWER 116 + +/ { + model = "Socionext Developer Box"; + compatible = "socionext,developer-box", "socionext,synquacer"; + + gpio-keys { + compatible = "gpio-keys"; + interrupt-parent = <&exiu>; + + power { + label = "Power Button"; + linux,code = ; + interrupts = ; + wakeup-source; + }; + }; +}; + +#ifdef TPM2_ENABLE +&tpm { + status = "okay"; +}; +#endif + +&gpio { + gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; +}; + +&netsec { + phy-mode = "rgmii-id"; +}; + +&mdio_netsec { + phy_netsec: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi new file mode 100644 index 0000000000..1fe7d214b9 --- /dev/null +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -0,0 +1,595 @@ +/** @file + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +/* These are added for U-Boot to avoid compilation error */ +#define PcdNetsecEepromBase 0x08080000 +#define FixedPcdGet32(n) n + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &soc_uart0; + serial1 = &fuart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU4: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x200>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU5: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x201>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU6: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x300>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU7: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x301>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU8: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x400>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU9: cpu@401 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x401>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU10: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x500>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU11: cpu@501 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x501>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU12: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x600>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU13: cpu@601 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x601>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU14: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x700>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU15: cpu@701 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x701>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU16: cpu@800 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x800>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU17: cpu@801 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x801>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU18: cpu@900 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x900>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU19: cpu@901 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x901>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU20: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xa00>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU21: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xa01>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU22: cpu@b00 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xb00>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU23: cpu@b01 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0xb01>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU2>; + }; + core1 { + cpu = <&CPU3>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU6>; + }; + core1 { + cpu = <&CPU7>; + }; + }; + cluster4 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + }; + cluster5 { + core0 { + cpu = <&CPU10>; + }; + core1 { + cpu = <&CPU11>; + }; + }; + cluster6 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + }; + cluster7 { + core0 { + cpu = <&CPU14>; + }; + core1 { + cpu = <&CPU15>; + }; + }; + cluster8 { + core0 { + cpu = <&CPU16>; + }; + core1 { + cpu = <&CPU17>; + }; + }; + cluster9 { + core0 { + cpu = <&CPU18>; + }; + core1 { + cpu = <&CPU19>; + }; + }; + cluster10 { + core0 { + cpu = <&CPU20>; + }; + core1 { + cpu = <&CPU21>; + }; + }; + cluster11 { + core0 { + cpu = <&CPU22>; + }; + core1 { + cpu = <&CPU23>; + }; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <1200>; + min-residency-us = <2500>; + local-timer-stop; + }; + }; + + gic: interrupt-controller@30000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x30000000 0x0 0x10000>, // GICD + <0x0 0x30400000 0x0 0x300000>, // GICR + <0x0 0x2c000000 0x0 0x2000>, // GICC + <0x0 0x2c010000 0x0 0x1000>, // GICH + <0x0 0x2c020000 0x0 0x10000>; // GICV + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + interrupts = ; + + its: gic-its@30020000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30020000 0x0 0x20000>; + #msi-cells = <1>; + msi-controller; + socionext,synquacer-pre-its = <0x58000000 0x200000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , // secure + , // non-secure + , // virtual + ; // HYP + }; + + mmio-timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <0>; + interrupts = ; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + clk_uart: refclk62500khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "uartclk"; + }; + + clk_apb: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + soc_uart0: uart@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_uart>, <&clk_apb>; + clock-names = "uartclk", "apb_pclk"; + }; + + fuart: uart@51040000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x51040000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_uart>, <&clk_apb>; + clock-names = "baudclk", "apb_pclk"; + reg-io-width = <4>; + reg-shift = <2>; + }; + + clk_netsec: refclk250mhz { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + #clock-cells = <0>; + }; + + netsec: ethernet@522d0000 { + compatible = "socionext,synquacer-netsec"; + reg = <0 0x522d0000 0x0 0x10000>, + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; + interrupts = ; + clocks = <&clk_netsec>; + clock-names = "phy_ref_clk"; + max-speed = <1000>; + max-frame-size = <9000>; + phy-handle = <&phy_netsec>; + dma-coherent; + + mdio_netsec: mdio { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + smmu: iommu@582c0000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0x0 0x582c0000 0x0 0x10000>; + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + status = "disabled"; + }; + + pcie0: pcie@60000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x60000000 0x0 0x7f00000>; + bus-range = <0x0 0x7e>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>, + <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>, + <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + + msi-map = <0x000 &its 0x0 0x7f00>; + dma-coherent; + status = "disabled"; + }; + + pcie1: pcie@70000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x70000000 0x0 0x7f00000>; + bus-range = <0x0 0x7e>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, + <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + + msi-map = <0x0 &its 0x10000 0x7f00>; + dma-coherent; + status = "disabled"; + }; + + gpio: gpio@51000000 { + compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio"; + reg = <0x0 0x51000000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clk_apb>; + base = <0>; + }; + + exiu: interrupt-controller@510c0000 { + compatible = "socionext,synquacer-exiu"; + reg = <0x0 0x510c0000 0x0 0x20>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <3>; + socionext,spi-base = <112>; + }; + + clk_alw_b_0: bclk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "sd_bclk"; + }; + + clk_alw_c_0: sd4clk800 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sd_sd4clk"; + }; + + sdhci: sdhci@52300000 { + compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; + reg = <0 0x52300000 0x0 0x1000>; + interrupts = , + ; + bus-width = <8>; + cap-mmc-highspeed; + fujitsu,cmd-dat-delay-select; + clocks = <&clk_alw_c_0 &clk_alw_b_0>; + clock-names = "core", "iface"; + dma-coherent; + status = "disabled"; + }; + + clk_alw_1_8: spi_ihclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "iHCLK"; + }; + + spi: spi@54810000 { + compatible = "socionext,synquacer-spi"; + reg = <0x0 0x54810000 0x0 0x1000>; + interrupts = , + , + ; + clocks = <&clk_alw_1_8>; + clock-names = "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + clk_i2c: i2c_pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "pclk"; + }; + + i2c: i2c@51210000 { + compatible = "socionext,synquacer-i2c"; + reg = <0x0 0x51210000 0x0 0x1000>; + interrupts = ; + clocks = <&clk_i2c>; + clock-names = "pclk"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + tpm: tpm_tis@10000000 { + compatible = "socionext,synquacer-tpm-mmio"; + reg = <0x0 0x10000000 0x0 0x5000>; + status = "disabled"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; +}; + +#include "synquacer-sc2a11-caches.dtsi" From patchwork Mon May 10 06:32:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433041 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565599jao; Sun, 9 May 2021 23:33:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwM+0BbKiN+V5/rCSIhkXYkpYJL0oEDTFQNWYuz59kt9I78Hv1cytEQLIUmfSTwq5mLb15e X-Received: by 2002:a05:6402:3488:: with SMTP id v8mr26937679edc.51.1620628397734; Sun, 09 May 2021 23:33:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628397; cv=none; d=google.com; s=arc-20160816; b=g+byoEPMvF8k6NaNkctVsgnpCkPv3kL1gLDuXedLLnEwPQOGcSxTLXMYeapvp3j1G3 jXhHycPL13wPQ9ouPNpbjJBLFMkMVk0U1jOGAcTBfYq6qZoqazZWWBBVvo9SXW4/3CKR tE0XLcApl7yf4r3cW2eWohIgLc9P10GloGY54hoIPASLKTJBmJ53MrKF5sNT6QO+slji y3oyDQ7cndWXiAij1pbr0VHkuvYHihacpOCnNhyrrSVbTBRxZKGqsn3u6gqxtc22Glxy /SfsBfPWCdS0DVSzIfYdeXoldw96xAppHAfeicGVKSVZ8MNSWYsjqAxnuawYMf7Y+/B7 CLNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=OL5Q4QDJ9l7wOegsb372e6GTPhPOHbFMrIW35fPV7Lc=; b=dnacl0uKNBY7bYrfFBVsLAFhmK4DUHUNJelA1m9/3hE9RrRBsJsYtO7kbItw383OwX 2sjvkq9Wd89d/7tUDGhihKqV9uEVrAAIaR/+TuNVVmskWwioi0bRYx9VyxLw9AY/Xz9E W4K7aXgVWpcSoKczCkFsUSXiEAgrcoc/pAlAcEPelOp/WJTghK9FduZo1JpYPI2sesJL o/6CWzh8UrqhvX2656bEg6YPAClCGiOV3lf123MBU+mqpzMpXIMMnMs9uUHtH3msGT2Y BF1YEZBJgDs6lsyk/5n1ub6nRXtQ4X65a0l/OdiB9kxHwgYUBU3IwSX/vxn/YIlQtLu+ 5ZwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="e7kZqs/p"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id q7si12511209ejs.275.2021.05.09.23.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:33:17 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="e7kZqs/p"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DFA8482EDC; Mon, 10 May 2021 08:33:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="e7kZqs/p"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CB5BF82EDC; Mon, 10 May 2021 08:33:03 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BA09A82ED4 for ; Mon, 10 May 2021 08:32:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pg1-x534.google.com with SMTP id m124so12539055pgm.13 for ; Sun, 09 May 2021 23:32:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=OL5Q4QDJ9l7wOegsb372e6GTPhPOHbFMrIW35fPV7Lc=; b=e7kZqs/pJ9/K8Tlc1glIOzskYF+kbfIxgRgdMzj2LjDlu0YW+izAkadkrCDBwtj1/n 2ZppeEXqTJh35L1UUiiV/bbspzZp5BbL6be6TOEmZTid+zp7jQUKiWwSj3QOFFfjW8yL 2vJsZaWQ+iqbFI1ayOjXnoeS/0Lz5BLU9YYzHTO/YQO35H0k3aO4JFqoprMhihv2i37i IvdbUMbiLZe5FlC6XcyQ4BzokXCO2BDULaWphLhK+zI1E/i+lqmot6BYLQ8Rj6+O7Tbw nFC1mfAjVK0d41+H6QW+PgUbfh4Lm1BbDPoAI1c+vtI8e0asT9o0xgeaEaQZcamwcWot deFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=OL5Q4QDJ9l7wOegsb372e6GTPhPOHbFMrIW35fPV7Lc=; b=sI1Pp1NwdZLsvU1za9jH7JKYBTku17NkwLrpL/AKLOJnpMJSmWvnS75goFqzlSWdXo yNCcJIvq1tOEgoRWKNcp2uqtCe7cueCyWYkTYWt7RDWyNJP7AfKGCN1K135NINxvZAsS cW51g+XbEZjwCLKL2lrbD0XjkSNKEDooHw8xnxJS5OTx3AuDreghQM6pF/DGZLI8nO6R VRrBU1szeEuJKYnKOUQiHJzGswdjvfKllkMRqismFV8Shdh1VGuwhnWuWM0EdWL2MVp8 wkftkz5XFWYSq6oq7YJBOKoF+yBEDm1gXH3hSiE7BSxXL9lMv+/Dt74udyQGOPM8/s1n DKIA== X-Gm-Message-State: AOAM531Actk2uLsGbxRaARCq6QYQUMtgGV6C8MNf6+0dGlwnHcTZWXPt ttTAnyBaeMdLJSEyxckOjP8Pfg== X-Received: by 2002:a62:7790:0:b029:27d:3aea:83e5 with SMTP id s138-20020a6277900000b029027d3aea83e5mr22925256pfc.78.1620628376971; Sun, 09 May 2021 23:32:56 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id 23sm230370pgv.90.2021.05.09.23.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:32:56 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 11/14] board: synquacer: Add DeveloperBox 96boards EE support Date: Mon, 10 May 2021 15:32:51 +0900 Message-Id: <162062837154.501222.959991352405957601.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu --- Changes in v3: - Enable CONFIG_MMC_SDHCI_F_SDH30. - Enable CONFIG_CMD_GENERIC (fstype command) for distro boot. - Remove unneeded CONFIG_ONLY_GENERIC_GPIO. Changes in v2: - Do not include arch/gpio.h and remove arch-sc2a11/gpio.h. - Remove non-UEFI boot commands. - Use Distro boot. - Remove NOR-connected SPI node by path instead of alias. - Rename configs/SynQuacer_defconfig to configs/synquacer_developerbox_defconfig. - Rename include/configs/SynQuacer.h to include/configs/synquacer.h. - Move README under doc/board/socionext/ and make it .rst text. --- arch/arm/Kconfig | 14 +++ board/socionext/developerbox/Kconfig | 36 +++++++ board/socionext/developerbox/MAINTAINERS | 13 ++ board/socionext/developerbox/Makefile | 9 ++ board/socionext/developerbox/developerbox.c | 145 +++++++++++++++++++++++++++ configs/synquacer_developerbox_defconfig | 94 ++++++++++++++++++ doc/board/index.rst | 1 doc/board/socionext/developerbox.rst | 87 ++++++++++++++++ doc/board/socionext/index.rst | 9 ++ include/configs/synquacer.h | 106 ++++++++++++++++++++ 10 files changed, 514 insertions(+) create mode 100644 board/socionext/developerbox/Kconfig create mode 100644 board/socionext/developerbox/MAINTAINERS create mode 100644 board/socionext/developerbox/Makefile create mode 100644 board/socionext/developerbox/developerbox.c create mode 100644 configs/synquacer_developerbox_defconfig create mode 100644 doc/board/socionext/developerbox.rst create mode 100644 doc/board/socionext/index.rst create mode 100644 include/configs/synquacer.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 023824df77..7ff24535cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1760,6 +1760,19 @@ config ARCH_UNIPHIER Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) +config ARCH_SYNQUACER + bool "Socionext SynQuacer SoCs" + select ARM64 + select DM + select GIC_V3 + select PSCI_RESET + select SYSRESET + select SYSRESET_PSCI + select OF_CONTROL + help + Support for SynQuacer SoC family developed by Socionext Inc. + This SoC is used on 96boards EE DeveloperBox. + config ARCH_STM32 bool "Support STMicroelectronics STM32 MCU with cortex M" select CPU_V7M @@ -2102,6 +2115,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/socionext/developerbox/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig new file mode 100644 index 0000000000..706b8dc0f1 --- /dev/null +++ b/board/socionext/developerbox/Kconfig @@ -0,0 +1,36 @@ +if ARCH_SYNQUACER + +choice + prompt "SC2A11 Cortex-A53 MPCore 24cores" + optional + +config TARGET_DEVELOPERBOX + bool "Socionext DeveloperBox" + select PCI + select DM_PCI + select PCIE_ECAM_SYNQUACER + select SYS_DISABLE_DCACHE_OPS + select OF_BOARD_SETUP + help + Choose this option if you build the U-Boot for the DeveloperBox + 96boards Enterprise Edition. + This board will booted from SCP firmware and it enables SMMU, thus + the dcache is updated automatically when DMA operation is executed. +endchoice + +config SYS_SOC + default "sc2a11" + +if TARGET_DEVELOPERBOX + +config SYS_BOARD + default "developerbox" + +config SYS_VENDOR + default "socionext" + +config SYS_CONFIG_NAME + default "synquacer" + +endif +endif diff --git a/board/socionext/developerbox/MAINTAINERS b/board/socionext/developerbox/MAINTAINERS new file mode 100644 index 0000000000..d10ad3b8f7 --- /dev/null +++ b/board/socionext/developerbox/MAINTAINERS @@ -0,0 +1,13 @@ +DEVELOPER BOX +M: Masami Hiramatsu +M: Jassi Brar +S: Maintained +F: arch/arm/dts/synquacer-* +F: board/socionext/developerbox/* +F: configs/synquacer_developerbox_defconfig +F: drivers/mmc/f_sdh30.c +F: drivers/net/sni_netsec.c +F: drivers/pci/pcie_ecam_synquacer.c +F: drivers/spi/spi-synquacer.c +F: include/configs/synquacer.h +F: doc/board/socionext/developerbox.rst diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile new file mode 100644 index 0000000000..4a46de995a --- /dev/null +++ b/board/socionext/developerbox/Makefile @@ -0,0 +1,9 @@ +# +# Author: Masami Hiramatsu +# +# Copyright (C) 2021 Linaro Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := developerbox.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c new file mode 100644 index 0000000000..3e943a279c --- /dev/null +++ b/board/socionext/developerbox/developerbox.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * u-boot/board/socionext/developerbox/developerbox.c + * + * Copyright (C) 2016-2017 Socionext Inc. + * Copyright (C) 2021 Linaro Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mm_region sc2a11_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 1st DDR block */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = PHYS_SDRAM_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { + /* 2nd DDR place holder */ + 0, + }, { + /* 3rd DDR place holder */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sc2a11_mem_map; + +#define DDR_REGION_INDEX(i) (1 + (i)) +#define MAX_DDR_REGIONS 3 + +struct draminfo_entry { + u64 base; + u64 size; +}; + +struct draminfo { + u32 nr_regions; + u32 reserved; + struct draminfo_entry entry[3]; +}; + +struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + +DECLARE_GLOBAL_DATA_PTR; + +#define LOAD_OFFSET 0x100 + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET; + + gd->env_addr = (ulong)&default_environment[0]; + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove SPI NOR for making System DT compatible with EDK2 */ + fdt_del_node_and_alias(blob, "spi_nor"); + + return 0; +} + +/* + * DRAM configuration + */ + +int dram_init(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + struct mm_region *mr; + int i, ri; + + if (synquacer_draminfo->nr_regions < 1) { + log_err("Failed to get correct DRAM information\n"); + return -1; + } + + /* + * U-Boot RAM size must be under the first DRAM region so that it doesn't + * access secure memory which is at the end of the first DRAM region. + */ + gd->ram_size = ent[0].size; + + /* Update memory region maps */ + for (i = 0; i < synquacer_draminfo->nr_regions; i++) { + if (i >= MAX_DDR_REGIONS) + break; + + ri = DDR_REGION_INDEX(i); + mem_map[ri].phys = ent[i].base; + mem_map[ri].size = ent[i].size; + if (i == 0) + continue; + + mr = &mem_map[DDR_REGION_INDEX(0)]; + mem_map[ri].virt = mr->virt + mr->size; + mem_map[ri].attrs = mr->attrs; + } + + return 0; +} + +int dram_init_banksize(void) +{ + struct draminfo_entry *ent = synquacer_draminfo->entry; + int i; + + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + if (i < synquacer_draminfo->nr_regions) { + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); + gd->bd->bi_dram[i].start = ent[i].base; + gd->bd->bi_dram[i].size = ent[i].size; + } + } + + return 0; +} + +int print_cpuinfo(void) +{ + printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n"); + return 0; +} diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig new file mode 100644 index 0000000000..de12587775 --- /dev/null +++ b/configs/synquacer_developerbox_defconfig @@ -0,0 +1,94 @@ +CONFIG_ARM=y +CONFIG_ARCH_SYNQUACER=y +CONFIG_SYS_TEXT_BASE=0x08200000 +CONFIG_ENV_SIZE=0x30000 +CONFIG_ENV_OFFSET=0x300000 +CONFIG_DEBUG_UART_BASE=0x2a400000 +CONFIG_DEBUG_UART_CLOCK=62500000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_DEVELOPERBOX=y +CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" +CONFIG_AHCI=y +CONFIG_BOOTSTAGE_STASH_SIZE=4096 +CONFIG_LOGLEVEL=9 +CONFIG_LOG_MAX_LEVEL=7 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_CMD_DM=y +CONFIG_CMD_MII=y +CONFIG_CMD_NET=y +CONFIG_CMD_BOOTP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_NVME=y +CONFIG_CMD_USB=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)" +CONFIG_MTDIDS_DEFAULT="nor1=nor1" +CONFIG_CMD_LOG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_SEPARATE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_PROT_UDP=y +CONFIG_BAUDRATE=115200 +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y +CONFIG_SATA=y +CONFIG_NVME=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=31250000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHYLIB_10G=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +CONFIG_SNI_NETSEC=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_PHY_GIGE=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYNQUACER_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_STORAGE=y diff --git a/doc/board/index.rst b/doc/board/index.rst index a70d2de19d..242372b321 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -21,6 +21,7 @@ Board-specific doc rockchip/index sifive/index sipeed/index + socionext/index st/index tbs/index toradex/index diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst new file mode 100644 index 0000000000..2d943c23be --- /dev/null +++ b/doc/board/socionext/developerbox.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Introduction +============ + +DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: - + +* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard +* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default) +* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots + (1x slots are connected via PCIe bridge chip) +* 4 USB-3.0 ports +* 2 SATA ports +* 1 GbE network port +* 1 USB-UART serial port (micro USB) +* 64MB SPI NOR Flash +* 8GB eMMC Flash Storage +* 96boards LS connector + +The DeveloperBox schematic can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf + +And the other documents can be found here: - +https://www.96boards.org/documentation/enterprise/developerbox/ + + +Currently, the U-Boot port supports: - + +* USB +* eMMC +* SPI-NOR +* SATA +* GbE + +The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default. +The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as +BL33, but no need to combine with it. + +Compile from source +=================== + +You can build U-Boot without any additinal source code.:: + + cd u-boot + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make SynQuacer_defconfig + make -j `noproc` + +Then, expand the binary to 1MB for preparing flash.:: + + cp u-boot.bin SPI_NOR_UBOOT.fd + truncate -s 1M SPI_NOR_UBOOT.fd + +Installation +============ + +You can install the SNI_NOR_UBOOT.fd via NOR flash writer. + +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. + +*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* + +https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html + +When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: + + + /*------------------------------------------*/ + /* SC2A11 "SynQuacer" series Flash writer */ + /* */ + /* Version: cd254ac */ + /* Build: 12/15/17 11:25:45 */ + /*------------------------------------------*/ + + Command Input > + +Once the flasher tool is running we are ready flash the UEFI image:: + + flash rawwrite 200000 100000 + >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << + +*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* + +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. + diff --git a/doc/board/socionext/index.rst b/doc/board/socionext/index.rst new file mode 100644 index 0000000000..4673dcc45b --- /dev/null +++ b/doc/board/socionext/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Socionext +========= + +.. toctree:: + :maxdepth: 2 + + developerbox diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h new file mode 100644 index 0000000000..b2dd6d0f0f --- /dev/null +++ b/include/configs/synquacer.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2017 Socionext Inc. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Timers for fasp(TIMCLK) */ +#define CONFIG_SYS_HZ 1000 /* 1 msec */ +#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ + +/* + * SDRAM (for initialize) + */ +#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ + +#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ +#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE + +#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ + +/* + * Boot info + */ +#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */ +#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */ + +/* + * Hardware drivers support + */ + +/* Serial (pl011) */ +#define UART_CLK (62500000) +#define CONFIG_SERIAL_MULTI +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK UART_CLK +#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} + +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ + +/* Support MTD */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 128 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +/* #define CONFIG_SYS_PCI_64BIT 1 */ + +/* Distro boot settings */ +#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICE_USB(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICE_MMC(func) +#endif + +#ifdef CONFIG_CMD_NVME +#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0) +#else +#define BOOT_TARGET_DEVICE_NVME(func) +#endif + +#ifdef CONFIG_CMD_SCSI +#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1) +#else +#define BOOT_TARGET_DEVICE_SCSI(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICE_USB(func) \ + BOOT_TARGET_DEVICE_MMC(func) \ + BOOT_TARGET_DEVICE_SCSI(func) \ + BOOT_TARGET_DEVICE_NVME(func) \ + +#include +#else /* CONFIG_SPL_BUILD */ +#define BOOTENV +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr_r=0x9fe00000\0" \ + "kernel_addr_r=0x90000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "scriptaddr=0x88000000\0" \ + "pxefile_addr_r=0x88100000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ From patchwork Mon May 10 06:33:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433042 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565795jao; Sun, 9 May 2021 23:33:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQlMgHl0EbLmm3b+WVMIpjwMDthT+e0p8/y/z9Y1q+q6iIxI/yyDEJug4rDEMNXvz3JPAW X-Received: by 2002:a05:6402:36e:: with SMTP id s14mr27205405edw.338.1620628419007; Sun, 09 May 2021 23:33:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628419; cv=none; d=google.com; s=arc-20160816; b=iekopuG7XhNvFsQV2sbRKbp8GBZWBWN8F+LwhpON+9DTe1dxHT/j08gS0l9H6bx1Kp fbJkozi68s2UcF1oGPUtlT9bnYd3q9FhKdE/21HUrySk+NY56+oXRrtOgHxjGPi1CtXg U6a2RPHPKvLQ1EdKlvWfvkZ9XyGEYkMR2HDp7riGuWXnY9df6QE9T7vxgO6pv5MyO08F fhiZRsbIiULy+aAq/pD9tiDz97pblOI7fU1MUvfXcxmIZIaSNtb7j7MiytV7RdCyZjr7 akMAoKO74PorNaTTA6UFbqQQ8FP+FjPvO+/3klErNLjGGO8IsN9nrs7ni/3zqJg/Q/Wp mtMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=hi6WjBXzska5K8FmtBouIggwiytU0GYq4xvkaSVfBaU=; b=kysaUNJePW/E2s4kotWSm/hVI37drePROid0SlunC16A0pdqKk/AMJrQ/etwoQxFYq z5QAhRuGEp7WVxsXhVCk79J6pTGqyKBzoRftOpUX6nRmtMgEIilRGA0cfyTes/9b0lzh OIERBRmYUzw1yJlx9BVu+5GLEAO97pMwiGOm0XczVkx6vU3pafUYlv0wbukaGGmvM+yl WSw/HXkjTYXh2cG66XLVtfNOQ/jtXjmL4OLpqsArguTHLAzxuFLsqvnBwRlSIZnsb454 SrJcM1ER0EL/BZTX1aKDulsugSWneefu4ls5gMwKaCEop4jWpB1rLVhZzHbRKq2i5rdn Ljgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r6ZP7guF; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id r14si10869417edb.259.2021.05.09.23.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:33:38 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r6ZP7guF; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D5DDC82EE9; Mon, 10 May 2021 08:33:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="r6ZP7guF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4553382EED; Mon, 10 May 2021 08:33:12 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 6058C82EEC for ; Mon, 10 May 2021 08:33:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pg1-x52d.google.com with SMTP id i5so7822837pgm.0 for ; Sun, 09 May 2021 23:33:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=hi6WjBXzska5K8FmtBouIggwiytU0GYq4xvkaSVfBaU=; b=r6ZP7guFs0oaB4lb6bbveAOwnhNQsRmWTenl+/LhbimL6QY67Wikaq+n+3Xw29xYGU nfcdQGHtb1BYqb5LGKSzv1Dyda2f2GP48BYVuWxmjUMtEOi0K+s5nv2UhbIofpKIKCkj rozbndVJD4waTuufN3a7n8d17IUyAHn1RbFH6WS7qtCRQhJ8jO1JRIO0FSd7eLCBqKWE DgZo52KWTIudiuACH1xz9vFbj+KQB27Yrtp0qDNCrttBwE0HzODHaSYve6i3zaXI485e bMgLrOrZ/pRPjzX4/XeeBj8C+wyG578mCUqx0SIWdllt1ZXWqny5zzPI6Vw+OYpPbFRM hwGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=hi6WjBXzska5K8FmtBouIggwiytU0GYq4xvkaSVfBaU=; b=IREhiddnJc/VRX3fccxvHd+J8I/4ZfpGkUuEpvw85vBqlMbQ0HrWJ4wFvF/Qgbhuon 5KVYei7bydAhukC4Cdh8YKKqhApF9CstvtWZHYeYZ/RWykGUtpee++BP4uH6+DWO+dZg 6y2SdcdxJP/nwd1G2vYZXBTTVeZKcVqdi48z1vgLogXIJiaSVkqKCdtHWxtHyEgx3nU+ Lcl5VO225MRlB3thCZIkAfqXVVOQG4EBCtoX33vqDjcbs8mFVqmSQhgN6hPIrh9ZDatl ygmCSraPnCV6+v/uayHlEBUYva3FelKf88a7XgxSxqSUpuoCmQXB1eoOORoxStHsElWa Dnmg== X-Gm-Message-State: AOAM533o9LVT5O+su9IsAbVYWw026Ccf939meyM33cv20IhtfXP7bXdz 4ray/DvEAusQay8JyoGf55xIgg== X-Received: by 2002:a63:7c0e:: with SMTP id x14mr1859807pgc.219.1620628387826; Sun, 09 May 2021 23:33:07 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id b7sm9980189pjq.36.2021.05.09.23.33.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:33:07 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 12/14] dfu_mtd: Ignore non-implemented lock device failure Date: Mon, 10 May 2021 15:33:02 +0900 Message-Id: <162062838237.501222.11456115358325982186.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Ignore the non-implemented lock device failure on writing mtd via DFU. Without this fix, DFU write shows an error on such device even if it succeeded, because dfu->write_medium returns -EOPNOTSUPP. Signed-off-by: Masami Hiramatsu Cc: Lukasz Majewski --- drivers/dfu/dfu_mtd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index ca67585a7e..e58302c32d 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -152,6 +152,8 @@ static int mtd_block_op(enum dfu_op op, struct dfu_entity *dfu, ret = mtd_lock(mtd, lock_ofs, lock_len); if (ret && ret != -EOPNOTSUPP) printf("MTD device lock failed\n"); + if (ret == -EOPNOTSUPP) + ret = 0; } return ret; } From patchwork Mon May 10 06:33:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433043 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565879jao; Sun, 9 May 2021 23:33:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRB44O6Z8Z0n7B5KC2Tu36rgTv5ksA05OCYXrOvczyo0CWu9X+MC5bY7x56v4Irp1ivqNL X-Received: by 2002:a17:906:38c5:: with SMTP id r5mr22932391ejd.230.1620628430860; Sun, 09 May 2021 23:33:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628430; cv=none; d=google.com; s=arc-20160816; b=dzIjr+vp0ivDwNiv3S1gB19i7rmpWT9rX5CT9CR8IA1i7K+zK5aSIyowPz21d/T8H2 IT8gYCsVim5OrjvEXJFoZIBY+fb9h9QmWRWNWDbKJ2sinXAHGQlbphcq7lMm/L4tqzDQ 2L0BdUMyBX5bkGh4v72T/aUXMRV3FBKEDLrfEuF96jcNWLjDrio0GY1DNcH5Lq9ivvBi M1JVLEeu1OqPNXBjwulzjUOx5WPJp+7/n5r60Wn8YaqFKrOUU9FgFQ/29lmf3iPBEQXP Zv6FEDie253nQ0Y7dNgb7Fht9tdLxfYDbw8ZgIHncuxBA/+MxbOPlUDGo353NaHzx3fm IfOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=C84QPnrWb+SNq0zwr680+GUxeBQNRmJ86P2otfOHeCc=; b=JVfvC1LpJC5HoNDoCMxRrxRr6ulhR8jwcpN1orwO9XJSPP6SnxH6Zu8canrX9uWgoU nlVvLb/E5YpGJmOrVQQHYUGC4NMhs3a4hGDGCxk+zjNEGBgO64s+HlE3ibyKUAh7yv+v w+urwYqaKk6jcwL/WF78jew0Ikt8U718D2kmsFrz1WCE0YISnSaeRAv/mIugnvscdX9d JgDEIBwzstFwjWFOt0cyv00Hdx+7pk9fndwdbeiB051pT9xEqhB08erLt31k39h40FhH JuGFN7tsJUQRsQthkvz6s+uCFqlTQXGmVK16uxdsZcXtCMphosTXssSC3MjwiDdG02nv m02Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ciiAKxJt; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id j7si15375642ejm.492.2021.05.09.23.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:33:50 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ciiAKxJt; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B73D482EEF; Mon, 10 May 2021 08:33:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ciiAKxJt"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0AB4C81D43; Mon, 10 May 2021 08:33:23 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2FD7A81D43 for ; Mon, 10 May 2021 08:33:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pf1-x433.google.com with SMTP id x188so12912529pfd.7 for ; Sun, 09 May 2021 23:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=C84QPnrWb+SNq0zwr680+GUxeBQNRmJ86P2otfOHeCc=; b=ciiAKxJtyfh1Hyq3Iq4Zo/tP//Z5eLg8Tk0Ly8zA/rcVJQMMlcPQA4EvuEKo8Bek6M gb7uVXP4NwGlIHVKB0RwgGgxC/4EKFbW9eoG7V+TGzPsXP8z4lOAfVP1ucWX9VLV2NUW Vo70jBnayhDoEZh3jcKhcTUt0XFLIcJyTh6obCRvu3nAIP5PqhSSGQ7CF9i+VSRxJb3b fK2L6BFiDcQ8nLbxomdgNHict7tGyFgnyoY/V3KhpeJq3smoDoT8ivo3d5CsNSpdojFr SFoN8ObgV+EvK9r0m3ZXFNBZM/PnIvN/dg+zwDRBpr1VCrylduvTvozNzqm/yf9SGQ8G X4hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=C84QPnrWb+SNq0zwr680+GUxeBQNRmJ86P2otfOHeCc=; b=sucwjVVsUioZvI7CgBM4xICch0AS9IQvn8Yyzc5f2svbVhRRn4Kq19uE08/xiUpJ59 5DnC8bZFl6NhnhK6gJ23BSZS8hTaMwgOhxw3R3zycgssZe5p/08bzmVFaqz55gbTm1b5 BdrTh1o80VADhNDxSo26Y/rooM4uz3L0mOF9uRmO6tg/L5RPKe6c8/UYJ8oLbK/dWN5R eysH4qW4vQX2X8Nd8ZVDIGSdXJ3QDD37gZCAh7LaT29MyB2b5FbZ4XzYUg8Wu9MZ2lPc C1Wm5Yv1JHTKVGMsJ/VcKeZ/OFFadWkplaaciCDcp/q0GIgp8MkVVQoGVL5Qqk13UBKl 4O2Q== X-Gm-Message-State: AOAM5307pnIFclBd7esAWN1Kf4U5IQPaFO2RBQic/izKcJuDEYVv6qJ1 pq5KtvcrxQm9Af/ktKm835VCYw== X-Received: by 2002:a62:ee09:0:b029:211:1113:2e7c with SMTP id e9-20020a62ee090000b029021111132e7cmr23327732pfi.49.1620628398702; Sun, 09 May 2021 23:33:18 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id d8sm9719427pfl.156.2021.05.09.23.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:33:18 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 13/14] doc: qemu: arm64: Fix the documentation of capsule update Date: Mon, 10 May 2021 15:33:13 +0900 Message-Id: <162062839322.501222.2563286012019838613.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Since the EDK2 GenerateCapsule script is out of date and it doesn't generate the supported version capsule file, the document should refer the mkeficapsule in tools. Signed-off-by: Masami Hiramatsu --- doc/board/emulation/qemu_capsule_update.rst | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/doc/board/emulation/qemu_capsule_update.rst b/doc/board/emulation/qemu_capsule_update.rst index 33ce4bcd32..0a2286d039 100644 --- a/doc/board/emulation/qemu_capsule_update.rst +++ b/doc/board/emulation/qemu_capsule_update.rst @@ -39,16 +39,9 @@ In addition, the following config needs to be disabled(QEMU ARM specific):: CONFIG_TFABOOT -The capsule file can be generated by using the GenerateCapsule.py -script in EDKII:: - - $ ./BaseTools/BinWrappers/PosixLike/GenerateCapsule -e -o \ - --fw-version --lsv --guid \ - e2bb9c06-70e9-4b14-97a3-5a7913176e3f --verbose --update-image-index \ - --verbose +The capsule file can be generated by using the tools/mkeficapsule:: -The above is a wrapper script(GenerateCapsule) which eventually calls -the actual GenerateCapsule.py script. + $ mkeficapsule --raw --index 1 As per the UEFI specification, the capsule file needs to be placed on the EFI System Partition, under the \EFI\UpdateCapsule directory. The From patchwork Mon May 10 06:33:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masami Hiramatsu X-Patchwork-Id: 433044 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2565979jao; Sun, 9 May 2021 23:34:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJylQWK03g72Fuwa4djAykSlTHxdH9fZTBHDq/DfBxPQwk3cfFxh8xV7lLHkJ2ED8adgdfXG X-Received: by 2002:a50:fd0f:: with SMTP id i15mr17640061eds.278.1620628440983; Sun, 09 May 2021 23:34:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620628440; cv=none; d=google.com; s=arc-20160816; b=qFtb0m9IKsvQ9B/ZZ6+xG32DtRfUfjE2y0wy6uYVFv1rTV8Pcc8/K1VpmPT21RmpN2 6DvAM/tvdPfpKrh+CdE75CVy5yl5ZUzbfPZSq/8/i847j7Rq9HgCHsaQiTD7cbHExi3m uXr2F9bff7JEettEBLOAj6vqt8HY2V+lZx/qqxzRBx2rfSfPg+7Mz4e3UvwVYCISzb8z h21TU2q+YHbJQojbYanoWOKQUsfwPpURJN3AANQFnEGpBpuTQ9qO69KL4yx4bR7ktgrt myGVxCcBk2XVUvnXrv8PEiZM3QB9f80pDX6TVm2nN2EfickhQpPyctgA0ja/WT999d+I i/Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:user-agent:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=cAXWaGrwmYfjtml6DWj4MSnYiSNrD9FNfF1JAJu88tA=; b=SuJHHNQgbpgR/Gu3Ff/Ng+nvLRscb1mApRGJNHFvZptc5ksgqE/VSMN+nggOeO7OsC cdAd5ZHXoM8DTkXVDWkwstAN0b9uNxBZS6Oo9kYSwXtaYc00mhR66rVrYXSmi8A6+AcV c2NJYyBcpIEOPwG40p0Yn2Dc0vWia1NhkppdlWrjYDBOusOFEJaD0BXP5xZfaU/cPwKG FC0x++d+Q4hHEFyqcnGaKAmE5xbyno5f7I8tXR/aDwQD96IhI9g0jF4EIZUS2DEppc8d aDDyRbhE/Oq1qjBjmcvemTD38EgflXABc0Xd/MMC0WCoowAa4/2jl70IUk5HVutm5Fzc f4RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ze2A6eEo; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id d18si12924432ede.25.2021.05.09.23.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:34:00 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ze2A6eEo; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8AD4882EDA; Mon, 10 May 2021 08:33:35 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Ze2A6eEo"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AA86382EF3; Mon, 10 May 2021 08:33:33 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BFD2382ED4 for ; Mon, 10 May 2021 08:33:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=masami.hiramatsu@linaro.org Received: by mail-pj1-x102a.google.com with SMTP id t2-20020a17090a0242b0290155433387beso7710475pje.1 for ; Sun, 09 May 2021 23:33:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :user-agent:mime-version:content-transfer-encoding; bh=cAXWaGrwmYfjtml6DWj4MSnYiSNrD9FNfF1JAJu88tA=; b=Ze2A6eEoyptOHcn8g81ImHO9FMCw5nn3CD8rr4W6X88pQcTZQcsg6AnYqMa/Jx4nYk X7F83ZCyGhf5o8YjoVbKaCYJd4/6nhFQLCHg6VhmlUPTQB/ZeIUrFXSNV7Ff7KDS4EmY l/h3bPqLIM3y3l+hr7XaEhab5Vzgx+/oE1ICoOfmQrjvGPnasOfkHMRBTUYGFilPqXQU +L5PZhGUksbs+8N1T8/rwm0M+xicd5vDgMGozdvKbR8TVSMB2++55/vnevt0bcMxbGvI kWLCXQaJbADTz84W4XgoQ2B37KzpbpMzbEtyufIvV6p/sG0oQ9/10C5blYdKLNhpdYYQ s/Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:user-agent:mime-version:content-transfer-encoding; bh=cAXWaGrwmYfjtml6DWj4MSnYiSNrD9FNfF1JAJu88tA=; b=hVSQ9MdbTNbpdOUdbKRFpxfWaLVqDr7YLzvlqYw8nIUgQ1AlBSaHxBf0P3kMFqD+IY rGq38Gjnc9H0J6DsNbRTe5RRESn2QR2U4pKZj2TX6LR6Z0WnjzY6ttqXVj6rqkXmnqAl ISIMdB5Eo2O/peL6eew+VEtONY+x2up4UxOYZZfwHEEi15owAb0LsBOpBs2XA4hFDRMp 2UvJyx+SmhkF5/GPjtrkzHCZGQNVkbvahV2ekrK5TKD4EM9mqTcMplR69DerMqiQjbMD my/sEUxEBc19i140cQFxfSk7tXzVP1+cqrwdSbIUZlCPBoqVjbJUU7nUpdJiW4HvU+rQ DncA== X-Gm-Message-State: AOAM53045CqK3VPfLonH9mb3GC1PSN6RQrtAjpEOyn1irL+D3hr4YeQd 4RpAf6aMjVT2HEobeUd1hXwZrQ== X-Received: by 2002:a17:902:7b8e:b029:ec:f35a:918e with SMTP id w14-20020a1709027b8eb02900ecf35a918emr23523853pll.77.1620628409335; Sun, 09 May 2021 23:33:29 -0700 (PDT) Received: from localhost.localdomain (NE2965lan1.rev.em-net.ne.jp. [210.141.244.193]) by smtp.gmail.com with ESMTPSA id y13sm10380013pgs.93.2021.05.09.23.33.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 May 2021 23:33:29 -0700 (PDT) From: Masami Hiramatsu To: Peng Fan , Simon Glass , Tom Rini , Heinrich Schuchardt , Alexander Graf , Jagan Teki , Vignesh R , Joe Hershberger , Ramon Fried , Sughosh Ganu Cc: Masami Hiramatsu , Jassi Brar , Ilias Apalodimas , Masahisa Kojima , Takahiro Akashi , Tim Harvey , Bin Meng , u-boot@lists.denx.de Subject: [PATCH v3 14/14] configs: synquacer: Enable EFI capsule update support Date: Mon, 10 May 2021 15:33:24 +0900 Message-Id: <162062840411.501222.16663129773006491967.stgit@localhost> X-Mailer: git-send-email 2.25.1 In-Reply-To: <162062825393.501222.13616174511857694530.stgit@localhost> References: <162062825393.501222.13616174511857694530.stgit@localhost> User-Agent: StGit/0.19 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Enable EFI capsule update support. With the EFI capsule update, you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are usually combined as a FIP binary, but if the binary is bigger than 480KB, you have to modify FIP header, split the OP-TEE and stores the OP-TEE binary in the different place. This configuration supports both cases. Signed-off-by: Masami Hiramatsu --- Changes in v3: - Fix a typo in dfu_alt_info. --- configs/synquacer_developerbox_defconfig | 15 +++++++++++++++ include/configs/synquacer.h | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index de12587775..428c66fa58 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -92,3 +92,18 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_DFU=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_DFU_SF_PART=y +CONFIG_FIT=y +CONFIG_OF_LIBFDT=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_ERASEENV=y diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index b2dd6d0f0f..f88fa21eff 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -58,6 +58,11 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ /* #define CONFIG_SYS_PCI_64BIT 1 */ +#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ + "mtd nor1=u-boot.bin raw 200000 100000;" \ + "fip.bin raw 180000 78000;" \ + "optee.bin raw 500000 100000\0" + /* Distro boot settings */ #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_USB @@ -101,6 +106,7 @@ "ramdisk_addr_r=0xa0000000\0" \ "scriptaddr=0x88000000\0" \ "pxefile_addr_r=0x88100000\0" \ + DEFAULT_DFU_ALT_INFO \ BOOTENV #endif /* __CONFIG_H */