From patchwork Mon May 10 12:25:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433104 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2791612jao; Mon, 10 May 2021 05:26:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYkXUBzdwqtTrbG+ItYClnZEZWLvwcjTC2cdyAn54OFLRjVqwoMdTtesjKg1Rp6vwGShSG X-Received: by 2002:a67:c904:: with SMTP id w4mr5414619vsk.48.1620649595340; Mon, 10 May 2021 05:26:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649595; cv=none; d=google.com; s=arc-20160816; b=Qvqfu0Yl37LXVnwgpXE6yIzmUyv1rNjDzaR0egFTn+T9xzkwj2v2iaZUv4DhrpOQ53 mIbWuY0dJuGyoaAu7L6WduSfQW7RUJ26upK94JvmUjRhe1yPcjaioT3SXfUiidLpXgHE cRLbTZJt3G4pbYsfsFJQ2gWIJh84vLTmARAFVSpKI3fwUHXrTnuBHutpDgkTd+0P/e/W GNSliQz3VHlIfQrvhsT4CAmnJ2VlhlokckE5khV80Er0kefMx/BHF7B9bvW52I3ywSrA +uUe8km0CsjalyNz5rroUpX8wp0amSOInIzJE+ZKj1J0okgjxtqBczmCKKK2YiOrHGbp 0doQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SY9Eq14QwthAWesAyMtT78+tvNWJIa5qNzpG4zNe6V0=; b=A7p23K85bGa8H0m+7lFH0cEHVw0JOHRkU+EHTRX+V8WEZ4EpIb7Qme1JOk9qLfd1z5 e3yRds0KC6klxmmMopYQr8Ok+sXqXjVhnuG+0PTR6+15KrLR5KTtKqe6EPXY/gMZ3M6q Trev0OYJC/b8hIdsD/qBppKa+TvVrKEgXPYyliDSlKnPeWH2vHDD+yjNLsKYDtMC+3HK KHdTFyJ4eLCj5DoWLtDgXNz45UCgGbndFbzYyuKZ6s2lthdNo2yqBIdrCgNTrBb4FdOe LwY0IlaTacgSsAO/Q6aYEt8I7Yu59nz/tcRexIy1+1CiOj9MwSSIuzTSno7GfRj/agDq FB0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VQB0Sp7m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o25si6507625vsn.352.2021.05.10.05.26.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:26:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VQB0Sp7m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg4za-0005Xd-PZ for patch@linaro.org; Mon, 10 May 2021 08:26:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4yw-0005XJ-Tr for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:54 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:47056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yv-00038m-3S for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:54 -0400 Received: by mail-wr1-x42a.google.com with SMTP id x5so16403576wrv.13 for ; Mon, 10 May 2021 05:25:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SY9Eq14QwthAWesAyMtT78+tvNWJIa5qNzpG4zNe6V0=; b=VQB0Sp7mg22cLnnYLLq4fd9/DEHZIoQdDw8+saruK+ACYtTRoqmcKlVOm9+7JR6QqK 4go8vG8bEPZrRkhnN2nS4peJ1BCDOc76fzUSzN1Fhui9bQtQA6I2WSELxmhAtcrhem2B mwF4DFx9KXpp5U5M2XRXyvrpAe2c+VbU5LdLEaJ4Sv47D8SB+J9lfdXxritGv21HLfG4 3u9A8IVAs+R/H0A0pbeNThRI8TiIM9r2/eampdsJrVQ6APeH5dfSUWeVKAwFzFF+Nj1C V2xyu2eq3f1xDEnoegoNWh9v8YU7jB8E/GfOG8Y6TakgWz4vjlrhtxuYPFCAXXoxd3B1 a7Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SY9Eq14QwthAWesAyMtT78+tvNWJIa5qNzpG4zNe6V0=; b=BchU/Y8NlFOq2Ycqah6vvxN5rN1fOw1LnN1t+uXttPa2JOn6iD25Vtl8Nyd1kbSU/V fwTp7nO+UxqOYfvKOEm0sqFgvt9+KP9UgEZe/xaJJwnHn3Q7S4Xvr65wG5LO3ekEkftS 8m1T1mHNPCesOctbbPKJjL0smXW8C1xW1eg81dEQS04vXblnyfO09O/yS3Hl5X6RVbzp wuiUiF2YZTwf3+y83obGcWN/2UaBLuAvG0n5251Dra3gH61zqJFQ13sGdhl+UCwYF/Ck sBUlO8yWut9Mqp7erp0x5+KDfvPrTdBRaDVwvZTmrMOtjj8aK6uguU+q3Vofp0hE+C/e dybg== X-Gm-Message-State: AOAM532eNZ+ETC85aVphBXzmWI7YifEsQV2QxcOpa63UEjb6pkWgOdTH CJQgvhZawyKO3mbBoBpwIfzT+Oysx7QxHg== X-Received: by 2002:a5d:4d52:: with SMTP id a18mr30322493wru.45.1620649550909; Mon, 10 May 2021 05:25:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/26] docs: fix link in sbsa description Date: Mon, 10 May 2021 13:25:23 +0100 Message-Id: <20210510122548.28638-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée A trailing _ makes all the difference to the rendered link. Signed-off-by: Alex Bennée Message-id: 20210428131316.31390-1-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index b8ecfdb62fd..27b0999aaca 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -4,7 +4,7 @@ Arm Server Base System Architecture Reference board (``sbsa-ref``) While the `virt` board is a generic board platform that doesn't match any real hardware the `sbsa-ref` board intends to look like real hardware. The `Server Base System Architecture -` defines a +`_ defines a minimum base line of hardware support and importantly how the firmware reports that to any operating system. It is a static system that reports a very minimal DT to the firmware for non-discoverable From patchwork Mon May 10 12:25:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433102 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2791273jao; Mon, 10 May 2021 05:26:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxtzNS4CSNkihUeBar0TolTS9MnF9XhBaW/kWHRAKBk7DV8I6h3UNP/fVwpHO3c/QohsZYE X-Received: by 2002:ab0:6898:: with SMTP id t24mr10845635uar.120.1620649572055; Mon, 10 May 2021 05:26:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649572; cv=none; d=google.com; s=arc-20160816; b=LaJdaJ09TNDF5TdzJPjoeE7tqABLw2lZYAYE2pSQOWKgVD36yO3Cs4w6CuD7XoxWFS v+nP+VbUt4vXrNGKie0Rw+4qbKYzAPucYFLlvnoIi/eAXE0TjqkNJggfGQN2hAar0USu HNqDZ/A6ZQM0X4PNRpyqUh143n2t9UQzMZaCGwXcAR5oaZ2pojH6ex2zH/NABJ8clVqm L7q8PDmpNnI3j1TOZYCRCKx9ZBW94HyauuQVH08Q3+4cBnRgVCnT9Ac4F3gkMUXthzEo NyxSimQxXzvQz3SPNLYhfghfW7Alv2ux7qV79ebiVdNTnPfZHaPi0HqDuiOQGOqvliAJ qcDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=toJACPBD+agquDJNeNcjG7zq9jkLnO9aVFHB2e+yE4E=; b=oRUmX0XXe/IKVsHWesARkqWEyyd3VJHAeAoh0eGWvbUuGhWATC38cQHpR+8PPPFhkA PMD7dLycQR8Y9AcVlqp5kacn5fFaCjvWM2HCDxXo3R+DdllQKUI+DuvT9DZBj/boLngv HtJX/ZFxiU6WsImB6CYhsTJ7lbX6i+KRu5nJ6z1sOw89j+pDQ0qIbvUFdJpOx2oBcpSF mRHMBcA/YmsBZN4DzEHFVKQyYQJwXex+vjxafieDaTJyhXVQ82/ljGIw1/vPJWxz6u2z eLkICDs1dsHetbtptKfmsSqFqTfJE4o9//NbqXvbTXX9HvTZKz8D7XSLR/d43qFOWXvQ 87mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FhSqu6T1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s3si5308123uag.178.2021.05.10.05.26.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:26:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FhSqu6T1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg4zD-0005Za-BK for patch@linaro.org; Mon, 10 May 2021 08:26:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4yx-0005XR-Bc for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:55 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:33661) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yv-00038q-3M for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:55 -0400 Received: by mail-wr1-x42f.google.com with SMTP id n2so16476754wrm.0 for ; Mon, 10 May 2021 05:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=toJACPBD+agquDJNeNcjG7zq9jkLnO9aVFHB2e+yE4E=; b=FhSqu6T1mT/f9nwoF7e6KsBelEk847slEF/6uxSahdZeMEQ4BMbwNYSK4kYeuYMl5e J8ZBb5aF4SMNgpiWc/aPqGbYgoSd5n4cVLx58yOvbX4ZOOlXys5b8f/ab6/rytLxxtmx Cxj8b2GRsxT0kYko53IwRUe8Lea18yHaqc/GJ27mrrOH9+08cIZpEfVWg8NXxYhdL4Qc cJwRFu+Ijd6Jth1537B2QnnrbXGevIyiYSKqWLiUewI9SWstopBaUXq8Gsa6TOFF+Xw4 r1tkxpYPAWf0lMNZqccJo0eNIyYw5izqWNuII5tD312XcvFwzHKsa4Td4Z0+D9R1A+5+ Zztw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=toJACPBD+agquDJNeNcjG7zq9jkLnO9aVFHB2e+yE4E=; b=Nry/liVyhNzlkFk625umyqyteoqGHCHgXnuH33EqmcdA1Ty+G1gCrWDXyyrm3JYVni LpW2XFNnYf2SyztdNsDysID8SEf/7vi9IncCP91/O4JrfHubwzedfDqWquUMLtxLcpCz sS6rF94g5Xe2fzhrf99XRkMsrHHH3lzJXbnH0ue8EqDyHzfe7V+P6qA9oX9/w3Eqlh3E T+IhOm6bLPyj7pC3Lrh9YrrX1vI/wXrXll0kDUvwVLresYH76ha+LdilO72aKEBOf0up 7B8UpNVxwlCIsSrPK5+u6jgJkxjFSqD4G+GY4hom7Lo4orxmihevEQ6LpkxERyPxzUZk toOA== X-Gm-Message-State: AOAM5325nyCdQ1rObtk0BLIm4tng/zJTDkA2xKHowmTVMp4fHfgMwU81 YJybS0wPNps+/jR7lMC3Sn8clPFq2aMotw== X-Received: by 2002:adf:cc8c:: with SMTP id p12mr30388590wrj.407.1620649551510; Mon, 10 May 2021 05:25:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/26] linux-user/aarch64: Enable hwcap for RND, BTI, and MTE Date: Mon, 10 May 2021 13:25:24 +0100 Message-Id: <20210510122548.28638-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson These three features are already enabled by TCG, but are missing their hwcap bits. Update HWCAP2 from linux v5.12. Cc: qemu-stable@nongnu.org (for 6.0.1) Buglink: https://bugs.launchpad.net/bugs/1926044 Signed-off-by: Richard Henderson Message-id: 20210427214108.88503-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/elfload.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.20.1 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c6731013fde..fc9c4f12be9 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -586,6 +586,16 @@ enum { ARM_HWCAP2_A64_SVESM4 = 1 << 6, ARM_HWCAP2_A64_FLAGM2 = 1 << 7, ARM_HWCAP2_A64_FRINT = 1 << 8, + ARM_HWCAP2_A64_SVEI8MM = 1 << 9, + ARM_HWCAP2_A64_SVEF32MM = 1 << 10, + ARM_HWCAP2_A64_SVEF64MM = 1 << 11, + ARM_HWCAP2_A64_SVEBF16 = 1 << 12, + ARM_HWCAP2_A64_I8MM = 1 << 13, + ARM_HWCAP2_A64_BF16 = 1 << 14, + ARM_HWCAP2_A64_DGH = 1 << 15, + ARM_HWCAP2_A64_RNG = 1 << 16, + ARM_HWCAP2_A64_BTI = 1 << 17, + ARM_HWCAP2_A64_MTE = 1 << 18, }; #define ELF_HWCAP get_elf_hwcap() @@ -640,6 +650,9 @@ static uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); + GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); + GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); + GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); return hwcaps; } From patchwork Mon May 10 12:25:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433105 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2791674jao; Mon, 10 May 2021 05:26:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxkg9d1Wxw5f9B1N2G6z5aLdMW/FDWoMn4160RkJs85tPM1j8hIYFFKJ6+n98D2TqDf/V51 X-Received: by 2002:a9f:2662:: with SMTP id 89mr14903528uag.137.1620649598651; Mon, 10 May 2021 05:26:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649598; cv=none; d=google.com; s=arc-20160816; b=KKGClznQ6Hr5E9fIk8jYGuRIl8Kx3F2CbDIIQITZ0V4JJmA/XHJPC3bJgaancCyQXI g8B6fILb4x+xlDcf6Z3YWseqrpnofxF4oQu+fmNe9T4/kxVeLIupWMf5Vp3vR+7HyNmK XJCz1G2XhDlLLs5Y+VU6iJjBRiAFyB4XdMJTfQ+8nXFSK6mR689g4B50ydNABNurcae/ pKa8e1QuJmko5KZySMxERN1kqHBOhGpUZPeWtt+7Wh9Db8KDQd5xj1qim+wU32acbVpI kkeeAgocY6j2e32SlE6FZdffR2LL3mIJTKObIbjJoC6bkvMb2Q3AW/HJoyvsgILdzVkF S+AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BkwYn9GlEXVqXaAI4IuFCkOZqyIgHd283tDE2JpygwQ=; b=ac749x45tUsKYoqEgIF1acvlZsyfqHQJ543PZUzVIESwDiWV7M8mykW+uXc48jauhv qsNftk/ZZRgHLVXR3E8XpVE997SS6LbKn2ts7uahnMU5hFD244W1AJLlSPHN6LrEzOdK iQ2LnXvQLUahTiY08tqCPkqT9X1JROyHC1U8MvurZAb5atho1RGceCh8pHytYLka/EbR 796FIhVjK75MHXv8feCrK+37Fwp6cxoG9H4pFz1u97TtFYbtpSG2ETSQiIXNz9AHX0pF UxwyVqU0OhlMge96slKbOqc8EtN0HXKwJQxjIS1kfFXHD5+XOfHJJ3gdAa4D+KvFK4TL g9zQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=poonjJnE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w190si5349762vkw.41.2021.05.10.05.26.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:26:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=poonjJnE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg4zd-0005bb-Te for patch@linaro.org; Mon, 10 May 2021 08:26:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4yy-0005Xp-8b for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:56 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yv-00038w-Bx for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:56 -0400 Received: by mail-wr1-x42e.google.com with SMTP id s8so16430772wrw.10 for ; Mon, 10 May 2021 05:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BkwYn9GlEXVqXaAI4IuFCkOZqyIgHd283tDE2JpygwQ=; b=poonjJnEhcjlVMVm69eI7lPupqtM4AnL7da3jOGUWEeFgALbu0W/KQAP7nhyyZK9Aq SE0veHREyWmB/zJX6PmfxNQp9A+Yuzia4vAj6J73BqcgMLTpq4GUR1tecOd+/6QLDU70 TU73wXNDjve7iHML1Yxgmeoq3I3hvDnI8W8yIJP3KJVkatyhp3F6ZWX5AZmxGyb7CFok gRq5kJPeAW/r2U8Iqprvopj9DDEuMlUxGIl/IVuoRBwCtRwyTLvWgwcGz0l+UUz/PNwF YACSnhsFjL0fZshWe7W/jHcJBkZ7z5NpG/da6BQX/zbcFQUt/+vlTN+sKLAHuukXvZL7 xZxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BkwYn9GlEXVqXaAI4IuFCkOZqyIgHd283tDE2JpygwQ=; b=fbXqsRmlRehEdR20kQju1V9FrZ2/6rZGCubJAvZQsm12mPvF/YzMxBBAn+oNGrEp6/ /CAuC99IY5daaarXJv3VJWdaWH9ipOeLO0a6hKK24CPfYIipLz2m9BxURLvZXxS5AljO ZFY5hxcTA0G9BwPPi/CKEwsvVUY9iQ/KZkyZC4EThMHAgAaJ+zynpQv191qmx5wOCU86 dZNYs0XaqHWQSwKTfXB1bXSGm6CYMnDZjjur1+Pg3kW6Nx5DXZaTaRXn3dlIlzprPeAO 7c2QfEjHXatZjd1Nv2/Sfy5NhokBywDhYvCPcZsK9a1WO7aXAJRvcmKzbvkM7gUMGYQB pTUw== X-Gm-Message-State: AOAM533n14ZzfkX1ao3XvOGHZlZW16z3njeur62pICDoni64A9YqAOvN 9tb/rF2gqTq1dKLW+Q+QlVCj0e5B1TQjig== X-Received: by 2002:adf:f60c:: with SMTP id t12mr26730290wrp.152.1620649552099; Mon, 10 May 2021 05:25:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/26] target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() Date: Mon, 10 May 2021 13:25:25 +0100 Message-Id: <20210510122548.28638-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In tlbi_aa64_vae2is_write() the calculation bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, pageaddr) has the two arms of the ?: expression reversed. Fix the bug. Fixes: b6ad6062f1e5 Reported-by: Rebecca Cran Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Rémi Denis-Courmont Reviewed-by: Rebecca Cran Message-id: 20210420123106.10861-1-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b1b98705f9..3b365a78cbc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4742,7 +4742,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t pageaddr = sextract64(value << 12, 0, 56); bool secure = arm_is_secure_below_el3(env); int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, + int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, pageaddr); tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); From patchwork Mon May 10 12:25:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433111 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2796671jao; Mon, 10 May 2021 05:33:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzhLzB89KmkX/R8wCJMv3QWkIuBUaXr7CLPy4aK4QFsoJLXUefO52NQNOaLJZ7joz1cUR2i X-Received: by 2002:a67:b10a:: with SMTP id w10mr952960vsl.36.1620649997274; Mon, 10 May 2021 05:33:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649997; cv=none; d=google.com; s=arc-20160816; b=xjC76kPj9rwDruljxW6zf8++AvNOTJdrvauhUXasGeWyBd6iU4oBCuMkMl7gtX3dCr JGrz6gFbDFrYToXl3n/+oUMPfKHQmVU0iX1QpxUE2raRW2EVWclmRWiv4nRRnB220Xql qMB2yZ/UFT468WVCX6V94JLw67WAfHrBfStlGNE1DNo2TG1X2eS2OUITecqjqCgxbgM6 ktx4CZ6BzSDuHJwXJnvAaBzfMr9zGNBEAo1fHZSyUT3S3Rjnk0lgcLDLvL2xlmt3haAd TJ/XW17Rz8XMCNGRoNGAAnbSPRxFy6c9ynAt5tLiKibQOK1eJXqEFm60uU/nScuR0MRf p/Mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6v1BFUcHTHuknKkZHtkSafnfLAhD43tM7z8g+lL3ix0=; b=zGVkM7HiT/THps9ArIyI1SjJBxthDeuzCqGRS5VxubxhR9H5Tvuw3zH323vlo2dfI+ MuZQ161tzAGpaRrvU0nHFtRtVOYIB/ICA6cqwK01TSfe6fP0IWQ+445O+RvaIuWpoSjn gDAjxWI4fZmb9ZADOqWlErDXWKSKq8HgAWSoX1IlSnshdlTU6/jjrEf3CZqd+GXF1h9U SwDqbSTQ9A9KmfGUShQ6jiarTlWh6Vhvfs2Soxq8NLSsuGJqwYQxlhUNsZFwsfbFXKQH NEwFBNV3NaJFdKvm5MN86oRch4fv3MxDsbH3gZi/66WLAtY8VfxOiWpy38Z0jV5rQw2s gSYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=On+j3o3I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u6si5420827uaa.196.2021.05.10.05.33.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:33:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=On+j3o3I; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg564-0000DA-LD for patch@linaro.org; Mon, 10 May 2021 08:33:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37374) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4yy-0005Xx-CK for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:56 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:45641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yv-000391-Vt for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:56 -0400 Received: by mail-wr1-x42f.google.com with SMTP id h4so16399113wrt.12 for ; Mon, 10 May 2021 05:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6v1BFUcHTHuknKkZHtkSafnfLAhD43tM7z8g+lL3ix0=; b=On+j3o3Iel7K5u61OE/pGWmx0QgVOWl5SGi0tmOk7dW/imQVTDYFl03K6FWiKn0Rot gvN7Z0eTTf8K5u75SnTZMhLPXW7mNoWlkYUCRIo4BU/AKLBqSm5b0Qq89DWCBngBPaJb fYNup2NGzRLlucxcW+1HovawQKVhpVuaNGJaw+AUw8MuaD1YPP1SCY1ZY+7LQU1/W+sx JYkxKoB7Q2rpJD01+H77uZcJfctq86dr9o2k4mi1q/B+J2x12C3eFbigR8wQ9BOq/EnN meDJ4xa6BBiJYcgR1QmBv3TkOWcSeL6tNiSl64ak74HwyENopxkaUf70gpaunOd3RDId e5Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6v1BFUcHTHuknKkZHtkSafnfLAhD43tM7z8g+lL3ix0=; b=Xvxicf4PkBUusgAv4BpGExL03PrJ3oe1mkPNVrn/GJwdVyoz/i9PkYnJzXufAZuiI/ I96USsIPoaFi8LNdRbM1XusjZpoMR5vkdAdpQ8N+NprgEGmCpJubliad3eqk84OCK61o 99I5hulx4JthI5GIguD5dxtXmAxnCDUhyESkOCMvPzj+VyVBzMhPxui/OQHD2IEoPxIi v3kPWr7G8jWSsKkxnPMOmXwrqA/h4jBCLoDZEwX/j/ZRVjX5D2P4YUHnysuAZueFT5nS ysJVjRzwbsYqXMIcSp4uZpIRdiZh7/hvl50U6lCQC/TseDCW8UEx28TDpOurBBKgBW7q +RMA== X-Gm-Message-State: AOAM5308TuY6t+yKOTvTqetNGsl9DFWgNTjkqe0w0ikG4zdUYVje8EmH ZjfyY/D0B3G/jS+IvnRHGWufRJPRb9RnMg== X-Received: by 2002:adf:ef90:: with SMTP id d16mr30323003wro.359.1620649552776; Mon, 10 May 2021 05:25:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/26] target/arm: Move constant expanders to translate.h Date: Mon, 10 May 2021 13:25:26 +0100 Message-Id: <20210510122548.28638-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Some of the constant expanders defined in translate.c are generically useful and will be used by the separate C files for VFP and Neon once they are created; move the expander definitions to translate.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-2-peter.maydell@linaro.org --- target/arm/translate.h | 24 ++++++++++++++++++++++++ target/arm/translate.c | 24 ------------------------ 2 files changed, 24 insertions(+), 24 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.h b/target/arm/translate.h index ccf60c96d84..b5b21619597 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -118,6 +118,30 @@ extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; +/* + * Constant expanders for the decoders. + */ + +static inline int negate(DisasContext *s, int x) +{ + return -x; +} + +static inline int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + +static inline int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +static inline int times_4(DisasContext *s, int x) +{ + return x * 4; +} + static inline int arm_dc_feature(DisasContext *dc, int feature) { return (dc->features & (1ULL << feature)) != 0; diff --git a/target/arm/translate.c b/target/arm/translate.c index 43ff0d4b8ac..bb9e228d1ae 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -109,30 +109,6 @@ static void arm_gen_condlabel(DisasContext *s) } } -/* - * Constant expanders for the decoders. - */ - -static int negate(DisasContext *s, int x) -{ - return -x; -} - -static int plus_2(DisasContext *s, int x) -{ - return x + 2; -} - -static int times_2(DisasContext *s, int x) -{ - return x * 2; -} - -static int times_4(DisasContext *s, int x) -{ - return x * 4; -} - /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ From patchwork Mon May 10 12:25:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433103 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2791307jao; Mon, 10 May 2021 05:26:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwBGa8M1R0uSt38x9Mbo2hs1o/m04+siTFcnriL8y2mhiyK4hW1x9X90qLlhS7/3vNJ5PXM X-Received: by 2002:ab0:5981:: with SMTP id g1mr16163605uad.39.1620649574680; Mon, 10 May 2021 05:26:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649574; cv=none; d=google.com; s=arc-20160816; b=wKpCwqdpFgWLPhGMjFFViYrV/Vj0ZTlru8oTqYER5mS8I6gtlPo4NsxSAHaV+2h3cd pMpz/v5ori9vk6fZbdARLjginlPKUFJa3tlqECpqM0nKsFI/pxabm40p4SIUxpPdvPUp vTnMnr2nCYdlUjW0iZt2Y3A/wiqiODTvLlgn3zsyAAghkexrUvMtPxglokNcWVwCZd4l IKzSkcMCnxwugaAfwLNZXk5XpLiX3dlYk731AZAL+tcLwSocZjWYNrvPn6Q/eo9cRvXg oxrXC4t9UYqZFNjlNGGfR2usYMBcrYiymmAeFOuKM3QqnqckQI6eBlxtVxD+/jweOo44 ipFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=U2MFf12jiBRiHqGWQfVsDrVn6+Y2J5P6G4QHCaHcmXY=; b=DXICyN4mhMhsotxg2NCPPAzs/wSA7CmlCWZKBaeL4r1p9uj9AVRoiJqgOikF6eXWq0 /jQqJtioY/cLIXgCgAV2NNpLI1sAPHMCWDDdVNZVk6h3yk/51jWfz/9pFwxPtyNR/fPG Or+KqqNz/yrEar4jgAEyIJymsKS56Z31K6xZnxmbfMSR1uOEYip2YCBaQlmYX1l75Q1Y EEKSCuaNzQLRRjM+1kNsLCdt9uIkgFRlBqnIQYl5V7T1BCfeg3cQ+91h/nmYsGysaSFk urmZK2kpeawMNQ/sPiNQqRkRrKzmdpCDk1l76bo368UHar4Q+/Crwgy6sdlIZeHVbJWx yb1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dBgdjzNe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d5si6110698uaj.170.2021.05.10.05.26.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:26:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dBgdjzNe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg4zG-0005hU-1N for patch@linaro.org; Mon, 10 May 2021 08:26:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4yz-0005b5-SO for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:57 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:47066) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yw-00039f-PP for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:57 -0400 Received: by mail-wr1-x434.google.com with SMTP id x5so16403746wrv.13 for ; Mon, 10 May 2021 05:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=U2MFf12jiBRiHqGWQfVsDrVn6+Y2J5P6G4QHCaHcmXY=; b=dBgdjzNetBSLLrfhgtslqpwt9Z7eNPpgeVaOQWVxQ2Nbklm0Bcd23SSxEAuwW12DPX HNGiOLrbddxhPpUoMtmWamUgRfgthDgqaMXuEh9A8zvyB0HtmRiLIRFVD2sOeIljdj3D uXVTlY+N20j1J8RMcAETp8VjXTpnr4n+l2IZ1OaHkL39POoV18eQe+viYrD5BO69vmSK RcGB503fgJUa/3fUU2Ee7v4FxSAoTL0VYqroGKNJp9WG9NaKYeGfpwNZ7K9Q/7r9Dx48 /lqOfCeQHOTeUqu3AqbKTKsaqv1tm5lgTVbC2qrNUYgG2jEuL2MX4omPxJXHbqsN+FVA UECQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U2MFf12jiBRiHqGWQfVsDrVn6+Y2J5P6G4QHCaHcmXY=; b=OzJ+WKP4QXdNu1mZgpIyJMFPS7bVJyPZmFGUTvHEfAFX9Rxk6zQA+Sj0fft9XeK4vg ZaHa63SGGR54JAOhEkYkjsNP7gmyS99Ibj91LgFDUdskHhPZgBVC/HTxlGZFeD5E0JwL fLnNMcFtKsK6zmK7YvQtbmXMHe9E+P4Fb1OdYuF/sZtEwvtPaMUlrui4qI3HOY/OX3vu CctpZhwm1Qb4PO6fKcnsbI5dESIclCEl59Unjtxjcp68fsdqt2UPutAE06H84wcMcgoP FjU+BaWefEFZK9uui2CzbimCSWKE8d7vdHais0H34y1N8aixrByS+el9sj27YP1DmJps ICaQ== X-Gm-Message-State: AOAM5326PkIvo0aoojrykWIDTkY28/f3+puXznGZh6HbQQ1lscm2qw0u 33sOn+TaE3S/njtJkivanecSVYH2tqnkow== X-Received: by 2002:adf:e40f:: with SMTP id g15mr29970910wrm.392.1620649553443; Mon, 10 May 2021 05:25:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/26] target/arm: Share unallocated_encoding() and gen_exception_insn() Date: Mon, 10 May 2021 13:25:27 +0100 Message-Id: <20210510122548.28638-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The unallocated_encoding() function is the same in both translate-a64.c and translate.c; make the translate.c function global and drop the translate-a64.c version. To do this we need to also share gen_exception_insn(), which currently exists in two slightly different versions for A32 and A64: merge those into a single function that can work for both. This will be useful for splitting up translate.c, which will require unallocated_encoding() to no longer be file-local. It's also hopefully less confusing to have only one version of the function rather than two. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-3-peter.maydell@linaro.org --- target/arm/translate-a64.h | 2 -- target/arm/translate.h | 3 +++ target/arm/translate-a64.c | 15 --------------- target/arm/translate.c | 14 +++++++++----- 4 files changed, 12 insertions(+), 22 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 868d3550486..89437276e70 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -18,8 +18,6 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H -void unallocated_encoding(DisasContext *s); - #define unsupported_encoding(s, insn) \ do { \ qemu_log_mask(LOG_UNIMP, \ diff --git a/target/arm/translate.h b/target/arm/translate.h index b5b21619597..8130a3be29d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -229,6 +229,9 @@ void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); +void unallocated_encoding(DisasContext *s); +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el); /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 95897e63af0..0c80d0b5055 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -359,14 +359,6 @@ static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, - uint32_t syndrome, uint32_t target_el) -{ - gen_a64_set_pc_im(pc); - gen_exception(excp, syndrome, target_el); - s->base.is_jmp = DISAS_NORETURN; -} - static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { TCGv_i32 tcg_syn; @@ -437,13 +429,6 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) } } -void unallocated_encoding(DisasContext *s) -{ - /* Unallocated and reserved encodings are uncategorized */ - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); -} - static void init_tmp_a64_array(DisasContext *s) { #ifdef CONFIG_DEBUG_TCG diff --git a/target/arm/translate.c b/target/arm/translate.c index bb9e228d1ae..8b71b1c41b6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1069,11 +1069,15 @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp) s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp, - int syn, uint32_t target_el) +void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, + uint32_t syn, uint32_t target_el) { - gen_set_condexec(s); - gen_set_pc_im(s, pc); + if (s->aarch64) { + gen_a64_set_pc_im(pc); + } else { + gen_set_condexec(s); + gen_set_pc_im(s, pc); + } gen_exception(excp, syn, target_el); s->base.is_jmp = DISAS_NORETURN; } @@ -1090,7 +1094,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) s->base.is_jmp = DISAS_NORETURN; } -static void unallocated_encoding(DisasContext *s) +void unallocated_encoding(DisasContext *s) { /* Unallocated and reserved encodings are uncategorized */ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), From patchwork Mon May 10 12:25:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433109 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2793774jao; Mon, 10 May 2021 05:29:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKXp5+U31MhruxkxxtEt3N6GWCDDttrwgzK105WSeh5QragOLw7Ly1yNjJREviocdObiMs X-Received: by 2002:a67:d11d:: with SMTP id u29mr18984047vsi.53.1620649775531; Mon, 10 May 2021 05:29:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649775; cv=none; d=google.com; s=arc-20160816; b=lTDtWioK1msA8OYTMO0DgbRtfgstT+mNrYTPdjyBmyeK+foiTo0WX8Fn6ostr9U2aa /j5OyRhLUZLF54QQV6/6Rj3vwTR6W0xBYCu7aM+KtUFvqNk2MlCFBRXV4hO4UaMOwgAI XsMuxrURbMBQ6wlQSVHapVCamFarVYp29Pb0U/D84D5b2mQ/vnhexJAgxqczn5WR7IWk 7PZAnBSc111cWZ/Pmh8XM4IDsEjQhfpAxVKRPab//3lUcDmZwdhdXNI+k3NNEtzpkB8z D95KWbP9iXBGVlP7Mi39M8dOUoD2OVlUccFPzXsyoUvCj8sK9T9ygOUfsr6qAZ+IGvRU X0iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eNgDwIHAHZi/N+OKQ2tL85y+Mlg0PqWvQx6aJ/qV3gs=; b=ykNd6Rw8shTSPRtGZ0+HfytENurbmdon3OkL7CcrAJOrqT209y5v82Mo5/n6woG7Z0 cNqqSRiaGxrs5tgJd1fQRNS3SjetlAgKFt8Uzd4/ceWHjjSw7uYX2LCIxcEzuRaP5Xim YjpKRNIJWMSt63EUDmCKkzj2LECkS0gHYO7AnDTSYHg29x26xVsiETpkOOpMCyMwP1nq COXH5XoVdl7Y6yowM7hC/jLribOk/Fhfd2eFBuydzsAVRUQIFce7FAdJMrVnDTMixWpR eEl1J3IsoP0YAc5hgTekNApN7VaeSVXj6EXqWZxLMGO18YKrDox6bz7cM0NW12suW5sg 1BcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xYIA2krQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u10si5740950uaq.146.2021.05.10.05.29.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:29:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xYIA2krQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg52U-0002iG-Lp for patch@linaro.org; Mon, 10 May 2021 08:29:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4yz-0005Zk-BW for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:57 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:43720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yx-0003AJ-Cb for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:57 -0400 Received: by mail-wr1-x434.google.com with SMTP id s8so16430905wrw.10 for ; Mon, 10 May 2021 05:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eNgDwIHAHZi/N+OKQ2tL85y+Mlg0PqWvQx6aJ/qV3gs=; b=xYIA2krQXBgOdz3tA04a3MOKjbgN5jxpPiEVkb3MIKj5etkz4j73qR2vwdAX1M8Bba iKVeRJiYlRK5OPGRDDpWqyH47uSLKtrP99HmTOi2giP7qaYE20qluSPX3mWpLtGQa+tp oM0VsClLqx9AN4eIhyadTesa17gtPtoUYTECRtbhYhMhryOTVnr0e69pGS0P40Qm7nSD 7C0nGA2mit3vZAK1DoEHOXFcwbtWB6FVhIW3JMN5ZH8r1mmz+h3MR50TkZ3BWi/Q+a16 Et1/fezkQaL281OhMUwiHGy8SklbEcifx/9p6FHHO8vSMrDjEWTxRwqgbZ47T1qawBUw Ne3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eNgDwIHAHZi/N+OKQ2tL85y+Mlg0PqWvQx6aJ/qV3gs=; b=jUW6JGQHznlsNf/uPIIg6lh/qYByCkVVSHRTibL5w/l/T6F0VDUF48mDRt2jJ8U4en O13G4q/D0TKARXxFGYL3PX6bL0YGiPtue4BQv4IECEk3WzlWWQfNTtHzyfa9+TxHl5SE CJXS2M9+FOnZQIhYywqDobcIAeF1cu1uww9Id+y6RQiLFD0YiaoB7NeYnmSqB0N6oSBY v7NtzWWHFye/yPDwcRzFoKU+OdgtX41vD2ka0ejR9mEINSNTvWaLrkpNq4x7WHHQUKlR QHXwG4un0l+3lWlflzErV/wkSt7YyMHRV9m2ecDZVbZyldEBDbdTYi0oBsyiMwVbI+0k eIwg== X-Gm-Message-State: AOAM531iri2Q625kfihCodQ91K813oZM0BIKlj8KkzxIGVuVOC0qurCg UH7fmlc5KcwfuQK9cGi4IQH2bh8Oq6KxlA== X-Received: by 2002:a05:6000:1846:: with SMTP id c6mr29730110wri.129.1620649554127; Mon, 10 May 2021 05:25:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/26] target/arm: Make functions used by m-nocp global Date: Mon, 10 May 2021 13:25:28 +0100 Message-Id: <20210510122548.28638-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to split out the .c.inc files which are currently included into translate.c so they are separate compilation units. To do this we need to make some functions which are currently file-local to translate.c have global scope; create a translate-a32.h paralleling the existing translate-a64.h as a place for these declarations to live, so that code moved into the new compilation units can call them. The functions made global here are those required by the m-nocp.decode functions, except that I have converted the whole family of {read,write}_neon_element* and also both the load_cpu and store_cpu functions for consistency, even though m-nocp only wants a few functions from each. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-4-peter.maydell@linaro.org --- target/arm/translate-a32.h | 57 ++++++++++++++++++++++++++++++++++ target/arm/translate.c | 39 +++++------------------ target/arm/translate-vfp.c.inc | 2 +- 3 files changed, 65 insertions(+), 33 deletions(-) create mode 100644 target/arm/translate-a32.h -- 2.20.1 diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h new file mode 100644 index 00000000000..c5d937b27e8 --- /dev/null +++ b/target/arm/translate-a32.h @@ -0,0 +1,57 @@ +/* + * AArch32 translation, common definitions. + * + * Copyright (c) 2021 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARM_TRANSLATE_A64_H +#define TARGET_ARM_TRANSLATE_A64_H + +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); +void arm_gen_condlabel(DisasContext *s); +bool vfp_access_check(DisasContext *s); +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); + +static inline TCGv_i32 load_cpu_offset(int offset) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_ld_i32(tmp, cpu_env, offset); + return tmp; +} + +#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) + +static inline void store_cpu_offset(TCGv_i32 var, int offset) +{ + tcg_gen_st_i32(var, cpu_env, offset); + tcg_temp_free_i32(var); +} + +#define store_cpu_field(var, name) \ + store_cpu_offset(var, offsetof(CPUARMState, name)) + +/* Create a new temporary and set it to the value of a CPU register. */ +static inline TCGv_i32 load_reg(DisasContext *s, int reg) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + load_reg_var(s, tmp, reg); + return tmp; +} + +#endif diff --git a/target/arm/translate.c b/target/arm/translate.c index 8b71b1c41b6..3c1d52279bc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -50,6 +50,7 @@ #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) #include "translate.h" +#include "translate-a32.h" #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 @@ -101,7 +102,7 @@ void arm_translate_init(void) } /* Generate a label used for skipping this instruction */ -static void arm_gen_condlabel(DisasContext *s) +void arm_gen_condlabel(DisasContext *s) { if (!s->condjmp) { s->condlabel = gen_new_label(); @@ -187,24 +188,6 @@ static inline int get_a32_user_mem_index(DisasContext *s) } } -static inline TCGv_i32 load_cpu_offset(int offset) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp, cpu_env, offset); - return tmp; -} - -#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) - -static inline void store_cpu_offset(TCGv_i32 var, int offset) -{ - tcg_gen_st_i32(var, cpu_env, offset); - tcg_temp_free_i32(var); -} - -#define store_cpu_field(var, name) \ - store_cpu_offset(var, offsetof(CPUARMState, name)) - /* The architectural value of PC. */ static uint32_t read_pc(DisasContext *s) { @@ -212,7 +195,7 @@ static uint32_t read_pc(DisasContext *s) } /* Set a variable to the value of a CPU register. */ -static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) +void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { if (reg == 15) { tcg_gen_movi_i32(var, read_pc(s)); @@ -221,14 +204,6 @@ static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) } } -/* Create a new temporary and set it to the value of a CPU register. */ -static inline TCGv_i32 load_reg(DisasContext *s, int reg) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - load_reg_var(s, tmp, reg); - return tmp; -} - /* * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4). * This is used for load/store for which use of PC implies (literal), @@ -1208,7 +1183,7 @@ static inline void vfp_store_reg32(TCGv_i32 var, int reg) tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); } -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) +void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) { long off = neon_element_offset(reg, ele, memop); @@ -1234,7 +1209,7 @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) } } -static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) +void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) { long off = neon_element_offset(reg, ele, memop); @@ -1253,7 +1228,7 @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) } } -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) +void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) { long off = neon_element_offset(reg, ele, memop); @@ -1272,7 +1247,7 @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) } } -static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) +void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) { long off = neon_element_offset(reg, ele, memop); diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index e20d9c7ba66..c368ada877b 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -191,7 +191,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) * The most usual kind of VFP access check, for everything except * FMXR/FMRX to the always-available special registers. */ -static bool vfp_access_check(DisasContext *s) +bool vfp_access_check(DisasContext *s) { return full_vfp_access_check(s, false); } From patchwork Mon May 10 12:25:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433110 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2793995jao; Mon, 10 May 2021 05:29:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwT/6LEFpSupdRzvU1hMz2lxcC7sy6ZNcr3cf4StUI19Ed12IsFPKSpQmSP30dUK/HzpxtJ X-Received: by 2002:a1f:1f81:: with SMTP id f123mr16517483vkf.6.1620649794691; Mon, 10 May 2021 05:29:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649794; cv=none; d=google.com; s=arc-20160816; b=gYnyH1AgeDoTkhWT12dNa3OPV96OUqcERM9Xt/G0KgXsYL6Qd2jImjNSUXxuQDEDvt KVHLMTt8Tddnv3qxo7zolbzOZDaRZGdZSdVQ4zJ0OXcPwRFsU4fLlXOwQix5+ILdwfhh cFW5+BOUOxfE/GBW4J/u41BQ0imErpCHULaMZYNHBPSAoCCoQi0zhuO4ILFDfJ98SKYW Ak0Vn/E3GXI4YUxiculcGqt0apAYbTo1Yhr+xscWN8NBfyeMF2+N+USxfOjSahAJRwMP e84kq+UnjROB2czAy1W4pBxhWs7VV0WJu96gy3mGZyVTE1RIbDB9cPh738ZxbuTABtw7 UrQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=yRSiZALFT64qDrmSPtMVCE1BqJtBCIPc/VUBPEipLiw=; b=cDHK4DjIknVUUs6gPOndSDVWMc7vPVWbHvsRha1k1zF9PONdqbk492SaCJKra7vkoZ wMDtVJBvz3e++fqiNywGO4pTzKhPeEG4DdyRCH3Gkyq+1ljrdCVEletrFtJk1pWSd6Q+ f0v1bf7fFu/v1lbIBwQ8P6n77TdFV8nqUZOXWNrwowiI/AMuRQ8O+5FYT13oGNgPB34w A4J3xBQnG8bm4VhVysn+73Ti6CQ674FjW+7wumULoiPixVEOtdbOVaktXH26T7KtxEvd 366KomEOQtI9BStCSy3dmTppMEaT8uFofB9CneB/ZBuj/2TTXG3ivgPjjJmxw/nLtdSq wWgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g76r0Ret; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 66si6758260vsv.28.2021.05.10.05.29.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:29:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=g76r0Ret; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg52m-00035A-D2 for patch@linaro.org; Mon, 10 May 2021 08:29:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z1-0005fo-8E for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:59 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:35557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yy-0003B9-F8 for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:59 -0400 Received: by mail-wr1-x432.google.com with SMTP id a4so16430930wrr.2 for ; Mon, 10 May 2021 05:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yRSiZALFT64qDrmSPtMVCE1BqJtBCIPc/VUBPEipLiw=; b=g76r0Ret83CIlEtPIsEuQxeeLLDw876BGcGKW+1bLo1yEThXeYL53MlmOed22jaVbm Jgg09agaoeJnkWzKyFGjTxtKK5B436dWXG1XYvC9zCalSyjrPOCisRRfoC1hDdgB6T50 lvyt61O7qW7WAhUUdcYEuYHszJ92GPjymIxSUcALXL5tcg7zu3Fyc3y+LEZdedVlnZWI E8luLTftVssul2s1pP3GcCdDFjKQUsgv0xpwarUJs7CEfTY3RuSHwqbH192RU3U0t1Ju zgHxRsusbfrJ+K69kW6UAWp3bPTTYguYwiL9jAwgiRg6LtHctwoivqQnbHwKdJmlEF3l zL8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yRSiZALFT64qDrmSPtMVCE1BqJtBCIPc/VUBPEipLiw=; b=kJdN7I7q7knSBONZYFS5MmNRmH/6LxFUDgtIqgVtB75DosIMeN9coLHesFLQohQxv6 NiwsOeDyHEaY8FlgWEXPpNheFeqV8aQYDH/uCVYTTYIBqrnlYOxw4/HCVP9GmDfaxcw8 4xquQzWo1b0Sz9DI4jl898lTMfmLzNaVGAecYOTZEjsAHh21CI/bmz7sE0Iswc2rmtEL f3YN6SqEVxyUo26m/xdqRvWAcPDcfAmbvxmduF/OnXwIv9z+kagFjOCe0GN0vMrSt5NM 25NOSXJzMKoKf+aV1WzVRpwFgHAP5uBB/tbltf4+5ivZBuPHx4xzsF/t6SfNblpJNwio 40Cw== X-Gm-Message-State: AOAM533Hl8G4GZdL5z9dgOJRaAOtei+QtFVd02PtCk26WXEbIYmqUVts D2PItZX3zLNq9FzXU3dJfnPjwzVT18iSkA== X-Received: by 2002:a5d:6402:: with SMTP id z2mr30036650wru.7.1620649555063; Mon, 10 May 2021 05:25:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/26] target/arm: Split m-nocp trans functions into their own file Date: Mon, 10 May 2021 13:25:29 +0100 Message-Id: <20210510122548.28638-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the trans functions for m-nocp.decode all live in translate-vfp.inc.c; move them out into their own translation unit, translate-m-nocp.c. The trans_* functions here are pure code motion with no changes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-5-peter.maydell@linaro.org --- target/arm/translate-a32.h | 3 + target/arm/translate-m-nocp.c | 221 +++++++++++++++++++++++++++++++++ target/arm/translate.c | 1 - target/arm/translate-vfp.c.inc | 196 ----------------------------- target/arm/meson.build | 3 +- 5 files changed, 226 insertions(+), 198 deletions(-) create mode 100644 target/arm/translate-m-nocp.c -- 2.20.1 diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index c5d937b27e8..cb451f70a42 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -20,6 +20,9 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H +/* Prototypes for autogenerated disassembler functions */ +bool disas_m_nocp(DisasContext *dc, uint32_t insn); + void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); void arm_gen_condlabel(DisasContext *s); bool vfp_access_check(DisasContext *s); diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c new file mode 100644 index 00000000000..d47eb8e1535 --- /dev/null +++ b/target/arm/translate-m-nocp.c @@ -0,0 +1,221 @@ +/* + * ARM translation: M-profile NOCP special-case instructions + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "translate.h" +#include "translate-a32.h" + +#include "decode-m-nocp.c.inc" + +/* + * Decode VLLDM and VLSTM are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that vfp_access_check() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. + */ +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) +{ + TCGv_i32 fptr; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + + if (a->op) { + /* + * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not + * to take the IMPDEF option to make memory accesses to the stack + * slots that correspond to the D16-D31 registers (discarding + * read data and writing UNKNOWN values), so for us the T2 + * encoding behaves identically to the T1 encoding. + */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + } else { + /* + * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. + * This is currently architecturally impossible, but we add the + * check to stay in line with the pseudocode. Note that we must + * emit code for the UNDEF so it takes precedence over the NOCP. + */ + if (dc_isar_feature(aa32_simd_r32, s)) { + unallocated_encoding(s); + return true; + } + } + + /* + * If not secure, UNDEF. We must emit code for this + * rather than returning false so that this takes + * precedence over the m-nocp.decode NOCP fallback. + */ + if (!s->v8m_secure) { + unallocated_encoding(s); + return true; + } + /* If no fpu, NOP. */ + if (!dc_isar_feature(aa32_vfp, s)) { + return true; + } + + fptr = load_reg(s, a->rn); + if (a->l) { + gen_helper_v7m_vlldm(cpu_env, fptr); + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp = DISAS_UPDATE_EXIT; + return true; +} + +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) +{ + int btmreg, topreg; + TCGv_i64 zero; + TCGv_i32 aspen, sfpa; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + /* Before v8.1M, fall through in decode to NOCP check */ + return false; + } + + /* Explicitly UNDEF because this takes precedence over NOCP */ + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { + unallocated_encoding(s); + return true; + } + + if (!dc_isar_feature(aa32_vfp_simd, s)) { + /* NOP if we have neither FP nor MVE */ + return true; + } + + /* + * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no + * active floating point context so we must NOP (without doing + * any lazy state preservation or the NOCP check). + */ + aspen = load_cpu_field(v7m.fpccr[M_REG_S]); + sfpa = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_or_i32(sfpa, sfpa, aspen); + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); + + if (s->fp_excp_el != 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + topreg = a->vd + a->imm - 1; + btmreg = a->vd; + + /* Convert to Sreg numbers if the insn specified in Dregs */ + if (a->size == 3) { + topreg = topreg * 2 + 1; + btmreg *= 2; + } + + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { + /* UNPREDICTABLE: we choose to undef */ + unallocated_encoding(s); + return true; + } + + /* Silently ignore requests to clear D16-D31 if they don't exist */ + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { + topreg = 31; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* Zero the Sregs from btmreg to topreg inclusive. */ + zero = tcg_const_i64(0); + if (btmreg & 1) { + write_neon_element64(zero, btmreg >> 1, 1, MO_32); + btmreg++; + } + for (; btmreg + 1 <= topreg; btmreg += 2) { + write_neon_element64(zero, btmreg >> 1, 0, MO_64); + } + if (btmreg == topreg) { + write_neon_element64(zero, btmreg >> 1, 0, MO_32); + btmreg++; + } + assert(btmreg == topreg + 1); + /* TODO: when MVE is implemented, zero VPR here */ + return true; +} + +static bool trans_NOCP(DisasContext *s, arg_nocp *a) +{ + /* + * Handle M-profile early check for disabled coprocessor: + * all we need to do here is emit the NOCP exception if + * the coprocessor is disabled. Otherwise we return false + * and the real VFP/etc decode will handle the insn. + */ + assert(arm_dc_feature(s, ARM_FEATURE_M)); + + if (a->cp == 11) { + a->cp = 10; + } + if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && + (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) { + /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ + a->cp = 10; + } + + if (a->cp != 10) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), default_exception_el(s)); + return true; + } + + if (s->fp_excp_el != 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + return false; +} + +static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) +{ + /* This range needs a coprocessor check for v8.1M and later only */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + return trans_NOCP(s, a); +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 3c1d52279bc..46f6dfcf421 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1273,7 +1273,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) #define ARM_CP_RW_BIT (1 << 20) /* Include the VFP and Neon decoders */ -#include "decode-m-nocp.c.inc" #include "translate-vfp.c.inc" #include "translate-neon.c.inc" diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index c368ada877b..500492f02fb 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3800,202 +3800,6 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) return true; } -/* - * Decode VLLDM and VLSTM are nonstandard because: - * * if there is no FPU then these insns must NOP in - * Secure state and UNDEF in Nonsecure state - * * if there is an FPU then these insns do not have - * the usual behaviour that vfp_access_check() provides of - * being controlled by CPACR/NSACR enable bits or the - * lazy-stacking logic. - */ -static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) -{ - TCGv_i32 fptr; - - if (!arm_dc_feature(s, ARM_FEATURE_M) || - !arm_dc_feature(s, ARM_FEATURE_V8)) { - return false; - } - - if (a->op) { - /* - * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not - * to take the IMPDEF option to make memory accesses to the stack - * slots that correspond to the D16-D31 registers (discarding - * read data and writing UNKNOWN values), so for us the T2 - * encoding behaves identically to the T1 encoding. - */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; - } - } else { - /* - * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. - * This is currently architecturally impossible, but we add the - * check to stay in line with the pseudocode. Note that we must - * emit code for the UNDEF so it takes precedence over the NOCP. - */ - if (dc_isar_feature(aa32_simd_r32, s)) { - unallocated_encoding(s); - return true; - } - } - - /* - * If not secure, UNDEF. We must emit code for this - * rather than returning false so that this takes - * precedence over the m-nocp.decode NOCP fallback. - */ - if (!s->v8m_secure) { - unallocated_encoding(s); - return true; - } - /* If no fpu, NOP. */ - if (!dc_isar_feature(aa32_vfp, s)) { - return true; - } - - fptr = load_reg(s, a->rn); - if (a->l) { - gen_helper_v7m_vlldm(cpu_env, fptr); - } else { - gen_helper_v7m_vlstm(cpu_env, fptr); - } - tcg_temp_free_i32(fptr); - - /* End the TB, because we have updated FP control bits */ - s->base.is_jmp = DISAS_UPDATE_EXIT; - return true; -} - -static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) -{ - int btmreg, topreg; - TCGv_i64 zero; - TCGv_i32 aspen, sfpa; - - if (!dc_isar_feature(aa32_m_sec_state, s)) { - /* Before v8.1M, fall through in decode to NOCP check */ - return false; - } - - /* Explicitly UNDEF because this takes precedence over NOCP */ - if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { - unallocated_encoding(s); - return true; - } - - if (!dc_isar_feature(aa32_vfp_simd, s)) { - /* NOP if we have neither FP nor MVE */ - return true; - } - - /* - * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no - * active floating point context so we must NOP (without doing - * any lazy state preservation or the NOCP check). - */ - aspen = load_cpu_field(v7m.fpccr[M_REG_S]); - sfpa = load_cpu_field(v7m.control[M_REG_S]); - tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); - tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); - tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); - tcg_gen_or_i32(sfpa, sfpa, aspen); - arm_gen_condlabel(s); - tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); - - if (s->fp_excp_el != 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); - return true; - } - - topreg = a->vd + a->imm - 1; - btmreg = a->vd; - - /* Convert to Sreg numbers if the insn specified in Dregs */ - if (a->size == 3) { - topreg = topreg * 2 + 1; - btmreg *= 2; - } - - if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { - /* UNPREDICTABLE: we choose to undef */ - unallocated_encoding(s); - return true; - } - - /* Silently ignore requests to clear D16-D31 if they don't exist */ - if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { - topreg = 31; - } - - if (!vfp_access_check(s)) { - return true; - } - - /* Zero the Sregs from btmreg to topreg inclusive. */ - zero = tcg_const_i64(0); - if (btmreg & 1) { - write_neon_element64(zero, btmreg >> 1, 1, MO_32); - btmreg++; - } - for (; btmreg + 1 <= topreg; btmreg += 2) { - write_neon_element64(zero, btmreg >> 1, 0, MO_64); - } - if (btmreg == topreg) { - write_neon_element64(zero, btmreg >> 1, 0, MO_32); - btmreg++; - } - assert(btmreg == topreg + 1); - /* TODO: when MVE is implemented, zero VPR here */ - return true; -} - -static bool trans_NOCP(DisasContext *s, arg_nocp *a) -{ - /* - * Handle M-profile early check for disabled coprocessor: - * all we need to do here is emit the NOCP exception if - * the coprocessor is disabled. Otherwise we return false - * and the real VFP/etc decode will handle the insn. - */ - assert(arm_dc_feature(s, ARM_FEATURE_M)); - - if (a->cp == 11) { - a->cp = 10; - } - if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && - (a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) { - /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ - a->cp = 10; - } - - if (a->cp != 10) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), default_exception_el(s)); - return true; - } - - if (s->fp_excp_el != 0) { - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), s->fp_excp_el); - return true; - } - - return false; -} - -static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) -{ - /* This range needs a coprocessor check for v8.1M and later only */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { - return false; - } - return trans_NOCP(s, a); -} - static bool trans_VINS(DisasContext *s, arg_VINS *a) { TCGv_i32 rd, rm; diff --git a/target/arm/meson.build b/target/arm/meson.build index 15b936c1010..bbee1325bc4 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -5,7 +5,7 @@ gen = [ decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'), decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'), - decodetree.process('m-nocp.decode', extra_args: '--static-decode=disas_m_nocp'), + decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), @@ -26,6 +26,7 @@ arm_ss.add(files( 'op_helper.c', 'tlb_helper.c', 'translate.c', + 'translate-m-nocp.c', 'vec_helper.c', 'vfp_helper.c', 'cpu_tcg.c', From patchwork Mon May 10 12:25:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433108 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2793341jao; Mon, 10 May 2021 05:28:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwWLxpRRVdEzca4Yv7o1Clx8MWf1GZKew8GmX1+V4bstEaIv53aYuOq5APiqsPEIB26YamS X-Received: by 2002:ad4:5c68:: with SMTP id i8mr23171587qvh.53.1620649737377; Mon, 10 May 2021 05:28:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620649737; cv=none; d=google.com; s=arc-20160816; b=g3GWRiv7k5xKn6C8yH4rdfz5DKbEv4w+WrVmqvrx2t21P5iKYJDMiq4ndpEIDEnXvP je1SeFyUh2uxQM1K08T6toTJzRHgkrh+/i4odkeN7iOsDzmaN5DOxXmnPexATGG1ndIU cgz5z0Xo+LIrDg7hs+ozkhc5kLf1TspWtgE8mtMaKlhESwg/Z0Cwvm0eDbxMqnaMrolM 5EpWJzcWJLNyMY1rC5sWkJGRM09r0r+ZsT14VR0F52HHeMF6r1zYEcwvNkMwRiUesLfT QAUU9/MCxgGDd22pdBzCFbOsUXBvXOxBn82tmGck1PGF5hxyLCcfYgCH+v6FyGjUvGLi QD5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F/y3Y82w4iYTV52gBLNIxeh3URAI90qoJNd+VV3fQQQ=; b=HULELUe15tTcnseRK9le6DcmDECXX+sGqdgo1fSnEdhM/d4eTlK39Fgf/RafqcXzaW 8xI9JLS2jR9Bg8Y8gNj0DBIUZYLTNG4bmSvoUsAS7DVj0eSDv55x/WJz6B7ykxB8bvOM VWmYENcZu011+433OW4XzrpIqWbxEuSCdpGWU8bgVYh6qCfBoCZTG2o9FkdHrecUgm1A xaqRpvBJtdorirEoAEdkTxCMJehrIVJQgNMw8/4ODGxLk7Kfn1+gzsZ6sdXbq74K7ZvG uOfg9kRNggiZrfTCr76QH4iTXGXDKYatKHkUCUfOHV+VR6FAu9wwyzsbHyq9gXY3jIxP ophQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z2UCd05y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gy12si4719426qvb.191.2021.05.10.05.28.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:28:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z2UCd05y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg51s-0002zO-Lv for patch@linaro.org; Mon, 10 May 2021 08:28:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z2-0005ij-8e for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:00 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:39607) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yz-0003BJ-3H for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:59 -0400 Received: by mail-wr1-x430.google.com with SMTP id v12so16410741wrq.6 for ; Mon, 10 May 2021 05:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=F/y3Y82w4iYTV52gBLNIxeh3URAI90qoJNd+VV3fQQQ=; b=Z2UCd05yActMDhadWNFix+hksBPqUggmjdb0G8qWMNZ0rQ/OM+X48dfNv+TOG/8EU7 jnAIpTkAzJKKfZQ5btDTax2IDRx6lCR2cIJWKnm13pYWG474ETwGqg4DQ6HVOaY/928x tPCTAcNVgVyL3qpTXpnNH0yvhI+a3j9DRgH0yqyl6L5E4e9DZB4QO62VtPhLqLNRN/t/ AwSgcyfGr/Qyc4XS7Gis+Skyl3H5DD3NwbFP7PkeKzBx5G/t0sdNh4d7hgXL5jzGWRqE HG/TocFQemWTy5AZwP4QjQLjBK+MjOHl8OOxfCJk5ksHmz9w3gD0JV0WDcm3a8oMZ8Ro K//Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F/y3Y82w4iYTV52gBLNIxeh3URAI90qoJNd+VV3fQQQ=; b=EULARLTxd6Oyai/v1p8PBd1k1owjGB9lGKg7qKrLqao8MhdA522AIV7p+cXpaF4Jew o9ZYvyEI1PvaT2CAREn8AYmhBvei0cPp5i3iJyYpoYj6oCPeT5v72qmbP9qNdIOFgJzk oH3+j69fc11LQbUbya6kcDLvUwQfS/sk5BbosWFycYIZu2pWk66XcSl/aCbRIjWZCygs CV5RQ2F4VnC965LJqMy3a5vUuBoBWXOPCQW7VaYqzI91XVEkDRrcywtfNuooCOOMhslN cGI7E0mcPHlYVvpC8IfWA3tJnUs94ZhLGpLBca8bUudq//vccetjdtBfV4ifMFR7mkVn Omfg== X-Gm-Message-State: AOAM5335Y+kK07hDqg6k05k0Pk1+ACBZtCg5gkZQEtnQSLS3KqpltP76 M0fD52vCk0CipPN1Q5cMT3M9PWkeK48Ssw== X-Received: by 2002:a5d:45cb:: with SMTP id b11mr30692188wrs.343.1620649555799; Mon, 10 May 2021 05:25:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/26] target/arm: Move gen_aa32 functions to translate-a32.h Date: Mon, 10 May 2021 13:25:30 +0100 Message-Id: <20210510122548.28638-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the various gen_aa32* functions and macros out of translate.c and into translate-a32.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-6-peter.maydell@linaro.org --- target/arm/translate-a32.h | 53 ++++++++++++++++++++++++++++++++++++++ target/arm/translate.c | 51 ++++++++++++------------------------ 2 files changed, 69 insertions(+), 35 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index cb451f70a42..522aa83636a 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -57,4 +57,57 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) return tmp; } +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc); +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc); +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc); + +#define DO_GEN_LD(SUFF, OPC) \ + static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_ld_i32(s, val, a32, index, OPC); \ + } + +#define DO_GEN_ST(SUFF, OPC) \ + static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ + TCGv_i32 a32, int index) \ + { \ + gen_aa32_st_i32(s, val, a32, index, OPC); \ + } + +static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index) +{ + gen_aa32_ld_i64(s, val, a32, index, MO_Q); +} + +static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index) +{ + gen_aa32_st_i64(s, val, a32, index, MO_Q); +} + +DO_GEN_LD(8u, MO_UB) +DO_GEN_LD(16u, MO_UW) +DO_GEN_LD(32u, MO_UL) +DO_GEN_ST(8, MO_UB) +DO_GEN_ST(16, MO_UW) +DO_GEN_ST(32, MO_UL) + +#undef DO_GEN_LD +#undef DO_GEN_ST + #endif diff --git a/target/arm/translate.c b/target/arm/translate.c index 46f6dfcf421..5113cd2fea6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -899,24 +899,24 @@ static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) * Internal routines are used for NEON cases where the endianness * and/or alignment has already been taken into account and manipulated. */ -static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); tcg_temp_free(addr); } -static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr = gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); tcg_temp_free(addr); } -static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr = gen_aa32_addr(s, a32, opc); @@ -929,8 +929,8 @@ static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, tcg_temp_free(addr); } -static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index, MemOp opc) +void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, + TCGv_i32 a32, int index, MemOp opc) { TCGv addr = gen_aa32_addr(s, a32, opc); @@ -946,26 +946,26 @@ static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, tcg_temp_free(addr); } -static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } -static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc)); } -static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc)); } -static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, MemOp opc) +void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, + int index, MemOp opc) { gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc)); } @@ -984,25 +984,6 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, gen_aa32_st_i32(s, val, a32, index, OPC); \ } -static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index) -{ - gen_aa32_ld_i64(s, val, a32, index, MO_Q); -} - -static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, - TCGv_i32 a32, int index) -{ - gen_aa32_st_i64(s, val, a32, index, MO_Q); -} - -DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16u, MO_UW) -DO_GEN_LD(32u, MO_UL) -DO_GEN_ST(8, MO_UB) -DO_GEN_ST(16, MO_UW) -DO_GEN_ST(32, MO_UL) - static inline void gen_hvc(DisasContext *s, int imm16) { /* The pre HVC helper handles cases when HVC gets trapped From patchwork Mon May 10 12:25:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433120 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2798809jao; Mon, 10 May 2021 05:36:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4xqUs2SfT2cpAgQgPoy4g+fafaralYVeGBalaU+SIvQgiEzGdY4jQ1FVN9EqZjnZw1+kw X-Received: by 2002:ab0:2754:: with SMTP id c20mr6810405uap.18.1620650170377; Mon, 10 May 2021 05:36:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650170; cv=none; d=google.com; s=arc-20160816; b=pmh3NWR9F+tCYfZmpPNqF+xFN7w20y6iVnXrCMwrL677B05qgV6RFDlGrm3CvzMBWx YrD6XTo908pLzOBAdfWDOoAjY/hy2PKgY347MAr+asfrQBUJDvHK4IIFRhNXyY0lHL6M IKCE2J8bQt5cvi/ursUtcphrvH3SdAx18DeopBhBHTwFXMHVoTetxcZLZvYOUFK46IKJ AbxMdjfPjhcXgyVdxfsvHTgznTGtMAxCU+ubpw/WCd5dsKHtCjG+MXWuZ2d99keckUHd YJ5MZDqMlLDimdLTuJ7M7FzxspnMPs5wBkzxhwg7GXwKVHRw5v8gIurQ35MTrzPcjAHf 27cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=U9vKrM9bJI0jCQePxjhGf8sVA44g3YewHq3oiebDm8s=; b=drYjMbG0K3OdyX/myIsJwnsEsFvvNGjr+Rdbenr2vf+fuXhyJEduOrMR7ENnKYTDqK 8AN6KJ+fXmaLKOcq27UPmkRrQ7DILOAZ+eveOoDuTHUloANsAjoRgUHTO+mLo2qwr5Ic ukGUTiuc33APHLZnQoUvlfQNjP1P1YiVTDWKuTSfeLbCE1n/vwo6gNQLp87IkIEdbNE2 0oCtE5RdxMvPRnHNtVfILix3WnEWS3yyAJFqpY0pf/m4IrFdphwBemy3IncucTnE/rN8 bLXMxNQAeAkerjbZcZgmaDg+Dzp3iIq8DlvxluRydVGw5XlQA5r5m2DEeY97XuSfq/YQ 89UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Se1ER2SS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n14si6790245vsh.35.2021.05.10.05.36.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:36:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Se1ER2SS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg58r-00082A-OX for patch@linaro.org; Mon, 10 May 2021 08:36:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z1-0005gS-Hs for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:59 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43715) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4yz-0003Bb-Mc for qemu-devel@nongnu.org; Mon, 10 May 2021 08:25:59 -0400 Received: by mail-wr1-x42e.google.com with SMTP id s8so16431030wrw.10 for ; Mon, 10 May 2021 05:25:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=U9vKrM9bJI0jCQePxjhGf8sVA44g3YewHq3oiebDm8s=; b=Se1ER2SSWEapC9xPC5ew5OHUHeLunBBxDOyTxCO3bq5yjWQfn9jdAPbiqJastWKEPQ CbS7+sLynsBXMdrjQeJT9u1JqBdoS723B4mUa6vKflFDI3AUTIwLXs8uyaUyDik0sjz/ 7KgFwP/a7bKb9cjc+euhI6aJGGq0DPB4xpXVrPQb+vXGe74/5xxCBHnilow+CmWh/iNB hIVI4g6QWGgLFt8i71umNz+0lMod1Ow0bL3VaYuH7NaIoQWOQFeXN3wjrF33hpZz1bW8 yu0liS1HRUVeEXtd2XVVxCeGKimaO5YAhumJSwAcaxW4UaOcic/TG6xCV6nEwei+sWDW FJLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U9vKrM9bJI0jCQePxjhGf8sVA44g3YewHq3oiebDm8s=; b=EnatuDZCHjjeqnmX0YQU6uhQDPxVyTH+NUFBdwRiz1IowJIUefFyBH+ATMjnwZRUij ym3MJUfhsMG7/6y26qEJCC2NhZxE+0yFLUE59Nk+vVt2pZrmWk1EjhInMrh8UDyQfYrK wESHCC+B+gDoY7jk5d7ntjcHdHXLJ5ejaBUYqgqDvZ4fUxT0U+oyyEk5cnameAWInYm3 J6rNXX3AnnNWSWyrjF6iU3khqoKJPOdAW/oFCRo0Qeyo3wSYt5Gubx64Ffm9m1mDDMu+ AzN1EZ1wL7ILMtFLWHBKKKnBb9W13SXZnsTaBMBAqwSSTOoPgmVJpbE9afHwHNUFgHry tNdw== X-Gm-Message-State: AOAM531mPiM/QD0mLZokaF4p1QHfcN1HDCHlqh6vSAelAN9JomoECt6V a12kZX1GD0KlMMIK32rEG6k0WM7G5nIgcw== X-Received: by 2002:a5d:608a:: with SMTP id w10mr29657970wrt.371.1620649556489; Mon, 10 May 2021 05:25:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/26] target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.inc Date: Mon, 10 May 2021 13:25:31 +0100 Message-Id: <20210510122548.28638-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The functions vfp_load_reg32(), vfp_load_reg64(), vfp_store_reg32() and vfp_store_reg64() are used only in translate-vfp.c.inc. Move them to that file. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-7-peter.maydell@linaro.org --- target/arm/translate.c | 20 -------------------- target/arm/translate-vfp.c.inc | 20 ++++++++++++++++++++ 2 files changed, 20 insertions(+), 20 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5113cd2fea6..c8b9cedfcfd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1144,26 +1144,6 @@ static long vfp_reg_offset(bool dp, unsigned reg) } } -static inline void vfp_load_reg64(TCGv_i64 var, int reg) -{ - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); -} - -static inline void vfp_store_reg64(TCGv_i64 var, int reg) -{ - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); -} - -static inline void vfp_load_reg32(TCGv_i32 var, int reg) -{ - tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); -} - -static inline void vfp_store_reg32(TCGv_i32 var, int reg) -{ - tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); -} - void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) { long off = neon_element_offset(reg, ele, memop); diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 500492f02fb..1004d1fd095 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -30,6 +30,26 @@ #include "decode-vfp.c.inc" #include "decode-vfp-uncond.c.inc" +static inline void vfp_load_reg64(TCGv_i64 var, int reg) +{ + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); +} + +static inline void vfp_store_reg64(TCGv_i64 var, int reg) +{ + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); +} + +static inline void vfp_load_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + +static inline void vfp_store_reg32(TCGv_i32 var, int reg) +{ + tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); +} + /* * The imm8 encodes the sign bit, enough bits to represent an exponent in * the range 01....1xx to 10....0xx, and the most significant 4 bits of From patchwork Mon May 10 12:25:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433116 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2797059jao; Mon, 10 May 2021 05:33:48 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwg/tO5YmS8ROnpsWbBJjCGPcLIXU7Chw5wAgs2YMIshNX3iIt6qi7FJR9Jzi+FvEYtg1Tb X-Received: by 2002:ab0:7003:: with SMTP id k3mr19603558ual.67.1620650028510; Mon, 10 May 2021 05:33:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650028; cv=none; d=google.com; s=arc-20160816; b=XygxlTHZLtsINm1bDRQWehtn1KPjwSBLBx8vL1imwlRdhLglgzlYi09QaQzsoNMxPC qPSxJBGsA0XtHCH7Mu9Y6KjJQxjPeLmc70qGBw3PbhgIXtFHrEMymAtyeTpX55zy5mX8 mVRodw4GCCjGDmhtv8hSq1fmTYdN6InpUGOrtiurQAMzMCnhHT3Nm0WxaKxZx3RyQdCL NepWNgHi6wdVqi0K66zztry5rV6eERDRXatK2koiCEUK7qZF9/wL3PN/DNPQ5+k21NkP fkGK8BOk9GKhaEK0CQ/lh/eEx08gncG4ZxtmWqiuTS65Ye5Aj5p3YEnyL0myUwauOgsg rTCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+2+PC6B+zyTDO0jfQOvs3/TjHD3D5RvXNZJ5VbV7frc=; b=0ZAo26/sdBEtxIWjFUCvBGm9RkEm7QwkQH1DFXR0nowG3IQyC0lDcuGCO0fqh7jBQe RvG8aKupnhpd0zuJqUS54MbMX4GuFwmd5jj1bKpBqFIwUVfEnu4kQcLVtp6vZ7Z9Q7lf H++j8Hil5vjOCk5DBa83Gu3Bw0ISvW/RkoNlGpvZyXJIzYj94upbjzGDq+oYEv75Fywf uJ10M6jujqyOJdqwO4f8jzXifnMPrS6XyL3+BihDIzj72SoqoHYKmTv7HvRjZNc9BwMq jqyOV0DLU+X+cQ7RhiV32JPvdMrhfqjyvVRi2uzC4t8YKbnpsKivRBP8Lw9hjBWpQAT4 GLyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x7ck+QgH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n23si6568317vkk.57.2021.05.10.05.33.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:33:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x7ck+QgH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg56Z-0000NZ-RU for patch@linaro.org; Mon, 10 May 2021 08:33:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z2-0005jw-Ie for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:00 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:37605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z0-0003CM-Fo for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:00 -0400 Received: by mail-wr1-x434.google.com with SMTP id z6so16428907wrm.4 for ; Mon, 10 May 2021 05:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+2+PC6B+zyTDO0jfQOvs3/TjHD3D5RvXNZJ5VbV7frc=; b=x7ck+QgHJwwOW2gjQ8RtpEbEWgH/FWR77oJmd89/ujcpT0Ks4GiLLETYZK7TyFCtQJ HnxLRMgUM2JrfR8N3sc7gi7wPjfKXrXKNm3OEDXcAGrjGJ5L3kO1z3dUkHvQy6/ZP3Qs Bi9yP/ZCepDPJg5Dc2nJC26s7YbDeOwof/lGODN412GY9AAqBjIIupCP++LPM2TJI3tJ P5f5u3EMe3psnWT3fD+DmDfuynet8SvO7YVmoVMwaauHGZVSqW0FweGfkw7Pmlx/pBdQ YzoF0UpSXt/kMWjVhQfQKLnvmYBr83e71fbB9aA/QH3BxoH6Cwa0q0QAr+QIj+Es17VW og0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+2+PC6B+zyTDO0jfQOvs3/TjHD3D5RvXNZJ5VbV7frc=; b=UG1YZr3wSFEsH1Cu57nce7zPXxDuzsUTe4Ikl7EhoZw5JwdgySfil/h7m/Yn5MQJB0 L8qk05ZrZzlmmnBtP5a+SEHnNmhogyb9swiKIS5KyltVlAox5M1GjPqrKg8Kkj+jChhm ZYj3SLJJ0umrBt1y0EulPbHg9YeJggxcHEWFdRHBq1AZfwKA+OK9z3v+FqkRzEaqdfWx njssgvUK4c3R/AmW7VMzlN9TAQ1S6lvBWVXdw93xZGGvUBIW8AvM0HFlLamczjFOOMfY J6KJyBl99SED9kyyND0cRkJxeCHuEv6joLDLp6l/qSiTbqAeXR08etgNjYqHr38hfqRl 0XhA== X-Gm-Message-State: AOAM533z/ERE807zRrpd2t/pFlxiF1YKAvuGAO2hARwQhYicJV3aDiEs xs3XnVmJKU0XolsdN8j+BECYKGey4fCTBQ== X-Received: by 2002:a5d:498c:: with SMTP id r12mr30500084wrq.31.1620649557178; Mon, 10 May 2021 05:25:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/26] target/arm: Make functions used by translate-vfp global Date: Mon, 10 May 2021 13:25:32 +0100 Message-Id: <20210510122548.28638-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make the remaining functions which are needed by translate-vfp.c.inc global. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-8-peter.maydell@linaro.org --- target/arm/translate-a32.h | 18 ++++++++++++++++++ target/arm/translate.c | 25 ++++++++----------------- 2 files changed, 26 insertions(+), 17 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 522aa83636a..326cbafe996 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -30,6 +30,13 @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); +void gen_set_cpsr(TCGv_i32 var, uint32_t mask); +void gen_set_condexec(DisasContext *s); +void gen_set_pc_im(DisasContext *s, target_ulong val); +void gen_lookup_tb(DisasContext *s); +long vfp_reg_offset(bool dp, unsigned reg); +long neon_full_reg_offset(unsigned reg); static inline TCGv_i32 load_cpu_offset(int offset) { @@ -57,6 +64,8 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) return tmp; } +void store_reg(DisasContext *s, int reg, TCGv_i32 var); + void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc); void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, @@ -110,4 +119,13 @@ DO_GEN_ST(32, MO_UL) #undef DO_GEN_LD #undef DO_GEN_ST +#if defined(CONFIG_USER_ONLY) +#define IS_USER(s) 1 +#else +#define IS_USER(s) (s->user) +#endif + +/* Set NZCV flags from the high 4 bits of var. */ +#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) + #endif diff --git a/target/arm/translate.c b/target/arm/translate.c index c8b9cedfcfd..c83f2205b67 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -52,12 +52,6 @@ #include "translate.h" #include "translate-a32.h" -#if defined(CONFIG_USER_ONLY) -#define IS_USER(s) 1 -#else -#define IS_USER(s) (s->user) -#endif - /* These are TCG temporaries used only by the legacy iwMMXt decoder */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ @@ -209,7 +203,7 @@ void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) * This is used for load/store for which use of PC implies (literal), * or ADD that implies ADR. */ -static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) { TCGv_i32 tmp = tcg_temp_new_i32(); @@ -223,7 +217,7 @@ static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) /* Set a CPU register. The source must be a temporary and will be marked as dead. */ -static void store_reg(DisasContext *s, int reg, TCGv_i32 var) +void store_reg(DisasContext *s, int reg, TCGv_i32 var) { if (reg == 15) { /* In Thumb mode, we must ignore bit 0. @@ -264,15 +258,12 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 var) #define gen_sxtb16(var) gen_helper_sxtb16(var, var) #define gen_uxtb16(var) gen_helper_uxtb16(var, var) - -static inline void gen_set_cpsr(TCGv_i32 var, uint32_t mask) +void gen_set_cpsr(TCGv_i32 var, uint32_t mask) { TCGv_i32 tmp_mask = tcg_const_i32(mask); gen_helper_cpsr_write(cpu_env, var, tmp_mask); tcg_temp_free_i32(tmp_mask); } -/* Set NZCV flags from the high 4 bits of var. */ -#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) static void gen_exception_internal(int excp) { @@ -697,7 +688,7 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } -static inline void gen_set_condexec(DisasContext *s) +void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); @@ -707,7 +698,7 @@ static inline void gen_set_condexec(DisasContext *s) } } -static inline void gen_set_pc_im(DisasContext *s, target_ulong val) +void gen_set_pc_im(DisasContext *s, target_ulong val) { tcg_gen_movi_i32(cpu_R[15], val); } @@ -1074,7 +1065,7 @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, } /* Force a TB lookup after an instruction that changes the CPU state. */ -static inline void gen_lookup_tb(DisasContext *s) +void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->base.pc_next); s->base.is_jmp = DISAS_EXIT; @@ -1109,7 +1100,7 @@ static inline void gen_hlt(DisasContext *s, int imm) /* * Return the offset of a "full" NEON Dreg. */ -static long neon_full_reg_offset(unsigned reg) +long neon_full_reg_offset(unsigned reg) { return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); } @@ -1135,7 +1126,7 @@ static long neon_element_offset(int reg, int element, MemOp memop) } /* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ -static long vfp_reg_offset(bool dp, unsigned reg) +long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { return neon_element_offset(reg, 0, MO_64); From patchwork Mon May 10 12:25:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433114 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2796802jao; Mon, 10 May 2021 05:33:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzH4gYyEqYuAzWeTwzYST7dRwNw88Yp/zUR7V5WnzsxMMXXoFuDQH+Zw0ygxXJ9e+SreGfj X-Received: by 2002:a67:324e:: with SMTP id y75mr6200931vsy.26.1620650003106; Mon, 10 May 2021 05:33:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650003; cv=none; d=google.com; s=arc-20160816; b=gGPPacy5uwUTNrI10j5uVoRYT01GAAAMUnFi9vbkOyUyP/wKM8opObgEaxITBXEdr2 ax0CLMVT8NH1uSTr8VzoWwwTQERpyWdAbl6LMCF299kzhRQuMhrbBzvYk9dzuv+kBIFT wPic6vScgEGe/5f5V0stQOOxEVnYH48dDyD71BL6zDU+Tl9Q+QCoB6976inuDC0YzqYL yhE8KWr25w1bBGAZnfk3fnv3iix1NoPJulO4fP0AvAWDioLDoekj6rEuxeE/plpdLeu0 Mb5WZ8qg7+CNkRUlsK9L3RdPb6gWeXld0dmTkqOrLicOtCimHjIXYTx3WhtTawGzhUp3 M60Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KidqP9C++Nfg7TlswLUfpndbQ6x9/TKgLrZ9dvnXn4A=; b=QYY5HiUj8136TXigyQorDvjVxPhylpwvI01w7suAnQ8iaFgA3toa5g7I7MB21JCe34 w+xe0PrBhX7vQIaou9MSvbEd7jBbflyLk9LCRZlkUkpsdIWeXQTEyKvXC3QRfZTCtg8+ pfbnKUuDm7prz5YgiQ3o855rWssl4EjF7YP+tavjgcNZ2RpofXxNysJ8yk+8njU7oRo7 n0qjyVx5Lbc10kaO8Yem1xFVuPpX/ScbTalPCiTm1pe/VnbI8ol8EUp+4Obr/zCP+2Eg ZtwYsCbReZgk6f5c+YkfhwVCwfrAlfA06NwOT6Jhr0VdAt1/du/UBn99fasDnqVzQl88 h1Qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gDduUEIM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q1si5855432uar.92.2021.05.10.05.33.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:33:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gDduUEIM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg56A-0000cS-Du for patch@linaro.org; Mon, 10 May 2021 08:33:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z3-0005mm-8Q for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:01 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:35554) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z1-0003D3-3q for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:00 -0400 Received: by mail-wr1-x42e.google.com with SMTP id a4so16431072wrr.2 for ; Mon, 10 May 2021 05:25:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KidqP9C++Nfg7TlswLUfpndbQ6x9/TKgLrZ9dvnXn4A=; b=gDduUEIM0Ys6Qbe491E20vIX6/RcSGDu/qJhqm3TgR+/coGrB0VpUyxEUQpSPGknAV 3+UplfsjZkJsTcmM9gutR5V1wsPVCi7ONPuJZQ86AYS30gXV3r09x5ncuPB0C1MNw2w7 +6lhCSVlaqrsZ3eWb0RogJWcJ12jgPnDaVLPOMzOuSGwd21WGcm411MSm06HWznRH0NB 5qed39SZpcu/kaE03I0TPnjXlvBUVB9ZAFwxGamyJWgIDjboKpk5+y5vLe9qHc854C8/ /FRpBS45GXAPumAfEeiti65jkRbyYUf0i04BI+6dVs/LviYY0m8+A59UQIh/k5QxxN9G WqSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KidqP9C++Nfg7TlswLUfpndbQ6x9/TKgLrZ9dvnXn4A=; b=tqdYpbmpkPSqJzXxzCCOe4iZwbPBtgd/ICzRiJ3KmcJ1jkvcJbW0KISH134Q2vMsBz 4czkbYH7Vl80vmeTcj2dNLu356/yIQpzFVEb2FDCaqljW/kvpJIfWrUX9KjaQZ0+wPAL p1fB8X5t121IlqJ5TGn5gn7VGdh6m4gfu4zAfxzRlLlnjaYIhRtlYqPt13zi/T7q91LJ EDURJ0V2iOsrUg2q8LErKEZN520dd9U+S7+J08j/CApDvmHuOOluud14lSv8g49QZYH7 x/HkmDcN70jFMZ4DJoRSRDRbqO5YFeqNAY24L+v4Iaj8d5HPMrAKT4VFBRpTbm+6WEF4 MxoA== X-Gm-Message-State: AOAM533eSvuIXlRFSOhKfkCnFOpjrXZmePEK90kpranBo10R7WFj5qBx yJVkn+si7gumtDqwSVfHuZsToR05Ug7RGw== X-Received: by 2002:adf:f805:: with SMTP id s5mr30095932wrp.143.1620649557876; Mon, 10 May 2021 05:25:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/26] target/arm: Make translate-vfp.c.inc its own compilation unit Date: Mon, 10 May 2021 13:25:33 +0100 Message-Id: <20210510122548.28638-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch translate-vfp.c.inc from being #included into translate.c to being its own compilation unit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-9-peter.maydell@linaro.org --- target/arm/translate-a32.h | 2 ++ target/arm/{translate-vfp.c.inc => translate-vfp.c} | 12 +++++++----- target/arm/translate.c | 3 +-- target/arm/meson.build | 5 +++-- 4 files changed, 13 insertions(+), 9 deletions(-) rename target/arm/{translate-vfp.c.inc => translate-vfp.c} (99%) -- 2.20.1 diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 326cbafe996..e767366f694 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -22,6 +22,8 @@ /* Prototypes for autogenerated disassembler functions */ bool disas_m_nocp(DisasContext *dc, uint32_t insn); +bool disas_vfp(DisasContext *s, uint32_t insn); +bool disas_vfp_uncond(DisasContext *s, uint32_t insn); void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); void arm_gen_condlabel(DisasContext *s); diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c similarity index 99% rename from target/arm/translate-vfp.c.inc rename to target/arm/translate-vfp.c index 1004d1fd095..3da84f30a01 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c @@ -20,11 +20,13 @@ * License along with this library; if not, see . */ -/* - * This file is intended to be included from translate.c; it uses - * some macros and definitions provided by that file. - * It might be possible to convert it to a standalone .c file eventually. - */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "translate.h" +#include "translate-a32.h" /* Include the generated VFP decoder */ #include "decode-vfp.c.inc" diff --git a/target/arm/translate.c b/target/arm/translate.c index c83f2205b67..6aec494e81d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1224,8 +1224,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) #define ARM_CP_RW_BIT (1 << 20) -/* Include the VFP and Neon decoders */ -#include "translate-vfp.c.inc" +/* Include the Neon decoder */ #include "translate-neon.c.inc" static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) diff --git a/target/arm/meson.build b/target/arm/meson.build index bbee1325bc4..f6360f33f11 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -3,8 +3,8 @@ gen = [ decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'), decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'), decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), - decodetree.process('vfp.decode', extra_args: '--static-decode=disas_vfp'), - decodetree.process('vfp-uncond.decode', extra_args: '--static-decode=disas_vfp_uncond'), + decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), + decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), @@ -27,6 +27,7 @@ arm_ss.add(files( 'tlb_helper.c', 'translate.c', 'translate-m-nocp.c', + 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', 'cpu_tcg.c', From patchwork Mon May 10 12:25:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433124 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2801006jao; Mon, 10 May 2021 05:38:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzF/m2Mc5K9KnDJvuAqOsx/hxGitGiPUN6ztBqTuxtCwzrk/QocvXxVL7fakWIdLUzEPEMM X-Received: by 2002:a1f:3f11:: with SMTP id m17mr2583016vka.18.1620650335586; Mon, 10 May 2021 05:38:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650335; cv=none; d=google.com; s=arc-20160816; b=euRLwrBCp+CFM2eFhaLDCvYGyKD/+F+m5ABklggzumOFt55/R2Kor0DwzCFI8LfdUt z3mynvLX9X5liaHK5nZgwMkvHRWlWBid0wvH7wzGOtkSwEeFy1GueYEhiIF3xXUT2DM8 LCERhdomO6oQfrnkXwpUg1834qUdHHY2Pnx8USZLNBwq44swi5d3ZGs9K8wD1o4RMoNK ElskYbw2/fpzoorj5dSW2Ify7Yk6UbunofonZQ5LXFP4e03ZLgP0Hg9yrI8g+8XDA0LK 9quycg+aQeVuEjVr/k01iBjEWtdzUTBtU/AxDSUgkmmu249EPdsURxlCfPPBKFPRJBVf bxzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iAZOHv3Mz91JXANOFYbo1E1cKSNrhKoMABMJmJt4HPc=; b=lViDAmc8HmPFWNDw7H5/aar1/b08spbfsD92Y306DVPWObl//A0a2eeBw5izFZku/A cRBG0Fc+b1Ui2f2ssw1AUyUrTDFjeMhSDkEE+1zvAWb2mrUzeyLvayxejT8TiZXfMaf1 vBz05ryTXdHKFYQa6eNaijH5W8K26+9Yp25n4AEoKvXEswZBDWeQnwcT1iXMAHfJeLvF ygk2IO87oRfmrrdUvDy5YxPx5Kq1Yue2rk/vRMFJLgbfM/6NYrWK4GrpJGiZJCTVowWg bweNK12O6uJ+4ze8Dodrzto8kFlOo+kX+mvWSiCMQKrLU2xUk1Ks3HTKvqEpeix5nBas rtCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GN7cUI83; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w26si1816141vsi.269.2021.05.10.05.38.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:38:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GN7cUI83; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5BW-0005MB-V2 for patch@linaro.org; Mon, 10 May 2021 08:38:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z3-0005pB-Qt for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:01 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:37486) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z2-0003Di-5h for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:01 -0400 Received: by mail-wm1-x32d.google.com with SMTP id b11-20020a7bc24b0000b0290148da0694ffso11045369wmj.2 for ; Mon, 10 May 2021 05:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iAZOHv3Mz91JXANOFYbo1E1cKSNrhKoMABMJmJt4HPc=; b=GN7cUI83kVTTGcYnMJwRU5hadMV9brTUVyiFwC9RFzeMqFUFGh9QdXcHMHGMukSeBB mhQw5jjMDgBTlUCu2SvX6uxXyOdHfWut0c5rfPUjBh7y+Y1mrx4JCYQ0FbLUIzOtfvUp xWonzjzMYGCJflhzonoc6KW4S/B/jwKzPeToE7P7MCT5TkK+T8A4nmMt50KU0tEAQOfr NTUKEdOrWyFFudu/oEMgBp3C+mI2lEwgvWeQCfTKaKlqtP4oMBxBR3U05G3yDNVmKH7j 13MtCrSaRr1hmKpZMEL9+YrO89vvVp9IJVxpSFh1hsI5WJOQ+KWB65rOTSD7MxIV0zsf NGwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iAZOHv3Mz91JXANOFYbo1E1cKSNrhKoMABMJmJt4HPc=; b=V7rxxubolDkcNgA2IfFu1DOC4AUr9m+YuhbM/086PTJuca8v26bYsHzmOFFDtH8Q4E vasrgb3l6xR907XJoj7XRpewplBZd/yiYRmnZerVnCVp7bZ4C1Z9r9XT92V7+BBv9cLG z4YdmymeY8terAPKYEovj7wpy32cS3UfO/l+yXf6W5D/AGjIsIfHAqA58IabXTBrBgJV k7Rpp8e5J195/Zpr5uL59Yy2HzMRlXtsESCQQGc8Q3tp5Ysie9+oXsI41/WzH/ZvsSil X0STAqbhtN+M6QckTgNJMayb/uwazf/SxQFlBB94c5aa20CI72D4cNbayrHccxfrN1wJ 00tw== X-Gm-Message-State: AOAM533h/k1eOcFc/1H3V59e20i62wZ1QvelC/0qSu9U4YtITcdjaBYP 4NWBbmwe6zYVoEw9xJh+9VilnUh0KzHPqw== X-Received: by 2002:a7b:ca4b:: with SMTP id m11mr26309087wml.34.1620649558570; Mon, 10 May 2021 05:25:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/26] target/arm: Move vfp_reg_ptr() to translate-neon.c.inc Date: Mon, 10 May 2021 13:25:34 +0100 Message-Id: <20210510122548.28638-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The function vfp_reg_ptr() is used only in translate-neon.c.inc; move it there. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-10-peter.maydell@linaro.org --- target/arm/translate.c | 7 ------- target/arm/translate-neon.c.inc | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 6aec494e81d..095b5c509e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1215,13 +1215,6 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) } } -static TCGv_ptr vfp_reg_ptr(bool dp, int reg) -{ - TCGv_ptr ret = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); - return ret; -} - #define ARM_CP_RW_BIT (1 << 20) /* Include the Neon decoder */ diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index a02b8369a1d..73bf376ed32 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -60,6 +60,13 @@ static inline int neon_3same_fp_size(DisasContext *s, int x) #include "decode-neon-ls.c.inc" #include "decode-neon-shared.c.inc" +static TCGv_ptr vfp_reg_ptr(bool dp, int reg) +{ + TCGv_ptr ret = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); + return ret; +} + static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) { long offset = neon_element_offset(reg, ele, mop & MO_SIZE); From patchwork Mon May 10 12:25:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433115 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2796995jao; Mon, 10 May 2021 05:33:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyF0S7JFE+IP88ibxlg/ccOrxfy1aM+DHgjolsK7DaQQx9/MFgTdR60u0aKrIswaxGS+S1u X-Received: by 2002:a1f:2254:: with SMTP id i81mr3670032vki.5.1620650023970; Mon, 10 May 2021 05:33:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650023; cv=none; d=google.com; s=arc-20160816; b=JeX3hOtxGm3Sjbn9lyImdUwfaUI1T2pou9z7xhmYmp7+BCc/wSJgfHlTjBrmcEvcbc 6H2jUfCxtdVyg5vvRV8TevVcM02F+hML1/bUtJsvzumjmr46FUaMoDT44sYhJ4vbkbEM eKIM9pZZG57IpX6KelstBeKt408q8F89D8HWhvbQ5oXtFVPpgEmqDEHjwtQexEpumYaG 4NkWH8Slm7hsRo/y2YSeKlzM9YJmcZ79JinLqdJtfpydsT7cEcjn3mpj+i8B1BmXlKJU WB+214FqHYl2+D8SO1qLLkZMEUVOqfcQB7p+A+mmHVhMQAFPeLXFtV9hEDpQOdsfmol9 j++Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=npXNIiYkeWt5H2uCDWYRlI5CamdzntGn3P3qzZfcjMs=; b=bWb6Q1hR7Brci79l6V6WI5qK6PR7TBtg0PK9TLJdzXlsDIbApuYWU+asFuxJC0Hdol ogJMYri81234aYYbQgrvI82n7ViS6A67EfUn+uh2LZr71SGz+v9WUYQGoewZj3NvpmBl NYtYLjh+k6UZeXG6FzevBG3AFdLieQbT4J404mCB4KyvTP/PEMZcA1yo9qXcTVrHFP7w no5OZa8GyA1x5XNrBPHhRc6xl9BhxEp3EEzwlJcTQCrTO4HZCd6VM90IyXM00hD0f7Tp lOB8ag1yFDHS5OoxFcULqVmQz+/pnYXjj1Ad8GhOZBh5bOj752kqj2VCifi+G1WEIrx6 IFrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JRlLrIsR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d19si5645320uak.117.2021.05.10.05.33.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:33:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JRlLrIsR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg56V-0000AC-Ce for patch@linaro.org; Mon, 10 May 2021 08:33:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z4-0005qM-3y for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:02 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:47065) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z2-0003Dt-EY for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:01 -0400 Received: by mail-wr1-x432.google.com with SMTP id x5so16404065wrv.13 for ; Mon, 10 May 2021 05:25:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=npXNIiYkeWt5H2uCDWYRlI5CamdzntGn3P3qzZfcjMs=; b=JRlLrIsRKJGGbovlOGiY2o9e0uyuegJN96HmHlgCE3d4cwaKTu2zQKUaC8ed58kFKV DXF9lOvHu+E7WNTomksN3EQ0vAO+sl6CpuCaaFS72p57YzOnG+6HUPzMptCtbBLzE/IY ulS0M3u8g3VA5n9xCloJlhS33GmnWrEutk2U6z3SU8m+844VTtakXYceUnK8U3QyrYmm 5+FQmnHawp7NwXcYm9L29dmdPrumJbsYU/M/f/MgMju5lOMeDZaD4EEl+83x+4I3VtZ6 U4pG8EentSMZeJx8x6Ff6kIv92PXyJPBnrshHXhSFWAxS30sEXToMO/XAafux8euQitU DWYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=npXNIiYkeWt5H2uCDWYRlI5CamdzntGn3P3qzZfcjMs=; b=AgeE0NZtRV5ZVN/qJIf7OGaNtq0t9mdjxH8MWb5EoEUvC4o7Z14C+6rB4g5ytdbacC O1RVHzpyvGQbd1/V5CwUA43rvg8IaXi8hutJ9P4K91i9URK+K57DNTfeSxtXeuObA8lF unsyujvVpt3wwIkG+WdXUSq6Xnf7iAVFnYPmtyXDhkecoUTEGPFh3CdBVVVU/J7HdUuL Y74MKfQ6075KUdNeREtSDmtNDETsxpqQ4FPkHVFJEfIPkK4L+Dv2HxNQAqFXahfBBWNc TLTf2FrT6AIXDOmiXzvZq5dqu22zylutjHuqEYBzD5V/yBtbgLJctDHO7s90JP+zB3/d eSZA== X-Gm-Message-State: AOAM532KUoazH+4KDQGEM38+ODgdkBzAjgAhTgoIDZ6UxNbMbkHifVDS srNtv40VJe4rHk293CvmgpfTXCzjNNL4wQ== X-Received: by 2002:adf:dcc5:: with SMTP id x5mr31003477wrm.1.1620649559162; Mon, 10 May 2021 05:25:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/26] target/arm: Delete unused typedef Date: Mon, 10 May 2021 13:25:35 +0100 Message-Id: <20210510122548.28638-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The VFPGenFixPointFn typedef is unused; delete it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210430132740.10391-11-peter.maydell@linaro.org --- target/arm/translate.c | 2 -- 1 file changed, 2 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 095b5c509e1..58cb3e8aafe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -69,8 +69,6 @@ static const char * const regnames[] = /* Function prototypes for gen_ functions calling Neon helpers. */ typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32, TCGv_i32); -/* Function prototypes for gen_ functions for fix point conversions */ -typedef void VFPGenFixPointFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); /* initialize TCG globals. */ void arm_translate_init(void) From patchwork Mon May 10 12:25:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433117 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2798181jao; Mon, 10 May 2021 05:35:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7PgkQhRh5EB1h9mZVEr6ldkcP+utc5ZFaVEb3XvuBoGhXsoL74KgHL36c+z6h2n7W1mKV X-Received: by 2002:a9f:25a1:: with SMTP id 30mr19011559uaf.109.1620650121207; Mon, 10 May 2021 05:35:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650121; cv=none; d=google.com; s=arc-20160816; b=S5bH5z0ZrEZJ2RDogI5SWARqcjCJ78H5onKqbED4coI5d3JbQRm+oo8mfv2TdYm94x 1mV6bxzsS+Wfyq3kkKW1YkujwxxwGGpO37eUC1ZNoN89KcbxLwVSCsRy15qwyeMMyB2u m1d/04rHvQRyitIFmwLxR3Z7QMa1MPMLbZoWCAuAI4DhHURb8bVMcydcgeaHri7b4ZPu EIfryfptmv7evrU8CTqN/Kvp0SmP6WuMiHUug26Hv+BmtXwbwi/r/ttMOs2jXl9Lgbeq 2cXXh5pL7IUBtNU5bmQ8694JDiHQpgqiJLRyKIb/sxICSxHANy1U7rdg3hf9KZ3qHwzc aTrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9vWwmItMfiJpiaUNbqSiAbeORN9VsWlu2JR+tQ7wf/s=; b=gt2HeNJlLVSE45mUug5J2bX1tQz2ihKrZJVB9gfD0LEAIOOVwwqom2w0OcBqQS73+W IVavYjqtLY3kJqHzndIcqVLyckxkd0OTJ3hy2QWvA6U0g2EBe1owHM6QK3g72ikuzWjz YksKCtpCx6TDDQ1owDRp2w4Vwv2gQDHobKbU/JEls8/RxDUY0Gox9cNh9yaSHuH8Y2fk KhtNAbgomqQhxd/2gtQECi5NraBhXj8IqX5DaabYwhDmyHNYS5P9xpGos6BhCs8vA5v/ ouWe4mEfKMMrKwYe5tQqqfJD20Ld5sM4Ew6VvOdzcWAQwKmhk4+9HqAMSPsyjCrSgt7O wJyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7GIEp7x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r16si6063829vsn.313.2021.05.10.05.35.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:35:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7GIEp7x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg584-0005oi-It for patch@linaro.org; Mon, 10 May 2021 08:35:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z5-0005tq-0l for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:03 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:39602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z3-0003E5-62 for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:02 -0400 Received: by mail-wr1-x42a.google.com with SMTP id v12so16410937wrq.6 for ; Mon, 10 May 2021 05:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9vWwmItMfiJpiaUNbqSiAbeORN9VsWlu2JR+tQ7wf/s=; b=L7GIEp7xKpTDgxif6xZU5+L7nBOJJ/zAEEzJw2AXhOub8w4JY4BBCg48mmTMxayJsT 8Xgeq6hxvPnF0uxRP642rGVIEYAwF0Zs9UVw1/GwfDOJy6bE2LVANsa5+2KxiN8vloXX 2KLkfoj+dIOXZSiTfomEfI0pG3pjNEkED5UNMf2U2wnL5ovAyVfry34ilKdEMQgqe2Be k0ykKSant6gz6x3xkhkYdTgFofbIaLSIcacD78fVIAt02D9phd+6QkAct39bgA7UN5sx lMFKa2Wm38oG3863FTFu6r4n2ho13D/4QsMR42RyUwQSJRAShHYHlENEtSpMQLlfqNiK bh1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9vWwmItMfiJpiaUNbqSiAbeORN9VsWlu2JR+tQ7wf/s=; b=omSTusacsIC96Z2yrZfd1++K+sJrMKwOInS8orq1TRDRGgs7N5+DxQyii/XKvLhR0G /DlQlVOQaygZyngyVlWEd5yIaMxOIN5Y7MDze79U0jMRiHDboeTt2ZugKnH/Exynmak5 XGRpdimOBWmlonXWxXRYi1xphJAN8asB5Kmnl3b1DnBKC4FeU3+DFbVRu08cP9UwmFmQ SWKhiz8zbq81/+vG9M4FNO8VzL03Ek3njo0GFlMy4Q9UA2UcaFiJFqwWnfx+H8ptEoxQ 2qR8B0jFGG4A4TRSbzb8w/x+beDAyKyVsej/c06QhPwEFG2BkLkX+6JGn1bcEaZ6smqU qWrQ== X-Gm-Message-State: AOAM531HR2dI9I1Z+HgHtCNTSavSF3UfjkEFIkE2KBr2W25cfa0s2h1e X9XE45B+WkMuyEEzbvsavZ0AeP1v4fxF3Q== X-Received: by 2002:a5d:6088:: with SMTP id w8mr29639823wrt.424.1620649559861; Mon, 10 May 2021 05:25:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:25:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/26] target/arm: Move NeonGenThreeOpEnvFn typedef to translate.h Date: Mon, 10 May 2021 13:25:36 +0100 Message-Id: <20210510122548.28638-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the NeonGenThreeOpEnvFn typedef to translate.h together with the other similar typedefs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210430132740.10391-12-peter.maydell@linaro.org --- target/arm/translate.h | 2 ++ target/arm/translate.c | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.h b/target/arm/translate.h index 8130a3be29d..12c28b0d32c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -409,6 +409,8 @@ typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); +typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, + TCGv_i32, TCGv_i32); typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); diff --git a/target/arm/translate.c b/target/arm/translate.c index 58cb3e8aafe..7ff0425c752 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -66,9 +66,6 @@ static const char * const regnames[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; -/* Function prototypes for gen_ functions calling Neon helpers. */ -typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, - TCGv_i32, TCGv_i32); /* initialize TCG globals. */ void arm_translate_init(void) From patchwork Mon May 10 12:25:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433118 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2798245jao; Mon, 10 May 2021 05:35:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyqGbpiNIJfanzB9bsDj2lW7nUeq5Zk+qz+8NKAizuDttRbl5BdYd8m6k1pH+DTSxn+Gcp/ X-Received: by 2002:a67:1984:: with SMTP id 126mr19049137vsz.46.1620650125978; Mon, 10 May 2021 05:35:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650125; cv=none; d=google.com; s=arc-20160816; b=gIMdsNtnftckFuqR3EINTBEiK5Q5+2cNpXZtTg4eGlmpmW9DExrlwTZlozDk+xqQOr TS2o013mn0Dj8HKNaNJfAWtdZH+7E/bp3CX8HqzDk0x4Souf+yhHjhHP3tjke2He4GbV N4CZwef3lC2xB597dd/WBiqWsvNVmEQ7Co0oUREsapPprRB/FgiLeAsJzQogVfv9Wiya LE4198rRXhz1WC5fKMzQV1zW2RbpiJB9Phl+NGPURq7bJ9Ecy+0auRxWXNl/3qTwXgZ0 0A19PrB39F393aUI8WOqLdITXSvTJ+inKvg1i454eKb+sXCIPAVkRV0HlUDbXU2c1w6M RYzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YHOfv/PBxmnVIlFlC3MHXDqVhwWqJxzCamVnqIwXV4Y=; b=vKzpMyFu8bv2fOXc6Da0DPJn+UENOCVj6fTLnno/bZ5Uy+etNgE6KqRZQbOHPt3C6D fimQYaf1xjR3fEYwRsUwfxoUjrSGdoOfrTR7pv+6riTBLKdiRsSm4Akz8Ylbk9e9kJdl ClLBSnx8/0W2OvUOZf5x0UO+I2SGj5TGdccvVKk3+o7ydVFAS4+hQGD55Gz34sY2/dW8 tI6bAVruk2HmWQapX3Mmg/5pLUt0CGoWkyVDYN3uAnFmMKdnqdLbq83u30TBQggVbm5i eGxnKwLPtz4lcspecrOJY7sI6tFrDOMI8ip01qKySs0OL4tdo3/q/DuMxlvvIsD/2ei9 LEcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GRB0ym43; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b196si5443873vsd.101.2021.05.10.05.35.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:35:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GRB0ym43; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40344 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg589-00065f-Cn for patch@linaro.org; Mon, 10 May 2021 08:35:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z6-0005zt-IC for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:04 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:34422) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z3-0003EF-Pd for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:04 -0400 Received: by mail-wr1-x432.google.com with SMTP id t18so16432074wry.1 for ; Mon, 10 May 2021 05:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YHOfv/PBxmnVIlFlC3MHXDqVhwWqJxzCamVnqIwXV4Y=; b=GRB0ym43etGNDWQHugaw3JdHAm2dC532LMyiK+sdqwbBDLMcOXQgMeL4Zma46zPS3M S27yyrD0VfxBX8BRoEi6ASOtd6w9t7DTqkPN3gswSZBiIf1oPvZnlX2vGMqsltaiXuDC 9tYErKkHOw2xc031c/cL8tQSd+jQl5vpA8sOOmxLT02rAYb9Z2Rpk8XUCUO1bLMGnWHk UUVkJZD9Elfg2WrdIzw9RP/vtkygMmpEBQyArTipMqsf2+LptiQdeFLRlp+Po2oEHDDk mmq6W+iANEsP++RlODUPGzn+OpkrIzeow9VLgk6dbH4EJH1Z8BvG7XXVDWtjEtNejrLV 5iYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YHOfv/PBxmnVIlFlC3MHXDqVhwWqJxzCamVnqIwXV4Y=; b=oiWuVWNBjjvOO9FI2hgqoFxz8qYuwGe9nJP0JbE7ttMkgWCCwNgFpSJgQ86UzKdrly bSv53pFlhR8OWw0X2O+NA5MFpsNtuyIjskLhZUKDpsvSUwsPrW5LzknFtCqo2qGKQDm4 Wbd953SpRb+Qb5HWmSxNsCwtsw2UY6mLNoZR7kXAlxzAC+61Wpr6KJhq73GYPcN8RS/Q 7+cAcDGYjJaQSQtVCIFjEM1uGtxZkLzLbs1fPp7iYS6tRE7934fgNNDZ4yZpmzlMelOk w7uB8yUV6Z2NzVB/f77L/ndyGP7Ww2HY+3675MCtESYHTaifBxo5KnRIBRhGSYQhSx4J raNw== X-Gm-Message-State: AOAM533DT+oy+5Q4SILGqSGbgsWOUqF/ThxdYj74qWEnQ54q67+SK+rd pGiLtlGDaEyTaTSIOj/G/TR5N52/HTmciQ== X-Received: by 2002:adf:e98c:: with SMTP id h12mr29718179wrm.314.1620649560521; Mon, 10 May 2021 05:26:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.25.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/26] target/arm: Make functions used by translate-neon global Date: Mon, 10 May 2021 13:25:37 +0100 Message-Id: <20210510122548.28638-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make the remaining functions needed by the translate-neon code global. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-13-peter.maydell@linaro.org --- target/arm/translate-a32.h | 8 ++++++++ target/arm/translate.c | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index e767366f694..3ddb76b76b5 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -39,6 +39,8 @@ void gen_set_pc_im(DisasContext *s, target_ulong val); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); +long neon_element_offset(int reg, int element, MemOp memop); +void gen_rev16(TCGv_i32 dest, TCGv_i32 var); static inline TCGv_i32 load_cpu_offset(int offset) { @@ -130,4 +132,10 @@ DO_GEN_ST(32, MO_UL) /* Set NZCV flags from the high 4 bits of var. */ #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) +/* Swap low and high halfwords. */ +static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) +{ + tcg_gen_rotri_i32(dest, var, 16); +} + #endif diff --git a/target/arm/translate.c b/target/arm/translate.c index 7ff0425c752..18de16ebd0a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -325,7 +325,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) +void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 mask = tcg_const_i32(0x00ff00ff); @@ -346,12 +346,6 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) tcg_gen_ext16s_i32(dest, var); } -/* Swap low and high halfwords. */ -static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) -{ - tcg_gen_rotri_i32(dest, var, 16); -} - /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. tmp = (t0 ^ t1) & 0x8000; t0 &= ~0x8000; @@ -1104,7 +1098,7 @@ long neon_full_reg_offset(unsigned reg) * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, * where 0 is the least significant end of the register. */ -static long neon_element_offset(int reg, int element, MemOp memop) +long neon_element_offset(int reg, int element, MemOp memop) { int element_size = 1 << (memop & MO_SIZE); int ofs = element * element_size; From patchwork Mon May 10 12:25:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433119 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2798808jao; Mon, 10 May 2021 05:36:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3Va981jsga4AgaCW6mdQAfUq8101AjhTmUwrpXeGUqy1+p3FmjFrIEdXCSyg8axPnt/KI X-Received: by 2002:ab0:3b0d:: with SMTP id n13mr1985314uaw.94.1620650170411; Mon, 10 May 2021 05:36:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650170; cv=none; d=google.com; s=arc-20160816; b=e6bXh1xtjz4kLR6bzm27qN+LxmaTEKugNn03tYb21z6tUlMNanb6Z8O/JHodyHKRaP 5w5IXeRRNw6+QqVVLEFsGvFzbEL+JrI4HBjMTr6AjhJANa6dWRova9EXNJ8NomVE0H3Z nW+63CrvEKQrgexhjFLeRmYUoSWb/2xc/iE4r+M2ZhPuvkryrJEWdp0coTjVtHKTgPDE wFpSbhAR3jmn18y0Kbld3EGwoDv6pQ1yrtgSmIb0COdW9IAtOkC4gii+Gjm6qFIIuPiC i0MdzZRIMelxIWKmCUA/OhSWuuToBLrmPFsQS53v1pKKABc7/T4WS7Yif7wBPnScwZDP NQmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FCYtPBdqiR2hai1rH40sFtaLEHo/VB2Vh1+jPJDC+nE=; b=CttcK1DCvkG7CjA855wzoGjtbz18G4+eFDjdPnZOjG8thBTKL/a8ApnKUn0pnmSrHC wQPHnnnhEKcx6aVPJgHFSAPzIlwyHrEmmapKXe7DasFrELFmVVkFmBiaixGVLWnKh2Xk 5x4z3RQ1lw93NotuFN3sSFQ6BixSiKl266M9Yk0Kv81eH8TxcCJyQRi/E8txYgG9mIwS +39Pn/FWLoceLfxZ+PoEDbSWUUpOdyHrAapOMag3zQNI174CIdDa9WmY2Dv+v96Kq6SQ NnE1MgBZxngEINmjIDmRMTHKGo5PN7HVWyLQazgDdLT1Ern90yGh1v7O3dWmIz6MZ/Ew 0ilQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NGhjM/ze"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v23si6852918vsd.23.2021.05.10.05.36.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:36:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="NGhjM/ze"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg58r-0006Ka-N6 for patch@linaro.org; Mon, 10 May 2021 08:36:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z7-000618-1B for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:05 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:35562) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z4-0003ES-I3 for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:04 -0400 Received: by mail-wr1-x436.google.com with SMTP id a4so16431242wrr.2 for ; Mon, 10 May 2021 05:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FCYtPBdqiR2hai1rH40sFtaLEHo/VB2Vh1+jPJDC+nE=; b=NGhjM/zegVyZ6J1N/ymapXRb8YW5wlMtSTNcjrEZYtJvy+MlMkAi9NDwFvpzpZzNcF SQHo2sgc4n4aaun3piHbCyUHjn/ztmsDXR5ffW0K2gT9VDE2dwLh84TBmeXne76RYu// q+P9jID8plWRMtwmD91xIRjmFKYldYApXgkjBr+PMug66OXMVPiJFoA9IetmKqeC4tkV QSvIIY76jjLfIXXhe2lwAA69wSXJZrAAsYIRpCTWaj/HKb7bCSCk4GCgEHI1BJcS1SK2 6yLHVDygoOiGxpOkTXvwtvLJCMEyIv9j/IRjs2JLdDDxYyMa9eEnW1qrDksz2DDVZ1BG vY3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FCYtPBdqiR2hai1rH40sFtaLEHo/VB2Vh1+jPJDC+nE=; b=Dg6y27vntAVZAa+F7mPmrkJ6qw0urwgR3Mtj1r5g9Z07B72qL23GK4+tiHhlT+CgZ7 cYMYZC5Y8tlrLXvH/JG0qEUc7oF0hij+KL/pOXhPpzNMy4XIPPpBJ4RvQCU1EBxNimSi 9JpbQVvZTrO/Yn/5kOEsxyjE9GgE3ee2ESKwEVpj8gyHp3ZHtuoE8l3cMllP8IgXuMLH SPg+c4Vy4jxu4dQsKZ2DOod/bSwHfq2DBBvgRvU3Fk10yWfLM3AKmsEuO+sdukbGnEvn +oIW007ripaXvZxTubQxq1wAUGI73PajbSgXWq+O2B6QnsMX0x5OTSf5q0GlV3VCuPtT tVRw== X-Gm-Message-State: AOAM5309tsS8sbSvEYbY1IaynlEc2aGU4VzEqAabf0td9Q9zjDMay1EB gvbbiXSZPA9S1rCE1bjquMa1UaH/q5m2eQ== X-Received: by 2002:a5d:6402:: with SMTP id z2mr30037182wru.7.1620649561150; Mon, 10 May 2021 05:26:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/26] target/arm: Make translate-neon.c.inc its own compilation unit Date: Mon, 10 May 2021 13:25:38 +0100 Message-Id: <20210510122548.28638-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch translate-neon.c.inc from being #included into translate.c to being its own compilation unit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20210430132740.10391-14-peter.maydell@linaro.org --- target/arm/translate-a32.h | 3 +++ .../arm/{translate-neon.c.inc => translate-neon.c} | 12 +++++++----- target/arm/translate.c | 3 --- target/arm/meson.build | 7 ++++--- 4 files changed, 14 insertions(+), 11 deletions(-) rename target/arm/{translate-neon.c.inc => translate-neon.c} (99%) -- 2.20.1 diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 3ddb76b76b5..c997f4e3216 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -24,6 +24,9 @@ bool disas_m_nocp(DisasContext *dc, uint32_t insn); bool disas_vfp(DisasContext *s, uint32_t insn); bool disas_vfp_uncond(DisasContext *s, uint32_t insn); +bool disas_neon_dp(DisasContext *s, uint32_t insn); +bool disas_neon_ls(DisasContext *s, uint32_t insn); +bool disas_neon_shared(DisasContext *s, uint32_t insn); void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); void arm_gen_condlabel(DisasContext *s); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c similarity index 99% rename from target/arm/translate-neon.c.inc rename to target/arm/translate-neon.c index 73bf376ed32..658bd275dac 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c @@ -20,11 +20,13 @@ * License along with this library; if not, see . */ -/* - * This file is intended to be included from translate.c; it uses - * some macros and definitions provided by that file. - * It might be possible to convert it to a standalone .c file eventually. - */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "translate.h" +#include "translate-a32.h" static inline int plus1(DisasContext *s, int x) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 18de16ebd0a..455352bcf60 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1206,9 +1206,6 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) #define ARM_CP_RW_BIT (1 << 20) -/* Include the Neon decoder */ -#include "translate-neon.c.inc" - static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) { tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); diff --git a/target/arm/meson.build b/target/arm/meson.build index f6360f33f11..5bfaf43b500 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,8 +1,8 @@ gen = [ decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), - decodetree.process('neon-shared.decode', extra_args: '--static-decode=disas_neon_shared'), - decodetree.process('neon-dp.decode', extra_args: '--static-decode=disas_neon_dp'), - decodetree.process('neon-ls.decode', extra_args: '--static-decode=disas_neon_ls'), + decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), + decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), + decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), @@ -27,6 +27,7 @@ arm_ss.add(files( 'tlb_helper.c', 'translate.c', 'translate-m-nocp.c', + 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', From patchwork Mon May 10 12:25:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433121 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2799935jao; Mon, 10 May 2021 05:37:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwPKC96rrliixrZnoKAtMy5j8sW1Av2l7YKF0wV3W3muEDtw/0mc1+JUNUs1TsSrKyu7f6h X-Received: by 2002:a67:7711:: with SMTP id s17mr19237086vsc.37.1620650251996; Mon, 10 May 2021 05:37:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650251; cv=none; d=google.com; s=arc-20160816; b=Pq5YH3yx9DKI2tty08RFc6fT5aR86V8SqCSAbdD1puv26ZHes2Y0W4geOyJdb4zqRG 2/lEz3iuxjdEUTMhhJWcMFGO6RSTlu/ehDsyIc2RwJLZCGUGTwbOB07B6GxDYh4q5n1k WgmTZQ96EANkJtiBAn7esWaNb6e1NBVVhLJze1JtLnqbAtKeqnA8GIvojABxxtQ+UIwS 03WGpwBQd91qm0qQnW71V8IsXKDqFAHeWtVxMN8Z3gjYVvrYO9bIVwpq6eok861fEx/m d65YW/paDx5d2Gy9ySrRjmLZ63yQgCOHJFhKHh2kIhiiKH0w0froa0nxzPN2saYqwnnO YWYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JL7HH1O51sX2ceg9tbB6Rc1ZArs66XI/7qZrVHYeGK8=; b=C0YBct1XbPZ0icjPdbZFVvw/SlendGGkhup1Hl6jMM60MaCn104lvqXKyN5DUioLGE wbqHeo3RxzOri9li8L7/W01hotNSG/5/QG7e1IapLrVsbT54SN6JPY5DZBM1giw8sDGc HVXWcgI16+CCiM4qh6V6T/VZPQLWaye6s4HxPjngFZxqgahlucj0IdOOa2Vw1Ytdqrjq lCvuFeEjowmZasxADhnP1AhHjrQQSDBVHKvq93ZjVW767qac4Q6tJRFofi7Buzp4YnSR kmw+NlH/DahmpgetFKJKJfub28NDomNff13MLhH6EdN8V74FURh2jojXzDTSWuJXaiQ/ 44GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OXA5Mh3H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q99si307062uaq.150.2021.05.10.05.37.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:37:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OXA5Mh3H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48990 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5AB-0003OU-BX for patch@linaro.org; Mon, 10 May 2021 08:37:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37622) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z8-000673-Eq for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:06 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:36655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z5-0003FH-6c for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:06 -0400 Received: by mail-wr1-x430.google.com with SMTP id m9so16437496wrx.3 for ; Mon, 10 May 2021 05:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JL7HH1O51sX2ceg9tbB6Rc1ZArs66XI/7qZrVHYeGK8=; b=OXA5Mh3Hm41Dn5xwmqhzHyxWGmDVLG26MccGUbL70LwtX+UhyCG8KZ6uCeLRDA+cK4 FEaXBKvIGfE0lI7X3+GsOPoKewjX//Oh6F5s9Xw3+dX9u4AzxsCNgMuxlgqSUzJYl2+E rN2vkrL/PCz9mQSmmzboYOD/+lMQLPXbwDNeY3tAtusT6Tkbno0sfCtDBggelXAtyQvE M4YIJa/UBknLDAw8VAf67Kmj7/U/36CQJXLyqMs1KObk2FVMgCxR1JG1uQEn33YFPY3l AZdZqbAI9WsAiVBX9xvZpVSLeopsOPzx9ON/sPurJn6tlWbWCCuLH5P1u+xk/yoznYCr jzYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JL7HH1O51sX2ceg9tbB6Rc1ZArs66XI/7qZrVHYeGK8=; b=Ubz2OfBlS81ExCM5IrpSFnruUClc26vIK/8TIG6OxQ9yNU7z+S5Eh+nzNPbmBjTd7d qkMKMwp5PFvfSrw7NXEjy9nGZ8IdryI+mmoAlOj63L53rDOtAGu6RlMST7iVsR952SmK u5j8mXceA5UrqjbKW6a2LXozJ3qVQhQLcwOhagU8TGeruN1LAqaKN0NDc6NSR5bTWXyb neUFyq83ERHATsavfV+2P43demkng3u4v3SzWdZXWA/Q6w6Cpeeipk6/C1b8FWvcvxBm ihM9SMC8tRrnWY1b8QBk5gan7zn7UDDrtyrsbSuIBwGgL6S+PXT/9OrE6K+JZtsXUBIG AzLg== X-Gm-Message-State: AOAM530cwteT7ViB8hpiM7q0i7oemsD/ps2fQhtxgA62SPp2E2CHqMTD /50e2AT040lOb5qc0hLmo7qlOULH/PWL5g== X-Received: by 2002:a05:6000:108f:: with SMTP id y15mr31362080wrw.115.1620649561878; Mon, 10 May 2021 05:26:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/26] target/arm: Make WFI a NOP for userspace emulators Date: Mon, 10 May 2021 13:25:39 +0100 Message-Id: <20210510122548.28638-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The WFI insn is not system-mode only, though it doesn't usually make a huge amount of sense for userspace code to execute it. Currently if you try it in qemu-arm then the helper function will raise an EXCP_HLT exception, which is not covered by the switch in cpu_loop() and results in an abort: qemu: unhandled CPU exception 0x10001 - aborting R00=00000001 R01=408003e4 R02=408003ec R03=000102ec R04=00010a28 R05=00010158 R06=00087460 R07=00010158 R08=00000000 R09=00000000 R10=00085b7c R11=408002a4 R12=408002b8 R13=408002a0 R14=0001057c R15=000102f8 PSR=60000010 -ZC- A usr32 qemu:handle_cpu_signal received signal outside vCPU context @ pc=0x7fcbfa4f0a12 Make the WFI helper function return immediately in the usermode emulator. This turns WFI into a NOP, which is OK because: * architecturally "WFI is a NOP" is a permitted implementation * aarch64 Linux kernels use the SCTLR_EL1.nTWI bit to trap userspace WFI and NOP it (though aarch32 kernels currently just let WFI do whatever it would do) We could in theory make the translate.c code special case user-mode emulation and NOP the insn entirely rather than making the helper do nothing, but because no real world code will be trying to execute WFI we don't care about efficiency and the helper provides a single place where we can make the change rather than having to touch multiple places in translate.c and translate-a64.c. Fixes: https://bugs.launchpad.net/qemu/+bug/1926759 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210430162212.825-1-peter.maydell@linaro.org --- target/arm/op_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.20.1 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 78b831f1811..381f7857efb 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -285,6 +285,17 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) { +#ifdef CONFIG_USER_ONLY + /* + * WFI in the user-mode emulator is technically permitted but not + * something any real-world code would do. AArch64 Linux kernels + * trap it via SCTRL_EL1.nTWI and make it an (expensive) NOP; + * AArch32 kernels don't trap it so it will delay a bit. + * For QEMU, make it NOP here, because trying to raise EXCP_HLT + * would trigger an abort. + */ + return; +#else CPUState *cs = env_cpu(env); int target_el = check_wfx_trap(env, false); @@ -309,6 +320,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) cs->exception_index = EXCP_HLT; cs->halted = 1; cpu_loop_exit(cs); +#endif } void HELPER(wfe)(CPUARMState *env) From patchwork Mon May 10 12:25:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433128 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2802803jao; Mon, 10 May 2021 05:41:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxK7ZHHjupFWJ/uP47gAlnBHO+3FqjNvfN3QKviavF3Y7R5SOaqbozeJECz67poRAyrb785 X-Received: by 2002:a05:6e02:80b:: with SMTP id u11mr22068654ilm.153.1620650491689; Mon, 10 May 2021 05:41:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650491; cv=none; d=google.com; s=arc-20160816; b=VM2ldqmrI3E0iD0XpLYpLJ8UoShady1zUGYPMNnSMeM6mOHPqp3dXYosx8zMuFqgqH mk6G31MK0xEJ/Hk271wRubMe36giMwKQ8d7KTntiC+XtTVd0deDUBdfcu+YVpneCAln9 DlPsb2jYSwINc+eoulvNCLavxs7ZcVmyNXsq+JN0VkJ+6OIwnXJYBlwXxFyr0R00Q+05 UfP/aORGnNaQUgbFjCEHcJ7ic4/anYGeSc6N1CR5OZAQjO8B0pUkcxa3cBXbzzIctv1U 6nUuzVWlYGE010s2qh/zePLQwb91iSV3zXu8Tvb+W018N56rTqXUnjBTLpxuj0LMx7fi 7QBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NwdX6azGIkk9RW5w8G/+mwtZRtmOOUwHdFzdJF/aMkw=; b=n46oDC8iXM6p3OvZYnyZNGS+2m4wkySkf7BtE76mZ2/FDVgpbguvB8bl5xgaK7h6eK id1+DYBLM2qIaYvNFyzGi1QKHeUJIy/XQuZ0RvG1RNTA5PO1+lAU1BTR5v3AeBe8mpq1 AZaiyXeUd+5VLA8wdujXeMzL5jt/Fg6Ef/RBUptYY1qrrmxiUTlTf+atFf0WI3tWY3Gd KGqlb6/QC1zLpMb/FggRFqdVXtS36ea7TTceCVmsZidiyOH7Wo9cX+GUpAMCsgTPJTGD SJqotSYvd1uI93H7gE26m0+ESDsMol5uk7fArKwYqcJ5OIWOFnyDVjTF+2xTge9UjONY H7mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XJKzl2gP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l2si16894803ios.47.2021.05.10.05.41.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:41:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XJKzl2gP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5E1-0002cH-1p for patch@linaro.org; Mon, 10 May 2021 08:41:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z8-00066B-8K for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:06 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:40515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z5-0003Fm-P2 for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:05 -0400 Received: by mail-wr1-x42f.google.com with SMTP id d4so16408610wru.7 for ; Mon, 10 May 2021 05:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NwdX6azGIkk9RW5w8G/+mwtZRtmOOUwHdFzdJF/aMkw=; b=XJKzl2gP+a0CoHFbJLf1g1cqUlGuKJCIArd7A5KGKBetziWfzT3b/FFC7Ly/CjyUxB Xib/7dUfn+TV2cpn4t4pOEKpaVoXCpEQwwOfgIKly+lazwWwG5wcXt6YHbnMacQeW2UA HJI98chOBDoYnzWiMhm7EdqUwUXKLEJO161n66OCxe670MCnmrH/rk/dc6Ny7JM5T59t k3n/OlHKDll/EeaPAUlmwkboQhXarECggTD9cCGl8Yw2AGSMUf5Hq4xO1QTYxQw1XGhf FK/KZode0Ouxz8mA+vlEw6l2AlXH5gzDjPX9DFcXz3uWgPC0BZQzY9d+iakv3kiUIp6W mfwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NwdX6azGIkk9RW5w8G/+mwtZRtmOOUwHdFzdJF/aMkw=; b=piDJEz5sSnVRvU2JLKWIaNQC0/TvjVPt0jO4RYu6+FUK+CH6oH2HHSutl5Fhl4Khww 50n+JcOqohFkw4R1y3rexAteGEbGwCO1/hbbvhfxzrnAHWEsui1aQS+lDKHMctpOlS3u vsUwnKAl33/wrswPfDTVf9i9WOVbUkygCzjprb+2IyFGZ/5IYZ5jb2BzWJRABhY+diUn 0v7PEedtix0T2lnlW+v2t9DVBPZYeLWyW9SAnCMZZ9fFUDdrnth+zuloE3IaJbcAl32v k+uctMzwdNv5zAvCIXwa2GwN84wkBoVVkEKQNuoT8OLrohA2xOKNOrDqUaCB095wisDy NH0Q== X-Gm-Message-State: AOAM530n6MCf4yhi0YmWc6mWZQPK8VfqMd8a7HKymp2hwrLuxtQ/psZ9 wr3mkl+okO5Ok4id+KfIxbsOIV3EoVUzsA== X-Received: by 2002:a5d:45cb:: with SMTP id b11mr30692843wrs.343.1620649562463; Mon, 10 May 2021 05:26:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/26] hw/sd/omap_mmc: Use device_cold_reset() instead of device_legacy_reset() Date: Mon, 10 May 2021 13:25:40 +0100 Message-Id: <20210510122548.28638-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The omap_mmc_reset() function resets its SD card via device_legacy_reset(). We know that the SD card does not have a qbus of its own, so the new device_cold_reset() function (which resets both the device and its child buses) is equivalent here to device_legacy_reset() and we can just switch to the new API. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210430222348.8514-1-peter.maydell@linaro.org --- hw/sd/omap_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index 1f946908fe1..b67def63813 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -318,7 +318,7 @@ void omap_mmc_reset(struct omap_mmc_s *host) * into any bus, and we must reset it manually. When omap_mmc is * QOMified this must move into the QOM reset function. */ - device_legacy_reset(DEVICE(host->card)); + device_cold_reset(DEVICE(host->card)); } static uint64_t omap_mmc_read(void *opaque, hwaddr offset, From patchwork Mon May 10 12:25:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433127 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2802011jao; Mon, 10 May 2021 05:40:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwvosDq3JPDlFs6jzXc8mydE8S7p8PNaPNTDMVycZcBo9V4tfvKbbIH8zXj6ndPL81SpQ01 X-Received: by 2002:a05:6e02:80b:: with SMTP id u11mr22063919ilm.153.1620650416552; Mon, 10 May 2021 05:40:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650416; cv=none; d=google.com; s=arc-20160816; b=QyQmkh2uYYyl7t00WmfUS5Cv9nD3sWtOru1TDgdvrLlCgEstVYmIlrjDfBQ+XrnNe1 K0LjMdMW4eGW0hmLz/DMrXyprD6ozmmpLD5vD5ttoCweOlnOaVpldgHMAuAomvw6yk5w 3mc4sQYPB9p0ZKdOY2+zSXcuVIk27OOWPi22g2J0AFMvQ9p0jdO4PLWnaNAXOHvMbASz rabJczBNyUsRgd6i80OYSTGsjFXEKQ1jgD7o1fdW+PIR586m1ZANq5tVc0p7TcOcwGpF 9jQRssvBy9UbnJh7ty099fYS4h+oBzJSl9pjbSaJqFrPNmQ6UcgI7niZWvqs2/R2h0Rn omlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PTv2d7AJ+CSiaH9XIWvIX/fDTG8P2ni/pY19lKB3JJ8=; b=JNNPru7ZKcKdvnkEwdq50T8gwSfh8pY+pIRfHLXsV7XitZOSEooVa683x85kep+NTV Otu4CfgU/zE5j0GQzuSazYhA88PWOYKZHTMMT5/Mo87akd9y8IS94DW6sM0gT21s/spA LOXu24vg7BeaioTbnvPg66bj5ITrr0MwoKuN/dF/9MwteRPevxDkR5tUk0pHoDr9KHXj A03qoRdwFcJHdrAFd/81Xg/QDKAQJZCL0pSE0OMNzIWjFQFbbJebK3DrmrpsKConW6GC fkM9Ucd0wzyQXOA8ECwbvsY7XMz7uuclzXjkZwjJM2v+3PWi75VGMfS/J2bH5tV9/8yA hLKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M9LTFNjv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p2si16577209ilq.68.2021.05.10.05.40.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:40:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M9LTFNjv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5Cp-0000cE-VQ for patch@linaro.org; Mon, 10 May 2021 08:40:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z9-0006Bh-Iz for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:07 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:52107) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z6-0003GG-NP for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:07 -0400 Received: by mail-wm1-x330.google.com with SMTP id n205so9093380wmf.1 for ; Mon, 10 May 2021 05:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PTv2d7AJ+CSiaH9XIWvIX/fDTG8P2ni/pY19lKB3JJ8=; b=M9LTFNjvNVAnihtQWe2WFDBdFpSA6ReEyLMRIEyW5Ip51H4BMAELTrWO4zeYclwI2+ nVcjWmIUYGmhG0ui7sFt842sEHz9NI24SEaS4mcthb3rxwljbZEo11eaBgfOooAdHL8r Kbu16aiMTBVgaNm/jdlo8wf0oE8axUEG3Nvh4wl0wcQ4g/wMY5pFDGrlAY11LsXPA0pN +m6fGQT7Kz5snSqM8LrjgidP+M8zD9gDkewrwisoBAPZxSYVQt6nViy+ZtWYtREPjLCW C77aUVLFFSVh9dgNcJsjEP2KrkUmKrPjt/Aicw5od3N07miw5sOCvzuwX0u1lVTo9ev5 4OuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PTv2d7AJ+CSiaH9XIWvIX/fDTG8P2ni/pY19lKB3JJ8=; b=UtSNZCfAITTNLSPms94C6VXhFvlCDFheRI4NQ7ihKwa7DiIAB2JRru3H+LKbtVTvp3 V/U05uFKJBmLdf1exYH1UFhqU+yp9eQHPSCqxh5eOn5IQgPo22Qp+bITcbHHLk0XTE36 TcaBldMxt/6xgBTIry0znpALLkVjkhj8iWZ89B2arvT0M6efukz8gHKDOTgcM8AxSp88 Bzw0WAdpa8sFaZdwHI/9+6vGPTez34KliLttNfQ5Mat/k4N3cMsamyNMQFEjsgajR9uM AsuyL4qflSUwc3Ix7j41XNWnIw7YFklWvWtVWiy0JfoVoUa4EFVxZMaAkZ+/qlDZN/Sk 1PaQ== X-Gm-Message-State: AOAM533v6aP9FuFyz02f1qAbfcSvehusF5kcHB7FH5qxwS2hVGQfUC4h rRDzU7u6kKRkY5IM6cwf5ELQQ4XKYjnxWA== X-Received: by 2002:a05:600c:2296:: with SMTP id 22mr38042134wmf.165.1620649563127; Mon, 10 May 2021 05:26:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/26] osdep: Make os-win32.h and os-posix.h handle 'extern "C"' themselves Date: Mon, 10 May 2021 13:25:41 +0100 Message-Id: <20210510122548.28638-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both os-win32.h and os-posix.h include system header files. Instead of having osdep.h include them inside its 'extern "C"' block, make these headers handle that themselves, so that we don't include the system headers inside 'extern "C"'. This doesn't fix any current problems, but it's conceptually the right way to handle system headers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/qemu/osdep.h | 8 ++++---- include/sysemu/os-posix.h | 8 ++++++++ include/sysemu/os-win32.h | 8 ++++++++ 3 files changed, 20 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index cb2a07e472e..4c6f2390be4 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -131,10 +131,6 @@ QEMU_EXTERN_C int daemon(int, int); */ #include "glib-compat.h" -#ifdef __cplusplus -extern "C" { -#endif - #ifdef _WIN32 #include "sysemu/os-win32.h" #endif @@ -143,6 +139,10 @@ extern "C" { #include "sysemu/os-posix.h" #endif +#ifdef __cplusplus +extern "C" { +#endif + #include "qemu/typedefs.h" /* diff --git a/include/sysemu/os-posix.h b/include/sysemu/os-posix.h index 629c8c648b7..2edf33658a4 100644 --- a/include/sysemu/os-posix.h +++ b/include/sysemu/os-posix.h @@ -38,6 +38,10 @@ #include #endif +#ifdef __cplusplus +extern "C" { +#endif + void os_set_line_buffering(void); void os_set_proc_name(const char *s); void os_setup_signal_handling(void); @@ -92,4 +96,8 @@ static inline void qemu_funlockfile(FILE *f) funlockfile(f); } +#ifdef __cplusplus +} +#endif + #endif diff --git a/include/sysemu/os-win32.h b/include/sysemu/os-win32.h index 5346d51e890..43f569b5c21 100644 --- a/include/sysemu/os-win32.h +++ b/include/sysemu/os-win32.h @@ -30,6 +30,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + #if defined(_WIN64) /* On w64, setjmp is implemented by _setjmp which needs a second parameter. * If this parameter is NULL, longjump does no stack unwinding. @@ -194,4 +198,8 @@ ssize_t qemu_recv_wrap(int sockfd, void *buf, size_t len, int flags); ssize_t qemu_recvfrom_wrap(int sockfd, void *buf, size_t len, int flags, struct sockaddr *addr, socklen_t *addrlen); +#ifdef __cplusplus +} +#endif + #endif From patchwork Mon May 10 12:25:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433122 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2799988jao; Mon, 10 May 2021 05:37:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzD3ikJNRVxmdV9K047LiaYnGWEWXVNzbRKDrb7gmVqA/lG8WCbFBVz04NJqAYUzkmScVNk X-Received: by 2002:a67:7956:: with SMTP id u83mr1419900vsc.20.1620650256723; Mon, 10 May 2021 05:37:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650256; cv=none; d=google.com; s=arc-20160816; b=TA8FBFdvakoQmHnbIqG/pBQnIBGkaSdZD5VplYuJl3M8VTnISlR1G/RHvLQqNUCDpe Scg++35vNW+MCbq4GvXGflRYp+Pemm7/+a/yEOhuD/Yu0sCSCdk7dZufgjA6NBM6g9UZ 5CkIih3Zs3GNzPlpE+tgNNhEz3phGO3WmKMJLqPlBZ10bGQyGHtREqDpvLj1LMycka3z xB4QezP48LpT1K21o3epF0/hqAJL+kIeV2vdARWiHEgiVHIUeQI3ymTeEqK7m5eKd6zT Q78Lv3bODtlP12r11dfjoE87sBOReaM3JlwQWtVBFCVhgGopcQrsUJ8QDIndKY8szGcE fo5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+F6jleEXVhgO8uJKJxLCSJYICGeVWVwwC0zqjUCJ2F8=; b=K2GT8lpbVSHm286GwJ+ohvcVhyjuMoJ3lPzxbB/k+kmiq5+qAIIarJAwLCZ8n/NRQN 0Vau6QrZk/hv4cjs50RfKUVw9myPgBQkQy3L+yiPYDUpihBYqb9nxNzwX5SoMUfMOL2N PnmaS5rcG3Fv+MKUi/b+UXTzAPXBOLLuYvJrySWnShf1kcgjpg01NqF07IbW8bWouCfc r2YunME9SMLW1Fn4na/RlMj1bvpGAkpcq40HR9OmuayaFUhlaKbHOFnRgf0a4YVAJDqb Bnh03uYLM4Doz5J82jgGwqHxkq78w3IUvnf0oUJjc2KVU4UDGX/n8VPFMmojioHYtYk9 emgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eCstmKh4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p14si2498884vsh.232.2021.05.10.05.37.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:37:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eCstmKh4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5AG-0003gR-2m for patch@linaro.org; Mon, 10 May 2021 08:37:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4z9-00069H-0H for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:07 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:47062) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z7-0003Gz-3Z for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:06 -0400 Received: by mail-wr1-x42e.google.com with SMTP id x5so16404324wrv.13 for ; Mon, 10 May 2021 05:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+F6jleEXVhgO8uJKJxLCSJYICGeVWVwwC0zqjUCJ2F8=; b=eCstmKh4h7H92VgQYnQCoCE0If4SdYdx3o96Efo5RaD0LHvGvPQBS/Q0vUm60dQJNi 0Dwu4ZVuRU2YnYS+6qz2AygmNixw7kpwMII+ssEtVpiIswpXb+1gNCFAX+yliS4cspYW D28YlGhmHSwHRiP3UdxFfRxjnSK1FlhDCH9DNVUAscPlooU3X8ub1rDiUKTi5N1uMWHv smxN/KObS61UZXQmX2IUiYRuSFlGz5nnppMMvc8aj00EXJXCMgpwZRvhdcfFGRhoJX/b Zob4b6MuY1DVH20pIZdLOUPV1O93Ld2zZeaNM359dFsPDvjkK8P4QS+JlALCNPsxdRG2 SosA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+F6jleEXVhgO8uJKJxLCSJYICGeVWVwwC0zqjUCJ2F8=; b=qvelcRZLRNhpDyK1JIQli1u3sXtUsDWZF0Bafft8Y0/SdFl4aPC1q22ramJAPImdhX WNU3iFy6HOJwpHVCA4dFPirewnpW4ylA0K0Z/qR0kLKm/LkwyNYqj5knOnMD7LlMXyw1 qorWqUJvdFQSHvBsN9FeX27S4jWrxPujdeoMB0oGSBUnsbFUVWhDZtlWk61LHFKVRfig 0Ru4Ws3rsf3po6501h/bTWZKAege5iYy2DZ6OV5Q1xumOT5OT4UcAl2XV6wD5lcJZ6pY zitpQRy/UGuG0a6whFX04z1WdS0fLaS+2G6VAbbSqPxxvX2mbp96OzHJRVO+kVZzBzM5 44jA== X-Gm-Message-State: AOAM5307OMZxcQUTWHvc+4fq4cLXPpDocUrmpyz+wMc6d3GXyslLABFz TfBDQIc5//zOSOybvSq41geeX3tYh3HlmQ== X-Received: by 2002:adf:e40f:: with SMTP id g15mr29971856wrm.392.1620649563794; Mon, 10 May 2021 05:26:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/26] include/qemu/bswap.h: Handle being included outside extern "C" block Date: Mon, 10 May 2021 13:25:42 +0100 Message-Id: <20210510122548.28638-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make bswap.h handle being included outside an 'extern "C"' block: all system headers are included first, then all declarations are put inside an 'extern "C"' block. This requires a little rearrangement as currently we have an ifdef ladder that has some system includes and some local declarations or definitions, and we need to separate those out. We want to do this because dis-asm.h includes bswap.h, dis-asm.h may need to be included from C++ files, and system headers should not be included within 'extern "C"' blocks. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/qemu/bswap.h | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 4aaf992b5d7..2d3bb8bbedd 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -1,8 +1,6 @@ #ifndef BSWAP_H #define BSWAP_H -#include "fpu/softfloat-types.h" - #ifdef CONFIG_MACHINE_BSWAP_H # include # include @@ -12,7 +10,18 @@ # include #elif defined(CONFIG_BYTESWAP_H) # include +#define BSWAP_FROM_BYTESWAP +# else +#define BSWAP_FROM_FALLBACKS +#endif /* ! CONFIG_MACHINE_BSWAP_H */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "fpu/softfloat-types.h" + +#ifdef BSWAP_FROM_BYTESWAP static inline uint16_t bswap16(uint16_t x) { return bswap_16(x); @@ -27,7 +36,9 @@ static inline uint64_t bswap64(uint64_t x) { return bswap_64(x); } -# else +#endif + +#ifdef BSWAP_FROM_FALLBACKS static inline uint16_t bswap16(uint16_t x) { return (((x & 0x00ff) << 8) | @@ -53,7 +64,10 @@ static inline uint64_t bswap64(uint64_t x) ((x & 0x00ff000000000000ULL) >> 40) | ((x & 0xff00000000000000ULL) >> 56)); } -#endif /* ! CONFIG_MACHINE_BSWAP_H */ +#endif + +#undef BSWAP_FROM_BYTESWAP +#undef BSWAP_FROM_FALLBACKS static inline void bswap16s(uint16_t *s) { @@ -494,4 +508,8 @@ DO_STN_LDN_P(be) #undef le_bswaps #undef be_bswaps +#ifdef __cplusplus +} +#endif + #endif /* BSWAP_H */ From patchwork Mon May 10 12:25:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433125 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2801716jao; Mon, 10 May 2021 05:39:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAdNTS2Psh2uxv2Z2XKeQGq7FEvrDnD7IW8u6q050fVc8W9XZ9Mjlpf+KU5TvohFc4wIkK X-Received: by 2002:a6b:7c0b:: with SMTP id m11mr18033729iok.9.1620650387815; Mon, 10 May 2021 05:39:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650387; cv=none; d=google.com; s=arc-20160816; b=V18Wn7pgFEVl39jE8LPn6UocmPSZRpY6695oHp+YPfe2rJl7b+7QItqKMNdZQzMTLI 5izvOqaSibomTKvEKqs7v/6F+rFm3D2XIUfgTun5S7jVKlvPWg9TdRp+cNY6w2jng5Hf tHns0DgBCA4hXsQCrQym0U3oGNv3zJd9WjwRrp4kW1/esWwegR4jc3xCTsM3CvMPPQzX jIXaq8BR8U2mZXfp3GxTnjHX4RXcVvuXHNhGvRwDilsmWFYFJvCyVss3NNHcSWXXft3Q 7GeY89VLu3Ic9wgw1pKUFqxYeov5BmmhDHSBpwkO2oM1h2eegZoTyshyofJPqJFiTnXv x+Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OR9pef3HduyOmvWH82pNcRMO4dLmxiN0+TVKetu9P78=; b=bhWE7YYMOBvra7yGGGfsJEErB8lnpMCEU8C+DyigjjlcrPP+pJfUsT8X5EpsV9Xkpe io+26Z7TZ10p/AdSz0Rwd2kcbaBVKVCaa1YinlvPdF+n/udhRn0HUMVvkhvY21Q50hcU AebCDgyMtBiyDZZBzqlJBXr4Vf8o9rtqgKbOlmtW7EJ2q2wFcYHxH8+Sh1gvs5AZ+PhQ 4VEQwheBLYOiH1Vw7RetFi4pDCHSOyCSrladECGAUVS9mxGbrUkHczheM553MTBNmzph 7sx3KzUu2RbO/buEEFjVaClGklXEId+DqSvch+ylsF6M4cJmQ2M6wFCiGWGO1Tu7EOKI GHNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K2oagKTx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g2si4227273jam.93.2021.05.10.05.39.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:39:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K2oagKTx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5CN-0000yf-80 for patch@linaro.org; Mon, 10 May 2021 08:39:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4zB-0006JR-NX for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:09 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:40554) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z7-0003HB-On for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:09 -0400 Received: by mail-wm1-x32d.google.com with SMTP id y124-20020a1c32820000b029010c93864955so11040499wmy.5 for ; Mon, 10 May 2021 05:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OR9pef3HduyOmvWH82pNcRMO4dLmxiN0+TVKetu9P78=; b=K2oagKTxhtSLw/i+ufp40hNXRveWuaKvXfLyPvThCK4+y+etStfDhYHtnKG8wmNYae DRfOxLcjRT65ICBMUWRgismjDoMS51EkcDOGJ8ZTInfgM8CPgf6xeXggiFJNAZ9O4+Lb zgVswkzGr2eH4sQMX8fdoBdRnw496zNcQH+v/BV3DOslysj7HgYaTa+ZKhQa06Wqlk2/ cvXyBvWWXdUN0KWMmpsVOmFACa9CFFBXuDRefk8svl5S63uSMAWzPmoRPjGPltIzrAj+ Fdda1xXaaLxwF72WGW26uxtHqZv6VQilmjKsczznyXRqlzECyPNBbD9WnZD/VZ72NRAi MhRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OR9pef3HduyOmvWH82pNcRMO4dLmxiN0+TVKetu9P78=; b=lyAsWaeIE8ByavexHsuHYqKGVVQJ8RUs9r1A7IZEPmRcDxgV1spqff0WzP9xXMM9qB ZBy0tAQ848gjbDzyIsXzY5hnnS/H81dsA8jUpx2YJ5gd1KQFi62/czr4oZkdC8vXwPAz cW/4L23F+u/SR97GHoGDMMvUjpZPjMH/Xj2otLnyMTTnp1P/mWeIxP96DcDGTYr/AtvT CkFQR2lHTHppt3rk0i//xyuUsOVo7Q+BA/dw0Chhzq2+WrRf6BIUHtJ7Rw4/wrYblqZs n0MrENOjpS/OTKTzGjToYLD17gukeL0Qzbseacl0WAEG5ZFHzo7R5J5vEIknOv8iqdEd +gwg== X-Gm-Message-State: AOAM531icx+FKLXA/mtvg/6U4U1E95QF9Rwgipt7WORABg0ysWjfFSl2 xUQXMTkr8zit8buMYFe1pQ87yaoQHrHeWQ== X-Received: by 2002:a05:600c:4998:: with SMTP id h24mr36808508wmp.10.1620649564379; Mon, 10 May 2021 05:26:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/26] include/disas/dis-asm.h: Handle being included outside 'extern "C"' Date: Mon, 10 May 2021 13:25:43 +0100 Message-Id: <20210510122548.28638-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make dis-asm.h handle being included outside an 'extern "C"' block; this allows us to remove the 'extern "C"' blocks that our two C++ files that include it are using. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/disas/dis-asm.h | 12 ++++++++++-- disas/arm-a64.cc | 2 -- disas/nanomips.cpp | 2 -- 3 files changed, 10 insertions(+), 6 deletions(-) -- 2.20.1 diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 13fa1edd411..4701445e806 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -9,6 +9,12 @@ #ifndef DISAS_DIS_ASM_H #define DISAS_DIS_ASM_H +#include "qemu/bswap.h" + +#ifdef __cplusplus +extern "C" { +#endif + typedef void *PTR; typedef uint64_t bfd_vma; typedef int64_t bfd_signed_vma; @@ -479,8 +485,6 @@ bool cap_disas_plugin(disassemble_info *info, uint64_t pc, size_t size); /* from libbfd */ -#include "qemu/bswap.h" - static inline bfd_vma bfd_getl64(const bfd_byte *addr) { return ldq_le_p(addr); @@ -508,4 +512,8 @@ static inline bfd_vma bfd_getb16(const bfd_byte *addr) typedef bool bfd_boolean; +#ifdef __cplusplus +} +#endif + #endif /* DISAS_DIS_ASM_H */ diff --git a/disas/arm-a64.cc b/disas/arm-a64.cc index 27613d4b256..a1402a2e071 100644 --- a/disas/arm-a64.cc +++ b/disas/arm-a64.cc @@ -18,9 +18,7 @@ */ #include "qemu/osdep.h" -extern "C" { #include "disas/dis-asm.h" -} #include "vixl/a64/disasm-a64.h" diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp index 8ddef897f0d..9be8df75dd6 100644 --- a/disas/nanomips.cpp +++ b/disas/nanomips.cpp @@ -28,9 +28,7 @@ */ #include "qemu/osdep.h" -extern "C" { #include "disas/dis-asm.h" -} #include #include From patchwork Mon May 10 12:25:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433123 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2800362jao; Mon, 10 May 2021 05:38:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyNfauVieYb1FkmFK12rlbkPM4t7OGPTv+YAWGmbwabXPpBynFH7FuqWdPn6iZZGLJile0l X-Received: by 2002:ab0:4e0b:: with SMTP id g11mr981046uah.22.1620650285832; Mon, 10 May 2021 05:38:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650285; cv=none; d=google.com; s=arc-20160816; b=LJsujgCSi2mrluweK+PpsLhEyP/xce9fJ7tUCBamosbSefGGRFS7DxV/nowjHh/gsJ XTvab7/+5GGAv57EJqA+T4rNQ16IH4H+rnbsU54AUkCrm3NagrQ5IJZtkiplS7ogeu5g tQA54sXHWnoJFWDc8+nOGviRlowk6CFMzgRwRQ7uOB43VF9fiT2aFwD0LoUBVffFADHi ttM2JHL4MQ+mFEnj+789EJ/+kehEK/FVi/mik2D/g6TV/eHxHdhEBsFFnZUmstGd2gEg Pxv3jYrNSWnyln7ZT41RliRqZLUE6aQkC9udOyVKOh+CWVH22x+ugC+GzVcQ3acJxmtK SULA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jvz4r6apxuW1lveLKyXMmu2dN42LHk0Z7q4wIAJ/vfQ=; b=BvshCz+FttJZTiVqvCfRnM0JSCL0E9QcCzGXg1+h350HBNKcXPDNDOFnGSZGi2XNSH W70gTw+i/LnB21ALTjzE1HeTrDNQuOQPYHrxg7bmPYhtRimWj7Ol0xPPfmCkFt+czehN uQ5VKaA14oAgqBIHVn29MrBTAVh4LG7bhuSlnuox7F2GXIpgpsGJ/W+NVxzHnZYqohO8 zW/XQPOHPWnPMmsP5x99tVdrzVAa80GXGC8N/V/jWvyn57P9NTtKpKb6kr1hY/nf8C7Q dQQT/Ij2mjznx/mzVwXeL0PjUVDnjdqWGpy7QJTBzJcc04INKl/U5V8Pu09pfyXvLHNQ fQZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m/yDxsSh"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x16si6497320uaq.232.2021.05.10.05.38.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:38:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m/yDxsSh"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5Aj-00035G-8N for patch@linaro.org; Mon, 10 May 2021 08:38:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4zA-0006Dz-CG for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:08 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:34754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z8-0003HN-DS for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:08 -0400 Received: by mail-wm1-x32b.google.com with SMTP id u5-20020a7bc0450000b02901480e40338bso9587471wmc.1 for ; Mon, 10 May 2021 05:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jvz4r6apxuW1lveLKyXMmu2dN42LHk0Z7q4wIAJ/vfQ=; b=m/yDxsShYOEeC6jKCttdzIqe6TXsRLmd7nL1cWGdb7SzL2NSuCS8Kne+13/c+TNqaM 2dBIIcr5Tgc6RqdEPGIXYJRSKa0CUKP8nc4UnMThH3nixkmdUOh+Sc0H5ieL6d/4POfr lrt90oyv8EqJSPMB7F78NizAWsYJMNOCU7Iwr7cPb/EbvA4JpAxV2NtEJrk2Eb9FHZdE DiEGjms5VVMRcBpoQbKi28hHVH2Z5tdVSv8rTH0f8mrNtfsLy5AAXVPv0CsXTNDNU9tE 4250VwIQ8sMnzFZzSVPEq1vHut2cm4EEwX7ZoN7tYiHU7XMl4DG0lilVO45iJoxRPRq3 Lw4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jvz4r6apxuW1lveLKyXMmu2dN42LHk0Z7q4wIAJ/vfQ=; b=AKEftpxIyn6Zz0g19+TAB9cwU/rZG23iiFA7vY6CKI0d/PMgpNx/nVhbXrIP5EyQvp jryuya5zavvsZFi4MZLz+INyxkREV6n37S3G0ibQmg9B+hH3J6DSVLgdz9K9f5q3qYKx sIEg5Mw6AgC4vgjdg/j9iom5HNpoJ+LnWgYbSrIfZO1yUyRDakf8qX6ABH8AncTzM8i4 OvPygkDCstIBLvXwT0qPgNBUhiQdEAnO3d2nvYgx7xXpMdVTadJ1vF/LryRg6BBYWGFO xRh1UPlUOiVZEnAu2vIe9tCKdPdjYwaQlq5dZ27Arlcp4E4aMggWmRL83CDkcuSGFWOD q8tw== X-Gm-Message-State: AOAM530PCMuez2/M49XuxSb/SOIJ7uyI9rObUjQcrD/z4CLceadq+VIf 0r2IaemZtsOwbmBx12PyQuZKNQEXUpvY7Q== X-Received: by 2002:a7b:c5c1:: with SMTP id n1mr36584967wmk.83.1620649564994; Mon, 10 May 2021 05:26:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/26] hw/arm/imx25_pdk: Fix error message for invalid RAM size Date: Mon, 10 May 2021 13:25:44 +0100 Message-Id: <20210510122548.28638-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé The i.MX25 PDK board has 2 banks for SDRAM, each can address up to 256 MiB. So the total RAM usable for this board is 512M. When we ask for more we get a misleading error message: $ qemu-system-arm -M imx25-pdk -m 513M qemu-system-arm: Invalid RAM size, should be 128 MiB Update the error message to better match the reality: $ qemu-system-arm -M imx25-pdk -m 513M qemu-system-arm: RAM size more than 512 MiB is not supported Fixes: bf350daae02 ("arm/imx25_pdk: drop RAM size fixup") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Igor Mammedov Message-id: 20210407225608.1882855-1-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/imx25_pdk.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 11426e5ec0c..bd16acd4d9f 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -65,7 +65,6 @@ static struct arm_boot_info imx25_pdk_binfo; static void imx25_pdk_init(MachineState *machine) { - MachineClass *mc = MACHINE_GET_CLASS(machine); IMX25PDK *s = g_new0(IMX25PDK, 1); unsigned int ram_size; unsigned int alias_offset; @@ -77,8 +76,8 @@ static void imx25_pdk_init(MachineState *machine) /* We need to initialize our memory */ if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) { - char *sz = size_to_str(mc->default_ram_size); - error_report("Invalid RAM size, should be %s", sz); + char *sz = size_to_str(FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE); + error_report("RAM size more than %s is not supported", sz); g_free(sz); exit(EXIT_FAILURE); } From patchwork Mon May 10 12:25:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433129 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2803506jao; Mon, 10 May 2021 05:42:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9Zs9Asl1JclmvM8LLMBm7o9YM8g1kHS3TC2hbI95CuzZv9IC+dR5zaoWljnmlg4k/nOsy X-Received: by 2002:a02:2a8c:: with SMTP id w134mr21003568jaw.138.1620650549699; Mon, 10 May 2021 05:42:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650549; cv=none; d=google.com; s=arc-20160816; b=iuOLbUn0Dlwd3efWj530UFUONbi3ToLq7RHaYj14Bl5Ni+/AOuk7Mjv5pQx1KJaqGd Xbq6slSNT6HCnZ3eUcaEZMGUpJXrhlZFuPZ4iCTFTEPi6fsq3NQeQN3AhuG2CSv3014F /mB7z3/dfIECOIQ0NZ0N3aO6ESCia7fijfdbILTWvZM+RgTnDIn4+Tgak6RWokPLjKcm eG7wz8wp4AMdeYpVWtktaYM6TjhOOboqu8MU8QiklHBrInRapsoqM/cCrVWNQNup6EVJ qTyp0ZX/kwvSoBpv7NIUXvuqoWvJfguRnGj3lveloqWH2WJNE/D9iryto9jQvJelhj+m 9W/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=y2OKc7vP5DzVlkf/WS5AgktrZwPw/A4L8DIPa/tOpOY=; b=scNpdsReK2fqkJ3pD3P5OpvUdArV0KV1+BcQS6UPVi4f7TMMLzjTjtHXJwdt+kbe09 FIb6875LQnl6ooBaRyimpSOdqjY57YPGWqg6/n7K+kmAoH+8xFFY5pfvB6jIIk1paXhJ Fn170/p9mpziC/QY1Aowk8qLz2KNeZ2t6bQEWd8uNOluq5orsIqGFRjRZRy6j4IkMxzK uV3qLdtQX2yFScQv3u45EpBaPBDDg20S20nqJ0YHwo12CfLumYiBJuDArqjVszxtUXr6 nkBhafJbR+QbP+gNMIrifCpPfjV5sUu/XxH+6h2oYZRpSsmYiCCDI4l6XkxCNY3bD2HV b6pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xDZQon8G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j14si15595155ils.113.2021.05.10.05.42.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:42:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xDZQon8G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5Ez-0006NI-46 for patch@linaro.org; Mon, 10 May 2021 08:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4zA-0006FC-Lv for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:08 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:38725) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z8-0003Hn-V9 for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:08 -0400 Received: by mail-wr1-x42f.google.com with SMTP id l14so16426270wrx.5 for ; Mon, 10 May 2021 05:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=y2OKc7vP5DzVlkf/WS5AgktrZwPw/A4L8DIPa/tOpOY=; b=xDZQon8G1Uqtysu5cS+YPXt2vio4UBBFBQHd2gBLgBWjLF9Zk3+0L39bktME+B6dEK 65JPJFNzOsLhm3i61R55eiIExL402MpeF0vOUQIiUTJ/oXprEbOX7KgE37/hCfeNuh1L EyorV5yDWVRz5dQyLbElglEKWDaM5n8B9wUUQVqkaRbL2KOTOheR8Z196Y921USHHCyR Wi6AUD3hX3N6Ls1ymo+NwuMZYYkikpytMJtxHLKptrd7lqAj+C8/TUvpqmf9qRGtt5PZ Ze1IyCxgJXw8oURF0kTlxX+jqW8Ku1m4E/VpoX+q+Sxyoseg1hyU1doG+wB1aJL8xYs/ Gw7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y2OKc7vP5DzVlkf/WS5AgktrZwPw/A4L8DIPa/tOpOY=; b=lLQqJURnhA822g4PFMgkMHAnvc6f8/S+YlFGqtGj/tZM5JZQZnhGhPlN9jwt1ZeWIY udHqg/xu21m68AVIp4yCpaolSqZ6TfE0IUHZJ3SHvEY1ZyQqAGGfzs8dXBT5U70eIVgF eXqn+h7MEpKi7UAosF3cBX83yQp4YXWC8e1ermdA5C8p9+7ObzPCf08gDnUBWPg1xwZR /0RPMqtF9q3JSLg+UUW7QCQR8ilxln7Jtw8E/uxawMPqi8SyqHyR1aik/zcU4nrwdcen Oldn8k9ee01A6/UyHRfRwXJyKlg0rVV+fQFUXH3L5iKU4dHeeBDTsGKux4Ct12w9D0S5 S5dg== X-Gm-Message-State: AOAM530LcpPO3P9I3+Mklp+6cy7SIh2Fbo3r/4Y6J2u8YB4TA82nveOG Do5hYXd1IeSLvJBuj4l0a56LL0RuTbTWrg== X-Received: by 2002:a05:6000:237:: with SMTP id l23mr25580165wrz.138.1620649565643; Mon, 10 May 2021 05:26:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/26] hw/misc/mps2-scc: Add "QEMU interface" comment Date: Mon, 10 May 2021 13:25:45 +0100 Message-Id: <20210510122548.28638-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The MPS2 SCC device doesn't have any documentation of its properties; add a "QEMU interface" format comment describing them. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210504120912.23094-2-peter.maydell@linaro.org --- include/hw/misc/mps2-scc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.20.1 diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index 49d070616aa..ea261ea30d6 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -9,6 +9,18 @@ * (at your option) any later version. */ +/* + * This is a model of the Serial Communication Controller (SCC) + * block found in most MPS FPGA images. + * + * QEMU interface: + * + sysbus MMIO region 0: the register bank + * + QOM property "scc-cfg4": value of the read-only CFG4 register + * + QOM property "scc-aid": value of the read-only SCC_AID register + * + QOM property "scc-id": value of the read-only SCC_ID register + * + QOM property array "oscclk": reset values of the OSCCLK registers + * (which are accessed via the SYS_CFG channel provided by this device) + */ #ifndef MPS2_SCC_H #define MPS2_SCC_H From patchwork Mon May 10 12:25:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433130 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2803557jao; Mon, 10 May 2021 05:42:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyS95uN3BdivRE1NXm4CoHIHQChLIYSPzPfQ2nOxysJ7F7AXvNZ9s2LpIwU/DtK7f1AOvBr X-Received: by 2002:a05:6e02:156c:: with SMTP id k12mr21096910ilu.49.1620650554095; Mon, 10 May 2021 05:42:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650554; cv=none; d=google.com; s=arc-20160816; b=wS/RhF+ky0m2nDqCAkiTz7OtjKYLAVsFAWuxeY7pqgcIFkkadBvfi0gzR/KzgaI/aF 1zApopfyUEXpDMns52Un1ak1mJQNqk/9fk6doo523i6rSu6N8O69yVGbTz5p4WydRkxd 6ggG1UHCmH8HlncRWOYsyhTu3rdBByeeHTd9IejoG1kAGOPwNQETQKw14jfqMpM+CoO8 apqIrNamzSPeLTnW17VA20EprFgqZzw+ngHijEpmn7aPpoF/wdddBg6UgKSo9YBgQfMj S4B+YlQZyNslrgdHPTkmUEuj2r//QcWAVR+rXXKCh1E4WTpqoNNB/bZ3E0btwYYSFeM8 9EjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RfECNInbRl2xXf0mzEIYRXmPMWJAKt9xNNm+oX0Cj7A=; b=Dl+UPjanSPlRphGtgPYdwswb51Em/3iKpBqK691SaMIJYdKr2AOJ0aMqWS2HUWFPq7 M/ridW46g7L4B+ZaEh5yX5BS5NaNN1c8GtTimxePCMi1SeC6LqQXTgGgKTltYKP58xeG VbIrizI0XUTEOV621ughT7HBVuV/Rbk0rc24JtAS6svcEcBSaDCF0vnDDEvjSfLSv9Dj 9nR5CMTI+zGZEJisyI4tZ04Gs3gkcxnr7VA8XID3WZzo+vqlhblWPKHAMw26dhJ/DSMe EvRQLfz4HLW0AbkVm9JjJEp5bvxA4hoyNd+05CLD696k38xVURxAxcm9TfTR5sultOLt M98g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GLhogsEw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x9si18097496ilu.119.2021.05.10.05.42.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:42:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GLhogsEw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5F3-0006i6-HU for patch@linaro.org; Mon, 10 May 2021 08:42:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4zD-0006Qr-Io for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:11 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40514) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4z9-0003IL-Mw for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:11 -0400 Received: by mail-wr1-x42d.google.com with SMTP id d4so16408841wru.7 for ; Mon, 10 May 2021 05:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RfECNInbRl2xXf0mzEIYRXmPMWJAKt9xNNm+oX0Cj7A=; b=GLhogsEwvEHUbpCMhT3XXAvnmzq1ck5CDIP25VUqGRenXGX1nn77W9I6YIR9kUrMBO 64+B1X7tccoVIwNVBU1RegIkonfLftmwQXR8cdlXmm+t0z5532SYud/OidefSI19PuNF FlKX03dAWC/ERX8IddG6TAWMmweJVusl98SZm0GZRj3pUxB68NUy44sPI+XRXoHKgvVl GQVMt/1cTra33RPBDpK2hWZ8IxYQXGiR3/Kfz+niU9ACPJuikvW0XMy47skL+JgFDXxM YddtN+fJJbyZ0t6eO5rYu4eHw/E/gaDyJA2nzJOSgYda5VsUFwHHNx3BaBu4tn5lV0UM LvbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RfECNInbRl2xXf0mzEIYRXmPMWJAKt9xNNm+oX0Cj7A=; b=iptslnsIUnQabNZ5K07F7gH43KyGN2EmJLc3+Q7jhAH1DyWkEqQt47VhwCh6ObRxii 4jHysNC6Jq/uaTcoGIdw1LZ3XZanE7hNT0hwHNZvtHWXpU4G+5LkpqqAnPsFTFC3SlVR yUa6DQHZkPIoiQLSf6Ly9/FzC+ZwRqw37XexbnoUzhE3GoBrl0EuVOXpXjUn7mzDle3N ieOK/wfkokKYrI8deKUvMB9wLa5hpGHUfdPZ3SypZVxP0/6BcqLwsJFQ+gaUPll3boHO nLcnY3PcDShPY9WRcRVdUPKIugb+43DMy+ePgrp4lK+xWKwpjOIqQx+eI/W4y4JtFUbp ePtQ== X-Gm-Message-State: AOAM530IyEc26Z9yh4kiXIZYRxKL7csyK1xsMKpM7CWv7b20sVC/G4Rq vAIUFbwFljiRtJl/7kmDSJ8QRCacyIXhcA== X-Received: by 2002:adf:dcc5:: with SMTP id x5mr31004196wrm.1.1620649566316; Mon, 10 May 2021 05:26:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/26] hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping Date: Mon, 10 May 2021 13:25:46 +0100 Message-Id: <20210510122548.28638-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" On some boards, SCC config register CFG0 bit 0 controls whether parts of the board memory map are remapped. Support this with: * a device property scc-cfg0 so the board can specify the initial value of the CFG0 register * an outbound GPIO line which tracks bit 0 and which the board can wire up to provide the remapping Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210504120912.23094-3-peter.maydell@linaro.org --- include/hw/misc/mps2-scc.h | 9 +++++++++ hw/misc/mps2-scc.c | 13 ++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index ea261ea30d6..3b2d13ac9c3 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -18,8 +18,14 @@ * + QOM property "scc-cfg4": value of the read-only CFG4 register * + QOM property "scc-aid": value of the read-only SCC_AID register * + QOM property "scc-id": value of the read-only SCC_ID register + * + QOM property "scc-cfg0": reset value of the CFG0 register * + QOM property array "oscclk": reset values of the OSCCLK registers * (which are accessed via the SYS_CFG channel provided by this device) + * + named GPIO output "remap": this tracks the value of CFG0 register + * bit 0. Boards where this bit controls memory remapping should + * connect this GPIO line to a function performing that mapping. + * Boards where bit 0 has no special function should leave the GPIO + * output disconnected. */ #ifndef MPS2_SCC_H #define MPS2_SCC_H @@ -55,6 +61,9 @@ struct MPS2SCC { uint32_t num_oscclk; uint32_t *oscclk; uint32_t *oscclk_reset; + uint32_t cfg0_reset; + + qemu_irq remap; }; #endif diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index c56aca86ad5..b3b42a792cd 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -23,6 +23,7 @@ #include "qemu/bitops.h" #include "trace.h" #include "hw/sysbus.h" +#include "hw/irq.h" #include "migration/vmstate.h" #include "hw/registerfields.h" #include "hw/misc/mps2-scc.h" @@ -186,10 +187,13 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case A_CFG0: /* - * TODO on some boards bit 0 controls RAM remapping; - * on others bit 1 is CPU_WAIT. + * On some boards bit 0 controls board-specific remapping; + * we always reflect bit 0 in the 'remap' GPIO output line, + * and let the board wire it up or not as it chooses. + * TODO on some boards bit 1 is CPU_WAIT. */ s->cfg0 = value; + qemu_set_irq(s->remap, s->cfg0 & 1); break; case A_CFG1: s->cfg1 = value; @@ -283,7 +287,7 @@ static void mps2_scc_reset(DeviceState *dev) int i; trace_mps2_scc_reset(); - s->cfg0 = 0; + s->cfg0 = s->cfg0_reset; s->cfg1 = 0; s->cfg2 = 0; s->cfg5 = 0; @@ -308,6 +312,7 @@ static void mps2_scc_init(Object *obj) memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000); sysbus_init_mmio(sbd, &s->iomem); + qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1); } static void mps2_scc_realize(DeviceState *dev, Error **errp) @@ -353,6 +358,8 @@ static Property mps2_scc_properties[] = { DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), + /* Reset value for CFG0 register */ + DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0), /* * These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the From patchwork Mon May 10 12:25:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433126 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2801965jao; Mon, 10 May 2021 05:40:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxr0/LnnefyG8UNt88cRsMVM8BAyl/jgPoEmXx/X7Gb84PzJBzKQ2+MwkvJHcw767bA24XU X-Received: by 2002:a6b:7306:: with SMTP id e6mr18223026ioh.75.1620650412774; Mon, 10 May 2021 05:40:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650412; cv=none; d=google.com; s=arc-20160816; b=Rch0ooW/CRKagFXOnvHtmgDUSxxHzcNHBOBkzpw9OsqoSvEvymRoDAbVf+bhdYo4ZI e2K5rHOX6b3tRKYE27GllUft/6McE7Ibw3LbHVMAJiFY+acqOozcR/b7iYt6uYF/6uoe tcH1J4til2hVuHbM4X/D0rGXRp9VrNj4Gb1UukDCP+op+mrDuVDneWCR+YpvHZm9rgZJ xTr/lF7aL6gFCzzA9boUOGaj4NYemQMvBeDYtZ99blrBhjeAy07JsbyzdFBnbd63s/ss DzaCky4OPrzs5Zb9o3u4Q3gOtoaP5R8UyqnMRaGud+2buuDbuOfsgUvcwwRr9vr/UukS 3qSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KfLZ6LXviV0zOceL8z32K11kNdm5AeMaXSYyQKbM+6I=; b=yiRYt8y0FCSk5MgQNKsUFrBTQwL5lJAjxkHVFSSa/vn+Zr+snHRN0GFetCOK+XY56h 123KVnF1iqFfGORo+yfOG57lkvC76hiEA4O4XfFZgMA9mmn+jrbTB6btB8ut7PGOs4kF iNl3xpbYLKHjaDsBowblv2zeNB9RP+egWTsmf8unlGhNJPvb0R3iHjUnmNAdWqAB515L WS9QI1nwZp5jGNRb+WzRY6nA7hhwE1tgqYY/yNvUc6t/5GwsgCgdLId0qAyxFCvPY6GU NPmEEdifdfbbBFPwuXtgpfru7t3Sv9esqXR5IxOf1swpVAOyefzUpWduhzdeVSDYzpir v/YA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UN1+T1xW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l2si16891880ios.47.2021.05.10.05.40.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:40:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UN1+T1xW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5Cm-0000L2-2U for patch@linaro.org; Mon, 10 May 2021 08:40:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4zC-0006O3-TV for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:10 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:44735) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4zA-0003JP-LE for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:10 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 82-20020a1c01550000b0290142562ff7c9so8774744wmb.3 for ; Mon, 10 May 2021 05:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KfLZ6LXviV0zOceL8z32K11kNdm5AeMaXSYyQKbM+6I=; b=UN1+T1xWwgQK6mQq3iKAmFqsq/Q6p6WNEby2V72sH2hLPOSoLJnsVgMosGDLk/3f8E liwMoJQLJliTPq9cy2EF72MBNlGt1L8vGNWWTN8Sck5ya56r812DvfofS5pkdxRk2AI1 vkLMD5ZKJ6/PZXzG/nqNJa+uOkMdCqZyIZibGHxTunmWN7mRnZeKdIMgu6zFBjBlrXs4 tG4UUDlwMl4CqyC9tXgT8sIA5jrdAER0FuYGAgEXLH4wkzki3b5zOeA/haOxQJui9ivI pekZkdzq0AEc6lrznhc2c5krfvtuDbdKp7AWVdJjTdu3HtcbNkSjjv5eb66nAzB1kl+A CYhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KfLZ6LXviV0zOceL8z32K11kNdm5AeMaXSYyQKbM+6I=; b=GC5VOuBG3igDPXstELlaLm8CNpMxvVV4DSim+x0amLviWG+eTSSQWaDk2y1ggM5mjk BXl3z1Ctg3IencKetBDM9f130zjfkFJQ83feHjUbf0apz1QQ5aC8OAnovXXoYzAjWuiq BmcS7w1rJ77qcsk4CCvj1F7eNeBRb8THrIByX64UV5yGaCU/1S1QgjiGK26YwBlrhJPY qgNiPoM+CUDFn1nKCT+Ww+nF19OgW7Rytrri3V+5XJTR5NuFEP0eiB/QnBMuTIb5cQns s0MTB3h3Ih85ulUqUDypG53CB2vQGApg0CVUxrtTyfehYGlBSzI5ZInpWcfBzTyPBP5n IdAg== X-Gm-Message-State: AOAM533tpKruwybgVc6bEQIMShi2xHdv8EwfNe9Fa1WUUkA68Nj4AaO4 Wm3hBymNt76xLo/1is99np77uhal9BweFA== X-Received: by 2002:a7b:cb4a:: with SMTP id v10mr25930955wmj.53.1620649567084; Mon, 10 May 2021 05:26:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/26] hw/arm/mps2-tz: Implement AN524 memory remapping via machine property Date: Mon, 10 May 2021 13:25:47 +0100 Message-Id: <20210510122548.28638-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN524 FPGA image supports two memory maps, which differ in where the QSPI and BRAM are. In the default map, the BRAM is at 0x0000_0000, and the QSPI at 0x2800_0000. In the second map, they are the other way around. In hardware, the initial mapping can be selected by the user by writing either "REMAP: BRAM" (the default) or "REMAP: QSPI" in the board configuration file. The board config file is acted on by the "Motherboard Configuration Controller", which is an entirely separate microcontroller on the dev board but outside the FPGA. The guest can also dynamically change the mapping via the SCC CFG_REG0 register. Implement this functionality for QEMU, using a machine property "remap" with valid values "BRAM" and "QSPI" to allow the user to set the initial mapping, in the same way they can on the FPGA, and wiring up the bit from the SCC register to also switch the mapping. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210504120912.23094-4-peter.maydell@linaro.org --- docs/system/arm/mps2.rst | 10 ++++ hw/arm/mps2-tz.c | 108 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 117 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index f83b1517871..8a75beb3a08 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -45,3 +45,13 @@ Differences between QEMU and real hardware: flash, but only as simple ROM, so attempting to rewrite the flash from the guest will fail - QEMU does not model the USB controller in MPS3 boards + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +remap + Supported for ``mps3-an524`` only. + Set ``BRAM``/``QSPI`` to select the initial memory mapping. The + default is ``BRAM``. diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 25016e464d9..70aa31a7f6c 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -55,6 +55,7 @@ #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "sysemu/reset.h" #include "hw/misc/unimp.h" #include "hw/char/cmsdk-apb-uart.h" #include "hw/timer/cmsdk-apb-timer.h" @@ -72,6 +73,7 @@ #include "hw/core/split-irq.h" #include "hw/qdev-clock.h" #include "qom/object.h" +#include "hw/irq.h" #define MPS2TZ_NUMIRQ_MAX 96 #define MPS2TZ_RAM_MAX 5 @@ -153,6 +155,9 @@ struct MPS2TZMachineState { SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; Clock *s32kclk; + + bool remap; + qemu_irq remap_irq; }; #define TYPE_MPS2TZ_MACHINE "mps2tz" @@ -228,6 +233,10 @@ static const RAMInfo an505_raminfo[] = { { }, }; +/* + * Note that the addresses and MPC numbering here should match up + * with those used in remap_memory(), which can swap the BRAM and QSPI. + */ static const RAMInfo an524_raminfo[] = { { .name = "bram", .base = 0x00000000, @@ -457,6 +466,7 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); sccdev = DEVICE(scc); + qdev_prop_set_uint32(sccdev, "scc-cfg0", mms->remap ? 1 : 0); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); @@ -573,6 +583,52 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } +static hwaddr boot_mem_base(MPS2TZMachineState *mms) +{ + /* + * Return the canonical address of the block which will be mapped + * at address 0x0 (i.e. where the vector table is). + * This is usually 0, but if the AN524 alternate memory map is + * enabled it will be the base address of the QSPI block. + */ + return mms->remap ? 0x28000000 : 0; +} + +static void remap_memory(MPS2TZMachineState *mms, int map) +{ + /* + * Remap the memory for the AN524. 'map' is the value of + * SCC CFG_REG0 bit 0, i.e. 0 for the default map and 1 + * for the "option 1" mapping where QSPI is at address 0. + * + * Effectively we need to swap around the "upstream" ends of + * MPC 0 and MPC 1. + */ + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + int i; + + if (mmc->fpga_type != FPGA_AN524) { + return; + } + + memory_region_transaction_begin(); + for (i = 0; i < 2; i++) { + TZMPC *mpc = &mms->mpc[i]; + MemoryRegion *upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); + hwaddr addr = (i ^ map) ? 0x28000000 : 0; + + memory_region_set_address(upstream, addr); + } + memory_region_transaction_commit(); +} + +static void remap_irq_fn(void *opaque, int n, int level) +{ + MPS2TZMachineState *mms = opaque; + + remap_memory(mms, level); +} + static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) @@ -711,7 +767,7 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); for (p = mmc->raminfo; p->name; p++) { - if (p->base == 0) { + if (p->base == boot_mem_base(mms)) { return p->size; } } @@ -1095,6 +1151,16 @@ static void mps2tz_common_init(MachineState *machine) create_non_mpc_ram(mms); + if (mmc->fpga_type == FPGA_AN524) { + /* + * Connect the line from the SCC so that we can remap when the + * guest updates that register. + */ + mms->remap_irq = qemu_allocate_irq(remap_irq_fn, mms, 0); + qdev_connect_gpio_out_named(DEVICE(&mms->scc), "remap", 0, + mms->remap_irq); + } + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, boot_ram_size(mms)); } @@ -1117,12 +1183,47 @@ static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, *iregion = region; } +static char *mps2_get_remap(Object *obj, Error **errp) +{ + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); + const char *val = mms->remap ? "QSPI" : "BRAM"; + return g_strdup(val); +} + +static void mps2_set_remap(Object *obj, const char *value, Error **errp) +{ + MPS2TZMachineState *mms = MPS2TZ_MACHINE(obj); + + if (!strcmp(value, "BRAM")) { + mms->remap = false; + } else if (!strcmp(value, "QSPI")) { + mms->remap = true; + } else { + error_setg(errp, "Invalid remap value"); + error_append_hint(errp, "Valid values are BRAM and QSPI.\n"); + } +} + +static void mps2_machine_reset(MachineState *machine) +{ + MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); + + /* + * Set the initial memory mapping before triggering the reset of + * the rest of the system, so that the guest image loader and CPU + * reset see the correct mapping. + */ + remap_memory(mms, mms->remap); + qemu_devices_reset(); +} + static void mps2tz_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); mc->init = mps2tz_common_init; + mc->reset = mps2_machine_reset; iic->check = mps2_tz_idau_check; } @@ -1225,6 +1326,11 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) mmc->raminfo = an524_raminfo; mmc->armsse_type = TYPE_SSE200; mps2tz_set_default_ram_info(mmc); + + object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); + object_class_property_set_description(oc, "remap", + "Set memory mapping. Valid values " + "are BRAM (default) and QSPI."); } static void mps3tz_an547_class_init(ObjectClass *oc, void *data) From patchwork Mon May 10 12:25:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433131 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp2805356jao; Mon, 10 May 2021 05:45:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgvh4wiqLlelZ62eTgazTZpv6A4BrhahYbck+ny7bbk+OIAdhkSRg1kCmp+BNXLcXr4CJT X-Received: by 2002:a05:6638:1928:: with SMTP id p40mr21989689jal.22.1620650707529; Mon, 10 May 2021 05:45:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620650707; cv=none; d=google.com; s=arc-20160816; b=tub9oE6rouITWQSvKRHzN1qELwZ5O5cgln5YEVFBD0Dg2wIB4xjS6epJQjLaj23RZR eCkAf6cQEsPiNp7Xt1VH7y/0TXHPR2hjCQ4D5nFQxZ2K1X4K8zKo0GOz3kGQHQEqVT69 vOn/3FxdlVupg7AzYgvn6fvOz0E8MiCbowL1+f6MJAipiahuI9dvShD5DMxQkFFPwU51 mM1D7anvC2oack/s9cE0Sd5ah1yKL/3VvVKa9CgLuh/Mk/bXSJp9Yf5tyxaxnIdN6+w0 XBgtFNsf2zMvAMgIiQwqVoZSh3Vk3gGFX62I2tKCKOEZjT1io9udykaTAZ81J9cuDOUi CBRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CpwUsW78mEI5XjMCiM9bT5wLiUV9J5cA8qAnD0ZM2bc=; b=VhvCccyQBoRyPFUdn+NY+rVDi9I9BMRy5PgdAXEunoaS9d0FnsR9xB+W9uyWfWYS7f 0aEr3e1AQ5BEWde/BEFe1zBmb7xakoCV+qp4CjsQQq8T5vLTAHbNMD5/8hF0DORj9DAk AMslbjpvrDJ46dUQoZNLcrAbHzd0W/YQ0U9aNafEQLL75UqqmGahLlMZZhM/ghwYeoGt LxsEDD1aaNsx87zQ/7yS9qjnBviOsqpDTr53MoLUZnXQDRT+NvNbuw8UwExgy4Cl0S3f u6C3DPP+qI07Q78lxEKxg59AZtfwqhw4eUlheOiDvvWd+ttOD6f7IOfkjN9lZTl6+/fx bhMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zmlGde6Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a5si16684624ilv.74.2021.05.10.05.45.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 05:45:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zmlGde6Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lg5HX-0003wa-0E for patch@linaro.org; Mon, 10 May 2021 08:45:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37720) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lg4zE-0006Tg-8n for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:12 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:41961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lg4zB-0003Jl-2o for qemu-devel@nongnu.org; Mon, 10 May 2021 08:26:11 -0400 Received: by mail-wr1-x42e.google.com with SMTP id d11so16410471wrw.8 for ; Mon, 10 May 2021 05:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CpwUsW78mEI5XjMCiM9bT5wLiUV9J5cA8qAnD0ZM2bc=; b=zmlGde6ZSO/yhD7Ev8OVqXW/N+GKPRF4BFHfYq05t0qw3TCizhbM3DdPHp7ZudZN3D t/kfkNZGLf79HNjdbfYUIlo40nR8lz0mlrB0hWrleDVVRRD49WSs82TxIXMK2Dmq+OYJ LGpn9qAzlL9+Jrx6zegHHuda63zOugBrxtgrUY3M3IogwJP/PPabOrcZK/k+sPpcL/x8 Yvl0PqmGRWyXfdtzAyxgQ+whXbQOOSEs3dUstZzbkHCKhhoCi5lrtgLJMDddyC5NLdsr PoDqlOUMpHzLtglPIkuPEd78GOcxQNhS7kLx80xl/hePPGEGNVNuTqiHhBNu9V3Amtch RCeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CpwUsW78mEI5XjMCiM9bT5wLiUV9J5cA8qAnD0ZM2bc=; b=dOhW2Jw8ygThfApRcm2ImGc30DD06mn6JlrfPv8lyzC15d9GYadAurnGknlBbKpOUE aSokrZzQKv3vIFfQUF4VLx3yVqxqDsH1Ft6wCJ6BWxhfyPKe3RqQO9LcWPoMDnBnKW/d Aq8K6+fVlEWhPNe5zv/8pxq9fHati2DObNUEbmStKZNLbv0lS9wGs3Fnakjk5XoqdaaH 3i3ZnbekDS57Q9Jg7Qt59oSmsQnJO+m34IZkVnEybAxzZtHOerRYZ8lFsYTQ96oHk83D GRmDmHIMITsf2opVmShY2MqWB1wcjwj97f1ixVw/C+uGQ3Hp33lQ+DYk+/utprSg+INE 4ILg== X-Gm-Message-State: AOAM5329TI+D8+wbD/c/dmnr/TAlytxYkb4/qSACn725MKhIBvf53b4E l2lpjLhC8AE2tVbbzE4fYjfG3yQ17mBNDg== X-Received: by 2002:a5d:678d:: with SMTP id v13mr29614024wru.85.1620649567709; Mon, 10 May 2021 05:26:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d9sm22749897wrp.47.2021.05.10.05.26.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 05:26:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/26] hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9 Date: Mon, 10 May 2021 13:25:48 +0100 Message-Id: <20210510122548.28638-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122548.28638-1-peter.maydell@linaro.org> References: <20210510122548.28638-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Guenter Roeck Commit dfc388797cc4 ("hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23") configured the PHY address for xilinx-zynq-a9 to 23. When trying to boot xilinx-zynq-a9 with zynq-zc702.dtb or zynq-zc706.dtb, this results in the following error message when trying to use the Ethernet interface. macb e000b000.ethernet eth0: Could not attach PHY (-19) The devicetree files for ZC702 and ZC706 configure PHY address 7. The documentation for the ZC702 and ZC706 evaluation boards suggest that the PHY address is 7, not 23. Other boards use PHY address 0, 1, 3, or 7. I was unable to find a documentation or a devicetree file suggesting or using PHY address 23. The Ethernet interface starts working with zynq-zc702.dtb and zynq-zc706.dtb when setting the PHY address to 7, so let's use it. Cc: Bin Meng Signed-off-by: Guenter Roeck Reviewed-by: Bin Meng Acked-by: Edgar E. Iglesias Message-id: 20210504124140.1100346-1-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 85f25d15dbf..81af32dc428 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -118,7 +118,7 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) qemu_check_nic_model(nd, TYPE_CADENCE_GEM); qdev_set_nic_properties(dev, nd); } - object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); + object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, base);