From patchwork Mon May 10 19:08:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433168 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3128174jao; Mon, 10 May 2021 12:13:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyaEgeLqIMiH7EjZiHXaGwlEeOYdAUq7rp1GGxQwTWIxYjpN+jJE0W/uJoM3Fwu7amC7H16 X-Received: by 2002:a92:cd85:: with SMTP id r5mr22884604ilb.169.1620673992897; Mon, 10 May 2021 12:13:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620673992; cv=none; d=google.com; s=arc-20160816; b=dnXwfjW6DJVbQOiBLmxMYZP6Nkn/GSx9bYNq3QPRAHAOipJjLpDct4dAjWhbgUKV7V Ru6kdtMASEf3jEryxLa0pMsd6S3bHp0/OSTnB+vQpMaScV79+xcCqWcEEnGpsXfmzvQL Jcu1wM74vh7f2MEPgrJ9WrscTZ2FzPMpwIdPiBXX2Stm9Ij2DXK7epvwkpilFO7N2VTM 5mB2NuljisKoWeRANnrsyRU39iiDzb5w8pivMxaGdPEMFBGxBATroB7/F/nfb1VDcrUk S9tZt8WcJhadzT80outq6mFjg3idxZsUlrSSWIT1x93Rae/MWQsO5GYL6vGra7S6AqxK K5Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IA8v2i4O86UnUvs9gQRCAZoRczka9Szx0p0QDCUmjDk=; b=c1kCD4jujVfWyaxuVoqa9Cu/FsIkDdx3+ApfejHXplHe0gH1j5LShHMbyl+ifY59Tz FKukbs5iLAtGzV2jDQZ0Jjt65CRXCl3u3/clj50u3ordOYpfkONgzByekJHajPY/bMVU /hbndeWH27au6RLV29X3k08GdZ2PTM3x10MaQAlDX+cWXC4BQXyLn+UlBibQ7ged9nVQ VIwkKpNFdmjqh4y125ia90kzgmTuD9qzbY6PpY/xTURqn/pb+/hDCcaQdtVIbgw8386q JLrahQK8yBfSvcynntxfPNvqiqUNmCwVOLdTbtrTYt4PZ0WAaqMRWsJVgH5ONWS5aI8m ywnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QIny4iol; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i21si22511643iov.29.2021.05.10.12.13.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 May 2021 12:13:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QIny4iol; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lgBL6-0005ua-9p for patch@linaro.org; Mon, 10 May 2021 15:13:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lgBGv-0000Y4-MK for qemu-devel@nongnu.org; Mon, 10 May 2021 15:08:53 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:38882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lgBGs-0004wY-Bu for qemu-devel@nongnu.org; Mon, 10 May 2021 15:08:53 -0400 Received: by mail-wr1-x42f.google.com with SMTP id l14so17735409wrx.5 for ; Mon, 10 May 2021 12:08:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IA8v2i4O86UnUvs9gQRCAZoRczka9Szx0p0QDCUmjDk=; b=QIny4iolu9yKKYUTFrdgum0Gv26tKcGF4dPMa59+N/QGC1WPIJOfjMKMLbqX8Zt7Kw shW6eIHUnSgzezRhr/ejiVXYAv6dNKCiYi0wzYzx31oSmCQ4jquzI+1/7oQwq1JgfPFN CeF8dv3rXNE6Z/vTQaqAVYLfotKJ5V8zP2lZgshbJayss9E2JjWLka8f/pk+kf81Ka8k ft9KGnOPHfrb0liIBk+/+SdQ2pccSmO0yQt5uqUgjbT7o04XOoVOJRNFrI7vCX7Sugob NijMVUpiW/UAJtto4vZILd3cvE5ZvjTPpjIWIVQPZpI+1J6bGm8YtsEaxFdAYKixdJaW X2tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IA8v2i4O86UnUvs9gQRCAZoRczka9Szx0p0QDCUmjDk=; b=hPn9wCOCleAMSiAS2pr39tEgRyMhR9D/gITEES8ITpwQTgimWPnNi3/SrsU9iwPhq3 Z+QpnoRdIcjynHaiZcQ4AlWmJqkmu+w4hSC/L9YS8kSk9GLqX9x/EONuWhrDfDRXSe/5 /x7ZIGXwl46iylhrEHEfFqFhbHhraeo/PVQGHQ7EP3h0MW8+FnkMuJn/W3248nvrTeCt hnS6CWdMIkMXufQvfFf7oiW8TM6IRExjKPtdfwynu9p5SL8CaubnnxHyNdAawMkZBHpo 9DUIw+mq9DPJ/4ZfjNtoglm4cx1NKyEs1I4LAop8egBHb5sUotf8GEPwV+3OApmQv1QZ DLSQ== X-Gm-Message-State: AOAM532IVIvRMJDltRYF5NlsSW4Y+rQqU66Eg8ducZklPFoDbD78BDOV 6ilGW0x6PjWoTwMdzwhpSjuqqQ== X-Received: by 2002:a5d:54c2:: with SMTP id x2mr31703446wrv.278.1620673728710; Mon, 10 May 2021 12:08:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id t23sm463892wmj.31.2021.05.10.12.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 12:08:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/6] hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524 Date: Mon, 10 May 2021 20:08:39 +0100 Message-Id: <20210510190844.17799-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510190844.17799-1-peter.maydell@linaro.org> References: <20210510190844.17799-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Jimmy Brisson , Kevin Townsend , Devaraj Ranganna Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model it that way in hw/arm/armsse.c (along with the associated MPCs). We incorrectly also added an entry to the RAMInfo array for the AN524 in hw/arm/mps2-tz.c, which was pointless because the CPU would never see it. Delete it. The bug had no guest-visible effect because devices in the SSE-200 take priority over those in the board model (armsse.c maps s->board_memory at priority -2). Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 70aa31a7f6c..77ff83acb06 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -243,19 +243,13 @@ static const RAMInfo an524_raminfo[] = { { .size = 512 * KiB, .mpc = 0, .mrindex = 0, - }, { - .name = "sram", - .base = 0x20000000, - .size = 32 * 4 * KiB, - .mpc = -1, - .mrindex = 1, }, { /* We don't model QSPI flash yet; for now expose it as simple ROM */ .name = "QSPI", .base = 0x28000000, .size = 8 * MiB, .mpc = 1, - .mrindex = 2, + .mrindex = 1, .flags = IS_ROM, }, { .name = "DDR", From patchwork Mon May 10 19:08:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433167 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3127362jao; Mon, 10 May 2021 12:12:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOfQGc3UIvaCMDVJkXf09BT/Sejm1ejCxaDxUy8GJJ1/1L3d7cqsiqQfQ7j6irnzl+w/x/ X-Received: by 2002:a92:d242:: with SMTP id v2mr22924183ilg.135.1620673926912; Mon, 10 May 2021 12:12:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620673926; cv=none; d=google.com; s=arc-20160816; b=ARdwHHcf5XtPK9x2eyneyKs5UQqfpqcRaYNa1w0i/HuIeANnTgOQfE0+Aq9PX8IvtG o4PnObY0xH9TmnA7ytc6q00cKk6nvAmLwjEJdxMzzBcJKttOelTgFI0gp54n9TcFi3aW K2ayJMpCs2/+GEn+ZLbQcXiS7BZr2125UhfVqBWZV6qE3QZ4KYh0GZcJ30gX8DWnr2r0 HMXc+EIv31PFbcxGuCON+fMtqyyjiWn6J57AkLpr8ijZkXfn+37ZGhDnl9WWWy2xbKDP S3t6aXjCSFBpIMwUkmEbZLRk2r9q71JfrYxoXy0+chXBo8ikfLwuSL79GLSiMEgTO0NE pd4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0bAVgHwIjQtf8To6Si8JBYpO2wJiNylkQh5/jVI8Anc=; b=n6nw36w3fijiwoN5AWXl5fYq99cqRqw4nuyZNb9igjDdu+21D3QxJdILOKooQaFURD wQJVJUnBgkZA90wm9MK8sidV8/1b4x4eafzoxTYCasQ7p/MqmORtYQ1bIPDtYfOFF/+5 rbxFo6mBE4L0gDQkcdSC/LZsGv62GFj0FCbnOIWQYU0/ap8WvILFzvPoA8flXxAyjyjB Zo1l2Nq+tOP2zp9A8dOPOectljL8M9nEMqC8IhdW7EU0fYb5uv2FBD/3nsWw4MHHDeX5 onGg2wpTu7Yh7HuxRSw0p4Xs0nlW7OlacFTsUOd5QcXM9Rea5sA9j9Sb5I+5utBdiL6+ /YAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JP94KqFZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t23sm463892wmj.31.2021.05.10.12.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 12:08:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/6] hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific Date: Mon, 10 May 2021 20:08:40 +0100 Message-Id: <20210510190844.17799-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510190844.17799-1-peter.maydell@linaro.org> References: <20210510190844.17799-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Jimmy Brisson , Kevin Townsend , Devaraj Ranganna Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN547 sets the SRAM_ADDR_WIDTH for the SSE-300 to 21; since this is not the default value for the SSE-300, model this in mps2-tz.c as a per-board value. Reported-by: Devaraj Ranganna Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 77ff83acb06..f2595b1c7f7 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -123,6 +123,7 @@ struct MPS2TZMachineClass { int numirq; /* Number of external interrupts */ int uart_overflow_irq; /* number of the combined UART overflow IRQ */ uint32_t init_svtor; /* init-svtor setting for SSE */ + uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ const RAMInfo *raminfo; const char *armsse_type; }; @@ -806,6 +807,7 @@ static void mps2tz_common_init(MachineState *machine) OBJECT(system_memory), &error_abort); qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); + qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); @@ -1263,6 +1265,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->numirq = 92; mmc->uart_overflow_irq = 47; mmc->init_svtor = 0x10000000; + mmc->sram_addr_width = 15; mmc->raminfo = an505_raminfo; mmc->armsse_type = TYPE_IOTKIT; mps2tz_set_default_ram_info(mmc); @@ -1290,6 +1293,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->numirq = 92; mmc->uart_overflow_irq = 47; mmc->init_svtor = 0x10000000; + mmc->sram_addr_width = 15; mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type = TYPE_SSE200; mps2tz_set_default_ram_info(mmc); @@ -1317,6 +1321,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) mmc->numirq = 95; mmc->uart_overflow_irq = 47; mmc->init_svtor = 0x10000000; + mmc->sram_addr_width = 15; mmc->raminfo = an524_raminfo; mmc->armsse_type = TYPE_SSE200; mps2tz_set_default_ram_info(mmc); @@ -1349,6 +1354,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) mmc->numirq = 96; mmc->uart_overflow_irq = 48; mmc->init_svtor = 0x00000000; + mmc->sram_addr_width = 21; mmc->raminfo = an547_raminfo; mmc->armsse_type = TYPE_SSE300; mps2tz_set_default_ram_info(mmc); From patchwork Mon May 10 19:08:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433171 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3131125jao; Mon, 10 May 2021 12:17:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyS9brx3UsyaK4myB0+T4MBM0oKiib69ILZDEL57kb3eUKv8i/DoN5QuJVX+46k9nFCUDE1 X-Received: by 2002:a5d:8e08:: with SMTP id e8mr19419055iod.47.1620674237767; Mon, 10 May 2021 12:17:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620674237; cv=none; d=google.com; s=arc-20160816; b=MbEhgV99jIqOk5cfUrHZHvQ4dxHp5AhwmFLWv9z35rHC44GeMLK20Lc7G2went74Un xhE9dDlyegX+3ViwJCyhcLYDuO1tl82GS+m/+ToY99GqYJ1T/bppzqifH6Frini0t2KL 9uF7flggGkkYPlLl3KuROvRyzY+gFpONyenpUhXFL91zP6RowZs+zqK7xnluh2AeX47X AG2lfFQwU1+SAH6FopFrV0qp/a/YJaUwjJlVN8aNdp6iCw94WJkamSFdnYImfKendrca YRgE6J6gXvJCo6S2N5ZZT3Q/yYHDTWuz6JSzCKTk861Upe6rQM0aArB/4fguszaUKjX/ 3OlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ad4UlI6darwKHtTKEKCPbY9frkKNCFD/9SwZN13PKXc=; b=bvcwJuoZlZUP3osAthWQFybf9HQRqz1mqsNOPnKGq8d25SxNJhhz/pZPSuc7qpfEke l7l3q2oojqfYYFsXXPHAUzAqZiMS5dxYxzdXowp/jNYWnXIr9WlV/mrS1ANkFg27idfa zfdwpWT1F2OOH630pqXPeRtQ1fZzHKlnvCseDeLlEW7dI9vdBJJDmBDQ/tGUmvauVxcL aFveuTFBX0dxHzZzADZd8QlQjZB/5dtv7UwC/zRYg40BQCe2D/lrrTnHLacqlZTy7WvR JOc9zUV68q+WfZ9F0ol//WXI8Uxu6A3lduAsgA6JlMHNLi/WhWTIU7XeoJ8yKDUzIFhb EHfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UQfG965V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t23sm463892wmj.31.2021.05.10.12.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 12:08:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/6] hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs Date: Mon, 10 May 2021 20:08:41 +0100 Message-Id: <20210510190844.17799-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510190844.17799-1-peter.maydell@linaro.org> References: <20210510190844.17799-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Jimmy Brisson , Kevin Townsend , Devaraj Ranganna Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The SSE-300 was not correctly modelling its internal SRAMs: * the SRAM address width default is 18 * the SRAM is mapped at 0x2100_0000, not 0x2000_0000 like the SSE-200 and IoTKit The default address width is no longer guest-visible since our only SSE-300 board sets it explicitly to a non-default value, but following the hardware's default will help for any future boards we need to model. Reported-by: Devaraj Ranganna Signed-off-by: Peter Maydell --- hw/arm/armsse.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2e5d0679e7b..1729f09c7cb 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -59,6 +59,7 @@ struct ARMSSEInfo { const char *cpu_type; uint32_t sse_version; int sram_banks; + uint32_t sram_bank_base; int num_cpus; uint32_t sys_version; uint32_t iidr; @@ -102,7 +103,7 @@ static Property sse300_properties[] = { DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 18), DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), @@ -504,6 +505,7 @@ static const ARMSSEInfo armsse_variants[] = { .sse_version = ARMSSE_IOTKIT, .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), .sram_banks = 1, + .sram_bank_base = 0x20000000, .num_cpus = 1, .sys_version = 0x41743, .iidr = 0, @@ -523,6 +525,7 @@ static const ARMSSEInfo armsse_variants[] = { .sse_version = ARMSSE_SSE200, .cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"), .sram_banks = 4, + .sram_bank_base = 0x20000000, .num_cpus = 2, .sys_version = 0x22041743, .iidr = 0, @@ -542,6 +545,7 @@ static const ARMSSEInfo armsse_variants[] = { .sse_version = ARMSSE_SSE300, .cpu_type = ARM_CPU_TYPE_NAME("cortex-m55"), .sram_banks = 2, + .sram_bank_base = 0x21000000, .num_cpus = 1, .sys_version = 0x7e00043b, .iidr = 0x74a0043b, @@ -1161,7 +1165,7 @@ static void armsse_realize(DeviceState *dev, Error **errp) /* Map the upstream end of the MPC into the right place... */ sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]); memory_region_add_subregion(&s->container, - 0x20000000 + i * sram_bank_size, + info->sram_bank_base + i * sram_bank_size, sysbus_mmio_get_region(sbd_mpc, 1)); /* ...and its register interface */ memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000, From patchwork Mon May 10 19:08:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433169 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3129139jao; Mon, 10 May 2021 12:14:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzA28/f1MVZ01FGsgruyS7NERlAeg6NDXOQc89z8+NnJ4WyEbPL9OLMH354zLKy5cqlSLaJ X-Received: by 2002:a5e:c00e:: with SMTP id u14mr16269589iol.106.1620674076802; Mon, 10 May 2021 12:14:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620674076; cv=none; d=google.com; s=arc-20160816; b=iBtRktTswlF5LtpMcmnfhBqvqGpObTV4WyUdRYhhySDczNjuhnuUaIJ0ez3/9pkHPE MIzg/0bcHjBEOzJgdhHrHhis1IkrI/FzN5tnJGQEsmHscFdJGTNC+9GMu2MmFTRMiyTi VHKpnEXeE2gw1iZR3VPnK4C1z5XCqh4JDC48apktKS22gGi6MOZOc5CGRLI1Za30IqYK Ex0h6TMfqot346P2K2SBuJ25t5UQD9WgHnbonMIyxBflgRSo//jk45yGvgBWq/z9QgC2 tS3V6hJydb48RmNDBM3GG9v94+9rNttGmSStroVhkemDgh2sSY9UFijgCH0WpjalGklb VuLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NPiCr7uH0qLtwDI+9ztTOX0+Iqb2mkfB6dk1TyXG9m0=; b=kOQBxe7rWEW0gdWKewYsMG2tz82tK83gE9EVL3KAIHzty+FGYBk4d10Y+OGRUUAyeB b0btcWJhmo5qqDqpXlpwFopKm04LgU+LdODIcv8M5E4r14Bzi6rrz1OXilwuf2OS84zF ZkAxHn67RJ8GUppQSyLTmh5/sUIwOgH6As1Yf9NiErrt0PHEXFdBRC/Ekify4Imb3tFn Dd6JVRp+idL9OR7HhPdykaqOtnvXJ2fk95myywOcLnldnyWmEV3/PXX8tHrmUI4bqHQj /mDxEIStalTQjBOUcyXC3+q+G3XSy5GqrYVq3ng4aeqtrzB2qWgAzhbJ4m9HsBDYj8yR K+6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Llstzy4h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t23sm463892wmj.31.2021.05.10.12.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 12:08:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/6] hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD Date: Mon, 10 May 2021 20:08:42 +0100 Message-Id: <20210510190844.17799-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510190844.17799-1-peter.maydell@linaro.org> References: <20210510190844.17799-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Jimmy Brisson , Kevin Townsend , Devaraj Ranganna Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Convert armsse_realize() to use ERRP_GUARD(), following the rules in include/qapi/error.h. Signed-off-by: Peter Maydell --- We'll be adding a new error check in the next patch, so do this first to avoid adding more uses of legacy error_propagate(). --- hw/arm/armsse.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 1729f09c7cb..be5aa1f113a 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -913,7 +913,6 @@ static void armsse_realize(DeviceState *dev, Error **errp) const ARMSSEDeviceInfo *devinfo; int i; MemoryRegion *mr; - Error *err = NULL; SysBusDevice *sbd_apb_ppc0; SysBusDevice *sbd_secctl; DeviceState *dev_apb_ppc0; @@ -922,6 +921,8 @@ static void armsse_realize(DeviceState *dev, Error **errp) DeviceState *dev_splitter; uint32_t addr_width_max; + ERRP_GUARD(); + if (!s->board_memory) { error_setg(errp, "memory property was not set"); return; @@ -1151,10 +1152,9 @@ static void armsse_realize(DeviceState *dev, Error **errp) uint32_t sram_bank_size = 1 << s->sram_addr_width; memory_region_init_ram(&s->sram[i], NULL, ramname, - sram_bank_size, &err); + sram_bank_size, errp); g_free(ramname); - if (err) { - error_propagate(errp, err); + if (*errp) { return; } object_property_set_link(OBJECT(&s->mpc[i]), "downstream", From patchwork Mon May 10 19:08:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433170 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3129171jao; Mon, 10 May 2021 12:14:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyu6NllCKFXadus7vSABfOvIjfST9dhnSPh9ZVHukLLmxONZPB3fQNAO/+mPxQKuiFFTDOj X-Received: by 2002:a05:6e02:ec9:: with SMTP id i9mr11916698ilk.273.1620674080397; Mon, 10 May 2021 12:14:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620674080; cv=none; d=google.com; s=arc-20160816; b=vmz43It93/VBayoHO3AVUh5SvYLbmGW4W2SWq9mY8MgNiydh+EedxBAaozE1qehOys QxTrSfVFAH4A6RKjFrBjelRrz1PF12YwRXLoGwj8yjpMxYL6WI9CeSUUlnf7AzLFLTmq CPu6bujhNHj/vpqSxkFXuyy6zUV0KG2XQ/pnjTL6/aWnPwyiJu+1oLBPyETCry/IUl11 WoXwA2A4r8h+xTTr/p3j5/QTfhi0yi50/sX8efO+BunbjAgcJzBBZInipM48/CIh972P nB+N6S91cjtUndhEOUiPdO4i2Wgdha4qGqGVz60wp22P6qbHJFGaM/YCstb7Ce6D1PVo 9bvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xPwV84wK51NRUaX+1XqI0uenRCE3AdgkV7fRnhwYUkk=; b=kuN/FlZFCKglKfyINcVJ15dZWLnmojKjrxlfY2x2v70qO9soW35gYmCd/lI6PIZdHJ XcArUUnppKwJDkTXi03kyH2h50aes89KaQf7PQuoGC0XNDPkY+wbT177qdpLZyT8zNhP 4x0g1wAU6YcU7r9wFm+gvjAw75FUUsZQr8bQPlaKU1miygWEFHK37wLwZR9+F6gVpFDi MvTFSL7fsFKXNsF9iwYrxs1Ob3LSA55zRjkPHb4rBqi8rcaFFFoValokdB6ru1g+2+rV EaqFcRwxkXM/ymEpG2/ch9R5zuOFy1hwM2LDSnhD1BcxMwfv/EpoWeWvchw2vmyHCU3F E0rA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ifHqjlt5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t23sm463892wmj.31.2021.05.10.12.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 12:08:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/6] hw/arm/mps2-tz: Allow board to specify a boot RAM size Date: Mon, 10 May 2021 20:08:43 +0100 Message-Id: <20210510190844.17799-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510190844.17799-1-peter.maydell@linaro.org> References: <20210510190844.17799-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Jimmy Brisson , Kevin Townsend , Devaraj Ranganna Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently we model the ITCM in the AN547's RAMInfo list. This is incorrect because this RAM is really a part of the SSE-300. We can't just delete it from the RAMInfo list, though, because this would make boot_ram_size() assert because it wouldn't be able to find an entry in the list covering guest address 0. Allow a board to specify a boot RAM size manually if it doesn't have any RAM itself at address 0 and is relying on the SSE for that, and set the correct value for the AN547. The other boards can continue to use the "look it up from the RAMInfo list" logic. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index f2595b1c7f7..8d921afec14 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -126,6 +126,7 @@ struct MPS2TZMachineClass { uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ const RAMInfo *raminfo; const char *armsse_type; + uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ }; struct MPS2TZMachineState { @@ -761,6 +762,14 @@ static uint32_t boot_ram_size(MPS2TZMachineState *mms) const RAMInfo *p; MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + /* + * Use a per-board specification (for when the boot RAM is in + * the SSE and so doesn't have a RAMInfo list entry) + */ + if (mmc->boot_ram_size) { + return mmc->boot_ram_size; + } + for (p = mmc->raminfo; p->name; p++) { if (p->base == boot_mem_base(mms)) { return p->size; @@ -1268,6 +1277,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->sram_addr_width = 15; mmc->raminfo = an505_raminfo; mmc->armsse_type = TYPE_IOTKIT; + mmc->boot_ram_size = 0; mps2tz_set_default_ram_info(mmc); } @@ -1296,6 +1306,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->sram_addr_width = 15; mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type = TYPE_SSE200; + mmc->boot_ram_size = 0; mps2tz_set_default_ram_info(mmc); } @@ -1324,6 +1335,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void *data) mmc->sram_addr_width = 15; mmc->raminfo = an524_raminfo; mmc->armsse_type = TYPE_SSE200; + mmc->boot_ram_size = 0; mps2tz_set_default_ram_info(mmc); object_class_property_add_str(oc, "remap", mps2_get_remap, mps2_set_remap); @@ -1357,6 +1369,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) mmc->sram_addr_width = 21; mmc->raminfo = an547_raminfo; mmc->armsse_type = TYPE_SSE300; + mmc->boot_ram_size = 512 * KiB; mps2tz_set_default_ram_info(mmc); } From patchwork Mon May 10 19:08:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 433172 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3134463jao; Mon, 10 May 2021 12:22:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7TpHYJtmzfgsLkttLEfSIZnpN/7JZse9Uf1xI8+CipTAd/uNG4CejH414YYiEjjap2NcM X-Received: by 2002:a92:c746:: with SMTP id y6mr23493456ilp.30.1620674525793; Mon, 10 May 2021 12:22:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620674525; cv=none; d=google.com; s=arc-20160816; b=o/9NM6TMw5d6p93Lp4oVZqnUKxHM/CdTfRN+PmIgULoo1cmQ1OnZBXLQB8PuqwZGs9 W58l/EfBjxf0U+TFWFDcXUuvxjkYLHHLBhRUhGHdoK0QQ9Xk+1d1/aK4cE4JCxN4xknR T/GsCqAon/rfZwRIQElxIeRWrMIvXXk9S9i0nXJGm+YEZE9YsHxjjzwrgqUIQTzMP6Yn LaqNspj+8Mit7ZkDx1JADHQKbFqq66CG3rhw1epi7ud1EJv3P4MWmTMrEF46cScYWCrt b4VQXEFV25WVS6f9rP5cnN1vfBZvsWEbqP5y1Mnc/NU4G6GKtC7tNDm0y/SdCFZLaxXB kx+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jPFTO/Pkb0tpTTdt3nZWuAHHHRL642BlgSkp2Crh+Tw=; b=FO8Z19lA9kLh1saiUglz+Xs3XzxNDB24SBg+l7GI2UbE94yrbq/zaSict/TZANM8In Y+Wso5vOnD1PrYYwjSTmgvWjdsqBkDEScUgGL0iJA1h0J1x/7w/aHZZOdLN9/pg1RBhK xPSUpz51Ix3Y/mXbX9FPfVarnSG3OA2G3bY0XDMvA+DK4Mzd048KkYyeJOa5774B/mom 2E9gCa3pRHzrLWvFHTZaP5ubFzdQV3OAOK1ZFkM1oGetAtELVZQYsLrVoodNJZf9B2sg DGyzfabt8g7qNQxuK8MJ0ejhiJh5LNgOD9W0+j5mGLOun/qd5CreZLkpnFY78JqioGj9 JOVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=R7JhgUnc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id t23sm463892wmj.31.2021.05.10.12.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 12:08:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 6/6] hw/arm: Model TCMs in the SSE-300, not the AN547 Date: Mon, 10 May 2021 20:08:44 +0100 Message-Id: <20210510190844.17799-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510190844.17799-1-peter.maydell@linaro.org> References: <20210510190844.17799-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Jimmy Brisson , Kevin Townsend , Devaraj Ranganna Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000. Currently we model these in the AN547 board, but this is conceptually wrong, because they are a part of the SSE-300 itself. Move the modelling of the TCMs out of mps2-tz.c into sse300.c. This has no guest-visible effects. Signed-off-by: Peter Maydell --- include/hw/arm/armsse.h | 2 ++ hw/arm/armsse.c | 19 +++++++++++++++++++ hw/arm/mps2-tz.c | 12 ------------ 3 files changed, 21 insertions(+), 12 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 36592be62c5..9648e7a4193 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -198,6 +198,8 @@ struct ARMSSE { MemoryRegion alias2; MemoryRegion alias3[SSE_MAX_CPUS]; MemoryRegion sram[MAX_SRAM_BANKS]; + MemoryRegion itcm; + MemoryRegion dtcm; qemu_irq *exp_irqs[SSE_MAX_CPUS]; qemu_irq ppc0_irq; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index be5aa1f113a..a1456cb0f42 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -13,6 +13,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qemu/bitops.h" +#include "qemu/units.h" #include "qapi/error.h" #include "trace.h" #include "hw/sysbus.h" @@ -70,6 +71,7 @@ struct ARMSSEInfo { bool has_cpuid; bool has_cpu_pwrctrl; bool has_sse_counter; + bool has_tcms; Property *props; const ARMSSEDeviceInfo *devinfo; const bool *irq_is_common; @@ -516,6 +518,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_cpuid = false, .has_cpu_pwrctrl = false, .has_sse_counter = false, + .has_tcms = false, .props = iotkit_properties, .devinfo = iotkit_devices, .irq_is_common = sse200_irq_is_common, @@ -536,6 +539,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_cpuid = true, .has_cpu_pwrctrl = false, .has_sse_counter = false, + .has_tcms = false, .props = sse200_properties, .devinfo = sse200_devices, .irq_is_common = sse200_irq_is_common, @@ -556,6 +560,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_cpuid = true, .has_cpu_pwrctrl = true, .has_sse_counter = true, + .has_tcms = true, .props = sse300_properties, .devinfo = sse300_devices, .irq_is_common = sse300_irq_is_common, @@ -1214,6 +1219,20 @@ static void armsse_realize(DeviceState *dev, Error **errp) sysbus_mmio_get_region(sbd, 1)); } + if (info->has_tcms) { + /* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000 */ + memory_region_init_ram(&s->itcm, NULL, "sse300-itcm", 512 * KiB, errp); + if (*errp) { + return; + } + memory_region_init_ram(&s->dtcm, NULL, "sse300-dtcm", 512 * KiB, errp); + if (*errp) { + return; + } + memory_region_add_subregion(&s->container, 0x00000000, &s->itcm); + memory_region_add_subregion(&s->container, 0x20000000, &s->dtcm); + } + /* Devices behind APB PPC0: * 0x40000000: timer0 * 0x40001000: timer1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 8d921afec14..e23830f4b7d 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -265,23 +265,11 @@ static const RAMInfo an524_raminfo[] = { { }; static const RAMInfo an547_raminfo[] = { { - .name = "itcm", - .base = 0x00000000, - .size = 512 * KiB, - .mpc = -1, - .mrindex = 0, - }, { .name = "sram", .base = 0x01000000, .size = 2 * MiB, .mpc = 0, .mrindex = 1, - }, { - .name = "dtcm", - .base = 0x20000000, - .size = 4 * 128 * KiB, - .mpc = -1, - .mrindex = 2, }, { .name = "sram 2", .base = 0x21000000,