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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id q19sm1091660lff.16.2021.05.10.14.37.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 14:37:22 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa , Arnd Bergmann , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 2/3] crypto: ixp4xx: Add DT bindings Date: Mon, 10 May 2021 23:36:33 +0200 Message-Id: <20210510213634.600866-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210510213634.600866-1-linus.walleij@linaro.org> References: <20210510213634.600866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the ixp4xx crypto engine. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- Herbert, David: This can be applied separately once we are happy with the bindings, alternatively it can be merged with the support code into ARM SoC. --- .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml new file mode 100644 index 000000000000..28d75f4f9a76 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2018 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx cryptographic engine + +maintainers: + - Linus Walleij + +description: | + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE + (Network Processing Engine). Since it is not a device on its own + it is defined as a subnode of the NPE, if crypto support is + available on the platform. + +properties: + compatible: + const: intel,ixp4xx-crypto + + intel,npe-handle: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the NPE this ethernet instance is using + and the instance to use in the second cell + + queue-rx: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the RX queue on the NPE + + queue-txready: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: phandle to the TX READY queue on the NPE + +required: + - compatible + - intel,npe-handle + - queue-rx + - queue-txready + +additionalProperties: false + +examples: + - | + npe: npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + + crypto { + compatible = "intel,ixp4xx-crypto"; + intel,npe-handle = <&npe 2>; + queue-rx = <&qmgr 30>; + queue-txready = <&qmgr 29>; + }; + };