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[23.128.96.18]) by mx.google.com with ESMTP id ds10si19242517ejc.709.2021.05.10.21.21.00; Mon, 10 May 2021 21:21:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kHL5D5de; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230383AbhEKEWE (ORCPT + 17 others); Tue, 11 May 2021 00:22:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230351AbhEKEWD (ORCPT ); Tue, 11 May 2021 00:22:03 -0400 Received: from mail-oo1-xc35.google.com (mail-oo1-xc35.google.com [IPv6:2607:f8b0:4864:20::c35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EA6FC061761 for ; Mon, 10 May 2021 21:20:57 -0700 (PDT) Received: by mail-oo1-xc35.google.com with SMTP id s20-20020a4ae9940000b02902072d5df239so1468161ood.2 for ; Mon, 10 May 2021 21:20:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kq1BhPeNrbUbILjy2DK6JPnYvHJ/R6XjYtFB4u6ooZo=; b=kHL5D5deXsZOxircr2d9YXoUtkdt2CM+LoQokUnzGEgxtP9VctNeMk2I4xulnVIx9B I3d6oJt3l6FdI2U+U5sM7JBrGnG7FHb3dF5J08p80nS/u7ppBVKEfJaT1c9crm65ntuR G1aElnw2pE/tmcdiFJkW0L4FebcnuqBNLEFWiEDm7WisddSY73aKVrFwvyokexbhvZPY zWrqVSzGK3jaK1AjmUsitmxhWBS5uufwi4Sy18+/SjeF//lZLZl6nNq/nX4+gvukOX8G 2PPm0QdFONuY/WrL6dbUgIK3u9SPqJZ9FJoT8uHGaD/ayf3009tDyng65l8ohNczcnoJ 6mDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kq1BhPeNrbUbILjy2DK6JPnYvHJ/R6XjYtFB4u6ooZo=; b=q3pzTwLX16x+PPQ87pv88bhZG0JIB2v/fp7TcTpA4Ou+E+GueZPgVMtM7myLOfwlyV yEQ3prD51IYoophyAPpXFLbIShJ5nDJEzhfvwSCUylxoyJszSFK1WBw00G0T5xwrat9m 0MS+NKx0RNA7sHs45MwU0CWfT7majqqeVdrHVpQdjDf8rYzEF3tDBHq7YzGpdXCrfN4P dvQaMqTC488U/J5ZeZnRyGZIBop4T0YRJMYs8EUElv9afrOEJEAcJgqx93xfokCZZk+9 EAa0dSI1MWUr9BrXF5cVket3Jq96vojV2PVTCASsP6bfsDUD6IXYoeFffj6OBdkzofou yXFg== X-Gm-Message-State: AOAM531xf8GpgC7jfG0NnkUQ9R8MgXSMBGmpBsHbp4fx3FQqRphN8yMH WAlvxH6gJXjRTqZ7VtyKNn5TmA== X-Received: by 2002:a4a:b186:: with SMTP id c6mr4829155ooo.28.1620706856599; Mon, 10 May 2021 21:20:56 -0700 (PDT) Received: from localhost.localdomain ([2607:fb90:e623:42c1:10df:adff:fec2:f1d]) by smtp.gmail.com with ESMTPSA id r124sm3042294oig.38.2021.05.10.21.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 21:20:56 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Stephen Boyd , sbillaka@codeaurora.org Cc: Tanmay Shah , Chandan Uddaraju , Abhinav Kumar , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] drm/msm/dp: Store each subblock in the io region Date: Mon, 10 May 2021 23:20:41 -0500 Message-Id: <20210511042043.592802-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511042043.592802-1-bjorn.andersson@linaro.org> References: <20210511042043.592802-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all platforms has DP_P0 at offset 0x1000 from the beginning of the DP block. So move the offsets into dss_io_data, to make it possible in the next patch to specify alternative offsets and sizes of these segments. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_catalog.c | 57 ++++++++--------------------- drivers/gpu/drm/msm/dp/dp_parser.c | 10 +++++ drivers/gpu/drm/msm/dp/dp_parser.h | 8 ++++ 3 files changed, 33 insertions(+), 42 deletions(-) -- 2.29.2 Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 2eb37ee48e42..a0449a2867e4 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -24,15 +24,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2 -#define MSM_DP_CONTROLLER_AHB_OFFSET 0x0000 -#define MSM_DP_CONTROLLER_AHB_SIZE 0x0200 -#define MSM_DP_CONTROLLER_AUX_OFFSET 0x0200 -#define MSM_DP_CONTROLLER_AUX_SIZE 0x0200 -#define MSM_DP_CONTROLLER_LINK_OFFSET 0x0400 -#define MSM_DP_CONTROLLER_LINK_SIZE 0x0C00 -#define MSM_DP_CONTROLLER_P0_OFFSET 0x1000 -#define MSM_DP_CONTROLLER_P0_SIZE 0x0400 - #define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_I2C_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -64,75 +55,67 @@ struct dp_catalog_private { static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.aux + offset); } static inline void dp_write_aux(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AUX_OFFSET; /* * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.aux + offset); } static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.ahb + offset); } static inline void dp_write_ahb(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_AHB_OFFSET; /* * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.ahb + offset); } static inline void dp_write_p0(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.p0 + offset); } static inline u32 dp_read_p0(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_P0_OFFSET; /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.p0 + offset); } static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; - return readl_relaxed(catalog->io->dp_controller.base + offset); + return readl_relaxed(catalog->io->dp_controller.link + offset); } static inline void dp_write_link(struct dp_catalog_private *catalog, u32 offset, u32 data) { - offset += MSM_DP_CONTROLLER_LINK_OFFSET; /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.base + offset); + writel(data, catalog->io->dp_controller.link + offset); } /* aux related catalog functions */ @@ -267,29 +250,21 @@ static void dump_regs(void __iomem *base, int len) void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) { - u32 offset, len; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + struct dss_io_data *io = &catalog->io->dp_controller; pr_info("AHB regs\n"); - offset = MSM_DP_CONTROLLER_AHB_OFFSET; - len = MSM_DP_CONTROLLER_AHB_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->ahb, io->ahb_len); pr_info("AUXCLK regs\n"); - offset = MSM_DP_CONTROLLER_AUX_OFFSET; - len = MSM_DP_CONTROLLER_AUX_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->aux, io->aux_len); pr_info("LCLK regs\n"); - offset = MSM_DP_CONTROLLER_LINK_OFFSET; - len = MSM_DP_CONTROLLER_LINK_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->link, io->link_len); pr_info("P0CLK regs\n"); - offset = MSM_DP_CONTROLLER_P0_OFFSET; - len = MSM_DP_CONTROLLER_P0_SIZE; - dump_regs(catalog->io->dp_controller.base + offset, len); + dump_regs(io->p0, io->p0_len); } int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) @@ -454,8 +429,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ - ret = readx_poll_timeout(readl, catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readx_poll_timeout(readl, catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -502,8 +476,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* Poll for mainlink ready status */ - ret = readl_poll_timeout(catalog->io->dp_controller.base + - MSM_DP_CONTROLLER_LINK_OFFSET + + ret = readl_poll_timeout(catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 0519dd3ac3c3..51ec85b4803b 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -250,6 +250,7 @@ static int dp_parser_clock(struct dp_parser *parser) static int dp_parser_parse(struct dp_parser *parser) { + struct dss_io_data *io = &parser->io.dp_controller; int rc = 0; if (!parser) { @@ -275,6 +276,15 @@ static int dp_parser_parse(struct dp_parser *parser) */ parser->regulator_cfg = &sdm845_dp_reg_cfg; + io->ahb = io->base + 0x0; + io->ahb_len = 0x200; + io->aux = io->base + 0x200; + io->aux_len = 0x200; + io->link = io->base + 0x400; + io->link_len = 0x600; + io->p0 = io->base + 0x1000; + io->p0_len = 0x400; + return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 34b49628bbaf..ff4774109c63 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -28,6 +28,14 @@ enum dp_pm_type { struct dss_io_data { u32 len; void __iomem *base; + void __iomem *ahb; + size_t ahb_len; + void __iomem *aux; + size_t aux_len; + void __iomem *link; + size_t link_len; + void __iomem *p0; + size_t p0_len; }; static inline const char *dp_parser_pm_name(enum dp_pm_type module) From patchwork Tue May 11 04:20:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 434150 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3460779jao; Mon, 10 May 2021 21:21:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzyGrEs2N1WIWULBbFABglZmFejYXhTuC/hxu7IBFwdMFkM4MBMMRbtxXY11EWAwkFvF8ur X-Received: by 2002:a17:907:1c15:: with SMTP id nc21mr29887322ejc.49.1620706861738; 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Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_catalog.c | 1 + 1 file changed, 1 insertion(+) -- 2.29.2 Reviewed-by: Abhinav Kumar diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index a0449a2867e4..e3996eef5518 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -707,6 +707,7 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog) dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, dp_catalog->width_blanking); dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active); + dp_write_p0(catalog, MMSS_DP_INTF_CONFIG, 0); return 0; } From patchwork Tue May 11 04:20:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 434302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB1D9C433ED for ; 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Mon, 10 May 2021 21:21:00 -0700 (PDT) Received: from localhost.localdomain ([2607:fb90:e623:42c1:10df:adff:fec2:f1d]) by smtp.gmail.com with ESMTPSA id r124sm3042294oig.38.2021.05.10.21.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 May 2021 21:21:00 -0700 (PDT) From: Bjorn Andersson To: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Stephen Boyd , sbillaka@codeaurora.org Cc: Tanmay Shah , Chandan Uddaraju , Abhinav Kumar , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] drm/msm/dp: Add support for SC8180x eDP Date: Mon, 10 May 2021 23:20:43 -0500 Message-Id: <20210511042043.592802-5-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511042043.592802-1-bjorn.andersson@linaro.org> References: <20210511042043.592802-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The eDP controller found in SC8180x is at large compatible with the current implementation, but has its register blocks at slightly different offsets. Add the compatible and the new register layout. Signed-off-by: Bjorn Andersson --- drivers/gpu/drm/msm/dp/dp_display.c | 1 + drivers/gpu/drm/msm/dp/dp_parser.c | 28 ++++++++++++++++++++-------- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index d1319b58e901..0be03bdc882c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -121,6 +121,7 @@ struct dp_display_private { static const struct of_device_id dp_dt_match[] = { {.compatible = "qcom,sc7180-dp"}, + { .compatible = "qcom,sc8180x-edp" }, {} }; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 51ec85b4803b..47cf18bba4b2 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -251,6 +251,7 @@ static int dp_parser_clock(struct dp_parser *parser) static int dp_parser_parse(struct dp_parser *parser) { struct dss_io_data *io = &parser->io.dp_controller; + struct device *dev = &parser->pdev->dev; int rc = 0; if (!parser) { @@ -276,14 +277,25 @@ static int dp_parser_parse(struct dp_parser *parser) */ parser->regulator_cfg = &sdm845_dp_reg_cfg; - io->ahb = io->base + 0x0; - io->ahb_len = 0x200; - io->aux = io->base + 0x200; - io->aux_len = 0x200; - io->link = io->base + 0x400; - io->link_len = 0x600; - io->p0 = io->base + 0x1000; - io->p0_len = 0x400; + if (of_device_is_compatible(dev->of_node, "qcom,sc8180x-edp")) { + io->ahb = io->base + 0x0; + io->ahb_len = 0x200; + io->aux = io->base + 0x200; + io->aux_len = 0x200; + io->link = io->base + 0x400; + io->link_len = 0x600; + io->p0 = io->base + 0xa00; + io->p0_len = 0x400; + } else { + io->ahb = io->base + 0x0; + io->ahb_len = 0x200; + io->aux = io->base + 0x200; + io->aux_len = 0x200; + io->link = io->base + 0x400; + io->link_len = 0x600; + io->p0 = io->base + 0x1000; + io->p0_len = 0x400; + } return 0; }