From patchwork Wed Jun 27 07:04:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 140301 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp505756ljj; Wed, 27 Jun 2018 00:04:54 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfzFCUBidl+/cZcswl7Ke8/Wfug+B914weMT/oy2TaGWbh/LAsHGUamtmqfEd3QjChlwKbA X-Received: by 2002:a17:902:530a:: with SMTP id b10-v6mr482641pli.316.1530083094687; Wed, 27 Jun 2018 00:04:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530083094; cv=none; d=google.com; s=arc-20160816; b=zY+CWWZXnwOBa6Unhg1hEFBUd9kbAgCeeZc46++hazQxs8T+u3GjEl5s+BXEQCANaN 4Boj/naPnYH9QKQdtmloyTRTZ5U5bNrO3CNHmI73WsbiWCSdKobZEEYX835V6POSSSqZ 6JNk45Bl5wlYEu73rW0lIIR6BETesVh3P30O+VCn7FgO3XNvAqEd10vDdhqvqbB4EacZ 0Q8AM4OFDJefGLjQP72e5jFfb3rNzm75GuA+j7ceqgFy+bdHww5SuX4G/YBhr8/7fsY9 /xLEHjeycqz+k9QR5MyLIiurT3Z+E9nR578i/XZTtwXEMXCgYLM/wXKNT0uxJ2Fn3vfJ y+GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=V7A+6hcHId8jc95xk5H5LujHeNIVYGJI/Ml972uJLL0=; b=zL3JKnmEy8X5/sPH03L1R/bzIGvbiv/Kl3oTs0XGYzPuBHPvzpCKy5u0zFOAsjkfFE pJwKd2IfQmaC9gH4KSOvEITJ1eyZj8uAW/sEOY7kqTFaj1VY14vkeShoXdl9a1Ov4/Pl DVdyi/X57DMw0zjm3tWI7Ube25h0kikc1Ua56t0cdpdXFR98T3IvIuQo/wcish9sNRNp iCiyYErgdfsxDi34N1Hu3Az5z2TnsVzkwyfquk0ceg5n1xA7dq5Y2Odurv5vIVyks9l7 TKqo6PnVRdYLeUYYjn1Rd3BjnrIhNV6SPx3/ny8dvP8wbKVUhALK/dbkU/bQkAptnk52 8bFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NeZLDrfe; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id t128-v6si2810300pgt.598.2018.06.27.00.04.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jun 2018 00:04:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NeZLDrfe; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 53A47202E5403; Wed, 27 Jun 2018 00:04:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::244; helo=mail-pl0-x244.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x244.google.com (mail-pl0-x244.google.com [IPv6:2607:f8b0:400e:c01::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 719EE202E53E5 for ; Wed, 27 Jun 2018 00:04:53 -0700 (PDT) Received: by mail-pl0-x244.google.com with SMTP id bi1-v6so601299plb.12 for ; Wed, 27 Jun 2018 00:04:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mlfumr3jZt2RttbjoqWZt9kscP8aJlugqY5OjZJpCL8=; b=NeZLDrfeSbi9KsaUejF7L4yU9V0r1OOCuGHcFRcwywgKZZoxnGThH62dYC8cSMTZZr /NCCfVg8k7Xy2lUYiQ2kQ5KAS5X1ZljkC2Ep3GuIR2aOZuOoZ2lTxgRofTwjsxZGHeBd ZlIeO106D/UYGaDNY+oTCY9LxEGliZ9J5hzZk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Mlfumr3jZt2RttbjoqWZt9kscP8aJlugqY5OjZJpCL8=; b=cnPSpNtiFkMZjeiUWmOBxMYLYCo/E7eDgn+On3i5uFuCzSy5a4Gu8qNfSYbRu5IxWz musFIFLUeL9ive712UWne7gRnOKwb+rce6fgDKd2TdxvqYJ7/ajFgWfMNJpae7Ql0GcA RjAIr5q3k4zYjVTiKCLH2dbSguqWQcck4thfU6NeJpI0fvW3JRWOXY9j6gHuIiDc0JK3 M0/jnGrIoEe4ZLPfa20zXlUh7YlOPvUVpIdm8Uvg05vVudgE7Hp365Oz7V5PbaUBNbKn 9Nf0KI9Tr7LfAHgJQMs/LR9mcmkRJaRb5ijLc07GMgd3Sornj+F4L50KbB2tpjyWX6d7 zcMg== X-Gm-Message-State: APt69E2gICRuX6FetSYHOTDoun0ss/cdeL4WD+tVTt578JlBIA76dljC q+B0wX7y/53FWqm+Gyyc6LKkVwMbDms= X-Received: by 2002:a17:902:5942:: with SMTP id e2-v6mr4986650plj.64.1530083093191; Wed, 27 Jun 2018 00:04:53 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id q6-v6sm4128833pgc.21.2018.06.27.00.04.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Jun 2018 00:04:52 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 27 Jun 2018 15:04:38 +0800 Message-Id: <20180627070443.42886-2-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, Ming Huang , zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The edk2 commit bacfd6e let CpuDxe running latter. CpuDxe should run early. CpuDxe is needed by gDS->SetMemorySpaceAttributes, and gDS->SetMemorySpaceAttributes is invoked by several drivers. Add several drives to APRIORI scope for implementing the ordering. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/D03.fdf | 10 +++++++++- Platform/Hisilicon/D05/D05.fdf | 6 +++++- 2 files changed, 14 insertions(+), 2 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 1383aa1091..027b53a6cf 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -146,6 +146,14 @@ READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + } + INF MdeModulePkg/Core/Dxe/DxeMain.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf @@ -153,6 +161,7 @@ READ_LOCK_STATUS = TRUE # # PI DXE Drivers producing Architectural Protocols (EFI Services) # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf @@ -186,7 +195,6 @@ READ_LOCK_STATUS = TRUE # Simple TextIn/TextOut for UEFI Terminal - INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 4503776d63..37d9cc0c18 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -148,6 +148,10 @@ READ_LOCK_STATUS = TRUE APRIORI DXE { INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf } INF MdeModulePkg/Core/Dxe/DxeMain.inf @@ -157,6 +161,7 @@ READ_LOCK_STATUS = TRUE # # PI DXE Drivers producing Architectural Protocols (EFI Services) # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf @@ -190,7 +195,6 @@ READ_LOCK_STATUS = TRUE # Simple TextIn/TextOut for UEFI Terminal - INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf From patchwork Wed Jun 27 07:04:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 140302 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp505794ljj; Wed, 27 Jun 2018 00:04:58 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLXnXqUkCLl7bj5q6EUB7P2LYDv8QV884YCjRzoN9XaEfcXBxGkHaOdRp0ePoOpihay6S0L X-Received: by 2002:a65:5c4b:: with SMTP id v11-v6mr4138691pgr.445.1530083097874; Wed, 27 Jun 2018 00:04:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530083097; cv=none; d=google.com; s=arc-20160816; b=qeZkDi8GqAumwMtOXmzr9249NNVlSGgTEQLgsMnbEC5aACLBGaW/d/hpdKJ8wxkzyN ws64O7OEz1x+TzjkJ7sogeMNv2iJlGqkO5WOPw94Mgp6fHa3yLvVCSmjiyz7y6jEs3PU 7dbaNj1WBwImpLFirVEr99N/30EQt6ihSxNg5yKoKMArBM8VOH9Qr8nO5bbyqyPYaBHR OQnruwSj6gt8KfBuitG6ZKpkSuqUjUK+4n40UZbPkjHyv8fP372fgGz/QVckEOEXuGNj H1t/yjJUpyjI7JTKA913FHsYqxP1t07kCpdCeoWkZQrWgblyajOYYR9VlbWG6Q8I1MQc CgEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=3SzEOy3RU/mF1NU3LvVBJqPubNYObohh8XdBV+JpBTY=; b=E8lj+zAsvK24h09rig3buYin+9wc0UJTZFz5Hr6XRDNm1eg4a3xrztB6HR6agGj9F0 U8mnPkPF1t6YcPyN12avfXN4Z+R1z5cjqCU8whoxe8UpgSVeqn6OFFIoQO/RLXgdpW+Y 2HSokUba3hGeSwFap48q3khsQGNW/XE8yd9AuXTcypk8gHKt7QBrWIFmyZb4gXlq57yG gthTHWPyoIBQvri9NofOhVHmmHXMoqk9UtF+0hBm+U9MCke6Xcsgm8Bu3wIv/JvFn+zL ViGIvdh2UcawOo8z9I5hSQysUbXDLZMW1d2Ywy2Yy4Gizxxwu6OpbwRL6FazxdTdSXjF bphw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FCSK5BYN; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id l23-v6si3534907pfg.326.2018.06.27.00.04.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jun 2018 00:04:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FCSK5BYN; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7E49D202E5402; Wed, 27 Jun 2018 00:04:57 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::243; helo=mail-pf0-x243.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x243.google.com (mail-pf0-x243.google.com [IPv6:2607:f8b0:400e:c00::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7EC92202E53E5 for ; Wed, 27 Jun 2018 00:04:56 -0700 (PDT) Received: by mail-pf0-x243.google.com with SMTP id q1-v6so558159pff.13 for ; Wed, 27 Jun 2018 00:04:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eVWucS/j26op3zbHs7QzFX1SIKxDy2ASWOJkY2smFgk=; b=FCSK5BYNhd9CNkU/tR2LfpBzH9PVt/8eqjijh+urREEgkPu6NwLfanZTX5flW33rbq fseSMyBkAoi5+u6VcKEoZmJWthVdH7k+AHXQAmzfJU8VLif1Mj7HlBL5HYxyu8/LIFwO VkOc7jCA0W7De1D6F8lNiqHYQV0X75QbeKIko= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eVWucS/j26op3zbHs7QzFX1SIKxDy2ASWOJkY2smFgk=; b=n9YTk4kGNLektFqfc6k6o+OebXJrRasez7aBjYQrnsfolA1RA/0/MvP61D0wueR2Vh ZIDe35vmZN9dqReSpDQzIygafAgo1Ubw9fAVEwRKE+62bT+8r40wXuRVXMO54/9X6N6B PWHal3m/Ofmn3pd1JlEMsdgWSxpE5kS4Rl+35iOlQxgaGbcjqk/q3g06Tp1vAGq7uH9g 6GMQKOrgtjKcEcEn9jL0DnfWp1S9zKcrOqkpI0YsEO2ybp4N/S1asVZn5yFfxw7gm1Z+ Qg1KkXBNX3leFDvDvc+6UExW32wCYrUDp64gHrgHw3gAHTEa/6Hjv1nOgn477u8ZiGAu 1/Uw== X-Gm-Message-State: APt69E0ur5k5h6Y4afLUAZ0PeNDi9jVjhvHevGt/rO7JhEOVrfOIc4L2 2zXu5Kmn+SpzwHDhE/d8RREqhQ== X-Received: by 2002:a62:c819:: with SMTP id z25-v6mr4061146pff.44.1530083096198; Wed, 27 Jun 2018 00:04:56 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id q6-v6sm4128833pgc.21.2018.06.27.00.04.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Jun 2018 00:04:55 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 27 Jun 2018 15:04:39 +0800 Message-Id: <20180627070443.42886-3-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, Ming Huang , zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Jason Zhang 1. During test PCIe mcs9922 UART card, the card can't work because the IO ATU config is overlap by Cfg0/Cfg1 ATU address. 2. After adjust the ATU windows, Cfg0/Cfg1 config as below: Cfg0 is equal to "ECAM + (BusBase, 0, 0)" Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang Signed-off-by: Heyi Guo Signed-off-by: Ming Huang --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 55b80aa4e4..e5f66eaa4a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -640,11 +640,12 @@ void SetAtuConfig0RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; + UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); @@ -666,12 +667,12 @@ void SetAtuConfig1RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; - + UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); From patchwork Wed Jun 27 07:04:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 140303 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp505833ljj; Wed, 27 Jun 2018 00:05:01 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKGKLSA1mAyKKNTwo86aXPYgdjAOitGZY0FesZc7iFMYoSbDFopzlIoej6/I5ZgCRrx8g1b X-Received: by 2002:a63:2c9:: with SMTP id 192-v6mr4196548pgc.354.1530083101035; Wed, 27 Jun 2018 00:05:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530083101; cv=none; d=google.com; s=arc-20160816; b=T6Pyh0lVm4kXKrMg00RltxdQrntk1/5FOAX0eFcE+FVWkjIi12SuiWp4vNmISg2pZJ 3uvUCUf5d1+Lmy6NsA/5QJ2SJBF4mXz/rRmAMpLmGM6Mrkf+hkfcBfAeB00UrAIEYTXE TbSY1yvT0tQLK//SsNptCsIa4g5ke6n6RS+pioQlZtLKFFeW/5FYDKugwzHlBVsmxyd+ zD7jLBGNkUAATAHwTqy/apLZ+S+Kv7q5EHXYqq2TH1gH0/mqXSsBdhNglEK7+6fU/05i 8Fl9mcwjYOPbetsnAGlaBGLvLrDTzOfzn/4mAyt45RSsU6fQlYQYnAuCewHd56sjkYFR oGKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=1WImzD11H6Gk60bK2v08yYBSiZjc5Td+wgiz/+WKy7g=; b=MlDj1WbmKeBG4gx7ND7KFEnNNECyojr5cp2dVNRDAfTkh7a2g9ADdEoZ60RLZutqVn auES7hvfES7IqqL1LB5lYUqvykTen/a1lnpqLfOQDer5vq5IwLlO8PBATWj6Xqa06wBl 9Nmzk80WZakuXFDdUaDFNw7JnUz2v7mzQnWz/0lt7ZVBbBlTsKs7kgw/3ZCYPMAV1isI msilL/5NIegCl1Td33WqQM8fHOH2V2uRtchDaxWYkGvn+PQ8hB5L6PYyNMbPg0O03KE5 XtXq5VFaGSC7/wtMhMYx3enVkh1z81g+7OQN5YU/vWlUjYet/T9HoKoGTDqnjmucIOZt v4Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KfiFwJJ9; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id v18-v6si3440590plo.285.2018.06.27.00.05.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jun 2018 00:05:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KfiFwJJ9; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A7734202E540C; Wed, 27 Jun 2018 00:05:00 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 80266202E540B for ; Wed, 27 Jun 2018 00:04:59 -0700 (PDT) Received: by mail-pg0-x242.google.com with SMTP id o11-v6so532835pgv.4 for ; Wed, 27 Jun 2018 00:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=buApLzbytp/eU+y5SkiUgXplzV/QuA5DH7Tx2BdUVg4=; b=KfiFwJJ9U3Ws4u8o32dCNBiMygFVDWhLGTB/ZidW481m0TWJpA59xsrMuAaGFAU/j8 4a936PktBwSdSu5ItB66QmqWXIpZblN27VJ67lE4PcLe5HbGKBhJp4DKckHbgLlLNdm+ DxjjC+6ORL97mzMKdhMscJxm9NGy4MgKkVYZw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=buApLzbytp/eU+y5SkiUgXplzV/QuA5DH7Tx2BdUVg4=; b=OS9i4PU1we8n2Se4h5mxCn00GXPSaSJb1zHmAeEGUXVeM8w/lbcnST7GDJLNU86uJh 6/O1jrPg9KdyD9aP9kTUxKA9Cj/tRa9il1Rf8nw3AdWU3azg6nL1UC+CMxqPsNJl4W+6 JkEwLnT0GPYC4RFETp8/cz0am8FH+D89xxKylDYrh+rPUzhqbB7ozinjLQiA0Nk8Bq1H Fgy+rKLoMaxHHX53EQxdvOIrNym2aWE5Q21wLWRlPSWxpPt+eJUt644oHDlKNcAtE1uF suPM6vsz+o7tJKt+9fdzg4OC1XyvlZE6FDDDl08dOwgpMC3mtEs3GL7qsJMool4SkeeB k66A== X-Gm-Message-State: APt69E1M4L1WvYd0sh/B/g992B29dQAmVAGb08xMmL/N8gdtOrBFV3GN fEKMyy5XrnyiwGRAEK/fQhPW3w== X-Received: by 2002:a65:5784:: with SMTP id b4-v6mr4158061pgr.315.1530083099232; Wed, 27 Jun 2018 00:04:59 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id q6-v6sm4128833pgc.21.2018.06.27.00.04.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Jun 2018 00:04:58 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 27 Jun 2018 15:04:40 +0800 Message-Id: <20180627070443.42886-4-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, Ming Huang , zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The MemLimit is wrong when the Private->BusLimit equal 0xFF. This patch fix enumerating device plug in switch cart failed issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index e5f66eaa4a..3f894e8eec 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -666,7 +666,7 @@ void SetAtuConfig1RW ( ) { UINTN RbPciBase = Private->RbPciBar; - UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; + UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit, 0x1F, 0x07, 0xFFF); UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); From patchwork Wed Jun 27 07:04:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 140304 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp505876ljj; Wed, 27 Jun 2018 00:05:04 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI81xaM9A1NcdTPbW0EZTCfO2HWm2QmlCPDR3pE28dQqejCY9M3vrpjEjSLFdwA5EImOvsn X-Received: by 2002:a17:902:bcc3:: with SMTP id o3-v6mr4880602pls.336.1530083104237; Wed, 27 Jun 2018 00:05:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530083104; cv=none; d=google.com; s=arc-20160816; b=Y5RNMHvVoys2BeYbzzcqXwkKauI0k79fp67IyaLpxGb4OAwz05pCGxtB+USLXKt2xa +Q9NnSgHX7iyr+DaQZRthsCcvsaXXVFDDMs3Byx24X7tkhachWOvagg6bKx2Tex6jRPs uLyXkIiydk7IoHaZ6Vs4728vQuGxkLXa2Usj3tm4+cE2TcuJ0aoAkC0fsd+XxyH6J4d1 EO29QPd7Qq5cyMxGXLEsE2UgmrQnxaz1nEmBuegfii3E8csc5K/cpXTY7Flp5/gWXb/t vw3+XgawHWkmI09KR50Lcm5i+9Me0Pnv87Agd/OPTE1zIvrb8oTADjK8QXItf+Wus7zF ZsoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=NrmvihAYjmG2RRmU8EUe+X0u76gwTEZ+3f2jBPDGbzc=; b=JHrWHNcRe4ccZ+u5rDQw739kKhcLgclb6BB3DqyLvGv9tJiD61F8hMfbP/7Rxe+rz1 T1m3FvZRDfctjODKjj4tTCaWWJ7+lBRJRRvNpCZxQmBlHqX3/pxEAiGRyNRgdrGp5NJJ bjuGcpPQjSy6fZX0wNvIehiQiR+HhGaScUbdwZmSOZOAiiDyVoAY1LmPKhT8Hd6URdLO CoAEOZKKr5nZ1CKwm01N4/YbYY2F/cbZ4xl4A7SPCgkAzCkf+jFD2PGxcj0+O1SPgbDI z4xyTM4SYcvsTR/hCGE2YHOqLfJL8e4UnrgxnJ79HX3mbHlFxmUPerTws/rrUKJ5efy7 JklA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Psb44A9A; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id n1-v6si2838090pge.263.2018.06.27.00.05.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jun 2018 00:05:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Psb44A9A; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D63BC202E540B; Wed, 27 Jun 2018 00:05:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A26EA202E540B for ; Wed, 27 Jun 2018 00:05:02 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id a7-v6so614761plp.3 for ; Wed, 27 Jun 2018 00:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xRe/urAWwysMHHsxtHieSYgrQAtjQI696BfNH4z434g=; b=Psb44A9Aotb4St5BHa/Nz2hsjJ32pk4mi3y8gmRClVH9rxuCPXOXy33eV1rG5rcqav TXfA8HPASkFRj4hTTylLZ2gwkbea/3DKHCIRJ8kYqPPTrjg+u+uRsmO9Oh4B3xn9NmjM OK5fCTfCqIS4584swP4F7yprjvnAm+RvywKQ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xRe/urAWwysMHHsxtHieSYgrQAtjQI696BfNH4z434g=; b=uW6VBv7RsUWIm871WMEipJReyO6JhLYYE62rGKsMnYz4PRn2O/eRmZTw+kpPTPIKgF WEzMypvuHn3US4HkHjIGvb7HxJQBo/PbZni9ua8NT0nj5hcp9uylRX6lDMQqc6pZ/kq8 hpxXsGBeP7jVZ9HAPvMoY2pgGfvco17Y7gFEBBhXb6KO2fBClfHDBuqSAijOz6uONBNo 0DIhMdNnyQZr+xgU0MOt2cIJ1C6CYczJleIwdJLvShSCdHcEpWeWiGczjdbXsxv8E4/+ 4GJ+ukjDSG9AwW+FA1FjVw3zO8uRlOO6yRtBnqOZK+heSK+tSKSDDsWdPWzzDwL/CQch gTRQ== X-Gm-Message-State: APt69E3oN1aH9NiATbIgClrQZYVeSvSAS7vZRcBnj/9GrdIAuIhBYniQ lU3ULqjAhxIhHo1EPfBWe5bSmtmi7Nw= X-Received: by 2002:a17:902:c85:: with SMTP id 5-v6mr4937935plt.126.1530083102296; Wed, 27 Jun 2018 00:05:02 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id q6-v6sm4128833pgc.21.2018.06.27.00.04.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Jun 2018 00:05:01 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 27 Jun 2018 15:04:41 +0800 Message-Id: <20180627070443.42886-5-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, Ming Huang , zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Fix the issue of onboard Nic not work kerenl with AMD GPU and NVME SSD in board. The GPU don't support 64 MSI, so need to allocate INTx, but the default interrupt number 255 is invalid, so Change all the PCI Device interrupt number to 0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 ++++++++++++++++++++ Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++++++++++ 4 files changed, 148 insertions(+) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b6e1a9d98a..0e6d5912a0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -629,6 +629,7 @@ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf # # Memory test diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 37d9cc0c18..32374e245e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -358,6 +358,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c new file mode 100644 index 0000000000..8519b7139d --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c @@ -0,0 +1,99 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include + +VOID +SetIntLine ( + ) +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 INTLine; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Fun; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); + gBS->FreePool ((VOID *)HandleBuffer); + return; + } + + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + Status = gBS->HandleProtocol ( + HandleBuffer[HandleIndex], + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + continue; + } + + INTLine = 0; + (VOID)PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + PCI_INT_LINE_OFFSET, + 1, + &INTLine); + (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun); + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device, Fun)); + } + + gBS->FreePool ((VOID *)HandleBuffer); + return; +} + +EFI_STATUS +EFIAPI +PlatformMiscDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SetIntLine, + NULL, + &gEfiEventReadyToBootGuid, + &Event + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status)); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf new file mode 100644 index 0000000000..0b365e7a53 --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformMiscDxe + FILE_GUID = a48f7a09-253f-468b-87c6-caf78baf47bb + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformMiscDxeEntry + +[Sources.common] + PlatformMiscDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[Guids] + gEfiEventReadyToBootGuid + +[Protocols] + gEfiPciIoProtocolGuid + +[LibraryClasses] + BaseLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + +[Depex] + TRUE From patchwork Wed Jun 27 07:04:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 140305 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp505922ljj; Wed, 27 Jun 2018 00:05:07 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJRMiot2XBCEvb/o57asdbjoj/7uc5MIhsTh7CgOpl7o3+2aseP0LDFI2vqkUps4hREyKQ9 X-Received: by 2002:a17:902:1081:: with SMTP id c1-v6mr4871151pla.153.1530083107426; Wed, 27 Jun 2018 00:05:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530083107; cv=none; d=google.com; s=arc-20160816; b=hWUiJzQUqXS1nEzb3oxjtAXzNWgHORBwBF4UvQqIcvdiWlMfk6YsDMNgqZbwVhBETi QDY1LhTEMsegXC9ctC/qQD/EkNVf6UkUFLTQ1mY3vjsBIIudl9iMEjo/S0YYC6DP2aGs lKxbW1jHrpntaDxFoZUSgXyifEYpBDzgT+E7xjcBqeYc8soj+1aAQ0Gn3QawKASpQd9G TO90bpN735EaFh7be3+TJOlX6+ghiUAYOJGKcVvSbXZVn3L6ZfVqF3zdUxq7P1G6uAnL w8qiFlwYRzdDDLTqY/oTzZoomPym+f0VMzgwJPXusN3JH8kN72XGaLkRSleJI05p8oi5 feeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=X4NWRTzCoKf5gHorEzHWWkUeZgjQpfnMOLoX9sccH+M=; b=xpcIG7XB536u69GSxtV9gDTr0Kma46AOrPaJ5RLmKmbx3v20tsYmB6R44gXFyl/FHI QwXYuS8BsNDY4hH+NoHqcI/fplbGy7xvIwlr0NLv6xAxABmQ9I9lyTHlKZhJyos1u7aG ZqReQErKEBfhvmNhlSCP86eHgVjf5az2EZ0eylzNl8ApAmH5F5XBxF9fV1RpFai5lduq dLBaGbDyGcnRuBejOeOne4D5pDW0vABE14cN+/GlLJCmVHREdp/gDMF/ZdPNuiNjeUA1 kbyvQn+ptaiAK4ZHkUccsOyz+oGuLmgkUQTPsJCV8kOJBqGyBSjMzHZvQ8IgwHTz/8rP KCrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UCRmf568; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id l4-v6si3332614plb.213.2018.06.27.00.05.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jun 2018 00:05:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UCRmf568; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1217E202E541A; Wed, 27 Jun 2018 00:05:07 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::241; helo=mail-pg0-x241.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CF746202E5419 for ; Wed, 27 Jun 2018 00:05:05 -0700 (PDT) Received: by mail-pg0-x241.google.com with SMTP id n2-v6so530973pgq.6 for ; Wed, 27 Jun 2018 00:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A+M5+sAEB/cNqK92kBnSQlZCLUxo1R5kCvkAL13vgDY=; b=UCRmf568x4JKkU8RAdpOU87VFvc5YsiFYq+jv3wD991VLZlNXulbXG92mHAeaDc/KC t8hWJvpQgZp6509G87uksvMuWz5er7S16kdhR5Jl71RasFn4mOth66JYZ57rie+8Jz4L dQVoPKotSyO7CowkyAimhqa+d/bHa0BiPhZ3k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A+M5+sAEB/cNqK92kBnSQlZCLUxo1R5kCvkAL13vgDY=; b=IfgLW5NQVnMCjKAQdLD3OODwM2n2XjhomWcgPxoaiHW9lFiXFaFiA0Up9hEOpwoAqD oOO8guRV0rXaA54M9X9D+ln237ljN395Y4LveG2xq6Eqxf/P2kAc0ApS0gZs1IPm/zOR cN516ZkMi88943Nsb/ICGun6RvRp7E3mt4oP9b51oEUE9dc7b69610ztDz5waGDkdoH6 rH0lq+iqKyLQktkaWLJIHp8w8mEj4TIpc+ag4Gy7nubgTtHzrSVB9+5W+2laPJQU92Pc qebGnGEzrlE06MQLlsZ/zD5mmyev/tcNl7NBo4y4OCcqGmbikd+wgpYdZQXX8h4PEhJK /30g== X-Gm-Message-State: APt69E2KP1qmQ749K1XPQPX305LejNPiaTla28bUO6hXqPJgY+43vWFt RtJU9N3+fMTAZ/cezeLHL1zbbg== X-Received: by 2002:a65:4308:: with SMTP id j8-v6mr4070473pgq.351.1530083105357; Wed, 27 Jun 2018 00:05:05 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id q6-v6sm4128833pgc.21.2018.06.27.00.05.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Jun 2018 00:05:04 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 27 Jun 2018 15:04:42 +0800 Message-Id: <20180627070443.42886-6-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 5/6] Hisilicon/D05/Pcie: optimize two pcie ports space X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, Ming Huang , zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Optimize pcie space for promoting usage rate.Change regions order of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion can satisfy the requirement of larger address alignment. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 12 ++++---- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 ++++++++++---------- 5 files changed, 34 insertions(+), 34 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 0e6d5912a0..ab7c5caf86 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -305,13 +305,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 @@ -336,10 +336,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 @@ -353,10 +353,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 57283a1053..ed6c4ac321 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 2 */ { PCI_HB0RB2_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit + 0xF8, //BusBase + 0xFF, //BusLimit PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 5 */ { PCI_HB0RB5_ECAM_BASE,//ecam - 0x0, //BusBase - 0x7, //BusLimit + 0x78, //BusBase + 0x7F, //BusLimit PCI_HB0RB5_CPUMEMREGIONBASE, //Membase PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB5_IO_BASE), //IoBase diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 50ccac1b06..9955f6dbeb 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -412,9 +412,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 -[0004] Input base : 00008000 +[0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 00008000 +[0004] Output Base : 0000f800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -469,9 +469,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 -[0004] Input base : 00000000 +[0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00000000 +[0004] Output Base : 00007800 [0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index b47cfec7bd..64807b1714 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0xa0000000, //Base Address 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x87, //End Bus Number + 0xF8, //Start Bus Number + 0xFF, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe0 @@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0x8b0000000, //Base Address 0x5, //Segment Group Number - 0x0, //Start Bus Number - 0x7, //End Bus Number + 0x78, //Start Bus Number + 0x7F, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe2 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 122e4f072c..3f09e5e568 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -89,15 +89,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number + Name(_BBN, 0xF8) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x87, // AddressMaximum - Maximum Bus Number + 0xF8, // AddressMinimum - Minimum Bus Number + 0xFF, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -109,8 +109,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xa8800000, // Min Base Address - 0xaffeffff, // Max Base Address + 0xa8000000, // Min Base Address + 0xaf7effff, // Max Base Address 0x0, // Translate 0x77f0000 // Length ) @@ -123,7 +123,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0xafff0000, // Translate + 0xaf7f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -165,7 +165,7 @@ Scope(_SB) { Name (_HID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff] }) Method (_STA, 0x0, NotSerialized) { @@ -280,15 +280,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 5) // Segment of this Root complex - Name(_BBN, 0x0) // Base Bus Number + Name(_BBN, 0x78) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x7, // AddressMaximum - Maximum Bus Number + 0x78, // AddressMinimum - Minimum Bus Number + 0x7f, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -300,8 +300,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xb0800000, // Min Base Address - 0xb7feffff, // Max Base Address + 0xb0000000, // Min Base Address + 0xb77effff, // Max Base Address 0x800000000, // Translate 0x77f0000 // Length ) @@ -314,7 +314,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0x8b7ff0000, // Translate + 0x8b77f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -593,7 +593,7 @@ Scope(_SB) 0x0, // Translate 0x800000 // Length ) - QwordMemory ( //ECAM space for [bus 0-7] + QwordMemory ( //ECAM space for [bus 78-7f] ResourceConsumer, PosDecode, MinFixed, @@ -601,8 +601,8 @@ Scope(_SB) NonCacheable, ReadWrite, 0x0, // Granularity - 0x8b0000000, // Min Base Address - 0x8b07fffff, // Max Base Address + 0x8b7800000, // Min Base Address + 0x8b7ffffff, // Max Base Address 0x0, // Translate 0x800000 // Length ) From patchwork Wed Jun 27 07:04:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 140306 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp505976ljj; Wed, 27 Jun 2018 00:05:10 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLAPfOG2FGIzfUvRKYdGqOmfIHOrHlvgG4ITZP3PP9OAyrvZItERhDLDbyn3f+L3CmjMRMO X-Received: by 2002:a65:450c:: with SMTP id n12-v6mr4173119pgq.242.1530083110725; Wed, 27 Jun 2018 00:05:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530083110; cv=none; d=google.com; s=arc-20160816; b=w8i6ginTilDWeMGZSDwGbd/paLYTqiQc96Lkj/TVOqg2erS3qxX4ICcsGW3wmqh6Ku TrkboGvvUKIZpKix10CbaOFLr6i9z+D828pX80m9d54S2ZmH3WxRe96itPoD+cygwWZn MVvYVXxslJ4Y7tJoYF2MuOuKJumyaG5zmpm5SFFdmDePJ1m7WQjI5Gxj7fllJe+e/vK5 1+gi90b0tpa5SKlVS+d2g6a9blKJVdzAjakZT3QaqHWTK1Kyy95un4pwOoUxhF9LWT4K BMnMzjbEC5ZCzp2iOeankiQ+uJltiwbmQ1/jTHiqR7f1igfRK67Yhx0ih/p5qvbxKDK5 ATIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=FGeLksboXOCjYBzn2ojOL7D5kDRbzXSQWr+BpVxHRA8=; b=oNbs7X9PspZtXz7ANO80c1exLugYcZ3dqu1HO8EHyujdfw75cc0qpqXvEjzvwe+jPf 11I+LQyyaezoqJpnQkFo7dklQJHLZiz1VSVorr/feGW9Kp7dlHTm/6fwSJfSUeYWoKIQ EmNJFvMjukNDowdwlAtnJ0HP7SUgdIq6mvMGU7S9V/3hh90eKHimIao+Af0tGY7pEKwR +nEbUacG2oO1pfNfnsniZkrG84iQIb6JZwIvMB1otMDzH0UCmrCeIjd3f1AiPr7XKKV9 hRMAyVZMTp5zTmSbbFMucO2Q6qldJRp+BHu5Mx5nlBSbls/UMJh/VNwr4teT2haSnP7z 5Exg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VtaJH2Yr; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id o6-v6si2933554plh.158.2018.06.27.00.05.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jun 2018 00:05:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VtaJH2Yr; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3C664202E541D; Wed, 27 Jun 2018 00:05:10 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::241; helo=mail-pg0-x241.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9DF16202E53E5 for ; Wed, 27 Jun 2018 00:05:08 -0700 (PDT) Received: by mail-pg0-x241.google.com with SMTP id e11-v6so538787pgq.0 for ; Wed, 27 Jun 2018 00:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xWLk29EGw3s9NQWq/MONaz7B4FkrWLi4cB3eyEnsuv8=; b=VtaJH2Yr5pDnUnpaZ7JhJriFov6yzsexPhcyxxO18rx5ybHN2luAa8nq+uFSReaeUS lp3AbA7Ackg5jp2yyErS5BgeIuYafWRFWjtzxJ9GtLYEigk7FTQWmolTH7xPOrCLUJEc eD23d1qQymaTXbgfVtiPfli/L2tqWo72XGGP8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xWLk29EGw3s9NQWq/MONaz7B4FkrWLi4cB3eyEnsuv8=; b=ku8xU+OaqJU/+8pNOvfo5YLeYU4xvI2tiIO90Ruld1nEVcIr8GxX+nfoOHqRsHqTSv uil2QdFWk5LSer7NyM50RMg9Db5oauLOnEaI24jTOP9RfN2rElC8LQwWebW6h1/OTsH0 4uRoGr18BR53Ik9AbJvniiJDFsZbWKsjHhKuokfTXu8zcKooqCE/01qNv8YOZdRqnFLJ UWcvWsEQa3NKxicMTYhaFEM9DvTFzFOUria5VxE7Y4IrxN12G6N7WPQQo5OSoXv0oweH Z5cfL6H+FbVGYuMkWCqhkNx4+3yJ12VXshCutUSGNGUod80qh3KNjadK4qAQb9LSIgJi 0fqQ== X-Gm-Message-State: APt69E0UpWEAPYrNspwofmWbsvciGB8wuEyIm0AARZoOkr6KMwuBkDNO P1HUZ8Y/H8eqEi+dE82OwEcG4g== X-Received: by 2002:a63:6ecb:: with SMTP id j194-v6mr4176503pgc.158.1530083108393; Wed, 27 Jun 2018 00:05:08 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id q6-v6sm4128833pgc.21.2018.06.27.00.05.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Jun 2018 00:05:07 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 27 Jun 2018 15:04:43 +0800 Message-Id: <20180627070443.42886-7-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 6/6] Hisilicon/D0x: Correct smbios product name X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, Ming Huang , zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The product name getting from BMC is not suitable. It may cause ambiguity. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c | 1 - 1 file changed, 1 deletion(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c index fcefe2442c..5e965c996c 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c @@ -86,7 +86,6 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL); } - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME), ProductNameType01); UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumType01); UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER), SystemManufacturerType01);