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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:08 -0700 Message-Id: <20180628030330.15615-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: [Qemu-devel] [PATCH v3 01/23] target/openrisc: Fix mtspr shadow gprs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Missing break. Signed-off-by: Richard Henderson --- target/openrisc/sys_helper.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index b284064381..2f337363ec 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -98,6 +98,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ idx = (spr - 1024); env->shadow_gpr[idx / 32][idx % 32] = rb; + break; case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); From patchwork Thu Jun 28 03:03:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140389 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1645451ljj; Wed, 27 Jun 2018 20:07:19 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfx7228NeLvqWsu90PqC0qK3AkjI2gMcLCkz57Ao3WXwzAXhMDxfbnjtENvivHWfeZ3fKqJ X-Received: by 2002:aed:2c63:: with SMTP id f90-v6mr7886851qtd.352.1530155239036; Wed, 27 Jun 2018 20:07:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155239; cv=none; d=google.com; s=arc-20160816; b=rzmOsV0NCRLrFajRki/0bkQ4eAfFyh/sEyEGi0NjACz3p694bOJ6S41HprrcpXisIZ R+kp6gRXDq47nFwlo8wcSZoZWE4oT55pZUjIkyPfVa+Ot36s5NhUcNNxuYbYTq1ow/Xy EeW4XJ1p8vRxUfJJYXAIoPiXHWq4s/lS3qM7+me2tUE9NhLxJ0/jxduGqNlDvK1lXfKQ 67FYemYM64mQ1+yzVuvpPMVD+1AW2A/O6abWEf5TdUjE+ljWG6nFPctxuTTBU1Ci1Mkl JU5OnfqpGyWZwnl32sclU8zyuOiYQvEUEEgI7OviakyNNCaD/wNEJIBoXwFyasILQA+0 X1Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=rjP0WcEQVKvrrKZaE1rx2rVvCp4c9dTWMv6CuqD2ckg=; b=JH04uBBYzSvMoecjorZQVtLTEj11NwKh2+1SrG3D4Tlvi1KZxX9AhOY0HmmVaQMVFq SgHefkYOh9l77nwrr1CyWI7s2278I+cDep4Px/zQXkq36PedD5JEApbUc+GzCVgI/zqq OK8+G9SRDE1o53vZl8nrJ0Mh4t0k2PwciqIXoTV1xlGOtPRoks4H6Cz/eBCj/khMv/G4 VmPBNhPFL1h3npDyOYiB3Sh7uk1tLslry8zpzpYVPiddxL6jUjzxtPKkaZdGzEnHLQqK +1MAB2XCqhE1eV29lcpZmZrAaQPmt47vC+uKVcO7eDdiab4/EpRBwOrO4u0XpgbeiFqv OTQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HML2g3Ua; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:09 -0700 Message-Id: <20180628030330.15615-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 02/23] target/openrisc: Add print_insn_or1k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than emit disassembly while translating, reuse the generated decoder to build a separate disassembler. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 1 + target/openrisc/cpu.c | 6 ++ target/openrisc/disas.c | 170 ++++++++++++++++++++++++++++++++++ target/openrisc/translate.c | 114 ----------------------- target/openrisc/Makefile.objs | 3 +- 5 files changed, 179 insertions(+), 115 deletions(-) create mode 100644 target/openrisc/disas.c -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 35cab65f11..c871d6bfe1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -358,6 +358,7 @@ void openrisc_translate_init(void); int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, int mmu_idx); int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); +int print_insn_or1k(bfd_vma addr, disassemble_info *info); #define cpu_list cpu_openrisc_list #define cpu_signal_handler cpu_openrisc_signal_handler diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index a692a98ec0..fa8e342ff7 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -35,6 +35,11 @@ static bool openrisc_cpu_has_work(CPUState *cs) CPU_INTERRUPT_TIMER); } +static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->print_insn = print_insn_or1k; +} + /* CPUClass::reset() */ static void openrisc_cpu_reset(CPUState *s) { @@ -152,6 +157,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) #endif cc->gdb_num_core_regs = 32 + 3; cc->tcg_initialize = openrisc_translate_init; + cc->disas_set_info = openrisc_disas_set_info; } /* Sort alphabetically by type name, except for "any". */ diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c new file mode 100644 index 0000000000..5acf4f4744 --- /dev/null +++ b/target/openrisc/disas.c @@ -0,0 +1,170 @@ +/* + * OpenRISC disassembler + * + * Copyright (c) 2018 Richard Henderson + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "disas/bfd.h" +#include "qemu/bitops.h" +#include "cpu.h" + +typedef disassemble_info DisasContext; + +/* Include the auto-generated decoder. */ +#include "decode.inc.c" + +#define output(mnemonic, format, ...) \ + info->fprintf_func(info->stream, "%-9s " format, \ + mnemonic, ##__VA_ARGS__) + +int print_insn_or1k(bfd_vma addr, disassemble_info *info) +{ + bfd_byte buffer[4]; + uint32_t insn; + int status; + + status = info->read_memory_func(addr, buffer, 4, info); + if (status != 0) { + info->memory_error_func(status, addr, info); + return -1; + } + insn = bfd_getb32(buffer); + + if (!decode(info, insn)) { + output(".long", "%#08x", insn); + } + return 4; +} + +#define INSN(opcode, format, ...) \ +static bool trans_l_##opcode(disassemble_info *info, \ + arg_l_##opcode *a, uint32_t insn) \ +{ \ + output("l." #opcode, format, ##__VA_ARGS__); \ + return true; \ +} + +INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(sra, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(ror, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(exths, "r%d, r%d", a->d, a->a) +INSN(extbs, "r%d, r%d", a->d, a->a) +INSN(exthz, "r%d, r%d", a->d, a->a) +INSN(extbz, "r%d, r%d", a->d, a->a) +INSN(cmov, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(ff1, "r%d, r%d", a->d, a->a) +INSN(fl1, "r%d, r%d", a->d, a->a) +INSN(mul, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(mulu, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(div, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(divu, "r%d, r%d, r%d", a->d, a->a, a->b) +INSN(muld, "r%d, r%d", a->a, a->b) +INSN(muldu, "r%d, r%d", a->a, a->b) +INSN(j, "%d", a->n) +INSN(jal, "%d", a->n) +INSN(bf, "%d", a->n) +INSN(bnf, "%d", a->n) +INSN(jr, "r%d", a->b) +INSN(jalr, "r%d", a->b) +INSN(lwa, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lwz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lws, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lbz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lbs, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lhz, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(lhs, "r%d, %d(r%d)", a->d, a->i, a->a) +INSN(swa, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b) +INSN(nop, "") +INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(maci, "r%d, %d", a->a, a->i) +INSN(andi, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(ori, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(xori, "r%d, r%d, %d", a->d, a->a, a->i) +INSN(mfspr, "r%d, r%d, %d", a->d, a->a, a->k) +INSN(mtspr, "r%d, r%d, %d", a->a, a->b, a->k) +INSN(mac, "r%d, r%d", a->a, a->b) +INSN(msb, "r%d, r%d", a->a, a->b) +INSN(macu, "r%d, r%d", a->a, a->b) +INSN(msbu, "r%d, r%d", a->a, a->b) +INSN(slli, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(srli, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(srai, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(rori, "r%d, r%d, %d", a->d, a->a, a->l) +INSN(movhi, "r%d, %d", a->d, a->k) +INSN(macrc, "r%d", a->d) +INSN(sfeq, "r%d, r%d", a->a, a->b) +INSN(sfne, "r%d, r%d", a->a, a->b) +INSN(sfgtu, "r%d, r%d", a->a, a->b) +INSN(sfgeu, "r%d, r%d", a->a, a->b) +INSN(sfltu, "r%d, r%d", a->a, a->b) +INSN(sfleu, "r%d, r%d", a->a, a->b) +INSN(sfgts, "r%d, r%d", a->a, a->b) +INSN(sfges, "r%d, r%d", a->a, a->b) +INSN(sflts, "r%d, r%d", a->a, a->b) +INSN(sfles, "r%d, r%d", a->a, a->b) +INSN(sfeqi, "r%d, %d", a->a, a->i) +INSN(sfnei, "r%d, %d", a->a, a->i) +INSN(sfgtui, "r%d, %d", a->a, a->i) +INSN(sfgeui, "r%d, %d", a->a, a->i) +INSN(sfltui, "r%d, %d", a->a, a->i) +INSN(sfleui, "r%d, %d", a->a, a->i) +INSN(sfgtsi, "r%d, %d", a->a, a->i) +INSN(sfgesi, "r%d, %d", a->a, a->i) +INSN(sfltsi, "r%d, %d", a->a, a->i) +INSN(sflesi, "r%d, %d", a->a, a->i) +INSN(sys, "%d", a->k) +INSN(trap, "%d", a->k) +INSN(msync, "") +INSN(psync, "") +INSN(csync, "") +INSN(rfe, "") + +#define FP_INSN(opcode, suffix, format, ...) \ +static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \ + arg_lf_##opcode##_##suffix *a, uint32_t insn) \ +{ \ + output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \ + return true; \ +} + +FP_INSN(add, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(sub, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(mul, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(div, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(rem, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(itof, s, "r%d, r%d", a->d, a->a) +FP_INSN(ftoi, s, "r%d, r%d", a->d, a->a) +FP_INSN(madd, s, "r%d, r%d, r%d", a->d, a->a, a->b) +FP_INSN(sfeq, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfne, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfge, s, "r%d, r%d", a->a, a->b) +FP_INSN(sflt, s, "r%d, r%d", a->a, a->b) +FP_INSN(sfle, s, "r%d, r%d", a->a, a->b) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d69f8d0422..fbdc2058dc 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -36,10 +36,6 @@ #include "trace-tcg.h" #include "exec/log.h" -#define LOG_DIS(str, ...) \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \ - ## __VA_ARGS__) - /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ @@ -457,7 +453,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.add r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -465,7 +460,6 @@ static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.addc r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -473,7 +467,6 @@ static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sub r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -481,7 +474,6 @@ static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.and r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -489,7 +481,6 @@ static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.or r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -497,7 +488,6 @@ static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.xor r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -505,7 +495,6 @@ static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sll r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -513,7 +502,6 @@ static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.srl r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -521,7 +509,6 @@ static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.sra r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -529,7 +516,6 @@ static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.ror r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -537,7 +523,6 @@ static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.exths r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -545,7 +530,6 @@ static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.extbs r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -553,7 +537,6 @@ static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.exthz r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -561,7 +544,6 @@ static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.extbz r%d, r%d\n", a->d, a->a); check_r0_write(a->d); tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]); return true; @@ -570,7 +552,6 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn) { TCGv zero; - LOG_DIS("l.cmov r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); zero = tcg_const_tl(0); @@ -582,8 +563,6 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.ff1 r%d, r%d\n", a->d, a->a); - check_r0_write(a->d); tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1); tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1); @@ -592,8 +571,6 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("l.fl1 r%d, r%d\n", a->d, a->a); - check_r0_write(a->d); tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS); tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]); @@ -602,8 +579,6 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn) static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.mul r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -611,8 +586,6 @@ static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.mulu r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -620,8 +593,6 @@ static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.div r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -629,8 +600,6 @@ static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("l.divu r%d, r%d, r%d\n", a->d, a->a, a->b); - check_r0_write(a->d); gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); return true; @@ -638,14 +607,12 @@ static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.muld r%d, r%d\n", a->a, a->b); gen_muld(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.muldu r%d, r%d\n", a->a, a->b); gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } @@ -654,7 +621,6 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn) { target_ulong tmp_pc = dc->base.pc_next + a->n * 4; - LOG_DIS("l.j %d\n", a->n); tcg_gen_movi_tl(jmp_pc, tmp_pc); dc->delayed_branch = 2; return true; @@ -665,7 +631,6 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn) target_ulong tmp_pc = dc->base.pc_next + a->n * 4; target_ulong ret_pc = dc->base.pc_next + 8; - LOG_DIS("l.jal %d\n", a->n); tcg_gen_movi_tl(cpu_R[9], ret_pc); /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc != ret_pc) { @@ -692,21 +657,18 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn) { - LOG_DIS("l.bf %d\n", a->n); do_bf(dc, a, TCG_COND_NE); return true; } static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn) { - LOG_DIS("l.bnf %d\n", a->n); do_bf(dc, a, TCG_COND_EQ); return true; } static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn) { - LOG_DIS("l.jr r%d\n", a->b); tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); dc->delayed_branch = 2; return true; @@ -714,7 +676,6 @@ static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn) static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn) { - LOG_DIS("l.jalr r%d\n", a->b); tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]); tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); dc->delayed_branch = 2; @@ -725,8 +686,6 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn) { TCGv ea; - LOG_DIS("l.lwa r%d, r%d, %d\n", a->d, a->a, a->i); - check_r0_write(a->d); ea = tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); @@ -750,42 +709,36 @@ static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop) static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lwz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TEUL); return true; } static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lws r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TESL); return true; } static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lbz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_UB); return true; } static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lbs r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_SB); return true; } static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lhz r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TEUW); return true; } static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn) { - LOG_DIS("l.lhs r%d, r%d, %d\n", a->d, a->a, a->i); do_load(dc, a, MO_TESW); return true; } @@ -795,8 +748,6 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn) TCGv ea, val; TCGLabel *lab_fail, *lab_done; - LOG_DIS("l.swa r%d, r%d, %d\n", a->a, a->b, a->i); - ea = tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R[a->a], a->i); @@ -837,28 +788,24 @@ static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop) static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sw r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_TEUL); return true; } static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sb r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_UB); return true; } static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn) { - LOG_DIS("l.sh r%d, r%d, %d\n", a->a, a->b, a->i); do_store(dc, a, MO_TEUW); return true; } static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn) { - LOG_DIS("l.nop %d\n", a->k); return true; } @@ -866,7 +813,6 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.addi r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 = tcg_const_tl(a->i); gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -878,7 +824,6 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.addic r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 = tcg_const_tl(a->i); gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -890,7 +835,6 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.muli r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); t0 = tcg_const_tl(a->i); gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0); @@ -902,7 +846,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn) { TCGv t0; - LOG_DIS("l.maci r%d, %d\n", a->a, a->i); t0 = tcg_const_tl(a->i); gen_mac(dc, cpu_R[a->a], t0); tcg_temp_free(t0); @@ -911,7 +854,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn) static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) { - LOG_DIS("l.andi r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; @@ -919,7 +861,6 @@ static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn) static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) { - LOG_DIS("l.ori r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k); return true; @@ -927,7 +868,6 @@ static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn) static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) { - LOG_DIS("l.xori r%d, r%d, %d\n", a->d, a->a, a->i); check_r0_write(a->d); tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i); return true; @@ -935,7 +875,6 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn) static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) { - LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k); check_r0_write(a->d); #ifdef CONFIG_USER_ONLY @@ -954,8 +893,6 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) { - LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k); - #ifdef CONFIG_USER_ONLY gen_illegal_exception(dc); #else @@ -972,35 +909,30 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); gen_mac(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); gen_msb(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.mac r%d, r%d\n", a->a, a->b); gen_macu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("l.msb r%d, r%d\n", a->a, a->b); gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1008,7 +940,6 @@ static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1016,7 +947,6 @@ static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1024,7 +954,6 @@ static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) { - LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l); check_r0_write(a->d); tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1)); return true; @@ -1032,7 +961,6 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn) static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn) { - LOG_DIS("l.movhi r%d, %d\n", a->d, a->k); check_r0_write(a->d); tcg_gen_movi_tl(cpu_R[a->d], a->k << 16); return true; @@ -1040,7 +968,6 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn) static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) { - LOG_DIS("l.macrc r%d\n", a->d); check_r0_write(a->d); tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac); tcg_gen_movi_i64(cpu_mac, 0); @@ -1049,147 +976,126 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn) static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfeq r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfne r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgtu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgeu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfltu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfleu r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfgts r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfges r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sflts r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond) { - LOG_DIS("l.sfles r%d, r%d\n", a->a, a->b); tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]); return true; } static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond) { - LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i); tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i); return true; } static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) { - LOG_DIS("l.sys %d\n", a->k); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_SYSCALL); dc->base.is_jmp = DISAS_NORETURN; @@ -1198,7 +1104,6 @@ static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) { - LOG_DIS("l.trap %d\n", a->k); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_TRAP); dc->base.is_jmp = DISAS_NORETURN; @@ -1207,27 +1112,22 @@ static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn) { - LOG_DIS("l.msync\n"); tcg_gen_mb(TCG_MO_ALL); return true; } static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn) { - LOG_DIS("l.psync\n"); return true; } static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) { - LOG_DIS("l.csync\n"); return true; } static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) { - LOG_DIS("l.rfe\n"); - #ifdef CONFIG_USER_ONLY gen_illegal_exception(dc); #else @@ -1274,56 +1174,48 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a, static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.add.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_add_s); return true; } static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.sub.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_sub_s); return true; } static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.mul.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_mul_s); return true; } static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.div.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_div_s); return true; } static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.rem.s r%d, r%d, r%d\n", a->d, a->a, a->b); do_fp3(dc, a, gen_helper_float_rem_s); return true; } static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("lf.itof.s r%d, r%d\n", a->d, a->a); do_fp2(dc, a, gen_helper_itofs); return true; } static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn) { - LOG_DIS("lf.ftoi.s r%d, r%d\n", a->d, a->a); do_fp2(dc, a, gen_helper_ftois); return true; } static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn) { - LOG_DIS("lf.madd.s r%d, r%d, r%d\n", a->d, a->a, a->b); check_r0_write(a->d); gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]); @@ -1333,42 +1225,36 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn) static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfeq.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); return true; } static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfne.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); return true; } static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfgt.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); return true; } static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfge.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_le_s, false, true); return true; } static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sflt.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); return true; } static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn) { - LOG_DIS("lf.sfle.s r%d, r%d\n", a->a, a->b); do_fpcmp(dc, a, gen_helper_float_le_s, false, false); return true; } diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 1b98a911ea..8b8a890c59 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -1,5 +1,5 @@ obj-$(CONFIG_SOFTMMU) += machine.o -obj-y += cpu.o exception.o interrupt.o mmu.o translate.o +obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o obj-y += exception_helper.o fpu_helper.o \ interrupt_helper.o mmu_helper.o sys_helper.o obj-y += gdbstub.o @@ -12,3 +12,4 @@ target/openrisc/decode.inc.c: \ $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@) target/openrisc/translate.o: target/openrisc/decode.inc.c +target/openrisc/disas.o: target/openrisc/decode.inc.c From patchwork Thu Jun 28 03:03:10 2018 Content-Type: text/plain; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:10 -0700 Message-Id: <20180628030330.15615-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PATCH v3 03/23] target/openrisc: Log interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/interrupt.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 3959671c59..25351d5de3 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -32,6 +32,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); CPUOpenRISCState *env = &cpu->env; + int exception = cs->exception_index; env->epcr = env->pc; if (env->dflag) { @@ -41,12 +42,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } else { env->sr &= ~SR_DSX; } - if (cs->exception_index == EXCP_SYSCALL) { + if (exception == EXCP_SYSCALL) { env->epcr += 4; } /* When we have an illegal instruction the error effective address shall be set to the illegal instruction address. */ - if (cs->exception_index == EXCP_ILLEGAL) { + if (exception == EXCP_ILLEGAL) { env->eear = env->pc; } @@ -66,8 +67,27 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; - if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { - hwaddr vect_pc = cs->exception_index << 8; + if (exception > 0 && exception < EXCP_NR) { + static const char * const int_name[EXCP_NR] = { + [EXCP_RESET] = "RESET", + [EXCP_BUSERR] = "BUSERR (bus error)", + [EXCP_DPF] = "DFP (data protection fault)", + [EXCP_IPF] = "IPF (code protection fault)", + [EXCP_TICK] = "TICK (timer interrupt)", + [EXCP_ALIGN] = "ALIGN", + [EXCP_ILLEGAL] = "ILLEGAL", + [EXCP_INT] = "INT (device interrupt)", + [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", + [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", + [EXCP_RANGE] = "RANGE", + [EXCP_SYSCALL] = "SYSCALL", + [EXCP_FPE] = "FPE", + [EXCP_TRAP] = "TRAP", + }; + + qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]); + + hwaddr vect_pc = exception << 8; if (env->cpucfgr & CPUCFGR_EVBARP) { vect_pc |= env->evbar; } @@ -76,7 +96,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) } env->pc = vect_pc; } else { - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", exception); } #endif From patchwork Thu Jun 28 03:03:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140387 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1645370ljj; Wed, 27 Jun 2018 20:07:11 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe2QhA6JEacoX/ZKIjAzbd86essjOgoFdw4A7YX/dsarwjeHBu3ioIUV44U2CDFcyij5OhC X-Received: by 2002:a37:4cd5:: with SMTP id z204-v6mr7684891qka.302.1530155231750; Wed, 27 Jun 2018 20:07:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155231; cv=none; d=google.com; s=arc-20160816; b=pI3iu8b3sFJcNERJ3jrcN5S2M143J199NcD/V3pnDKRdmaiM/tBeV7yZN2VhWWOXkz fw6yfB3lkR6Ro44MZW23z1wgYf0xufxGBqK3QF6WLYJ+RPsTP4AQInVeosWKKHxy5gmo JalIWhuS1tCR74LtW2BMPbqxB3jinjwqsOGtraDwDcWcS6aIzWotPIrQ/pAuHEpbeXc3 yB67ArFeOJFYYgS9avN3neSHMLVT0A5nmpg4jQcBJb9BqfkeD3SaBeKU1EvqneBVWZlo 6UqutVNsjjXtnqjsRAgnJ4Msg319r43oKEmWd0+j4+4OMDU9fCG/47eySfcPNzQ4RYbO QZvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RMq3UagQQRq1eCWiLtYcyhJ383CIfBeY/Y6nCwoDUMU=; b=xMti88SFBI3VIJvXOMzaS0BVhl8ePU3IQWILo0PP/hDSXPuiEfcdbfHhgdqYQJmtMw cruBf5yuxJEBU/YY7GXUHRjyLvUxkNCyNQzOgoXx84ugRfOWYZf2d/gNVqPRu/0+r1sb n8huvKqAsGkIuimknfIjFaqr32T34LpPzXYlRDUg7Tfqs5qLS33WG/hOQZRC6O0L8rxS zKW+MPUg/oLikc69vc82Dz16wtJms1jd71BZWfwTkhsLgUYBKrGf3M4vIYQpFpP57HCT xV1Lna8Hqaj/s4drq16G3OBI2WWrfgzQ8kq744pOyvdWtIgGDYd6kIR9B32hsDVZk9Ee qZbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TMkSBt5X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:11 -0700 Message-Id: <20180628030330.15615-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PATCH v3 04/23] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These values are unused. Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.17.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index fbdc2058dc..f5af515979 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -37,9 +37,7 @@ #include "exec/log.h" /* is_jmp field values */ -#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ -#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ typedef struct DisasContext { DisasContextBase base; @@ -1353,8 +1351,6 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_goto_tb(dc, 0, dc->base.pc_next); break; case DISAS_NORETURN: - case DISAS_JUMP: - case DISAS_TB_JUMP: break; case DISAS_UPDATE: /* indicate that the hash table must be used From patchwork Thu Jun 28 03:03:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140385 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1643088ljj; Wed, 27 Jun 2018 20:04:13 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeYmLys5EfbjH6B6PZnj3lNm0wY6b7wLKYX/7cuUnIZz490RDxZ9N+jFqp0Ytr5ZDIY+A0z X-Received: by 2002:a0c:be15:: with SMTP id k21-v6mr2281438qvg.1.1530155053593; Wed, 27 Jun 2018 20:04:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155053; cv=none; d=google.com; s=arc-20160816; b=iOCrOKYWjJdNQzixrkdyJIevpv3cL0lXqBVEzW+a+meDGAjrXn6YTJ/RQ63ah0jOzF 5bJemwVCjl+nl35qYGYOK4Dd+Tg+Bh77borBHGnxscrmMQiotNwVACgDWRaAlB4pLJSC ZijwgMZSg15zjMpaLETDXQmtfBmTG4DCooYMwymjpeg6IP96aw5cAuCYvBpkhoKcdKpk +mJRsjn97QfL14gPV14BtaTM6LkqajAQ+L2a9OuS+FUR9gCDxc24bEanSALct3kBqxAo yYaTojcoR9mTNtMTmNlChrc72O9yIEM0FJhPwNfGsD0KvW+bmGMc4Scwxmm2+M8Rll2N 3SXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aJQOgLhmdjBLyZG1/Zx4n3oTLHrsOdzZdDsXgKO1Fbs=; b=HtFcd4PI5UbDSOi+E92R+d37guyFmJ8k/EBjAHfmA6M37C6Z8N3Mx7wBC+Gm3WCskD EooqW4ILBLMi7NkkoH3m7b+2Yp0UG4Bgkq4eOGz8fsLxLuPwhz3vU2aDLFclFq2oMPAE MsPVrH6KpZSPf0X0DwVpz3XMcCGOdva/x64f003Z9PvCg3RWDIkeceXTuR2ODyZu2+iY afh8TwAGCndYu+cI6aG1gk2SL6fN4tj1DmzR6FZo+Nq4FBq6Hx6PwaFREXCvcoACwNd3 CpM6jRlWcfjLaq3F+vmq6c3rAB2piOXPvzQSMfrIC8SamdERd5b5a3idQO56Bc7hPwJX XaaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qc1QHJBt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:12 -0700 Message-Id: <20180628030330.15615-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH v3 05/23] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" No need to use the interrupt mechanisms when we can simply exit the tb directly. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/interrupt_helper.c | 3 +-- target/openrisc/translate.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index 56620e0571..b865738f8b 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -26,7 +26,6 @@ void HELPER(rfe)(CPUOpenRISCState *env) { OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - CPUState *cs = CPU(cpu); #ifndef CONFIG_USER_ONLY int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); @@ -53,8 +52,8 @@ void HELPER(rfe)(CPUOpenRISCState *env) } if (need_flush_tlb) { + CPUState *cs = CPU(cpu); tlb_flush(cs); } #endif - cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index f5af515979..43bdf378eb 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -37,6 +37,7 @@ #include "exec/log.h" /* is_jmp field values */ +#define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ typedef struct DisasContext { @@ -1133,7 +1134,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) gen_illegal_exception(dc); } else { gen_helper_rfe(cpu_env); - dc->base.is_jmp = DISAS_UPDATE; + dc->base.is_jmp = DISAS_EXIT; } #endif return true; @@ -1353,8 +1354,7 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_NORETURN: break; case DISAS_UPDATE: - /* indicate that the hash table must be used - to find the next TB */ + case DISAS_EXIT: tcg_gen_exit_tb(NULL, 0); break; default: From patchwork Thu Jun 28 03:03:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140388 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1645379ljj; Wed, 27 Jun 2018 20:07:13 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcOwEiWBwYa5dNX1iN8d/ILWXqtSzKbY/1Ab/iil6baKEGJtBJxQsQCCVWj6TrOk+41uh4M X-Received: by 2002:a0c:d112:: with SMTP id a18-v6mr3769848qvh.200.1530155233043; Wed, 27 Jun 2018 20:07:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155233; cv=none; d=google.com; s=arc-20160816; b=NBjqzryAWpLEBhoXp0t9Eh7/BnKaMCegPXTwD7AQUcXkcbCr50odnnPKmY7zvk3I+E ZVwliD45HbIQYB+dSVJHjI1AajF3JIDDb3/RYO9C3n2Cb2SQ69VYwx8lKzXkUTAJL8xR ncd4owxkcGAWoI8OjfoFuNTXfDMxBEBnnv1/Cojxkci6B5PZNimJfMVTNJqlPcjZmaeV SEQsVk8TqmVu8UMArM2JypH1zFZENxKPts7C0+e5/a6IrBxLjNW7Rh/OU8hvPsqPeY7a pXpoBavfeAOLmD8qw/Iwtfby2bEXuhp+YOhaLsSIm37lAz21s4GFtEIWP5+QtK6vmGaz yIVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=R3p19GQQCpUaCzZ/5gjeFqnHGorzb/Pkw8aTgWN7PMI=; b=E4qym/+V1dtGSDEiaCc7wc8g6AF2rNUs8QDfaPT340pl7mX/K6HJfjpVmHfgxhnjQ9 jSLORwDwgO3sJsjFHJ8OTIrwkFSNmKHP0E0DExibhZKfImrnwmUYConyQhM5D53hnzY4 Wk8m7A0Rv/EmYdkMHcEqk0L4rZWzv7CtLEeFu8qHFspxcRIsTX5EtafGVA0ZWq9QFFAN rHCOy1QjATbgc28wCCUZZR8QZ3R2sySA/r2h6TiLAY0LOPq22HK59NN8D6GVuaFGpWii iGOPqe5VW6ixNOd+w4n+rUhia9W92NDDVIRBHtE5DSw1nhkNPExLXBPh+YEJGgHyvYy6 GTsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="MFjR/1/Z"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:13 -0700 Message-Id: <20180628030330.15615-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We failed to store to cpu_pc before raising the exception, which caused us to re-execute the same insn that we stepped. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 43bdf378eb..22848b17ad 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1335,31 +1335,30 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + /* If we have already exited the TB, nothing following has effect. */ + if (dc->base.is_jmp == DISAS_NORETURN) { + return; + } + if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); } tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); - if (dc->base.is_jmp == DISAS_NEXT) { - dc->base.is_jmp = DISAS_UPDATE; - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - } - if (unlikely(dc->base.singlestep_enabled)) { - gen_exception(dc, EXCP_DEBUG); - } else { - switch (dc->base.is_jmp) { - case DISAS_TOO_MANY: - gen_goto_tb(dc, 0, dc->base.pc_next); - break; - case DISAS_NORETURN: - break; - case DISAS_UPDATE: - case DISAS_EXIT: + switch (dc->base.is_jmp) { + case DISAS_TOO_MANY: + gen_goto_tb(dc, 0, dc->base.pc_next); + break; + case DISAS_UPDATE: + case DISAS_EXIT: + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { tcg_gen_exit_tb(NULL, 0); - break; - default: - g_assert_not_reached(); } + break; + default: + g_assert_not_reached(); } } From patchwork Thu Jun 28 03:03:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140395 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1650088ljj; Wed, 27 Jun 2018 20:13:17 -0700 (PDT) X-Google-Smtp-Source: AAOMgpedLogi4ScOtRk8B3KSnBPBLtDh863REg6/GFKTNBGm7C3/lKgzVQVi3yldTHNrcqC/lRWe X-Received: by 2002:a0c:e24a:: with SMTP id x10-v6mr7742093qvl.244.1530155597740; Wed, 27 Jun 2018 20:13:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155597; cv=none; d=google.com; s=arc-20160816; b=BTsPR0aKBPXjJOeYLLjLUedsZoiN4HfBbhS6wHbuCqU07EqZvX9XQ7Ha3H+F8UzYXD E572kY4VLeSuFPzHiqr04M4bxH7Qdbm5jS0UFCjY45fbOuKsWqgxvmsO6zncgf1TBxto KK4dKOYtITTbd5ejggWfzZMgW2jb/8qSl13+Ui+beamY79oJWHTnIsiZ7Is1rSSA4MbB 2C5wtkaMZV1mixE9AQwZePDPAW4hNttVJztJU/c8gDYXIzITxOuCpbg2H5J9ua8Nxbiz o3sfKvmU6lK8zMqb/WLypy0VQy7qZRtWjhWANt1Pj/xCbKyQpKEGTwVCPoTUKA0aYYz5 lZ/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+cJgkwx/ep9kNHhp/NZWR+Qsl0Zh1HJMnithEE7rNEI=; b=kjZNPL7h7emt2Zk1pftpR5addJw/o2h7uZUnRLe/97XPIOC+GzFPnal8709j+tthoq ozZcJtArv2yRTcKkuj1a7kmXL4sAVdBJW5E79tpc7J7CuIoFEyMFstzGcx9moqE7b/5m z5OtcBM2XW2Io9x1qom8xIbgZiU7sLrNXokbZo9druEMxyzXhJ5vvKHjGCcCCOHepNMA /MZNZ1Xs243Ztk0C8cEw2ngXhXjSjxxb5cXot0vcmZbzsSFvO04GF2KxdkrxSY6+BurP 0wzt5fJNN/G1Mf+a5mjUtKM5pq7JW/pzZIWUhpVz7jahobRdrqQwpKVAwDFTgTv7hwLI 13hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XdghUrcA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o125-v6si5507885qkd.38.2018.06.27.20.13.17 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 27 Jun 2018 20:13:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XdghUrcA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34281 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNMz-0003W3-5A for patch@linaro.org; Wed, 27 Jun 2018 23:13:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYNDk-0004xu-UA for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYNDj-0007iL-JU for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:44 -0400 Received: from mail-pl0-x230.google.com ([2607:f8b0:400e:c01::230]:43239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYNDj-0007h6-Bx for qemu-devel@nongnu.org; Wed, 27 Jun 2018 23:03:43 -0400 Received: by mail-pl0-x230.google.com with SMTP id c41-v6so2003026plj.10 for ; Wed, 27 Jun 2018 20:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+cJgkwx/ep9kNHhp/NZWR+Qsl0Zh1HJMnithEE7rNEI=; b=XdghUrcA3PUsKTeIIO/xXyJjYMeUpMiU5gx5HCuxt5D+VtENUNoGXuWFbs83Z8KZvb WmGnm5pCA90Xm84cIlIGeL+ojzFySJyCAZXATTUE/E4+gR3c6GC+O2n2ABt6KYHbZoi2 LuGOjHx5aQvmeeILYJsreFzqpzDfZR2zOI1cA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+cJgkwx/ep9kNHhp/NZWR+Qsl0Zh1HJMnithEE7rNEI=; b=mRIRd3yN3Roh0qDVr5wS7VvshiKa2H0UC0oqIkkxSBB44zwV18fngLgHbM9y2rrr69 f9S651JF+cQVz+UOoDr9+XwGy55ZvHb6h7+8dTBA9zK4K+glu4yUo6P/UBi/pKBtn/Ex +5NgwNag1guMfXt6mj5omDZLUDnvJg3xmPvIkyO9GHG9fNTQJ19zgemytrMyvze7pPHx sBvZASqBUWMdoCAGVC5O8/SAUnS7y9GIaBXkXNGhaANvKngvNyaZf08hjzop3om7iz4W se1I9gJJ0waBCYMn4Luf6FF9glV4XG+uatkOkpE1W39UlX4o3gYtY24RHMMut19v5WEN Ydrg== X-Gm-Message-State: APt69E2AD+cA/oh/em0o7ILPZApDUMnW/1VArtJokgabMtx3/zjGKCGE XOxyoT5Lq9fTFkhcD6Gaxy/wTa+Abu8= X-Received: by 2002:a17:902:8d91:: with SMTP id v17-v6mr8773071plo.9.1530155022151; Wed, 27 Jun 2018 20:03:42 -0700 (PDT) Received: from cloudburst.twiddle.net (97-126-112-211.tukw.qwest.net. [97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:14 -0700 Message-Id: <20180628030330.15615-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3 07/23] target/openrisc: Link more translation blocks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Track direct jumps via dc->jmp_pc_imm. Use that in preference to jmp_pc when possible. Emit goto_tb in that case, and lookup_and_goto_tb otherwise. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 96 +++++++++++++++++++++---------------- 1 file changed, 55 insertions(+), 41 deletions(-) -- 2.17.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 22848b17ad..a618d39242 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -38,13 +38,16 @@ /* is_jmp field values */ #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ -#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ +#define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ typedef struct DisasContext { DisasContextBase base; uint32_t mem_idx; uint32_t tb_flags; uint32_t delayed_branch; + + /* If not -1, jmp_pc contains this value and so is a direct jump. */ + target_ulong jmp_pc_imm; } DisasContext; /* Include the auto-generated decoder. */ @@ -160,34 +163,6 @@ static void check_ov64s(DisasContext *dc) } \ } while (0) -static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) -{ - if (unlikely(dc->base.singlestep_enabled)) { - return false; - } - -#ifndef CONFIG_USER_ONLY - return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); -#else - return true; -#endif -} - -static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) -{ - if (use_goto_tb(dc, dest)) { - tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_goto_tb(n); - tcg_gen_exit_tb(dc->base.tb, n); - } else { - tcg_gen_movi_tl(cpu_pc, dest); - if (dc->base.singlestep_enabled) { - gen_exception(dc, EXCP_DEBUG); - } - tcg_gen_exit_tb(NULL, 0); - } -} - static void gen_ove_cy(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { @@ -621,6 +596,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn) target_ulong tmp_pc = dc->base.pc_next + a->n * 4; tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm = tmp_pc; dc->delayed_branch = 2; return true; } @@ -634,6 +610,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn) /* Optimize jal being used to load the PC for PIC. */ if (tmp_pc != ret_pc) { tcg_gen_movi_tl(jmp_pc, tmp_pc); + dc->jmp_pc_imm = tmp_pc; dc->delayed_branch = 2; } return true; @@ -1267,6 +1244,8 @@ static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) dc->mem_idx = cpu_mmu_index(env, false); dc->tb_flags = dc->base.tb->flags; dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; + dc->jmp_pc_imm = -1; + bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; dc->base.max_insns = MIN(dc->base.max_insns, bound); } @@ -1319,37 +1298,72 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } dc->base.pc_next += 4; - /* delay slot */ - if (dc->delayed_branch) { - dc->delayed_branch--; - if (!dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - dc->base.is_jmp = DISAS_UPDATE; - return; - } + /* When exiting the delay slot normally, exit via jmp_pc. + * For DISAS_NORETURN, we have raised an exception and already exited. + * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing + * in the manual saying this is illegal, but it surely it should. + * At least or1ksim overrides pcnext and ignores the branch. + */ + if (dc->delayed_branch + && --dc->delayed_branch == 0 + && dc->base.is_jmp == DISAS_NEXT) { + dc->base.is_jmp = DISAS_JUMP; } } static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong jmp_dest; /* If we have already exited the TB, nothing following has effect. */ if (dc->base.is_jmp == DISAS_NORETURN) { return; } + /* Adjust the delayed branch state for the next TB. */ if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); } - tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); + /* For DISAS_TOO_MANY, jump to the next insn. */ + jmp_dest = dc->base.pc_next; + tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); + switch (dc->base.is_jmp) { + case DISAS_JUMP: + jmp_dest = dc->jmp_pc_imm; + if (jmp_dest == -1) { + /* The jump destination is indirect/computed; use jmp_pc. */ + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + if (unlikely(dc->base.singlestep_enabled)) { + gen_exception(dc, EXCP_DEBUG); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + break; + } + /* The jump destination is direct; use jmp_pc_imm. + However, we will have stored into jmp_pc as well; + we know now that it wasn't needed. */ + tcg_gen_discard_tl(jmp_pc); + /* fallthru */ + case DISAS_TOO_MANY: - gen_goto_tb(dc, 0, dc->base.pc_next); + if (unlikely(dc->base.singlestep_enabled)) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + gen_exception(dc, EXCP_DEBUG); + } else if ((dc->base.pc_first ^ jmp_dest) & TARGET_PAGE_MASK) { + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_lookup_and_goto_ptr(); + } else { + tcg_gen_goto_tb(0); + tcg_gen_movi_tl(cpu_pc, jmp_dest); + tcg_gen_exit_tb(dc->base.tb, 0); + } break; - case DISAS_UPDATE: + case DISAS_EXIT: if (unlikely(dc->base.singlestep_enabled)) { gen_exception(dc, EXCP_DEBUG); From patchwork Thu Jun 28 03:03:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140393 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1649254ljj; Wed, 27 Jun 2018 20:12:18 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfynw7LwDV2OLChSCFIzfMlMuc+2B38W9nE383l/PDSrpZBX9ugvRigbqpP6GoLqjSkHVb1 X-Received: by 2002:ac8:1987:: with SMTP id u7-v6mr7750838qtj.296.1530155538284; Wed, 27 Jun 2018 20:12:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155538; cv=none; d=google.com; s=arc-20160816; b=FdPX8HOHdOuThxVtvnexUGS7SpdR/945HCOI6CIRbOCfx91QIwtYyozZkGZ27CrFHV uC98rVPnM5UbS6egXLD7i6l/0ilcttOXTuBYsMvY1AAEReZ0ZhP/duu1+Ilehk3PQlZk ndkVT30HrnljlalwzI0VUnLVta+IA4T0oc5V0qR58Zs4mSbFoZUYU5fQFeAGc1oTUZ61 4D4QZ8NRgXDbp5UVNPEnbyXozJWC1+gGNbByXb6xgm/Rk5VH3CZGLrJElx2O9ln4pd00 WZIsvopmrZ1aEgu6bxNgZBlPOq8XZWC3jqKbrPmEBLYrlJvB1aoQ8gEYXq8qD2On5fW0 y/pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=HfUf5ME0B58UupEHc+Qjiiql58dh2ZppYbSI6v7Vjbc=; b=Pk5qG1uxbxHmBdm54KxR6hQ9aWhJ55BDvZxoqO1N8uwSDpi6Zhq5kWSY3qpKITEn6T 09rb78Mn8g8BbJw8lYt8bsWnjjFqr5otu57p1sOd9QvP96wmxpMS7SgTcfnDDavovcVh 0pTiY++fNPToX1x+R+CRtcYGvsB14sukEjMdBUwC3THgD2uerlrTz6JRGhXLtimTXNAC 1R+LT2lshESMrFzOEn7rpelYtVBxW7iiRCxi1q0bk0i6bOH6nPgFs8a/3p+vL8oCdQj/ lLGeBvokLu1i+cbE1euACpxfSwO8jZV1DscwEd8ksnTauXlc3+LxRUJu4fZX1HiW9Bal 7RsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Y8Yij7/+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:15 -0700 Message-Id: <20180628030330.15615-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to limit the amount of ifdefs and isolate the test for usermode. Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a618d39242..db149986af 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -50,6 +50,15 @@ typedef struct DisasContext { target_ulong jmp_pc_imm; } DisasContext; +static inline bool is_user(DisasContext *dc) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return dc->mem_idx == MMU_USER_IDX; +#endif +} + /* Include the auto-generated decoder. */ #include "decode.inc.c" @@ -853,33 +862,25 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) { check_r0_write(a->d); -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx == MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { TCGv_i32 ti = tcg_const_i32(a->k); gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti); tcg_temp_free_i32(ti); } -#endif return true; } static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) { -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx == MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { TCGv_i32 ti = tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); } -#endif return true; } @@ -1104,16 +1105,12 @@ static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn) { -#ifdef CONFIG_USER_ONLY - gen_illegal_exception(dc); -#else - if (dc->mem_idx == MMU_USER_IDX) { + if (is_user(dc)) { gen_illegal_exception(dc); } else { gen_helper_rfe(cpu_env); dc->base.is_jmp = DISAS_EXIT; } -#endif return true; } From patchwork Thu Jun 28 03:03:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140390 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1647185ljj; Wed, 27 Jun 2018 20:09:38 -0700 (PDT) X-Google-Smtp-Source: AAOMgpc96CbIBaelFf0MbbCLRdKe2eB3XP99cZqn3oXLSHX6GP6FUKlaLVTeqfMaq055PvqfQYNV X-Received: by 2002:a37:15da:: with SMTP id 87-v6mr3402248qkv.67.1530155377900; Wed, 27 Jun 2018 20:09:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155377; cv=none; d=google.com; s=arc-20160816; b=EPpwOvKdj8sY3vY6+x1oHuAy3ZPVlUfPbrWIrq9VbATZI7tVO1vWcVFIaPXAF4uezl ijrZYGrHDC10/BvZCVZuAwEPtN3Bf8nvjdqaaPOkzgKoAJ1hxs5DkQbM0L7UANLzFqpw pn85sgKa8YcTAHQmfPji1WHuXXsqTG3Oc/nNzp4MxWLy4TgPa0rntUBlUiZdnhwPt5RD GtIZeXVJmLO7zYGfpdhhu/D/nKdmaF4erKJLMvctMVCfEXQqUR/cQueurTFF0TWnbIAO MbHuxpDZV67XM9maMxWFLCkDJFtDvlEmc4sR7nkWxgc7IRNnhgd3TJtj6ooLFON2GmNv EYOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=dSZQhtzn1k0rEud0t3gj0aR0y80zWn5TQzJYzMcrdao=; b=QTqPUtGncxlEup5xBUqslRSR1i1VDR1fFbA9D7SopqNBYOz5B23pwC1LYN1ZhTIYT2 CiIiZNcbfNWdvEFwSKE5cgfH06ZORjCNA8ZY8whVt2MjPNZj2pGkJtjbabVnDMRWMm4d Y+OJ/ypiJuWt6TU9ma1/cNdK25eu1EGKRR8y1uFbL3lf+cYl8K8IW7Fp3Zd0fWdoGZMO Hg+Kql+vusdL11mPmcEe+kpQS2FK/TLCtxFN2wc4lm5RobZrLwK7C8tlA638gxec33C5 Ru87G5pAuSTxd8G5c5/H9KlNevm2p+WVLsW31w32177DTPCPgeBHQSKXd65vY/qtEHan clfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Tmcbgj3r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:16 -0700 Message-Id: <20180628030330.15615-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A store to SR changes interrupt state, which should return to the main loop to recognize that state. Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index db149986af..59605aacca 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -877,7 +877,22 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti = tcg_const_i32(a->k); + TCGv_i32 ti; + + /* For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + + ti = tcg_const_i32(a->k); gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); tcg_temp_free_i32(ti); } From patchwork Thu Jun 28 03:03:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140392 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1647692ljj; Wed, 27 Jun 2018 20:10:19 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcL6pKDTocYHq5OfpiWCGdDJHc/yzyNIuG74wNBWeA0iN9k6u4axFZYKAVu9rL+k+N9EajC X-Received: by 2002:a37:5607:: with SMTP id k7-v6mr7266342qkb.342.1530155419141; Wed, 27 Jun 2018 20:10:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155419; cv=none; d=google.com; s=arc-20160816; b=Suv1+HI0RUU/BHX9TqJjWT2tPZvLA1+ODD68a12GmSUqem2SJOgjKF5QLA5l3hsYOH T0WIPiMMXPRReaKROmPc7w8/qt9efdzDu9fD4cfwg1fkgS9Uk/XMngAVe6HQ3fip0uoa TIcstGtvV5Ke5awBpmQZudsZfGAeniQ1FwRwjc7n7u12KgKvSoydaoEgo5rKzTNU7FF2 97Q67jQyjVc39BDXTUgJnGZuQ37YEAlMBb9r18csF8bFWyCHGiAv3aOxapFwkFcDEdIQ aq+W2aGlcuZMU34YY8iJ5y1Wufpby506zYOQV9UapBhl0cCOKwIXAgMNEw8RKX0V2Lsn aL0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=S4gTFeZHYbzKEYFy+mCAPw0hiMK8NeY0BQXvoQHvQSQ=; b=HJVOw3G5Qy5cEEHUezA7cVA88xXDBsKkblk7y9ZUEhNBol1pMMANsCaG+p7Yjn4gNE FjzpuembqCnvHjkVkUt0FtAwboIssNpcotggCz/v7ShGbxA5XyEQgetRD4//IYo8nrNh HGEaZA2XW/p7UChBkhJ2mVrSV80Bc7vCBun+elJgJQc7pgoqes5B75RrwMBCGMnYORTJ E75YonITcNdLIC7L+nwB1vSdvZXOzjcVa1y5f/sqwURjoIA1JTz3t15tO17/TuIgLNxL MEG6jbwvzL+PVikWpiTnIz3dVyMUZclqrQW9aghgF/ticcF7XVxyMrAvxqw4OuOR7z93 ofbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LahRxllt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:17 -0700 Message-Id: <20180628030330.15615-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from tcg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than pass base+offset to the helper, pass the full index. In most cases the base is r0 and optimization yields a constant. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/helper.h | 4 ++-- target/openrisc/sys_helper.c | 9 +++------ target/openrisc/translate.c | 16 +++++++++------- 3 files changed, 14 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index e37dabc77a..9db9bf3963 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -56,5 +56,5 @@ FOP_CMP(le) DEF_HELPER_FLAGS_1(rfe, 0, void, env) /* sys */ -DEF_HELPER_FLAGS_4(mtspr, 0, void, env, tl, tl, tl) -DEF_HELPER_FLAGS_4(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl, tl) +DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl) +DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 2f337363ec..2c959f63f4 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -27,13 +27,11 @@ #define TO_SPR(group, number) (((group) << 11) + (number)) -void HELPER(mtspr)(CPUOpenRISCState *env, - target_ulong ra, target_ulong rb, target_ulong offset) +void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) { #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); - int spr = (ra | offset); int idx; switch (spr) { @@ -202,13 +200,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, #endif } -target_ulong HELPER(mfspr)(CPUOpenRISCState *env, - target_ulong rd, target_ulong ra, uint32_t offset) +target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, + target_ulong spr) { #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); - int spr = (ra | offset); int idx; switch (spr) { diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 59605aacca..64b5e84630 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -865,9 +865,10 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti = tcg_const_i32(a->k); - gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti); - tcg_temp_free_i32(ti); + TCGv spr = tcg_temp_new(); + tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); + gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], spr); + tcg_temp_free(spr); } return true; } @@ -877,7 +878,7 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) if (is_user(dc)) { gen_illegal_exception(dc); } else { - TCGv_i32 ti; + TCGv spr; /* For SR, we will need to exit the TB to recognize the new * exception state. For NPC, in theory this counts as a branch @@ -892,9 +893,10 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn) } dc->base.is_jmp = DISAS_EXIT; - ti = tcg_const_i32(a->k); - gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti); - tcg_temp_free_i32(ti); + spr = tcg_temp_new(); + tcg_gen_ori_tl(spr, cpu_R[a->a], a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R[a->b]); + tcg_temp_free(spr); } return true; } From patchwork Thu Jun 28 03:03:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140399 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1651999ljj; Wed, 27 Jun 2018 20:16:02 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf/w1+3IbSS+jaxOJPXm6aIxYKjnlDigj8prETBkNzhMShI9kcUMe+hhMRavbvCu3cvtwkJ X-Received: by 2002:ac8:25f1:: with SMTP id f46-v6mr611433qtf.20.1530155762193; Wed, 27 Jun 2018 20:16:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155762; cv=none; d=google.com; s=arc-20160816; b=ssvFysfDv4tTBqwUefUI8YcX/GrWGT1l87S4JXXix0laNzjGsQxo4WIez2lvF1Z+8d +urlpvwESnbCywP5+Sg9twonD11Ysb8MG/CM0duVys3IZ/5N/MpnCShcAqjRBmhXpNNe KOMnoO6gwjzLcpDA68jQdx/kwStfwAj+S2B/e//tZu6De4XVoHQ1CA29AsfQ1WOSsPYp 2Nc4DHSYRgzipMuzhZBZB1tLMIYjLNsZBn6x+OirZMDK1tueOvuYI4EcEoHZs9KcOJVS cIP4OuBo9jU0nE480vpyTEPgu9Fo0kU0sTrjee68rngz8MGIDVfRhgNLGTL032bvbp8i ndIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=CrBclbME8h7vRl7FDGtoB5X2GKw8cuhuB68oMAULcgI=; b=goRxbfo2qIj2hxwCv+MXvdiaM+SNXECdG4Yi4wCQq0x5awEE3D+s8m1ISRL+AlwfES hxBUJpIQEAb+Yk1zR/0e+A0I2Ysew0mc2+Gvb2+1ZNtaK4oNLBPiibHfRNsA6vPtjIai M7LuKCybeKJI+JaN++G6M4efAdNBMmndDNhD4zr9jIXY144blSuyYCIMtQZzO9xPJyqj KXRN0VbvFiju+Acke1siWlW2HfLbGhlhXoaitAqutnPuSkF48hFEo3uIvsl4QQZ0JDOY cexyjSU4Ih3H5VAN780K60QHBwSD58FKH+VuQ/Ras3qmkDbcqp63J0B4sjAOFhEFbgd9 5KiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VnxZk0J+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:18 -0700 Message-Id: <20180628030330.15615-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PATCH v3 11/23] target/openrisc: Merge tlb allocation into CPUOpenRISCState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no reason to allocate this separately. This was probably copied from target/mips which makes the same mistake. While doing so, move tlb into the clear-on-reset range. While not all of the TLB bits are guaranteed zero on reset, all of the valid bits are cleared, and the rest of the bits are unspecified. Therefore clearing the whole of the TLB is correct. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 6 ++++-- target/openrisc/interrupt.c | 4 ++-- target/openrisc/interrupt_helper.c | 8 +++---- target/openrisc/machine.c | 15 ++++++------- target/openrisc/mmu.c | 34 ++++++++++++++---------------- target/openrisc/sys_helper.c | 28 ++++++++++++------------ 6 files changed, 46 insertions(+), 49 deletions(-) -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c871d6bfe1..96b7f58659 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -301,6 +301,10 @@ typedef struct CPUOpenRISCState { uint32_t dflag; /* In delay slot (boolean) */ +#ifndef CONFIG_USER_ONLY + CPUOpenRISCTLBContext tlb; +#endif + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; @@ -310,8 +314,6 @@ typedef struct CPUOpenRISCState { uint32_t cpucfgr; /* CPU configure register */ #ifndef CONFIG_USER_ONLY - CPUOpenRISCTLBContext * tlb; - QEMUTimer *timer; uint32_t ttmr; /* Timer tick mode register */ int is_counting; diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 25351d5de3..2d0b55afa9 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -63,8 +63,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &= ~SR_TEE; env->pmr &= ~PMR_DME; env->pmr &= ~PMR_SME; - env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; - env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; if (exception > 0 && exception < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index b865738f8b..dc97b38704 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -36,18 +36,18 @@ void HELPER(rfe)(CPUOpenRISCState *env) #ifndef CONFIG_USER_ONLY if (cpu->env.sr & SR_DME) { - cpu->env.tlb->cpu_openrisc_map_address_data = + cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_data; } else { - cpu->env.tlb->cpu_openrisc_map_address_data = + cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } if (cpu->env.sr & SR_IME) { - cpu->env.tlb->cpu_openrisc_map_address_code = + cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_code; } else { - cpu->env.tlb->cpu_openrisc_map_address_code = + cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 0a793eb14d..c10d28b055 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -30,18 +30,18 @@ static int env_post_load(void *opaque, int version_id) /* Restore MMU handlers */ if (env->sr & SR_DME) { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_data; } else { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } if (env->sr & SR_IME) { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_code; } else { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; } @@ -77,10 +77,6 @@ static const VMStateDescription vmstate_cpu_tlb = { } }; -#define VMSTATE_CPU_TLB(_f, _s) \ - VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) - - static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { CPUOpenRISCState *env = opaque; @@ -143,7 +139,8 @@ static const VMStateDescription vmstate_env = { VMSTATE_UINT32(fpcsr, CPUOpenRISCState), VMSTATE_UINT64(mac, CPUOpenRISCState), - VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), + VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1, + vmstate_cpu_tlb, CPUOpenRISCTLBContext), VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 2bd782f89b..5665bb7cc9 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -46,19 +46,19 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, int idx = vpn & ITLB_MASK; int right = 0; - if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) { + if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } if (cpu->env.sr & SR_SM) { /* supervisor mode */ - if (cpu->env.tlb->itlb[0][idx].tr & SXE) { + if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |= PAGE_EXEC; } } else { - if (cpu->env.tlb->itlb[0][idx].tr & UXE) { + if (cpu->env.tlb.itlb[0][idx].tr & UXE) { right |= PAGE_EXEC; } } @@ -67,7 +67,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) | + *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot = right; return TLBRET_MATCH; @@ -81,25 +81,25 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, int idx = vpn & DTLB_MASK; int right = 0; - if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) { + if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } if (cpu->env.sr & SR_SM) { /* supervisor mode */ - if (cpu->env.tlb->dtlb[0][idx].tr & SRE) { + if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |= PAGE_READ; } - if (cpu->env.tlb->dtlb[0][idx].tr & SWE) { + if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { right |= PAGE_WRITE; } } else { - if (cpu->env.tlb->dtlb[0][idx].tr & URE) { + if (cpu->env.tlb.dtlb[0][idx].tr & URE) { right |= PAGE_READ; } - if (cpu->env.tlb->dtlb[0][idx].tr & UWE) { + if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { right |= PAGE_WRITE; } } @@ -111,7 +111,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) | + *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | (address & (TARGET_PAGE_SIZE-1)); *prot = right; return TLBRET_MATCH; @@ -126,10 +126,10 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, if (rw == MMU_INST_FETCH) { /* ITLB */ *physical = 0; - ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical, + ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, prot, address, rw); } else { /* DTLB */ - ret = cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical, + ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, prot, address, rw); } @@ -247,9 +247,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) { - cpu->env.tlb = g_malloc0(sizeof(CPUOpenRISCTLBContext)); - - cpu->env.tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - cpu->env.tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; + cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; + cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 2c959f63f4..ff315f6f1a 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -61,18 +61,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } cpu_set_sr(env, rb); if (env->sr & SR_DME) { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_data; } else { - env->tlb->cpu_openrisc_map_address_data = + env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; } if (env->sr & SR_IME) { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_code; } else { - env->tlb->cpu_openrisc_map_address_code = + env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; } break; @@ -101,14 +101,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK); } - env->tlb->dtlb[0][idx].mr = rb; + env->tlb.dtlb[0][idx].mr = rb; break; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - env->tlb->dtlb[0][idx].tr = rb; + env->tlb.dtlb[0][idx].tr = rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -120,14 +120,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK); } - env->tlb->itlb[0][idx].mr = rb; + env->tlb.itlb[0][idx].mr = rb; break; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - env->tlb->itlb[0][idx].tr = rb; + env->tlb.itlb[0][idx].tr = rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -259,11 +259,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - return env->tlb->dtlb[0][idx].mr; + return env->tlb.dtlb[0][idx].mr; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - return env->tlb->dtlb[0][idx].tr; + return env->tlb.dtlb[0][idx].tr; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -275,11 +275,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - return env->tlb->itlb[0][idx].mr; + return env->tlb.itlb[0][idx].mr; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - return env->tlb->itlb[0][idx].tr; + return env->tlb.itlb[0][idx].tr; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ From patchwork Thu Jun 28 03:03:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140396 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1651304ljj; Wed, 27 Jun 2018 20:15:00 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdN/kmRzdmt0RAyhmz8hTLY3mMwsaNnMz3tL0v7E8nAQ4rBgzOTVD4ikKsdEw6pwvTi3Cm6 X-Received: by 2002:a37:258f:: with SMTP id l15-v6mr7539875qkl.88.1530155700408; Wed, 27 Jun 2018 20:15:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155700; cv=none; d=google.com; s=arc-20160816; b=vmdP27xm36K+PFqBvYeIA2jfpjY+ZpRRLVktTCUSw9tXGi8hdPo7ImmjOWAUw3+Nzp TAFOHos5UY33ykrHFSFeCHEZ3dH2sLiEWSoS9AhNvrm5iiCQzrAzZZj/8NPkdvCmxW65 z7DZm74LTOXb273AiCc1CArFvTpsD7KSYA5FmOyOjEZ6l4lkvxyIdgaddCI52G4caQKQ zhj7Dk9oFTG7jTRC32oF4FpfHC4nA6m+833gIOoRl/L+Bo1QdhSzpMOpVT+YkFGLz83Y QVSz5PilRKIATawtGAsx3Ss2YroJap62sxMKQZrrSBvkZAF5h63qEIElVUndppVUVDHa AhJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=n8zIBshyKm5ShnwDFhZMEvedoWaqKvRMo6Si4yG69yo=; b=YB14RFGQq95BCcwQJUyjXHWmlh4WCNR4gdhnQI02QBcRyy/IHc9MUOLWkGbAwyRJjE I4DO3PsFV9/QqE051yfZSvWaZoj2ZvTVv8uFtaLIuD02FpZJNVh348iUe7uTcyIrJ8ZB NK2gNZ4q/WEDTy0huzb9onPAwxCBwkaS5cHI2ISX50Hm/+4CApEqncERS/wk0sixUXyq yECLTji0ARQaXGjQLyQGNc0ixTFAF5CdYkiajQFtAGMFbzSXU7sh5Elgu8kB37krwYNr RFzC9Tqe3+pH7djBfa01OqrWV6W719B/0/vyjoiDKfFp7BUZ1Qmmsujr864rA8u9G2gG hPeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OaHaCWIK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:19 -0700 Message-Id: <20180628030330.15615-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-devel] [PATCH v3 12/23] target/openrisc: Remove indirect function calls for mmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no reason to use an indirect branch instead of simply testing the SR bits that control mmu state. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 11 ----- target/openrisc/cpu.c | 4 -- target/openrisc/interrupt.c | 2 - target/openrisc/interrupt_helper.c | 25 ++--------- target/openrisc/machine.c | 26 ------------ target/openrisc/mmu.c | 66 +++++++++++++----------------- target/openrisc/sys_helper.c | 15 ------- 7 files changed, 31 insertions(+), 118 deletions(-) -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 96b7f58659..a27adad085 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -379,17 +379,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu); -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw); #endif #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fa8e342ff7..b92de51ecf 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -92,10 +92,6 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu = OPENRISC_CPU(obj); cs->env_ptr = &cpu->env; - -#ifndef CONFIG_USER_ONLY - cpu_openrisc_mmu_init(cpu); -#endif } /* CPU models */ diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 2d0b55afa9..23abcf29ed 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -63,8 +63,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->sr &= ~SR_TEE; env->pmr &= ~PMR_DME; env->pmr &= ~PMR_SME; - env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; - env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; env->lock_addr = -1; if (exception > 0 && exception < EXCP_NR) { diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index dc97b38704..a2e9003969 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -29,31 +29,12 @@ void HELPER(rfe)(CPUOpenRISCState *env) #ifndef CONFIG_USER_ONLY int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); -#endif - cpu->env.pc = cpu->env.epcr; - cpu_set_sr(&cpu->env, cpu->env.esr); - cpu->env.lock_addr = -1; - -#ifndef CONFIG_USER_ONLY - if (cpu->env.sr & SR_DME) { - cpu->env.tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - cpu->env.tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (cpu->env.sr & SR_IME) { - cpu->env.tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - cpu->env.tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } - if (need_flush_tlb) { CPUState *cs = CPU(cpu); tlb_flush(cs); } #endif + cpu->env.pc = cpu->env.epcr; + cpu->env.lock_addr = -1; + cpu_set_sr(&cpu->env, cpu->env.esr); } diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index c10d28b055..73e0abcfd7 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -24,31 +24,6 @@ #include "hw/boards.h" #include "migration/cpu.h" -static int env_post_load(void *opaque, int version_id) -{ - CPUOpenRISCState *env = opaque; - - /* Restore MMU handlers */ - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } - - - return 0; -} - static const VMStateDescription vmstate_tlb_entry = { .name = "tlb_entry", .version_id = 1, @@ -102,7 +77,6 @@ static const VMStateDescription vmstate_env = { .name = "env", .version_id = 6, .minimum_version_id = 6, - .post_load = env_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), VMSTATE_UINTTL(pc, CPUOpenRISCState), diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 5665bb7cc9..b2effaa6d7 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,18 +29,16 @@ #endif #ifndef CONFIG_USER_ONLY -int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static inline int get_phys_nommu(hwaddr *physical, int *prot, + target_ulong address) { *physical = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } -int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & ITLB_MASK; @@ -52,8 +50,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.itlb[0][idx].tr & SXE) { right |= PAGE_EXEC; } @@ -62,7 +59,6 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, right |= PAGE_EXEC; } } - if ((rw & 2) && ((right & PAGE_EXEC) == 0)) { return TLBRET_BADADDR; } @@ -73,9 +69,8 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu, return TLBRET_MATCH; } -int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, int rw) +static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, + target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & DTLB_MASK; @@ -87,8 +82,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { return TLBRET_INVALID; } - - if (cpu->env.sr & SR_SM) { /* supervisor mode */ + if (supervisor) { if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { right |= PAGE_READ; } @@ -117,20 +111,24 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu, return TLBRET_MATCH; } -static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu, - hwaddr *physical, - int *prot, target_ulong address, - int rw) +static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, + int *prot, target_ulong address, int rw) { - int ret = TLBRET_MATCH; + bool supervisor = (cpu->env.sr & SR_SM) != 0; + int ret; - if (rw == MMU_INST_FETCH) { /* ITLB */ - *physical = 0; - ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical, - prot, address, rw); - } else { /* DTLB */ - ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical, - prot, address, rw); + /* Assume nommu results for a moment. */ + ret = get_phys_nommu(physical, prot, address); + + /* Overwrite with TLB lookup if enabled. */ + if (rw == MMU_INST_FETCH) { + if (cpu->env.sr & SR_IME) { + ret = get_phys_code(cpu, physical, prot, address, rw, supervisor); + } + } else { + if (cpu->env.sr & SR_DME) { + ret = get_phys_data(cpu, physical, prot, address, rw, supervisor); + } } return ret; @@ -186,8 +184,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, hwaddr physical = 0; int prot = 0; - ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot, - address, rw); + ret = get_phys_addr(cpu, &physical, &prot, address, rw); if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, @@ -225,17 +222,16 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) /* Check memory for any kind of address, since during debug the gdb can ask for anything, check data tlb for address */ - miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0); /* Check instruction tlb */ if (miss) { - miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, - MMU_INST_FETCH); + miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH); } /* Last, fall back to a plain address */ if (miss) { - miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0); + miss = get_phys_nommu(&phys_addr, &prot, addr); } if (miss) { @@ -244,10 +240,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } - -void cpu_openrisc_mmu_init(OpenRISCCPU *cpu) -{ - cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; - cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; -} #endif diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ff315f6f1a..9b4339b34e 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -60,21 +60,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) tlb_flush(cs); } cpu_set_sr(env, rb); - if (env->sr & SR_DME) { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_data; - } else { - env->tlb.cpu_openrisc_map_address_data = - &cpu_openrisc_get_phys_nommu; - } - - if (env->sr & SR_IME) { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_code; - } else { - env->tlb.cpu_openrisc_map_address_code = - &cpu_openrisc_get_phys_nommu; - } break; case TO_SPR(0, 18): /* PPC */ From patchwork Thu Jun 28 03:03:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140391 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1647498ljj; Wed, 27 Jun 2018 20:10:05 -0700 (PDT) X-Google-Smtp-Source: AAOMgpclkMoOeDXAoKyiknE6QzD3ht5I0iIvViw7iqIUxIGAszI202lE0vlWFOSyWgdsDwIsHGMb X-Received: by 2002:a37:4bd8:: with SMTP id y207-v6mr7045559qka.98.1530155405807; Wed, 27 Jun 2018 20:10:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155405; cv=none; d=google.com; s=arc-20160816; b=Fp5JdTsvrBW5DuMTM6Fmj2Xy5SXg4h7QebsIHWMVePdaFptkX7TL5QLgu/gdCwEXQY 15w6dZ97Ci/p3outSdpBSWIQPNnkvS2siw8uXhV7tp6gCtbHCVYw9dYH9PjDT4A+ai9A 5nKM6XyKwn8SnKGicrslp9tIcDPjK+hTqsLSV9qMcXHOaqbfcvdnbWdQ/xhb4GvUXqEJ fRIiboYvBLDa1AZAwD9w33cX6AWktvODDUshw2St1gurTJAMuLSzsj1p0CxQloBrgiUM TTYGPArAN3TUSXY7BQpBGY9jASpGpuCq+SUdWvIE68mQQTeALexSE0cz8yKGZ5H4mjW9 LBOg== ARC-Message-Signature: i=1; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:20 -0700 Message-Id: <20180628030330.15615-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v3 13/23] target/openrisc: Merge mmu_helper.c into mmu.c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With tlb_fill in mmu.c, we can simplify things further. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/mmu.c | 11 ++++++++++ target/openrisc/mmu_helper.c | 40 ----------------------------------- target/openrisc/Makefile.objs | 2 +- 3 files changed, 12 insertions(+), 41 deletions(-) delete mode 100644 target/openrisc/mmu_helper.c -- 2.17.1 diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index b2effaa6d7..9b4b5cf04f 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -240,4 +240,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } } + +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, + access_type, mmu_idx); + if (ret) { + /* Raise Exception. */ + cpu_loop_exit_restore(cs, retaddr); + } +} #endif diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c deleted file mode 100644 index 97e1d17b5a..0000000000 --- a/target/openrisc/mmu_helper.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * OpenRISC MMU helper routines - * - * Copyright (c) 2011-2012 Jia Liu - * Zhizhou Zhang - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "exec/cpu_ldst.h" - -#ifndef CONFIG_USER_ONLY - -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - - if (ret) { - /* Raise Exception. */ - cpu_loop_exit_restore(cs, retaddr); - } -} -#endif diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs index 8b8a890c59..b5432f4684 100644 --- a/target/openrisc/Makefile.objs +++ b/target/openrisc/Makefile.objs @@ -1,7 +1,7 @@ obj-$(CONFIG_SOFTMMU) += machine.o obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o obj-y += exception_helper.o fpu_helper.o \ - interrupt_helper.o mmu_helper.o sys_helper.o + interrupt_helper.o sys_helper.o obj-y += gdbstub.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py From patchwork Thu Jun 28 03:03:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140397 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1651437ljj; Wed, 27 Jun 2018 20:15:15 -0700 (PDT) X-Google-Smtp-Source: AAOMgpffZcZmq6jZy+3WYhnqolwLChTwg/gDSUriPoGzJTNC7oJ0KlGQAFGv1Neb2pCXhX/wz5Ez X-Received: by 2002:a0c:f489:: with SMTP id i9-v6mr7835679qvm.0.1530155715452; Wed, 27 Jun 2018 20:15:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155715; cv=none; d=google.com; s=arc-20160816; b=R59d2kHaojSKUuF+KFyL4w4rmA7CaZCXHh31QSBUvv8pjb+UIACFs/quo8KuVm+Fi6 1T1EC6UcAJ+ccdhRCvJ60SBqbgaEUkSNprij2eP8zhN16TnYUjdcfi2Gde4kfRNRCDMZ wyonNTomh1W2lP3egNhbpYSTi7UkKBWkWkoEP5YQTcyln9Si2YfGCQazM6pIfn93tMTc KkWp1BjooRbKWCwGdjhxRkDeQm4lbLZaW41aAGP2TUqwzECiR7uib3AEHjCwW3/lLCmJ Z2TUFr1AQAgwcrnuGFxXCELqXoHbczf89bGV3uy6Ka+02HbKO3RHfA6mIwIBDuEPVtSA ebEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Bil15QOSQ0zS0qJ7FyRf/MlAG01HeYBpt0dN9mHBhmM=; b=W0E1C74xWRNkGBI8Fso5qSmw/M3ev5iau6wz18tmNofVQ4UcUUSFqXCOiSaXSFj5Xt wMxuVtJ81X6IntDfvIFV7RYh1L15+W2od2uk51xLqKRRn0jyftRf8VF0Ggj497JAmB9C PxK9A7WRZT/vHWUYnauFIrxzJzszmy8iyr7UzSG0C/aBK2UeB69rr8Oz+ngiv1sYprPa TA9R8FwlyJZtgcrWXlDj0Ykalru85hwwTlseO7lXkAeraZPeW057ZZN9GD/ylZFNGnrn hqGHidPGKXGjBDqPdL2Ovx/6F/JaE8cmnA10JrFoLh24kePfG3Ew6YFdOYouOMtlj3jD 2scA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kAqMUXnb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:21 -0700 Message-Id: <20180628030330.15615-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v3 14/23] target/openrisc: Reduce tlb to a single dimension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 6 ++---- target/openrisc/machine.c | 6 ++---- target/openrisc/mmu.c | 30 ++++++++++++++++-------------- target/openrisc/sys_helper.c | 20 ++++++++++---------- 4 files changed, 30 insertions(+), 32 deletions(-) -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index a27adad085..eaf6cdd40e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { /* TLB size */ enum { - DTLB_WAYS = 1, DTLB_SIZE = 64, DTLB_MASK = (DTLB_SIZE-1), - ITLB_WAYS = 1, ITLB_SIZE = 64, ITLB_MASK = (ITLB_SIZE-1), }; @@ -256,8 +254,8 @@ typedef struct OpenRISCTLBEntry { #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE]; + OpenRISCTLBEntry itlb[ITLB_SIZE]; + OpenRISCTLBEntry dtlb[DTLB_SIZE]; int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 73e0abcfd7..b795b56dc6 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,11 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, - ITLB_WAYS, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, - DTLB_WAYS, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 9b4b5cf04f..856969a7f2 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -43,19 +43,21 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & ITLB_MASK; int right = 0; + uint32_t mr = cpu->env.tlb.itlb[idx].mr; + uint32_t tr = cpu->env.tlb.itlb[idx].tr; - if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.itlb[0][idx].tr & SXE) { + if (tr & SXE) { right |= PAGE_EXEC; } } else { - if (cpu->env.tlb.itlb[0][idx].tr & UXE) { + if (tr & UXE) { right |= PAGE_EXEC; } } @@ -63,8 +65,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); *prot = right; return TLBRET_MATCH; } @@ -75,25 +76,27 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, int vpn = address >> TARGET_PAGE_BITS; int idx = vpn & DTLB_MASK; int right = 0; + uint32_t mr = cpu->env.tlb.dtlb[idx].mr; + uint32_t tr = cpu->env.tlb.dtlb[idx].tr; - if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) { + if ((mr >> TARGET_PAGE_BITS) != vpn) { return TLBRET_NOMATCH; } - if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) { + if (!(mr & 1)) { return TLBRET_INVALID; } if (supervisor) { - if (cpu->env.tlb.dtlb[0][idx].tr & SRE) { + if (tr & SRE) { right |= PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & SWE) { + if (tr & SWE) { right |= PAGE_WRITE; } } else { - if (cpu->env.tlb.dtlb[0][idx].tr & URE) { + if (tr & URE) { right |= PAGE_READ; } - if (cpu->env.tlb.dtlb[0][idx].tr & UWE) { + if (tr & UWE) { right |= PAGE_WRITE; } } @@ -105,8 +108,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, return TLBRET_BADADDR; } - *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) | - (address & (TARGET_PAGE_SIZE-1)); + *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); *prot = right; return TLBRET_MATCH; } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 9b4339b34e..7f458b0d17 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -86,14 +86,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.dtlb[0][idx].mr = rb; + env->tlb.dtlb[idx].mr = rb; break; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - env->tlb.dtlb[0][idx].tr = rb; + env->tlb.dtlb[idx].tr = rb; break; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -105,14 +105,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK); + tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); } - env->tlb.itlb[0][idx].mr = rb; + env->tlb.itlb[idx].mr = rb; break; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - env->tlb.itlb[0][idx].tr = rb; + env->tlb.itlb[idx].tr = rb; break; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ @@ -244,11 +244,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - return env->tlb.dtlb[0][idx].mr; + return env->tlb.dtlb[idx].mr; case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); - return env->tlb.dtlb[0][idx].tr; + return env->tlb.dtlb[idx].tr; case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ @@ -260,11 +260,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - return env->tlb.itlb[0][idx].mr; + return env->tlb.itlb[idx].mr; case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); - return env->tlb.itlb[0][idx].tr; + return env->tlb.itlb[idx].tr; case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ From patchwork Thu Jun 28 03:03:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140394 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1649684ljj; Wed, 27 Jun 2018 20:12:50 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdWaImBPeohaxwdbo2HmBhh9e0LOKuGtt/TpZUXVu1KbGGqJwE7HHgnKKlV4oTKspQUWEBH X-Received: by 2002:aed:25ac:: with SMTP id x41-v6mr7843575qtc.286.1530155570211; Wed, 27 Jun 2018 20:12:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155570; cv=none; d=google.com; s=arc-20160816; b=bG0Zn2yBRYNQd4PyYs/YPSV06j7InB6QlsK0BzklJebqbfsfHcFE4jcJ4G+MyB/4W4 PrRkRucTx6RXCO8mQNVF6tRSXkjVpVpNptSnjkjN26/Ioz1YyvT3i87Onl0mAHxOjFbj K66T7IOPgDOEKhlu9X/l+n/oF22tUXedVgUyB6oI5gbhAehgP+MWlypUslp93PJL/JSY tOoPW3CI4yMaw0jC/Gb/vUCWSuaF153rH9hAQZvJO76mPkUlJgZARBinxauNKMNOtrjm 0c9KRbGKkCk0oFnH/GY2iXUOQ5mytMQQdRwGYZK5RKs850AdfPirooOyfWJTkiOxJkRV j8vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aHlqpS7RETtmpB2uggIW2fraBTAjhAqUaCXBJAbuBE8=; b=OGb2DONh6Zuded+/RW6lNuQzZgtRZFvMIDwM769jpRSyq6MQ0N/6+qMfcVzWeiLS2z /xchRSdIFYf7qYyCS0xpRahi8WLvUGOrelAEh+Z+oEBiXjQOwrMvtO2HK7/NxUDrozO0 Unm6qjkq04XSIHk/C9UqlgIh7/S40TKUUI0yHbLbCerYLwCAaaOWXMW8GTPmWPUVHGaI WSlqTSYZR0cEQeYawinxbr7DEC7bQDJ3oGM4sJLz4lCy424F+3yi6xPfeFX/QJ5KEb3i Hbz4/RcSov/3+o4xU1dFBmEfL+PiUpwZj0pPqYpqjvFt3I0cpeJ+hE2hPdJnMiXb9yEK XvAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CxdgLthm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:22 -0700 Message-Id: <20180628030330.15615-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PATCH v3 15/23] target/openrisc: Fix tlb flushing in mtspr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The previous code was confused, avoiding the flush of the old entry if the new entry is invalid. We need to flush the old page if the old entry is valid and the new page if the new entry is valid. This bug was masked by over-flushing elsewhere. Signed-off-by: Richard Henderson --- target/openrisc/sys_helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 7f458b0d17..c9702cd26c 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -32,6 +32,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) #ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); + target_ulong mr; int idx; switch (spr) { @@ -85,12 +86,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK); + mr = env->tlb.dtlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.dtlb[idx].mr = rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr = rb; @@ -102,14 +106,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; + case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); - if (!(rb & 1)) { - tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK); + mr = env->tlb.itlb[idx].mr; + if (mr & 1) { + tlb_flush_page(cs, mr & TARGET_PAGE_MASK); + } + if (rb & 1) { + tlb_flush_page(cs, rb & TARGET_PAGE_MASK); } env->tlb.itlb[idx].mr = rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr = rb; @@ -121,6 +129,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ break; + case TO_SPR(5, 1): /* MACLO */ env->mac = deposit64(env->mac, 0, 32, rb); break; From patchwork Thu Jun 28 03:03:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140402 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1653450ljj; Wed, 27 Jun 2018 20:18:13 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfq9vrhzgMBntMMh8P0dI4aJaZ3VBwOlw8mUveqimujXV6kUx89fjXkhGZgOCcOt1up/6D5 X-Received: by 2002:ac8:37b4:: with SMTP id d49-v6mr7937759qtc.369.1530155893483; Wed, 27 Jun 2018 20:18:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155893; cv=none; d=google.com; s=arc-20160816; b=azfeYz665CTwsO8vCPDwQ4H90PFAO0aVzdy91yCbfhZOq0mLJsL47FG7dcY2tQfnzU J/4X/yMOzDKq0TRDet3M6KTLvVI4AwULkE5pbVoU4YRtVYTwZj5hfVWVlkHD/AkCnxP0 QfV0CYQKtxhgl4JmfIcp8X11jHa1uJR2U4dDG/oCjCC2fMs9M0/MpIFQpU2yZkkdBRkf yz63bqV/HwP7QkI/XXw2lRapTPBIjf20t3oOwY1xaXo6Whdgw9LY7MJp4FC0OxN7/Avj qaK2mxWrEgF09yrC5m6rZEMB0YhOcuLXZvCSEAYBU00CBAK/rQOJVsNDH2sy/XMkKZdV gv2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=gqpkBrnMXmCHUNA04bgHmVGCH8EZrj3KsqVze2SkZ1g=; b=R/JBboHIH5uh3WDX/LsLqn/j+HxU+R9UMF18H4CRWs+iJu9uwJx4YqCYnGIQdyvZJY kcpQbDo9k7wbbMSJPJz9Fa9np3aT5XAhSd8nuaSxAiabjVb1hsKHZaPdc/3IYGEPHtDv Wyh3UwNCwvvav983hzsXOYMyS7mLYmsm1IdwwpCzrWc5u2/BJyAYKun+vVGIeEyRA9T8 DH3KvJjNU24+WX90Gn7VsUKY2srDy+Yn0sAv/XRjI8df1ac3JuNUfbtIPz4Jl8Gqzzdb WaD58OP2JBQkn0EoD/FgysWjhoexYhR6+Cdo1BXVttzHVT0xECxUoxrzcuIQe1VVL8iR vHdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UTkgQwfJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:23 -0700 Message-Id: <20180628030330.15615-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 16/23] target/openrisc: Fix cpu_mmu_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The code in cpu_mmu_index does not properly honor SR_DME. This bug has workarounds elsewhere in that we flush the tlb more often than necessary, on the state changes that should be reflected in a change of mmu_index. Fixing this means that we can respect the mmu_index that is given to tlb_flush. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 23 +++++++++++++-------- target/openrisc/interrupt.c | 4 ---- target/openrisc/interrupt_helper.c | 15 +++----------- target/openrisc/mmu.c | 33 +++++++++++++++++++++++++++--- target/openrisc/sys_helper.c | 4 ---- target/openrisc/translate.c | 2 +- 6 files changed, 49 insertions(+), 32 deletions(-) -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index eaf6cdd40e..c3a968ec4d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -385,9 +385,12 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #include "exec/cpu-all.h" -#define TB_FLAGS_DFLAG 1 -#define TB_FLAGS_R0_0 2 +#define TB_FLAGS_SM SR_SM +#define TB_FLAGS_DME SR_DME +#define TB_FLAGS_IME SR_IME #define TB_FLAGS_OVE SR_OVE +#define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ +#define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) { @@ -405,17 +408,21 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, { *pc = env->pc; *cs_base = 0; - *flags = (env->dflag - | (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0) - | (env->sr & SR_OVE)); + *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) { - if (!(env->sr & SR_IME)) { - return MMU_NOMMU_IDX; + int ret = MMU_NOMMU_IDX; /* mmu is disabled */ + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; } - return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; + + return ret; } static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index 23abcf29ed..138ad17f00 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -51,10 +51,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs) env->eear = env->pc; } - /* For machine-state changed between user-mode and supervisor mode, - we need flush TLB when we enter&exit EXCP. */ - tlb_flush(cs); - env->esr = cpu_get_sr(env); env->sr &= ~SR_DME; env->sr &= ~SR_IME; diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c index a2e9003969..9c5489f5f7 100644 --- a/target/openrisc/interrupt_helper.c +++ b/target/openrisc/interrupt_helper.c @@ -25,16 +25,7 @@ void HELPER(rfe)(CPUOpenRISCState *env) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); -#ifndef CONFIG_USER_ONLY - int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ - (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); - if (need_flush_tlb) { - CPUState *cs = CPU(cpu); - tlb_flush(cs); - } -#endif - cpu->env.pc = cpu->env.epcr; - cpu->env.lock_addr = -1; - cpu_set_sr(&cpu->env, cpu->env.esr); + env->pc = env->epcr; + env->lock_addr = -1; + cpu_set_sr(env, env->esr); } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 856969a7f2..b293b64e98 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -246,9 +246,36 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, - access_type, mmu_idx); - if (ret) { + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + int ret, prot = 0; + hwaddr physical = 0; + + if (mmu_idx == MMU_NOMMU_IDX) { + ret = get_phys_nommu(&physical, &prot, addr); + } else { + bool super = mmu_idx == MMU_SUPERVISOR_IDX; + if (access_type == MMU_INST_FETCH) { + ret = get_phys_code(cpu, &physical, &prot, addr, 2, super); + } else { + ret = get_phys_data(cpu, &physical, &prot, addr, + access_type == MMU_DATA_STORE, super); + } + } + + if (ret == TLBRET_MATCH) { + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + } else if (ret < 0) { + int rw; + if (access_type == MMU_INST_FETCH) { + rw = 2; + } else if (access_type == MMU_DATA_STORE) { + rw = 1; + } else { + rw = 0; + } + cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret); /* Raise Exception. */ cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index c9702cd26c..852b219f9b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -56,10 +56,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) break; case TO_SPR(0, 17): /* SR */ - if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ - (rb & (SR_IME | SR_DME | SR_SM))) { - tlb_flush(cs); - } cpu_set_sr(env, rb); break; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 64b5e84630..a271cd3903 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -55,7 +55,7 @@ static inline bool is_user(DisasContext *dc) #ifdef CONFIG_USER_ONLY return true; #else - return dc->mem_idx == MMU_USER_IDX; + return !(dc->tb_flags & TB_FLAGS_SM); #endif } From patchwork Thu Jun 28 03:03:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140401 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1653308ljj; Wed, 27 Jun 2018 20:18:01 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeN0fSay94yrC91jc0Q07W8pDeaj58/VUeawUeNhwjqD7ycNiAlmAUhUl7bGr2i8TcV+3sw X-Received: by 2002:ac8:f2c:: with SMTP id e41-v6mr4338709qtk.260.1530155880952; Wed, 27 Jun 2018 20:18:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155880; cv=none; d=google.com; s=arc-20160816; b=jZ4JhdsOsgCSGaFD3bZKEsvR366766975rveIiQ5GjihydS7LptC+iDaWUgWMR3LNb Kezfx8YrhUvV5enaogtaue3rIMGNMnwBjEmBGOO7IryiLArLYJWsV8eHeQZt74KaldYp TRMarQd/opSTSwxAqTu16Aoi5Hb6CsBJpgq0DR4U+PmtRRw5YkjE3LNWRPJLN17bPuo4 G3nn+qzmTmUBTYuoA9gRh8rN5bxGPqvQ1UQ6HsggpC7MXdwSZdpAM5xi7GUlf/I3bRam dVblw7l2J9WIFU0iK+Ypp62lWQVoWlLluBAuvkxfnUsULk1JsY1HttR423lRJ48iGkcF ErEw== ARC-Message-Signature: i=1; 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:24 -0700 Message-Id: <20180628030330.15615-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::234 Subject: [Qemu-devel] [PATCH v3 17/23] target/openrisc: Use identical sizes for ITLB and DTLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The sizes are already the same, however, we can improve things if they are identical by design. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++++------ target/openrisc/machine.c | 4 ++-- target/openrisc/mmu.c | 4 ++-- target/openrisc/sys_helper.c | 16 ++++++++-------- 4 files changed, 16 insertions(+), 18 deletions(-) -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c3a968ec4d..47e94659e1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,10 +222,8 @@ enum { /* TLB size */ enum { - DTLB_SIZE = 64, - DTLB_MASK = (DTLB_SIZE-1), - ITLB_SIZE = 64, - ITLB_MASK = (ITLB_SIZE-1), + TLB_SIZE = 64, + TLB_MASK = TLB_SIZE - 1, }; /* TLB prot */ @@ -254,8 +252,8 @@ typedef struct OpenRISCTLBEntry { #ifndef CONFIG_USER_ONLY typedef struct CPUOpenRISCTLBContext { - OpenRISCTLBEntry itlb[ITLB_SIZE]; - OpenRISCTLBEntry dtlb[DTLB_SIZE]; + OpenRISCTLBEntry itlb[TLB_SIZE]; + OpenRISCTLBEntry dtlb[TLB_SIZE]; int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, hwaddr *physical, diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index b795b56dc6..3fc837b925 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -42,9 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), - VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0, + VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), VMSTATE_END_OF_LIST() } diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index b293b64e98..a4613e9ae4 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -41,7 +41,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & ITLB_MASK; + int idx = vpn & TLB_MASK; int right = 0; uint32_t mr = cpu->env.tlb.itlb[idx].mr; uint32_t tr = cpu->env.tlb.itlb[idx].tr; @@ -74,7 +74,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw, bool supervisor) { int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & DTLB_MASK; + int idx = vpn & TLB_MASK; int right = 0; uint32_t mr = cpu->env.tlb.dtlb[idx].mr; uint32_t tr = cpu->env.tlb.dtlb[idx].tr; diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 852b219f9b..541615bfb3 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -80,7 +80,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) env->shadow_gpr[idx / 32][idx % 32] = rb; break; - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); mr = env->tlb.dtlb[idx].mr; if (mr & 1) { @@ -91,7 +91,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } env->tlb.dtlb[idx].mr = rb; break; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); env->tlb.dtlb[idx].tr = rb; break; @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); mr = env->tlb.itlb[idx].mr; if (mr & 1) { @@ -114,7 +114,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } env->tlb.itlb[idx].mr = rb; break; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); env->tlb.itlb[idx].tr = rb; break; @@ -247,11 +247,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, idx = (spr - 1024); return env->shadow_gpr[idx / 32][idx % 32]; - case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */ + case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ idx = spr - TO_SPR(1, 512); return env->tlb.dtlb[idx].mr; - case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */ + case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ idx = spr - TO_SPR(1, 640); return env->tlb.dtlb[idx].tr; @@ -263,11 +263,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ break; - case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */ + case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ idx = spr - TO_SPR(2, 512); return env->tlb.itlb[idx].mr; - case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */ + case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ idx = spr - TO_SPR(2, 640); return env->tlb.itlb[idx].tr; From patchwork Thu Jun 28 03:03:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140404 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1653831ljj; Wed, 27 Jun 2018 20:18:45 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcXlWSoiF/w0PhAkj1jj88Eq5U3kLmt3d1x0dPJvlD9xo1BaGsfcsDSGdeNG0vmqVWds2qw X-Received: by 2002:ae9:c002:: with SMTP id u2-v6mr3391386qkk.391.1530155925428; Wed, 27 Jun 2018 20:18:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155925; cv=none; d=google.com; s=arc-20160816; b=EoyhIEIxqbH9KtUdEUbxVlZr0ojnfVY62MOrDqepiUUMJBmPxPWaDVcZ+9GuCTtjNJ r7TWequZ7jLOUu5tvK5grTdOFgNYuWgN9DoTHYT7S7UsbyPZx9QEgdD6gnlsLZVspPYU HurM7rbZ2QY6kWQzQJvDUT2o9cDeHjKSYXtHZX5/4VSE5KjNl2tP4MFtiiRaTJuJjifZ PyjFkKNqA2O/beZUzzaTpzbwIcrcCBA/RzPBmSaP1t4RUJG7u1pezoqf/+lD02ykAT5Y tczTiZMmw3+XqkVVeZmY+acu85CVTJ36Eoeuh9bIdckC7L4oLOQXu/ktt6eGfJ3PY9mU 3lew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xQ7MuAb0CMxAlY812ETLA9j5/iyPIirofg3K3ekSZ3o=; b=gQyD8KmBA1mHdXdc6e+ojuS5huXfkdqpkhi1xPERWatuHTd550zsH32pvttG1JZH1O IIW+1kR9gGPuECqS7GAwf9iypLe4y1s9AAyxafjn/MF8PuEsXTSK1hknLk80KdhV57Wq ID1YVXd60u6aF0o30hKg4i2+chnbABRzrur7eFr/ENutVdTuI5zGDX/1yvadkp7q2Fcw R29CXYff0KyhgrA0wiFtmDNvpb9Rxtl8rHi78W1u3+3GbCwzCKAGEr0b5UQ6r7JsA9AJ Dhil33E6vcfsuu0740Vm3OKLFITJF4kFeJWTLUHjwuZgwtWUdJTHySR5mYl6DBCIDne/ Gq+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RUPwBz+W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:25 -0700 Message-Id: <20180628030330.15615-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::230 Subject: [Qemu-devel] [PATCH v3 18/23] target/openrisc: Stub out handle_mmu_fault for softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This hook is only used by CONFIG_USER_ONLY. Signed-off-by: Richard Henderson --- target/openrisc/mmu.c | 35 +++++------------------------------ 1 file changed, 5 insertions(+), 30 deletions(-) -- 2.17.1 diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index a4613e9ae4..f4c0a3e217 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -177,42 +177,17 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, cpu->env.lock_addr = -1; } -#ifndef CONFIG_USER_ONLY int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mmu_idx) { +#ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret = 0; - hwaddr physical = 0; - int prot = 0; - - ret = get_phys_addr(cpu, &physical, &prot, address, rw); - - if (ret == TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - ret = 0; - } else if (ret < 0) { - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret = 1; - } - - return ret; -} + cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0); + return 1; #else -int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, - int rw, int mmu_idx) -{ - OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret = 0; - - cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret); - ret = 1; - - return ret; -} + g_assert_not_reached(); #endif +} #ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) From patchwork Thu Jun 28 03:03:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140398 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1651606ljj; Wed, 27 Jun 2018 20:15:29 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdJltCZNbnpHqCsktH3dU11TwoZr9hqxnE1sv/BP8raEAsA+F23IPY1wBqjDoDBYLC1AE94 X-Received: by 2002:a37:8547:: with SMTP id h68-v6mr7457123qkd.340.1530155729820; Wed, 27 Jun 2018 20:15:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155729; cv=none; d=google.com; s=arc-20160816; b=SLaItJXvJpCoSBNcyf1RgeJKVng+KCUYL/qwZ6IiV5l+48cxv5d+SbOFHOoIBQd5ma ideJbUWaFb19qFf9ItRslN6nlqpF6XTwtG9BO7IzJfIOwid5+CO4jm/DLw1H/0mshRFX MD36NkHY0IZ4QJQSLYXo2q3jx6zht3u9BZS9CTNmqhvGvsuKwXxNNTbD+L9644pe+4Nr CAiJ4K73joYIIbuMkK8Y2AaUSmgkSuXnwO3M+IZgH2VENRkxKbFn+f6v7qm/2t7aIbpx 80aC7AA63N6Xmk5TXmgzLSOzDC0XHSsAA1OClba6pflMp/FOiXCoUgQuj+GNNolEbuec q0YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YC2RVVbcg0kjLTtKougHEu94D19YVoQfzJ/owdisDE8=; b=G1kuNwxTszW/DCtLudbwx5Hw7K8VBITgqPxnXbce+jK2yXb6VwpBWoOnXzBFNAqw0Q C2JCTzavrGH2gKfX39buZmFBDBoW/K2QBMJoDLi8uDcJklheJqoZHftaaIJ1/fBI/qyn A1ASZP45gIwi+8YHTMiM9ehBO7/9RTa9cg5qE2emTVc+oBDheUq69tNcQX/9prhc2AUi xu3l571q6OG3YNplnElZCnPb8ARBerFJNxsepk1CF9EvlurTrPMFHCwAFWUQYgUVaIXK XYxlxNZHTSBY3VA3Vv8v7ENGyuOmyEBuNHF4zMeGWmQ1AtcImPHhI9mRU9LwhV5OundK IsIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZAlE4GCe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:26 -0700 Message-Id: <20180628030330.15615-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PATCH v3 19/23] target/openrisc: Increase the TLB size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The architecture supports 128 TLB entries. There is no reason not to provide all of them. In the process we need to fix a bug that failed to parameterize the configuration register that tells the operating system the number of entries. Signed-off-by: Richard Henderson --- v2: - Change VMState version. --- target/openrisc/cpu.h | 2 +- target/openrisc/cpu.c | 6 ++++-- target/openrisc/machine.c | 5 ++--- 3 files changed, 7 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 47e94659e1..b180e30e9e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -222,7 +222,7 @@ enum { /* TLB size */ enum { - TLB_SIZE = 64, + TLB_SIZE = 128, TLB_MASK = TLB_SIZE - 1, }; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b92de51ecf..e01ce9ed1c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); - cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); + cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index 3fc837b925..1eedbf3dbe 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = { static const VMStateDescription vmstate_cpu_tlb = { .name = "cpu_tlb", - .version_id = 1, - .minimum_version_id = 1, - .minimum_version_id_old = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0, vmstate_tlb_entry, OpenRISCTLBEntry), From patchwork Thu Jun 28 03:03:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140403 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1653670ljj; Wed, 27 Jun 2018 20:18:30 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdDtObkRe0ipk2P4YjpXNuyONw4+wpnXTKlewR7f9Wh0OSRKYiPFAvY0FJhq9wEXkBzBrLH X-Received: by 2002:a0c:8c4c:: with SMTP id o12-v6mr7610491qvb.185.1530155910040; Wed, 27 Jun 2018 20:18:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155910; cv=none; d=google.com; s=arc-20160816; b=xZipV6hiwsqMmr39i5pWXAhdI07YYtVGEyMvE9FFgPGj8bvHyhy0scjSRnT7z3PUwb XpVSzOXUGMF+zOceIMFfZ6wu5iok5DlKbTGu4W37V59VL5LZkep7ZrgaFjbwYK/jlU+z AohCxbF0d6PJVSVDErqKUjUesaQxQj8A/eL/3BAwjkVhZXgUJ5sT/xu2SITaegFMS9T4 PlIjzjCKWLACyv+P9Te0tDVVCyX2fXChw+SRh2BnqkXFSqPdqkDFUe4pdZSXvA9rUQRE lHVqk+QNA36IPAUff9ySJpIIctxK5qpDIpJZwqjqct8P3c18o63a0+Vv4ss62YFgQ98v fp8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=gwN/7WgsND7BL7PgsVURX7sh5YIFP5WSPDM5slNfWQM=; b=h1OcQCD2OyCSmHRMI8oeUKOBA+qZsVkCl/BqdfFoOLjJmhqyMD4oxfjBrQ3mTmu2yr yQKoFsYDGZbI5MMVfQP1uMXsPC3qfmgd8IT5Tykpu15Ye7GlXvn5fkkieszVYL3lA/m2 hdzCel51FNRq7iNt17CMOj8K4MQl1vFSxTD7oI4rgPlioViR4sUnWfYlzR5vj2k5nSck nPlaEHrXbd+pQgx1MH20iOeyhYBDUavGfVJBmLi/RWHi4vrGQes0LssB/qemlYQcaFBy J3YDWKudPGKNLSBOTQaA2lffIXPaQwMxqW7uuFj6nGYrDC/izDxcTKrDswjFesqNysKu XlEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ie8oebXh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.03.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:03:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:27 -0700 Message-Id: <20180628030330.15615-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH v3 20/23] target/openrisc: Reorg tlb lookup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While openrisc has a split i/d tlb, qemu does not. Perform a lookup on both i & d tlbs in parallel and put the composite rights into qemu's tlb. This avoids ping-ponging the qemu tlb between EXEC and READ. Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 8 -- target/openrisc/mmu.c | 254 +++++++++++++++--------------------------- 2 files changed, 90 insertions(+), 172 deletions(-) -- 2.17.1 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b180e30e9e..f1b31bc24a 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -237,14 +237,6 @@ enum { UXE = (1 << 7), }; -/* check if tlb available */ -enum { - TLBRET_INVALID = -3, - TLBRET_NOMATCH = -2, - TLBRET_BADADDR = -1, - TLBRET_MATCH = 0 -}; - typedef struct OpenRISCTLBEntry { uint32_t mr; uint32_t tr; diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index f4c0a3e217..d3796ae41e 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -29,148 +29,78 @@ #endif #ifndef CONFIG_USER_ONLY -static inline int get_phys_nommu(hwaddr *physical, int *prot, - target_ulong address) +static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, + target_ulong address) { - *physical = address; + *phys_addr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; } -static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot, - target_ulong address, int rw, bool supervisor) +static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, + target_ulong addr, int need, bool super) { - int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & TLB_MASK; - int right = 0; - uint32_t mr = cpu->env.tlb.itlb[idx].mr; - uint32_t tr = cpu->env.tlb.itlb[idx].tr; + int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK; + uint32_t imr = cpu->env.tlb.itlb[idx].mr; + uint32_t itr = cpu->env.tlb.itlb[idx].tr; + uint32_t dmr = cpu->env.tlb.dtlb[idx].mr; + uint32_t dtr = cpu->env.tlb.dtlb[idx].tr; + int right, match, valid; - if ((mr >> TARGET_PAGE_BITS) != vpn) { - return TLBRET_NOMATCH; - } - if (!(mr & 1)) { - return TLBRET_INVALID; - } - if (supervisor) { - if (tr & SXE) { - right |= PAGE_EXEC; - } - } else { - if (tr & UXE) { - right |= PAGE_EXEC; + /* If the ITLB and DTLB indexes map to the same page, we want to + load all permissions all at once. If the destination pages do + not match, zap the one we don't need. */ + if (unlikely((itr ^ dtr) & TARGET_PAGE_MASK)) { + if (need & PAGE_EXEC) { + dmr = dtr = 0; + } else { + imr = itr = 0; } } - if ((rw & 2) && ((right & PAGE_EXEC) == 0)) { - return TLBRET_BADADDR; - } - *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); + /* Check if either of the entries matches the source address. */ + match = (imr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_EXEC; + match |= (dmr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_READ | PAGE_WRITE; + + /* Check if either of the entries is valid. */ + valid = imr & 1 ? PAGE_EXEC : 0; + valid |= dmr & 1 ? PAGE_READ | PAGE_WRITE : 0; + valid &= match; + + /* Collect the permissions from the entries. */ + right = itr & (super ? SXE : UXE) ? PAGE_EXEC : 0; + right |= dtr & (super ? SRE : URE) ? PAGE_READ : 0; + right |= dtr & (super ? SWE : UWE) ? PAGE_WRITE : 0; + right &= valid; + + /* Note that above we validated that itr and dtr match on page. + So oring them together changes nothing without having to + check which one we needed. We also want to store to these + variables even on failure, as it avoids compiler warnings. */ + *phys_addr = ((itr | dtr) & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE_MASK); *prot = right; - return TLBRET_MATCH; -} -static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot, - target_ulong address, int rw, bool supervisor) -{ - int vpn = address >> TARGET_PAGE_BITS; - int idx = vpn & TLB_MASK; - int right = 0; - uint32_t mr = cpu->env.tlb.dtlb[idx].mr; - uint32_t tr = cpu->env.tlb.dtlb[idx].tr; + qemu_log_mask(CPU_LOG_MMU, + "MMU lookup: need %d match %d valid %d right %d -> %s\n", + need, match, valid, right, (need & right) ? "OK" : "FAIL"); - if ((mr >> TARGET_PAGE_BITS) != vpn) { - return TLBRET_NOMATCH; + /* Check the collective permissions are present. */ + if (likely(need & right)) { + return 0; /* success! */ } - if (!(mr & 1)) { - return TLBRET_INVALID; - } - if (supervisor) { - if (tr & SRE) { - right |= PAGE_READ; - } - if (tr & SWE) { - right |= PAGE_WRITE; - } + + /* Determine what kind of failure we have. */ + if (need & valid) { + return need & PAGE_EXEC ? EXCP_IPF : EXCP_DPF; } else { - if (tr & URE) { - right |= PAGE_READ; - } - if (tr & UWE) { - right |= PAGE_WRITE; - } + return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS; } - - if (!(rw & 1) && ((right & PAGE_READ) == 0)) { - return TLBRET_BADADDR; - } - if ((rw & 1) && ((right & PAGE_WRITE) == 0)) { - return TLBRET_BADADDR; - } - - *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK); - *prot = right; - return TLBRET_MATCH; -} - -static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical, - int *prot, target_ulong address, int rw) -{ - bool supervisor = (cpu->env.sr & SR_SM) != 0; - int ret; - - /* Assume nommu results for a moment. */ - ret = get_phys_nommu(physical, prot, address); - - /* Overwrite with TLB lookup if enabled. */ - if (rw == MMU_INST_FETCH) { - if (cpu->env.sr & SR_IME) { - ret = get_phys_code(cpu, physical, prot, address, rw, supervisor); - } - } else { - if (cpu->env.sr & SR_DME) { - ret = get_phys_data(cpu, physical, prot, address, rw, supervisor); - } - } - - return ret; } #endif -static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu, - target_ulong address, - int rw, int tlb_error) +static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, + int exception) { CPUState *cs = CPU(cpu); - int exception = 0; - - switch (tlb_error) { - default: - if (rw == 2) { - exception = EXCP_IPF; - } else { - exception = EXCP_DPF; - } - break; -#ifndef CONFIG_USER_ONLY - case TLBRET_BADADDR: - if (rw == 2) { - exception = EXCP_IPF; - } else { - exception = EXCP_DPF; - } - break; - case TLBRET_INVALID: - case TLBRET_NOMATCH: - /* No TLB match for a mapped address */ - if (rw == 2) { - exception = EXCP_ITLBMISS; - } else { - exception = EXCP_DTLBMISS; - } - break; -#endif - } cs->exception_index = exception; cpu->env.eear = address; @@ -182,7 +112,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, { #ifdef CONFIG_USER_ONLY OpenRISCCPU *cpu = OPENRISC_CPU(cs); - cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0); + raise_mmu_exception(cpu, address, EXCP_DPF); return 1; #else g_assert_not_reached(); @@ -193,27 +123,32 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); + int prot, excp, sr = cpu->env.sr; hwaddr phys_addr; - int prot; - int miss; - /* Check memory for any kind of address, since during debug the - gdb can ask for anything, check data tlb for address */ - miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0); + switch (sr & (SR_DME | SR_IME)) { + case SR_DME | SR_IME: + /* The mmu is definitely enabled. */ + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, + PROT_EXEC | PROT_READ | PROT_WRITE, + (sr & SR_SM) != 0); + return excp ? -1 : phys_addr; - /* Check instruction tlb */ - if (miss) { - miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH); - } + default: + /* The mmu is partially enabled, and we don't really have + a "real" access type. Begin by trying the mmu, but if + that fails try again without. */ + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, + PROT_EXEC | PROT_READ | PROT_WRITE, + (sr & SR_SM) != 0); + if (!excp) { + return phys_addr; + } + /* fallthru */ - /* Last, fall back to a plain address */ - if (miss) { - miss = get_phys_nommu(&phys_addr, &prot, addr); - } - - if (miss) { - return -1; - } else { + case 0: + /* The mmu is definitely disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); return phys_addr; } } @@ -222,37 +157,28 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); - int ret, prot = 0; - hwaddr physical = 0; + int prot, excp; + hwaddr phys_addr; if (mmu_idx == MMU_NOMMU_IDX) { - ret = get_phys_nommu(&physical, &prot, addr); + /* The mmu is disabled; lookups never fail. */ + get_phys_nommu(&phys_addr, &prot, addr); + excp = 0; } else { bool super = mmu_idx == MMU_SUPERVISOR_IDX; - if (access_type == MMU_INST_FETCH) { - ret = get_phys_code(cpu, &physical, &prot, addr, 2, super); - } else { - ret = get_phys_data(cpu, &physical, &prot, addr, - access_type == MMU_DATA_STORE, super); - } + int need = (access_type == MMU_INST_FETCH ? PROT_EXEC + : access_type == MMU_DATA_STORE ? PROT_WRITE + : PROT_READ); + excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); } - if (ret == TLBRET_MATCH) { - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - } else if (ret < 0) { - int rw; - if (access_type == MMU_INST_FETCH) { - rw = 2; - } else if (access_type == MMU_DATA_STORE) { - rw = 1; - } else { - rw = 0; - } - cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret); - /* Raise Exception. */ + if (unlikely(excp)) { + raise_mmu_exception(cpu, addr, excp); cpu_loop_exit_restore(cs, retaddr); } + + tlb_set_page(cs, addr & TARGET_PAGE_MASK, + phys_addr & TARGET_PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); } #endif From patchwork Thu Jun 28 03:03:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140400 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1652358ljj; Wed, 27 Jun 2018 20:16:35 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdKWldi1uGUK9f1fDAHMkAZqj+nQBt+V2BsdOoeZncxnWlueFVOzKzNGkgJNnR1rSIY8s04 X-Received: by 2002:a0c:9e99:: with SMTP id r25-v6mr7625325qvd.230.1530155795186; Wed, 27 Jun 2018 20:16:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530155795; cv=none; d=google.com; s=arc-20160816; b=wVOvxNmAG5+nAh3m7UKIOjqndVpKIBGd/AnqmNOEMvI0oi4R0dd0sojMXcFNzjA8lG eysDtVzhfIXBw/DkAySZ/JrV0rQuInGXitud5z4qv7BMDdn+AyvPOPuw31ATgk7qiBlg HfMe4SEGjvUpe7NIi6yuDNmWZGdeqV2UUxMwmFH2blagIlZsrI5CVI+PJXa8RO9esE3N W9AOdI9bUKjCzg0ZwEqJ6mO5aQUU5RAZgSOueo8g0qsx1cAOU94ZXu1tLOuZ7NqRs7mA S1BnzXxjJ6z194UsOZndoqvoi1noyDrsBHN7+0TubyYTHQXPkIJWIwgEoVL2lf8uBLzm ZhaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=yIn6TyEZ6/crkb0RZ7okyByW0TTgtJ88YNc4nTVzFQw=; b=k+vcrA0aOIKanwRRbFZ4Pn8M1Sl+ZjuWrbx9M6t4rXJkx+bztPb3JgKR5HzZ48x/57 wpIdFVPOQP7WcQu4+aP3vID9p0WJYZCOnBOHIWrTvQiijHGGQ/BqbI/2STHcZ+l/JLYE RxGSKY1hB5MxK9ISXV2IjBjQLud6JY87NuKasEXfrLXFrIWFkWRtmSh2wWDUuq7eWL7k wjPH2VO75DbqA+Llt922me4D1PaYqmFgsQfww4D5c8HgQGC5k0VqgsHRvPlWS/El6PBT ymo2DMYeTGbbHkfY8a89GcIvJQvbenqTP5KcbkoPzyKf/lOiDuiAkrOJBHbxlAN2DGIL xIDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=C6dQG8g9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PATCH v3 21/23] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- scripts/qemu-binfmt-conf.sh | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index d7eefda0b8..a5cb96d79a 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -1,10 +1,10 @@ #!/bin/sh -# enable automatic i386/ARM/M68K/MIPS/SPARC/PPC/s390/HPPA/Xtensa/microblaze -# program execution by the kernel +# Enable automatic program execution by the kernel. qemu_target_list="i386 i486 alpha arm armeb sparc32plus ppc ppc64 ppc64le m68k \ mips mipsel mipsn32 mipsn32el mips64 mips64el \ -sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb microblaze microblazeel" +sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \ +microblaze microblazeel or1k" i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00' i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' @@ -124,6 +124,10 @@ microblazeel_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\ microblazeel_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff' microblazeel_family=microblazeel +or1k_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x5c' +or1k_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff' +or1k_family=or1k + qemu_get_family() { cpu=${HOST_ARCH:-$(uname -m)} case "$cpu" in From patchwork Thu Jun 28 03:03:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 140405 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1655389ljj; Wed, 27 Jun 2018 20:21:04 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcu9SkanWukZhcZ0TSAX4ubu3SW/SlP1vCkRYA2y90RyNz8Rlmqi4dkNRhNo6qT/SckXLjt X-Received: by 2002:a37:5041:: with SMTP id e62-v6mr7694316qkb.133.1530156064522; Wed, 27 Jun 2018 20:21:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530156064; cv=none; d=google.com; s=arc-20160816; b=PCf0YmLtvwj/mpWjDvVJD7oZEdQbhiGB2YyfidYuTG3t81JgXRNbTzIr6A+43VPywR dD7rU+ziDLjyAoMUreqrlfwYeyV8AcS4Kl87foaaN4a2cNwnoK68NU4fNR0XMcQ9+1rz /BLP54Kp0g96+9136FEtV9CizY/9QL8x2NN5vFmQ0LwzlWduUI9IXdh8eEuxjKd73b+W 6A5hHC0zvGTGDyFLn+DwXNt+o7a8LfipzxcjyPIradx3y73xrFazhtotuhKZUFSCqSpG N0A0KMLpNhCAaJ/MsA+cHsKPcE+AgvXzAwXBU12YXR8T/aQDQguMtMYG4ifIAz08kl6d PdWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=IqPETO/Jq5PSNTaUXXZrAP2OsLqa2P3bXXogxLvwuEY=; b=KEJHXNzEZ2296M5OvZ6JUFX2FXrIkYv8Qv6uYvlEBx3rezAu6yv7ro9ZVaepPNimJn eE6lH9mydVKAGxijg7dZYEg9v1eic710Ppv3II/m5fMoeNjUpDEb4/ypabg3VVwuj0VU N+3tqlXAiAcBnCjO2y8AUsX0Q3N/pFlNQuC3d7sbv4dKgeH72VEIP2PzekWf1qHDJJsq RBvVbLIzedREbpcQEYMTkdhx4BYEpp0CJBbDtbcTx7m/VdYF+pn/PIPidEU8e73+5aTW Q4CzmrUFBE5grq8SXrnwtq3H56F/udXD0YthGZHkHyVf/QyZyQbbxO3ZYDuddz3lg7Vq qFwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Auo+zJTj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id y15-v6sm8030489pfm.136.2018.06.27.20.04.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Jun 2018 20:04:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Jun 2018 20:03:29 -0700 Message-Id: <20180628030330.15615-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180628030330.15615-1-richard.henderson@linaro.org> References: <20180628030330.15615-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v3 22/23] linux-user: Implement signals for openrisc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" All of the existing code was boilerplate from elsewhere, and would crash the guest upon the first signal. Signed-off-by: Richard Henderson --- v2: Add a comment to the new definition of target_pt_regs. Install the signal mask into the ucontext. v3: Incorporate feedback from Laurent. --- linux-user/openrisc/target_syscall.h | 28 +--- linux-user/openrisc/signal.c | 213 +++++++++++---------------- linux-user/signal.c | 2 +- target/openrisc/cpu.c | 1 + 4 files changed, 92 insertions(+), 152 deletions(-) -- 2.17.1 diff --git a/linux-user/openrisc/target_syscall.h b/linux-user/openrisc/target_syscall.h index 03104f80af..d586d2a018 100644 --- a/linux-user/openrisc/target_syscall.h +++ b/linux-user/openrisc/target_syscall.h @@ -1,27 +1,15 @@ #ifndef OPENRISC_TARGET_SYSCALL_H #define OPENRISC_TARGET_SYSCALL_H +/* Note that in linux/arch/openrisc/include/uapi/asm/ptrace.h, + * this is called user_regs_struct. Given that this is what + * is used within struct sigcontext we need this definition. + * However, elfload.c wants this name. + */ struct target_pt_regs { - union { - struct { - /* Named registers */ - uint32_t sr; /* Stored in place of r0 */ - target_ulong sp; /* r1 */ - }; - struct { - /* Old style */ - target_ulong offset[2]; - target_ulong gprs[30]; - }; - struct { - /* New style */ - target_ulong gpr[32]; - }; - }; - target_ulong pc; - target_ulong orig_gpr11; /* For restarting system calls */ - uint32_t syscallno; /* Syscall number (used by strace) */ - target_ulong dummy; /* Cheap alignment fix */ + abi_ulong gpr[32]; + abi_ulong pc; + abi_ulong sr; }; #define UNAME_MACHINE "openrisc" diff --git a/linux-user/openrisc/signal.c b/linux-user/openrisc/signal.c index 8be0b74001..232ad82b98 100644 --- a/linux-user/openrisc/signal.c +++ b/linux-user/openrisc/signal.c @@ -21,124 +21,69 @@ #include "signal-common.h" #include "linux-user/trace.h" -struct target_sigcontext { +typedef struct target_sigcontext { struct target_pt_regs regs; abi_ulong oldmask; - abi_ulong usp; -}; +} target_sigcontext; -struct target_ucontext { +typedef struct target_ucontext { abi_ulong tuc_flags; abi_ulong tuc_link; target_stack_t tuc_stack; - struct target_sigcontext tuc_mcontext; + target_sigcontext tuc_mcontext; target_sigset_t tuc_sigmask; /* mask last for extensibility */ -}; +} target_ucontext; -struct target_rt_sigframe { - abi_ulong pinfo; - uint64_t puc; +typedef struct target_rt_sigframe { struct target_siginfo info; - struct target_sigcontext sc; - struct target_ucontext uc; - unsigned char retcode[16]; /* trampoline code */ -}; + target_ucontext uc; + uint32_t retcode[4]; /* trampoline code */ +} target_rt_sigframe; -/* This is the asm-generic/ucontext.h version */ -#if 0 -static int restore_sigcontext(CPUOpenRISCState *regs, - struct target_sigcontext *sc) +static void restore_sigcontext(CPUOpenRISCState *env, target_sigcontext *sc) { - unsigned int err = 0; - unsigned long old_usp; + int i; + abi_ulong v; - /* Alwys make any pending restarted system call return -EINTR */ - current_thread_info()->restart_block.fn = do_no_restart_syscall; - - /* restore the regs from &sc->regs (same as sc, since regs is first) - * (sc is already checked for VERIFY_READ since the sigframe was - * checked in sys_sigreturn previously) - */ - - if (copy_from_user(regs, &sc, sizeof(struct target_pt_regs))) { - goto badframe; + for (i = 0; i < 32; ++i) { + __get_user(v, &sc->regs.gpr[i]); + cpu_set_gpr(env, i, v); } + __get_user(env->pc, &sc->regs.pc); - /* make sure the U-flag is set so user-mode cannot fool us */ - - regs->sr &= ~SR_SM; - - /* restore the old USP as it was before we stacked the sc etc. - * (we cannot just pop the sigcontext since we aligned the sp and - * stuff after pushing it) - */ - - __get_user(old_usp, &sc->usp); - phx_signal("old_usp 0x%lx", old_usp); - - __PHX__ REALLY /* ??? */ - wrusp(old_usp); - regs->gpr[1] = old_usp; - - /* TODO: the other ports use regs->orig_XX to disable syscall checks - * after this completes, but we don't use that mechanism. maybe we can - * use it now ? - */ - - return err; - -badframe: - return 1; + /* Make sure the supervisor flag is clear. */ + __get_user(v, &sc->regs.sr); + cpu_set_sr(env, v & ~SR_SM); } -#endif /* Set up a signal frame. */ -static void setup_sigcontext(struct target_sigcontext *sc, - CPUOpenRISCState *regs, - unsigned long mask) +static void setup_sigcontext(target_sigcontext *sc, CPUOpenRISCState *env) { - unsigned long usp = cpu_get_gpr(regs, 1); + int i; - /* copy the regs. they are first in sc so we can use sc directly */ + for (i = 0; i < 32; ++i) { + __put_user(cpu_get_gpr(env, i), &sc->regs.gpr[i]); + } - /*copy_to_user(&sc, regs, sizeof(struct target_pt_regs));*/ - - /* Set the frametype to CRIS_FRAME_NORMAL for the execution of - the signal handler. The frametype will be restored to its previous - value in restore_sigcontext. */ - /*regs->frametype = CRIS_FRAME_NORMAL;*/ - - /* then some other stuff */ - __put_user(mask, &sc->oldmask); - __put_user(usp, &sc->usp); -} - -static inline unsigned long align_sigframe(unsigned long sp) -{ - return sp & ~3UL; + __put_user(env->pc, &sc->regs.pc); + __put_user(cpu_get_sr(env), &sc->regs.sr); } static inline abi_ulong get_sigframe(struct target_sigaction *ka, - CPUOpenRISCState *regs, + CPUOpenRISCState *env, size_t frame_size) { - unsigned long sp = get_sp_from_cpustate(regs); - int onsigstack = on_sig_stack(sp); + target_ulong sp = get_sp_from_cpustate(env); - /* redzone */ - sp = target_sigsp(sp, ka); - - sp = align_sigframe(sp - frame_size); - - /* - * If we are on the alternate signal stack and would overflow it, don't. - * Return an always-bogus address instead so we will die with SIGSEGV. + /* Honor redzone now. If we swap to signal stack, no need to waste + * the 128 bytes by subtracting afterward. */ + sp -= 128; - if (onsigstack && !likely(on_sig_stack(sp))) { - return -1L; - } + sp = target_sigsp(sp, ka); + sp -= frame_size; + sp = QEMU_ALIGN_DOWN(sp, 4); return sp; } @@ -147,11 +92,9 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *set, CPUOpenRISCState *env) { - int err = 0; abi_ulong frame_addr; - unsigned long return_ip; - struct target_rt_sigframe *frame; - abi_ulong info_addr, uc_addr; + target_rt_sigframe *frame; + int i; frame_addr = get_sigframe(ka, env, sizeof(*frame)); trace_user_setup_rt_frame(env, frame_addr); @@ -159,47 +102,37 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, goto give_sigsegv; } - info_addr = frame_addr + offsetof(struct target_rt_sigframe, info); - __put_user(info_addr, &frame->pinfo); - uc_addr = frame_addr + offsetof(struct target_rt_sigframe, uc); - __put_user(uc_addr, &frame->puc); - if (ka->sa_flags & SA_SIGINFO) { tswap_siginfo(&frame->info, info); } - /*err |= __clear_user(&frame->uc, offsetof(ucontext_t, uc_mcontext));*/ __put_user(0, &frame->uc.tuc_flags); __put_user(0, &frame->uc.tuc_link); + target_save_altstack(&frame->uc.tuc_stack, env); - setup_sigcontext(&frame->sc, env, set->sig[0]); - - /*err |= copy_to_user(frame->uc.tuc_sigmask, set, sizeof(*set));*/ - - /* trampoline - the desired return ip is the retcode itself */ - return_ip = (unsigned long)&frame->retcode; - /* This is l.ori r11,r0,__NR_sigreturn, l.sys 1 */ - __put_user(0xa960, (short *)(frame->retcode + 0)); - __put_user(TARGET_NR_rt_sigreturn, (short *)(frame->retcode + 2)); - __put_user(0x20000001, (unsigned long *)(frame->retcode + 4)); - __put_user(0x15000000, (unsigned long *)(frame->retcode + 8)); - - if (err) { - goto give_sigsegv; + setup_sigcontext(&frame->uc.tuc_mcontext, env); + for (i = 0; i < TARGET_NSIG_WORDS; ++i) { + __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); } - /* TODO what is the current->exec_domain stuff and invmap ? */ + /* This is l.ori r11,r0,__NR_sigreturn; l.sys 1; l.nop; l.nop */ + __put_user(0xa9600000 | TARGET_NR_rt_sigreturn, frame->retcode + 0); + __put_user(0x20000001, frame->retcode + 1); + __put_user(0x15000000, frame->retcode + 2); + __put_user(0x15000000, frame->retcode + 3); /* Set up registers for signal handler */ - env->pc = (unsigned long)ka->_sa_handler; /* what we enter NOW */ - cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LATER */ - cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */ - cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_t*) */ - cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext */ - - /* actually move the usp to reflect the stacked frame */ - cpu_set_gpr(env, 1, (unsigned long)frame); + cpu_set_gpr(env, 9, frame_addr + offsetof(target_rt_sigframe, retcode)); + cpu_set_gpr(env, 3, sig); + cpu_set_gpr(env, 4, frame_addr + offsetof(target_rt_sigframe, info)); + cpu_set_gpr(env, 5, frame_addr + offsetof(target_rt_sigframe, uc)); + cpu_set_gpr(env, 1, frame_addr); + /* For debugging convenience, set ppc to the insn that faulted. */ + env->ppc = env->pc; + /* When setting the PC for the signal handler, exit delay slot. */ + env->pc = ka->_sa_handler; + env->dflag = 0; return; give_sigsegv: @@ -207,16 +140,34 @@ give_sigsegv: force_sigsegv(sig); } -long do_sigreturn(CPUOpenRISCState *env) -{ - trace_user_do_sigreturn(env, 0); - fprintf(stderr, "do_sigreturn: not implemented\n"); - return -TARGET_ENOSYS; -} - long do_rt_sigreturn(CPUOpenRISCState *env) { + abi_ulong frame_addr = get_sp_from_cpustate(env); + target_rt_sigframe *frame; + sigset_t set; + trace_user_do_rt_sigreturn(env, 0); - fprintf(stderr, "do_rt_sigreturn: not implemented\n"); - return -TARGET_ENOSYS; + if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { + goto badframe; + } + if (frame_addr & 3) { + goto badframe; + } + + target_to_host_sigset(&set, &frame->uc.tuc_sigmask); + set_sigmask(&set); + + restore_sigcontext(env, &frame->uc.tuc_mcontext); + if (do_sigaltstack(frame_addr + offsetof(target_rt_sigframe, uc.tuc_stack), + 0, frame_addr) == -EFAULT) { + goto badframe; + } + + unlock_user_struct(frame, frame_addr, 0); + return cpu_get_gpr(env, 11); + + badframe: + unlock_user_struct(frame, frame_addr, 0); + force_sig(TARGET_SIGSEGV); + return 0; } diff --git a/linux-user/signal.c b/linux-user/signal.c index be2815b45d..602b631b92 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -236,7 +236,7 @@ int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset) return 0; } -#if !defined(TARGET_OPENRISC) && !defined(TARGET_NIOS2) +#if !defined(TARGET_NIOS2) /* Just set the guest's signal mask to the specified value; the * caller is assumed to have called block_signals() already. */ diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e01ce9ed1c..fb7cb5c507 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -27,6 +27,7 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) OpenRISCCPU *cpu = OPENRISC_CPU(cs); cpu->env.pc = value; + cpu->env.dflag = 0; } static bool openrisc_cpu_has_work(CPUState *cs) From patchwork Thu Jun 28 03:03:30 2018 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:400e:c01::234 Subject: [Qemu-devel] [PATCH v3 23/23] linux-user: Fix struct sigaltstack for openrisc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/openrisc/target_signal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/linux-user/openrisc/target_signal.h b/linux-user/openrisc/target_signal.h index c352a8b333..8283eaf544 100644 --- a/linux-user/openrisc/target_signal.h +++ b/linux-user/openrisc/target_signal.h @@ -5,8 +5,8 @@ typedef struct target_sigaltstack { abi_long ss_sp; + abi_int ss_flags; abi_ulong ss_size; - abi_long ss_flags; } target_stack_t; /* sigaltstack controls */