From patchwork Mon May 17 17:03:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 440494 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B39DC433B4 for ; Mon, 17 May 2021 17:19:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 31DA96128A for ; Mon, 17 May 2021 17:19:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236223AbhEQRVC (ORCPT ); Mon, 17 May 2021 13:21:02 -0400 Received: from azhdrrw-ex01.nvidia.com ([20.51.104.162]:1237 "EHLO AZHDRRW-EX01.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232996AbhEQRVC (ORCPT ); Mon, 17 May 2021 13:21:02 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.106) by mxs.oss.nvidia.com (10.13.234.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.12; Mon, 17 May 2021 10:04:44 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fgELBEgmpKD2m5N+7e/1DDJO78oFrwmgDbwxsyvWLiGNX9utlXaL5gsuAE/3dTWIdTtfaqnctYBPDqsOJLM7zg8qsH/P029siAYjpnKmJVddJUElZphOeAxasYDKFVqMiYRgDBS8g+5O89QINB6VjQPACEDNgLUKq5U89q9EEi777K5pFmNsXPQUspeaGx63eHwcJpv2CoiZPSrf721Cj/R0uAtTNgBg/gwKRfqtSimr7320UJlzW3b4ErnY4eOv8QbiKbBsjy57O6TItjSowVNFjmutdmDgVstig2KpKuN1OgS04hhfgNoCjznkcWUdBrT4OiSUHRHigo1eyCY3sA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DV5Z23eiSUiZ7DrvpHwEa9UTUWhqDnMqkNqBnwvTOc0=; b=DXVo+BM3CI4WFPa7JTHoB5qnhOWId6l2fFBYVGG5jc+qPFDvZ/z7L3/S6tMwTu9vHfbob//WT+Z0ZqWMJAT3Ci2/YYOR7TtXsDsmZWP3E6DGufcJvYhYB6H3HmC1vsrICks4Q/NjMrAM4nho5LRXJwsVJVGjA0xMmr7zAnDSqOnOSwDSIZNqaTZgocxq+FAnD//ub/2m8VP6QiKF6TXlTe2iEl5Q160fG8BXIbFVAqynzt/UMM74wzPtz1G7gPXJUEX/vjmkoJ01Kxt5rKjASj7AZimAQVzsd8Mko+3byWrsFkGpcUpuv78IKlIg5/W6TxVQXA3E8DclUGzG7vfC4A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DV5Z23eiSUiZ7DrvpHwEa9UTUWhqDnMqkNqBnwvTOc0=; b=VfC+kG0EuprpnLVL1685Nn1wCggmYjcFrkjnpK65SRBvTvb9ojFh2tKYmu084sO8qCuT7dTXFblnb0gHS7hHg6GpwMP4y/VJNifCCpJyHi0ghZXvAGNCOO9QY+iDQvec5iF15AjKNpvhHe6hh0VWdki9wAh8zqwYFkb3rBUnEhNCUX6LqK5mkCPiKAYaPfo9Ec3LP9OgqMNHdjz7+nkqLKc4dd3sJq9Luf0CEUW1mSzaPfietYAd+HeRGf71GarPTO3hWCob6B/M2YUl30Lg3XL3en9v6cU6mtoIiWvbZLv0Bvy6Eo2qRh1Ljs+3dUFJQfYZvXr9tanfoQsfIJHj3w== Received: from DM5PR18CA0053.namprd18.prod.outlook.com (2603:10b6:3:22::15) by SA0PR12MB4399.namprd12.prod.outlook.com (2603:10b6:806:98::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.28; Mon, 17 May 2021 17:04:43 +0000 Received: from DM6NAM11FT022.eop-nam11.prod.protection.outlook.com (2603:10b6:3:22:cafe::c7) by DM5PR18CA0053.outlook.office365.com (2603:10b6:3:22::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.24 via Frontend Transport; Mon, 17 May 2021 17:04:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Mon, 17 May 2021 17:04:43 +0000 Received: from shredder.mellanox.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 May 2021 17:04:37 +0000 From: Ido Schimmel To: CC: , , , , , , , Ido Schimmel Subject: [PATCH net-next 02/11] selftests: mlxsw: Make sampling test more robust Date: Mon, 17 May 2021 20:03:52 +0300 Message-ID: <20210517170401.188563-3-idosch@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517170401.188563-1-idosch@nvidia.com> References: <20210517170401.188563-1-idosch@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: af6f6ce3-364d-44cf-a2fc-08d91955ddba X-MS-TrafficTypeDiagnostic: SA0PR12MB4399: X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m8o/CYqaZ2MBUirxQN4oTCCIKV9GzbTBUcZ4cU+LOaenvtc4sWaLZand0BzkyrVfAfkXSJIDJiFaqCT1aWnY08dpGOCPsGr4lQ7HmDC1mjbj1rZRD1t6UIVLJfFYNYQ7Clv+JMUu9I94SW8MaffM2T3ZFGiUnqbc+0QRc+Rm9k9Tsn/5Ku8d9dLMeocTTv25+ALMggGIktc7wEhI6G0cQlMKM2TTKoIyESSl50JHK07L/L2xatLeHoWvb8dyrHmRnfBcDNTqLsH8NY9QgSnR2qTN2eE8YKzu29S8Kcu7SFm9g2RILX/CZj990qjx7d2utKDq+4VWMCRMuJgUcQtYbOyNaBihVkmgGZnse2zOZqXBCDgMbLt8g730c+k4TE3YhkTPZunEu8rLzofUmoSyuZ16uOPWaesFiE/wf/oqmyi2Vmj3I4SCLwP5xOuaC1WLd5WdfFvLRRoi32hiyZyvdMB0q6r6lhgozzFG2WFYNCFuq0nvJx01XwFX6e2NJPSC8Z995xlpwyB+2ZT8yhzu1LlMhVvgyZRYYGeQnKnn4BGuGVKO4ZwCDw3BZ7Ze1/gh+TiRqWhFfA0xblM/bmr04bxy9R1lEANjNdnkSxtWuMrq8pYhTqoKeREypkf1jR2B9uZcaMNQMo4G2jMiyA5yPA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(376002)(396003)(346002)(39860400002)(36840700001)(46966006)(426003)(54906003)(316002)(186003)(47076005)(16526019)(36906005)(336012)(5660300002)(6916009)(8676002)(2906002)(86362001)(8936002)(4326008)(2616005)(82310400003)(82740400003)(36860700001)(7636003)(356005)(36756003)(1076003)(83380400001)(107886003)(478600001)(26005)(70586007)(70206006)(6666004); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2021 17:04:43.0787 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af6f6ce3-364d-44cf-a2fc-08d91955ddba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4399 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The test sometimes fails with an error message such as: TEST: tc sample (w/ flower) rate (egress) [FAIL] Expected 100 packets, got 70 packets, which is -30% off. Required accuracy is +-25% Make the test more robust by generating more packets, therefore increasing the number of expected samples. Decrease the transmission delay in order not to needlessly prolong the test. Signed-off-by: Ido Schimmel --- .../testing/selftests/drivers/net/mlxsw/tc_sample.sh | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tools/testing/selftests/drivers/net/mlxsw/tc_sample.sh b/tools/testing/selftests/drivers/net/mlxsw/tc_sample.sh index 093bed088ad0..373d5f2a846e 100755 --- a/tools/testing/selftests/drivers/net/mlxsw/tc_sample.sh +++ b/tools/testing/selftests/drivers/net/mlxsw/tc_sample.sh @@ -234,15 +234,15 @@ __tc_sample_rate_test() psample_capture_start - ip vrf exec v$h1 $MZ $h1 -c 3200 -d 1msec -p 64 -A 192.0.2.1 \ + ip vrf exec v$h1 $MZ $h1 -c 320000 -d 100usec -p 64 -A 192.0.2.1 \ -B $dip -t udp dp=52768,sp=42768 -q psample_capture_stop pkts=$(grep -e "group 1 " $CAPTURE_FILE | wc -l) - pct=$((100 * (pkts - 100) / 100)) + pct=$((100 * (pkts - 10000) / 10000)) (( -25 <= pct && pct <= 25)) - check_err $? "Expected 100 packets, got $pkts packets, which is $pct% off. Required accuracy is +-25%" + check_err $? "Expected 10000 packets, got $pkts packets, which is $pct% off. Required accuracy is +-25%" log_test "tc sample rate ($desc)" @@ -587,15 +587,15 @@ __tc_sample_acl_rate_test() psample_capture_start - ip vrf exec v$h1 $MZ $h1 -c 3200 -d 1msec -p 64 -A 192.0.2.1 \ + ip vrf exec v$h1 $MZ $h1 -c 320000 -d 100usec -p 64 -A 192.0.2.1 \ -B 198.51.100.1 -t udp dp=52768,sp=42768 -q psample_capture_stop pkts=$(grep -e "group 1 " $CAPTURE_FILE | wc -l) - pct=$((100 * (pkts - 100) / 100)) + pct=$((100 * (pkts - 10000) / 10000)) (( -25 <= pct && pct <= 25)) - check_err $? "Expected 100 packets, got $pkts packets, which is $pct% off. Required accuracy is +-25%" + check_err $? "Expected 10000 packets, got $pkts packets, which is $pct% off. Required accuracy is +-25%" # Setup a filter that should not match any packet and make sure packets # are not sampled. From patchwork Mon May 17 17:03:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 440493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99673C433B4 for ; Mon, 17 May 2021 17:19:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F38B61285 for ; Mon, 17 May 2021 17:19:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236778AbhEQRVI (ORCPT ); Mon, 17 May 2021 13:21:08 -0400 Received: from azhdrrw-ex02.nvidia.com ([20.64.145.131]:52737 "EHLO AZHDRRW-EX02.NVIDIA.COM" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241395AbhEQRVH (ORCPT ); Mon, 17 May 2021 13:21:07 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.103) by mxs.oss.nvidia.com (10.13.234.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.12; Mon, 17 May 2021 10:04:49 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dGH177IC6tqpt589olUnwiWnp1BgGX5owiXWhSngZO2dnj89amPLzNCot7nk4ZUod5DQUpQ3L22vYWu/Ds90D3z2iJZtRo68qXjPhVEfnaAWZh2HI70RavH8QWofQNtxq+yQeuSpi+V6ob2DoC9vOVrlE0VwthWlHecXpGASqZWw5SsGFVe/fkD5VPNNTVXWphX3AOVaDtGzk9ZxF+xYe0Vm47Qht1r+EQ9PESbbVviMikhTEf36bqWPv/TWph6IbNA2Q1lUDemX7x4+IPcTGsJlGZrU1SGUYs8nNRZoeT5QTvhmwxHkU4/dAiqjtYQupvBvwOon3BVngtyA8CcXPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qDGNriyHlbvoY+s6F8k7xpNn394sRn/qQNtVexJZs3k=; b=clp0iL6p45gghoYNRD1Q30HMZHAE0D0XpISFzcmvBU/rQNU+8NU2rqRl6jQvrSjIQqsNFcMOthJMVxNrktdRmUsibghL+1pF4Lb4TETS1reOsgD+c9R9dYzUqS7CfSjaGO77g9s3ADUx3nROPYt6GMDRGiO3BqX/OAtITIf+eVb0lfs669isDl/0OiWDs8oV8JFgD8toBtwJKFVKyZ8aDWZK4JhAyq53n+z1i1CKq5ReQVfka+SWfjTEaK9bvrg6d8qdh7S4y18Ad348pTnCxGT6vcpqiLVsPMyBycB0jI5ZAH9rnLPtXZzrKKFbeMJXs1xnnLuLwaplciqFgm4rYA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qDGNriyHlbvoY+s6F8k7xpNn394sRn/qQNtVexJZs3k=; b=lLPSp/j/R/gRkGNNcRy1EmPbNP28VWKz9VjRF53oD49+B2jwdj3ZYqbcDLAa1/iFh1Yc8oU+sfrMsMzJJkzWHzUQQdB2Ch/SUx+ogw7Uf7VtUz/0GRR+K4NUfk1+XydceBKd0lXtbCGwHzdwTEJwRp6Km2Gre51UaXBg/e6j/9xE4VBoweiBwSU2DNdCESL5fJsI1tNxTZt4YLxJlng7yLGZPWx+8aZuZjItn0SE6JDgZQJkBaOYnnjABxiusf5Iu4sbqO1zWFPzmY7Uv1WHHi8VdeVIo6pmSa83+DRFmsNKsmQ9JRVSq0kwodyE4bmA+vxHldPwdphmr+zd3c25Wg== Received: from DM3PR12CA0114.namprd12.prod.outlook.com (2603:10b6:0:55::34) by BY5PR12MB5558.namprd12.prod.outlook.com (2603:10b6:a03:1d5::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.25; Mon, 17 May 2021 17:04:48 +0000 Received: from DM6NAM11FT027.eop-nam11.prod.protection.outlook.com (2603:10b6:0:55:cafe::38) by DM3PR12CA0114.outlook.office365.com (2603:10b6:0:55::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 17 May 2021 17:04:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT027.mail.protection.outlook.com (10.13.172.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Mon, 17 May 2021 17:04:48 +0000 Received: from shredder.mellanox.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 May 2021 17:04:44 +0000 From: Ido Schimmel To: CC: , , , , , , , Ido Schimmel Subject: [PATCH net-next 04/11] selftests: mlxsw: qos_pfc: Convert to iproute2 dcb Date: Mon, 17 May 2021 20:03:54 +0300 Message-ID: <20210517170401.188563-5-idosch@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517170401.188563-1-idosch@nvidia.com> References: <20210517170401.188563-1-idosch@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f0cfeaee-14cc-473c-3e51-08d91955e0b9 X-MS-TrafficTypeDiagnostic: BY5PR12MB5558: X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qute6oY81ZLDtZTdcft3oHKiAM0XpmAtTPtPjGFJYzJ3h1WSCH3syaFYhbuf7PBrd7TPrEGrEtn8xKQj0AK1XMlgUktRfv/XMh4cmqJi8y+B0lm0lAKAS/CmbkBnOSrkwbZQPPR6wHCpL/Blilpo6MjdAbrYso8Fi0dg4Wzm7QotFv6i/Jw8v+vKZYDQiMX7xdIJKOzBhkxqnAlC8HEwrsbeNZvO5Wv354Cdn0xXwWhV+QESEJR/7sfL8UtX7x+/zNX6QsXz9OBlHxffqSOQqYFdVLMzhh9LQuKSQGrII0y8tzNZloQDWWSAEb53MgMnXYi0kxM//t2cKO+mcxD1H3XGnbgKTnJdwRqAoZOxbPmRwuUqbvxOeao96+4TWblyBhRGQv8lizqcAnS/Pg4dr+8HX9Muwo8Tq3qL+1Lb0wi9gWxU6wa0ZVNv1Mliify2TFlHlyBMCywJHwGlrsNo1ubnCp1via//Ohe6YKvDdBRluciM6uDXbMAx025PUt1jEMXAnwGcVtr9gP5XMzKkFsjGgDY+bBTdmVyDOFC37/phjvOb3dF/YFKBCiPZbKBM/HKDq+l2/aC0XZ4Z5Y3oDOdhxhN68CNzbyQrYGSwp5EeyHNUpX1QryS8XHYsTU5I+Pedvlpu/Xop+vTJcvS2TA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(376002)(346002)(39860400002)(396003)(36840700001)(46966006)(316002)(36906005)(8676002)(8936002)(426003)(2616005)(107886003)(54906003)(16526019)(186003)(2906002)(36756003)(26005)(5660300002)(478600001)(356005)(336012)(82740400003)(1076003)(86362001)(47076005)(36860700001)(82310400003)(6916009)(7636003)(70206006)(4326008)(83380400001)(70586007)(6666004); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2021 17:04:48.1617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0cfeaee-14cc-473c-3e51-08d91955e0b9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB5558 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Petr Machata There is a dedicated tool for configuration of DCB in iproute2 now. Use it in the selftest instead of mlnx_qos. Signed-off-by: Petr Machata Signed-off-by: Ido Schimmel --- .../selftests/drivers/net/mlxsw/qos_pfc.sh | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tools/testing/selftests/drivers/net/mlxsw/qos_pfc.sh b/tools/testing/selftests/drivers/net/mlxsw/qos_pfc.sh index 5c7700212f75..5d5622fc2758 100755 --- a/tools/testing/selftests/drivers/net/mlxsw/qos_pfc.sh +++ b/tools/testing/selftests/drivers/net/mlxsw/qos_pfc.sh @@ -171,7 +171,7 @@ switch_create() # assignment. tc qdisc replace dev $swp1 root handle 1: \ ets bands 8 strict 8 priomap 7 6 - __mlnx_qos -i $swp1 --prio2buffer=0,1,0,0,0,0,0,0 >/dev/null + dcb buffer set dev $swp1 prio-buffer all:0 1:1 # $swp2 # ----- @@ -209,8 +209,8 @@ switch_create() # the lossless prio into a buffer of its own. Don't bother with buffer # sizes though, there is not going to be any pressure in the "backward" # direction. - __mlnx_qos -i $swp3 --prio2buffer=0,1,0,0,0,0,0,0 >/dev/null - __mlnx_qos -i $swp3 --pfc=0,1,0,0,0,0,0,0 >/dev/null + dcb buffer set dev $swp3 prio-buffer all:0 1:1 + dcb pfc set dev $swp3 prio-pfc all:off 1:on # $swp4 # ----- @@ -226,11 +226,11 @@ switch_create() # Configure qdisc so that we can hand-tune headroom. tc qdisc replace dev $swp4 root handle 1: \ ets bands 8 strict 8 priomap 7 6 - __mlnx_qos -i $swp4 --prio2buffer=0,1,0,0,0,0,0,0 >/dev/null - __mlnx_qos -i $swp4 --pfc=0,1,0,0,0,0,0,0 >/dev/null + dcb buffer set dev $swp4 prio-buffer all:0 1:1 + dcb pfc set dev $swp4 prio-pfc all:off 1:on # PG0 will get autoconfigured to Xoff, give PG1 arbitrarily 100K, which # is (-2*MTU) about 80K of delay provision. - __mlnx_qos -i $swp4 --buffer_size=0,$_100KB,0,0,0,0,0,0 >/dev/null + dcb buffer set dev $swp4 buffer-size all:0 1:$_100KB # bridges # ------- @@ -273,9 +273,9 @@ switch_destroy() # $swp4 # ----- - __mlnx_qos -i $swp4 --buffer_size=0,0,0,0,0,0,0,0 >/dev/null - __mlnx_qos -i $swp4 --pfc=0,0,0,0,0,0,0,0 >/dev/null - __mlnx_qos -i $swp4 --prio2buffer=0,0,0,0,0,0,0,0 >/dev/null + dcb buffer set dev $swp4 buffer-size all:0 + dcb pfc set dev $swp4 prio-pfc all:off + dcb buffer set dev $swp4 prio-buffer all:0 tc qdisc del dev $swp4 root devlink_tc_bind_pool_th_restore $swp4 1 ingress @@ -288,8 +288,8 @@ switch_destroy() # $swp3 # ----- - __mlnx_qos -i $swp3 --pfc=0,0,0,0,0,0,0,0 >/dev/null - __mlnx_qos -i $swp3 --prio2buffer=0,0,0,0,0,0,0,0 >/dev/null + dcb pfc set dev $swp3 prio-pfc all:off + dcb buffer set dev $swp3 prio-buffer all:0 tc qdisc del dev $swp3 root devlink_tc_bind_pool_th_restore $swp3 1 egress @@ -315,7 +315,7 @@ switch_destroy() # $swp1 # ----- - __mlnx_qos -i $swp1 --prio2buffer=0,0,0,0,0,0,0,0 >/dev/null + dcb buffer set dev $swp1 prio-buffer all:0 tc qdisc del dev $swp1 root devlink_tc_bind_pool_th_restore $swp1 1 ingress From patchwork Mon May 17 17:03:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 440492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B270C433B4 for ; Mon, 17 May 2021 17:20:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 286FC6128E for ; Mon, 17 May 2021 17:20:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242162AbhEQRVQ (ORCPT ); Mon, 17 May 2021 13:21:16 -0400 Received: from azhdrrw-ex01.nvidia.com ([20.51.104.162]:1244 "EHLO AZHDRRW-EX01.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231681AbhEQRVN (ORCPT ); Mon, 17 May 2021 13:21:13 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.170) by mxs.oss.nvidia.com (10.13.234.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.12; Mon, 17 May 2021 10:04:56 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=B8CCqAtzqNqGzEhyGH7DdNytkqLbsLwx9hJnmTOzPErInevVRpZM9veTuytgzXobgHDNomoR5SiUBoWrjUnaU5algIZaWH1kOi9TSsCJWF1ajaTe9qY02WMJhUF66SeqWmYdDnkAyo+aMEYDyfdrFiUtYcJWwzvN6h8+WHy3EuxizRsP0K+Qg7li23k2uoRRS+bouVRwHYlLLczcJIbaH4HqRGxN+FVW2LXKvQ55ILkcklt7TEVen2XZkfwPb32aNgITjHXYfl9VVWM4/QejFQUkJ796w7Llsy23QPOspjrwwd2HMdai16kQEelEU+PI7RFCHddVxfDmoBFsiQ1+iA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V6m1TZjTw7yY9wwsHwC98JGaYwljm/eIwSwWuNWJz9Y=; b=KJsrbpcz2zgZFtI7XJNcvTxXKHmCfTsuncRrtcEhqCg8D9PFYeugVZnaIQGPqUwTdvbF5CpVHIwB1i0UF5nU5nPyt+oMrCLkO2EjLRcrWYhj5+qTliLVnx4bAYUN4fBjrqQj7lDKBBdF9HDTVObVAaoLyW6MctpnF+S2QunhAZgzC1QZPIyTbPrO6bAGN32pJbotd5mt7UlzXxbFPIFBr4MUMqXIZlRD0MAZyWz82oJWFIECZdhVvGSOr0sLz5K/9lqyzCG0Nx/lBT79I2597OUVQ4v/Cjqr7Aqh5AC6sYpZrGwnhoI3G1NYXUt6Z+Zlqdc0uGNBpOIJ6n1aW3B4RA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V6m1TZjTw7yY9wwsHwC98JGaYwljm/eIwSwWuNWJz9Y=; b=rlUrC0Gd88bfUUEOLW3wTkGekMZDnRgRPRIAJL+mMT0M54tVOMLIB697WzRWo1co6nrgnSgSHL8rKlc0gPytcQdo/2f/f4GpkbfSrzSfup2U0TdSR1nPsbfRBCpJSeTMpnaBqLFRctW8iuMfdqOh9cx5zuQl5XFh+7BwlgKLyQdqi3hTJttZCzdZxb1UXT1yWbeJmXXc9FZR3sBC1/tQuzuhK9hUvLJykkB++P04ttwPPCA4EDXEluip3hwkSvTSzIDoYfQqhm9adRXfChOGo2Mpch0QjV7xJLC6H1clnW7SuE42FCTOiQAO9Qm1zj3NDsxBI97UHi7FxBnUgfrKrw== Received: from DM5PR21CA0044.namprd21.prod.outlook.com (2603:10b6:3:ed::30) by DM6PR12MB4123.namprd12.prod.outlook.com (2603:10b6:5:21f::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.26; Mon, 17 May 2021 17:04:55 +0000 Received: from DM6NAM11FT040.eop-nam11.prod.protection.outlook.com (2603:10b6:3:ed:cafe::a5) by DM5PR21CA0044.outlook.office365.com (2603:10b6:3:ed::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.4 via Frontend Transport; Mon, 17 May 2021 17:04:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT040.mail.protection.outlook.com (10.13.173.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Mon, 17 May 2021 17:04:55 +0000 Received: from shredder.mellanox.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 May 2021 17:04:51 +0000 From: Ido Schimmel To: CC: , , , , , , , Ido Schimmel Subject: [PATCH net-next 06/11] mlxsw: spectrum_buffers: Switch function arguments Date: Mon, 17 May 2021 20:03:56 +0300 Message-ID: <20210517170401.188563-7-idosch@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517170401.188563-1-idosch@nvidia.com> References: <20210517170401.188563-1-idosch@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c7a31e4d-5290-4e8a-dd54-08d91955e4e4 X-MS-TrafficTypeDiagnostic: DM6PR12MB4123: X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:3383; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: t/Mgpp2Hh151dtgvT2bUwfzF8EqPastNgOuYGlPGVJXBOQCZ3Y4byEOGDEriPZ0pzVs0KxeNDFo9RoCJv05oSUM6RX1DXqjUnmpABtE4b+WdjumknqUV28PgDDP9qWRRmkl+yZ+Qy7f1YSzj20TR4d8xCNhCbE5ZVd8+yOQB7kSwpuhU6+a524zy8eYDc5PqXhwIjs4Y1sfe2wEhSXThQSwaYyMZjTOcwIIxqkOisJCNaArNg7mHzCD1aDHCUVYxzfq+0ezKotuSBeNyOyBvcvZco5SWe/R0GdhHT1FX+kBwDlgACLI1OcpdElZRCdvnHXdoTkJHXDXtg7WKGawtPz7ZBNuIqmCe1d7PVKzb8YBiOFHR29tnHDyJn3XFPdAEQHForgM8QeKQp5LKBtKyTyi+Ec2RlXoEpq01zRkBtNzJU+FCrtyXdUvfGSNl+h+Sc0Hr54dhWKKL8dY3aXA+NGxx/eAdJ9d8GkHJwmKQb7Q05FwZGHpY4Y0gzSuhnvkO66mrHh0BJwQZSPoIcTJq0QCO9vMd/8XPlNmIMdzQb+uGl94Fw7chJUYfTFD6SXdQQkRXLiCUxFzcPRhWLvecibVhVmoP3sKNWuruJcCZUwS/nDuJCqKuk+q3rYNq4Zkl4I2IS1tWiyiupNSIShrJKrKMquY/Si0uu21mVx9uNSI= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(82310400003)(54906003)(336012)(498600001)(107886003)(8676002)(47076005)(426003)(83380400001)(16526019)(6916009)(36756003)(26005)(70586007)(70206006)(1076003)(36860700001)(36906005)(4326008)(356005)(86362001)(186003)(5660300002)(8936002)(2616005)(2906002)(7636003); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2021 17:04:55.1715 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c7a31e4d-5290-4e8a-dd54-08d91955e4e4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4123 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Danielle Ratson In the call path: mlxsw_sp_hdroom_bufs_reset_sizes() mlxsw_sp_hdroom_int_buf_size_get() ->int_buf_size_get() The 'speed' and 'mtu' arguments were mistakenly switched twice. The two bugs thus canceled each other. Clean this up by switching the arguments in both call sites, so that they are passed in the right order. Found during manual code inspection. Signed-off-by: Danielle Ratson Reviewed-by: Petr Machata Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c index 37ff29a1686e..9de160e740b2 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c @@ -364,7 +364,7 @@ static u16 mlxsw_sp_hdroom_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, static u32 mlxsw_sp_hdroom_int_buf_size_get(struct mlxsw_sp *mlxsw_sp, int mtu, u32 speed) { - u32 buffsize = mlxsw_sp->sb_ops->int_buf_size_get(speed, mtu); + u32 buffsize = mlxsw_sp->sb_ops->int_buf_size_get(mtu, speed); return mlxsw_sp_bytes_cells(mlxsw_sp, buffsize) + 1; } @@ -388,8 +388,8 @@ void mlxsw_sp_hdroom_bufs_reset_sizes(struct mlxsw_sp_port *mlxsw_sp_port, int i; /* Internal buffer. */ - reserve_cells = mlxsw_sp_hdroom_int_buf_size_get(mlxsw_sp, mlxsw_sp_port->max_speed, - mlxsw_sp_port->max_mtu); + reserve_cells = mlxsw_sp_hdroom_int_buf_size_get(mlxsw_sp, mlxsw_sp_port->max_mtu, + mlxsw_sp_port->max_speed); reserve_cells = mlxsw_sp_port_headroom_8x_adjust(mlxsw_sp_port, reserve_cells); hdroom->int_buf.reserve_cells = reserve_cells; From patchwork Mon May 17 17:03:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 440491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AA54C433B4 for ; Mon, 17 May 2021 17:20:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F6D960FD8 for ; Mon, 17 May 2021 17:20:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242674AbhEQRV1 (ORCPT ); Mon, 17 May 2021 13:21:27 -0400 Received: from azhdrrw-ex02.nvidia.com ([20.64.145.131]:52742 "EHLO AZHDRRW-EX02.NVIDIA.COM" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242634AbhEQRVX (ORCPT ); Mon, 17 May 2021 13:21:23 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.175) by mxs.oss.nvidia.com (10.13.234.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.12; Mon, 17 May 2021 10:05:03 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mzwoULW9jqXIfqPGY27AMpv5swYXOrTvBAqwUvJOEXc26LeQYV1EAnJtFSoGfEaXlWZm5lZtxj7JdtZgp8Ro3W0wTlQJUz5/m2xLtysUtekKNt9CWjWJmYXXyfC2vGfXfWIQI7SlxRI91FlOP6FNWxfji8vArvC+pIBXRkAnf4GHmzf+kc+qHhEhhY5JI0kmgy8wxP9y7QvkywqA1xKTBAxr2cWZYsypBROz2E4HfUIGEJIdImE7XmzTC7iqWE7c6R56Ye3Ph5hzmuNEyJSlAwOHqWhp2VIY98piGC0fblHCr4duxbdT4qAQ9dspwUPmr1kSz/z0mwbmPp6Senykqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zpHqQnLqnSf7SeLQuq6OeYgUZ2oRydJgLm+BED2FZGE=; b=Ljy3THXJKScakBJlbutvUcR+BpHev9Srn7Y5QI0IJm0Me6UyCa7by95DueiIoDRNyeAjzpAgiHweQi3rimkS6E1+c4NNVLJfV8TFUeagLGEK8UqlKUw92szj6X1qbUFnm9zlye7lvYZky+Q3IchiQbSozrTXXKJMzPRx5Obcl0fD3PBrWzigyiBUFr95QilVyQ11tS+nlpgjq2nlZRS+5dZilRTSPt9D/jMqsynH2AAnGQvw/IFRWGIKtheL514xRoXVOjD93TQVafSL3u4pDR2V62sxTQaJOfPVVA2cCAgYG+TcSsHCPyAl7m5q+7Dn9rUF6tHz0ttB1NR0KH9pMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zpHqQnLqnSf7SeLQuq6OeYgUZ2oRydJgLm+BED2FZGE=; b=JhAJnDrwYkToG49U80MD67ECtd4MKxmuivr9fyYD5vMI5EqBcyvZXFCskDH12f52vz0as4nDUbJyDX9oVgAKQP32S36ZYoAs3n2KfEXAXF9aCj9VH/TbekSxk3MoZjZ5/6qJlgfKEYgvGcrod5EMfSD7ubYQpRyujHIFyGhHiGoCpCZrhVWPoSFGTbxBy58ikaRzrnsLCNqGgPYnKpXCGzImCyRN30h3v/jdPJl/vlTlJm8gbIvIb2b/8/Uy8hp18spOM+LP0i4kpQZWP0H0khWH+4rhC2N3jo3JJqFBRYJPMyeuLia/Bh6ySJWteNwf5TLvvEOHcQW3JG30/AqQHw== Received: from DM5PR07CA0141.namprd07.prod.outlook.com (2603:10b6:3:13e::31) by DM5PR12MB1194.namprd12.prod.outlook.com (2603:10b6:3:6e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.26; Mon, 17 May 2021 17:05:02 +0000 Received: from DM6NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:3:13e:cafe::ac) by DM5PR07CA0141.outlook.office365.com (2603:10b6:3:13e::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.24 via Frontend Transport; Mon, 17 May 2021 17:05:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT049.mail.protection.outlook.com (10.13.172.188) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Mon, 17 May 2021 17:05:02 +0000 Received: from shredder.mellanox.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 May 2021 17:04:58 +0000 From: Ido Schimmel To: CC: , , , , , , , Ido Schimmel Subject: [PATCH net-next 08/11] mlxsw: core: Avoid unnecessary EMAD buffer copy Date: Mon, 17 May 2021 20:03:58 +0300 Message-ID: <20210517170401.188563-9-idosch@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517170401.188563-1-idosch@nvidia.com> References: <20210517170401.188563-1-idosch@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5381c74e-5d11-47b8-2922-08d91955e944 X-MS-TrafficTypeDiagnostic: DM5PR12MB1194: X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gM40WhxJPOwJkhfhVE8f2eO9Ahik8Ln2feq3tgXgGx+cXZlFvXH7tXfNMRYYxaJ8IO7UOEcjyiHkDyBoxi2Vepxqo4LZ06wNxkXwSyKlDk2/X5iJH6JpmNJBXJikGMIMnmt/FzTMr2IZLm2h1/3okoct6TmigkdY3YDxdQ+9AlMhGKtpzFlsH4ZAR25UeD1K2l6pduQ5L7AkSOAD9VGPfHjr44gfZgTdjj2X8AGfAYrezsTTO2BIOsAp8E4aj4Gi4NrUEq0qKffR7ayOKNYc+6WnCohGN0MY3Qk8qlZg9K0CAkNbYS8L607nwLG/Z5mFq7r3s0Ra30sjZgzlRV9SfkuFjorRCu+89ryl1oHFtFd/x/pFwp4yS7r7YylJujcCkpUlbXjPFbQEoQLlgPfRjUfeDJK6RuQhlBqPeqsdKayfTaugcakrf+gAT4oVsw0w7Km/U4USuxPtpbNaKxXDBtPpj0d86WKaCTpj6bh3U0irklZ/q8ofh3KFTHTQ/kdt2MJXh6xfyvfIptYnh/d7crSZ0SP9p+tbzuko1cCvwMucO0/hyeAfJhFPpRsErhr+4MWTDgEjwWbdeGjUysM0u3huifO9dCk0notxBv+OEBmaSvmeEWOWrxD4Ypuxj6OgyG/189SWtk77ncRNxEaerwQYpZ+TKYm29hqLOWR2tK8= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(396003)(136003)(346002)(376002)(46966006)(36840700001)(316002)(36906005)(107886003)(26005)(5660300002)(36756003)(4326008)(1076003)(54906003)(70206006)(70586007)(8676002)(16526019)(2616005)(426003)(336012)(8936002)(6916009)(186003)(86362001)(82740400003)(7636003)(36860700001)(47076005)(82310400003)(83380400001)(356005)(2906002)(478600001); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2021 17:05:02.4279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5381c74e-5d11-47b8-2922-08d91955e944 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1194 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org mlxsw_emad_transmit() takes care of sending EMAD transactions to the device. Since these transactions can time out, the driver performs up to 5 retransmissions, each time copying the skb with the original request. The data of the skb does not change throughout the process, so there is no need to copy it each time. Instead, only the skb itself can be copied. Therefore, use skb_clone() instead of skb_copy(). This reduces the latency of the function by about 16%. Signed-off-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index 7e9a7cb31720..ad93e01b2cda 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -630,7 +630,7 @@ static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb; int err; - skb = skb_copy(trans->tx_skb, GFP_KERNEL); + skb = skb_clone(trans->tx_skb, GFP_KERNEL); if (!skb) return -ENOMEM; From patchwork Mon May 17 17:04:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ido Schimmel X-Patchwork-Id: 440490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86E22C43460 for ; Mon, 17 May 2021 17:20:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 68AF260FD8 for ; Mon, 17 May 2021 17:20:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242754AbhEQRVa (ORCPT ); Mon, 17 May 2021 13:21:30 -0400 Received: from azhdrrw-ex02.nvidia.com ([20.64.145.131]:52745 "EHLO AZHDRRW-EX02.NVIDIA.COM" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242634AbhEQRV3 (ORCPT ); Mon, 17 May 2021 13:21:29 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (104.47.59.173) by mxs.oss.nvidia.com (10.13.234.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.12; Mon, 17 May 2021 10:05:11 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=efBlDztVTdn5C7cVTRpBD0xdMgXp++SPES2B/RIfEig5GZeUUHjVohilkqk3/i64J1LnPOieNHjJwzg/4vjdfypXdWlP5HRiTNUOXR3g/syn5UNYDSqvWZEHjdoocdgt8KHkqquggjBfyRj73GQRfzhNIA7Qigh9clDabDMhBTbZInajdgUIhS7nnWb2+3FB8zR03E8gMivazLSr5CUC182ZV66IC+i/P+F0cgztQM5dFoUpRkIvbp5ednmU6c5K3f38Yrx+j25OZ61oEINZiOVuvxjFKgcddEYPBIcITR/XleuRw6gmFx/q3HnaVBATOTosUEtPObhbS2MnSXUP/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YOEvS/le/p6rP2QgommtcVu/VMp2/6zoZuNjKhbdMcM=; b=cBNYHzaloYoeefIhzFJcFee+wXvvKl0kH721UFRLxABMUanWBosf44DPzOyO/RHI8G1MVHqZCPYyTtmA2IvOf//KdltF9t2f9Ud63H/a7bCxpRWizhQ1yI48BzE+Ix1s1K8tQjDllQj1ifIfPAKXLL8YE93ZLUGDb/IW9dt4oKLMKjxNCgZI0ylU46eTcOGtbdptvwnFsEWrP5p+6/1d4fhUrEoZBWVnBCkwwr4bI/eRq87C8ImNC+9aghwAuG+QEMchy5cZTCtKotji4cGa54DtNlKBSzpyGMtmWKI2a2dELxuU7MlN7fdnGctDO8QO8QPXdzee0Utt+wQQ2WeGUA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YOEvS/le/p6rP2QgommtcVu/VMp2/6zoZuNjKhbdMcM=; b=lHXS3xupVxFN779AeIvcaTV/tyn3yxKLofLEn1FddA0DK31qOOdudPULpDgOmZR8GU4bqhP1fWw1kU2bnslS7t7/3O740BUHhsfj3J1+bsayAMbuOMaWSV79Od97aJrkVNVbvNTj8hingcFS/dJuMEOulysECwJt3JyYMPWflsBveRSphmuZbo8Q2WzyjN8PHVaOP/CLKOWdhSq2FBQjNbzSJpai7aregSLeWvtqWW9DvwkYYaGqeAwtIr+hGVuoHuYt+3jFz1DZe0CpMjHY7H6gk3LFN6OpSsoXA6waL9Me3JTjFqAk3AmC41ihmHx9zKmepAtA/N2FxC7CHpr5dQ== Received: from DM5PR07CA0124.namprd07.prod.outlook.com (2603:10b6:3:13e::14) by CY4PR12MB1701.namprd12.prod.outlook.com (2603:10b6:903:121::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.28; Mon, 17 May 2021 17:05:09 +0000 Received: from DM6NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:3:13e:cafe::3a) by DM5PR07CA0124.outlook.office365.com (2603:10b6:3:13e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.25 via Frontend Transport; Mon, 17 May 2021 17:05:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT049.mail.protection.outlook.com (10.13.172.188) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4129.25 via Frontend Transport; Mon, 17 May 2021 17:05:09 +0000 Received: from shredder.mellanox.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 May 2021 17:05:06 +0000 From: Ido Schimmel To: CC: , , , , , , , Ido Schimmel Subject: [PATCH net-next 10/11] mlxsw: Remove Mellanox SwitchIB ASIC support Date: Mon, 17 May 2021 20:04:00 +0300 Message-ID: <20210517170401.188563-11-idosch@nvidia.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517170401.188563-1-idosch@nvidia.com> References: <20210517170401.188563-1-idosch@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b1be3331-5bcd-4ace-6e2f-08d91955ed70 X-MS-TrafficTypeDiagnostic: CY4PR12MB1701: X-Microsoft-Antispam-PRVS: X-MS-Exchange-Transport-Forked: True X-MS-Oob-TLC-OOBClassifiers: OLM:4125; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7L/orxJWX6Dp5HlRrmQJTwWw0gL4Y1nNsWlnvTu/hsmzFUl3hrAbKUOqPQwvLbXjyvmqJSfiMV05k1g3QMDGu5H0f5ZK5vjvHmDZtj/IYEev5s/yiCi6dBJT+Znz4ELv2/XnJSriQq8AMroE5hCpTRmwz48ePQ/5OKqPLBIpfAuT24TGEqpL6AmZtC7/NGl7pA/IfxtppcrjNirzFZACjS8/x27BhzXzmcvlKEHEnfkBz8KKB9OWRfP/Tcs2UTyKWxLKa6fQgagvxtagO7s6dY/lL9zTs88I1Us+8DITtvVSeF4OhUWHwvwLAV89k89tW65cO5pSQH9oAkUrp+EeN1yl6hNseNLq0Z5nG0GKRARjUO1xYFIYY7EHAnH0ZKJewLiREsP9Mzj0D2YMMGCrVdF6aGBQYB7Asoq4Zld8Oe5wSXi7OsiQ/Hd4Ag4nmPFs7RLU3Px3Z+C93sixwK3kAG3OOsh3eqXP+LXCHpsQ+cyKQ7XqVQHT+EAjEUSfIVBoMxzWAaLrY5pmYgroeETuhHeVQRD+b3xhimXUuJfaalupoMgLoVpotB8qyNxKWV8vhTqpBuGlFyCRTZh4BstcgQKK+qvqq83d3/7l3eKrqnwYZoCFlcb9KkArIKs5ntk+REIDbkPrRP7s15A7K2kqdjGLrU3qQQM4oaLFLX7wDu0= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(346002)(39860400002)(136003)(376002)(36840700001)(46966006)(2906002)(8676002)(54906003)(26005)(16526019)(186003)(70586007)(82310400003)(4326008)(83380400001)(2616005)(30864003)(426003)(478600001)(6916009)(82740400003)(336012)(36860700001)(47076005)(5660300002)(70206006)(1076003)(8936002)(107886003)(6666004)(86362001)(7636003)(36906005)(356005)(316002)(36756003); DIR:OUT; SFP:1101; X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2021 17:05:09.4849 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1be3331-5bcd-4ace-6e2f-08d91955ed70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1701 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Amit Cohen Initial support for the Mellanox SwitchIB and SwitchIB-2 ASICs was added in October 2016, but since then development of this driver stopped. Therefore, the driver does not support any offloads and simply registers devlink ports for its front panel ports, rendering it irrelevant for deployment. Given the driver is not used by any users and that there is no intention of investing in its development, remove it from the kernel. Signed-off-by: Amit Cohen Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko --- drivers/net/ethernet/mellanox/mlxsw/Kconfig | 11 - drivers/net/ethernet/mellanox/mlxsw/Makefile | 2 - drivers/net/ethernet/mellanox/mlxsw/pci.h | 2 - .../net/ethernet/mellanox/mlxsw/switchib.c | 595 ------------------ 4 files changed, 610 deletions(-) delete mode 100644 drivers/net/ethernet/mellanox/mlxsw/switchib.c diff --git a/drivers/net/ethernet/mellanox/mlxsw/Kconfig b/drivers/net/ethernet/mellanox/mlxsw/Kconfig index a619d90559f7..6509b5fab936 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/Kconfig +++ b/drivers/net/ethernet/mellanox/mlxsw/Kconfig @@ -49,17 +49,6 @@ config MLXSW_I2C To compile this driver as a module, choose M here: the module will be called mlxsw_i2c. -config MLXSW_SWITCHIB - tristate "Mellanox Technologies SwitchIB and SwitchIB-2 support" - depends on MLXSW_CORE && MLXSW_PCI && NET_SWITCHDEV - default m - help - This driver supports Mellanox Technologies SwitchIB and SwitchIB-2 - Infiniband Switch ASICs. - - To compile this driver as a module, choose M here: the - module will be called mlxsw_switchib. - config MLXSW_SWITCHX2 tristate "Mellanox Technologies SwitchX-2 support" depends on MLXSW_CORE && MLXSW_PCI && NET_SWITCHDEV diff --git a/drivers/net/ethernet/mellanox/mlxsw/Makefile b/drivers/net/ethernet/mellanox/mlxsw/Makefile index f545fd2c5896..b68e5ba323cc 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/Makefile +++ b/drivers/net/ethernet/mellanox/mlxsw/Makefile @@ -8,8 +8,6 @@ obj-$(CONFIG_MLXSW_PCI) += mlxsw_pci.o mlxsw_pci-objs := pci.o obj-$(CONFIG_MLXSW_I2C) += mlxsw_i2c.o mlxsw_i2c-objs := i2c.o -obj-$(CONFIG_MLXSW_SWITCHIB) += mlxsw_switchib.o -mlxsw_switchib-objs := switchib.o obj-$(CONFIG_MLXSW_SWITCHX2) += mlxsw_switchx2.o mlxsw_switchx2-objs := switchx2.o obj-$(CONFIG_MLXSW_SPECTRUM) += mlxsw_spectrum.o diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.h b/drivers/net/ethernet/mellanox/mlxsw/pci.h index 5b1323645a5d..b0702947d895 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.h +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.h @@ -10,8 +10,6 @@ #define PCI_DEVICE_ID_MELLANOX_SPECTRUM 0xcb84 #define PCI_DEVICE_ID_MELLANOX_SPECTRUM2 0xcf6c #define PCI_DEVICE_ID_MELLANOX_SPECTRUM3 0xcf70 -#define PCI_DEVICE_ID_MELLANOX_SWITCHIB 0xcb20 -#define PCI_DEVICE_ID_MELLANOX_SWITCHIB2 0xcf08 #if IS_ENABLED(CONFIG_MLXSW_PCI) diff --git a/drivers/net/ethernet/mellanox/mlxsw/switchib.c b/drivers/net/ethernet/mellanox/mlxsw/switchib.c deleted file mode 100644 index 1e561132eb1e..000000000000 --- a/drivers/net/ethernet/mellanox/mlxsw/switchib.c +++ /dev/null @@ -1,595 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 -/* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pci.h" -#include "core.h" -#include "reg.h" -#include "port.h" -#include "trap.h" -#include "txheader.h" -#include "ib.h" - -static const char mlxsw_sib_driver_name[] = "mlxsw_switchib"; -static const char mlxsw_sib2_driver_name[] = "mlxsw_switchib2"; - -struct mlxsw_sib_port; - -struct mlxsw_sib { - struct mlxsw_sib_port **ports; - struct mlxsw_core *core; - const struct mlxsw_bus_info *bus_info; - u8 hw_id[ETH_ALEN]; -}; - -struct mlxsw_sib_port { - struct mlxsw_sib *mlxsw_sib; - u8 local_port; - struct { - u8 module; - } mapping; -}; - -/* tx_v1_hdr_version - * Tx header version. - * Must be set to 1. - */ -MLXSW_ITEM32(tx_v1, hdr, version, 0x00, 28, 4); - -/* tx_v1_hdr_ctl - * Packet control type. - * 0 - Ethernet control (e.g. EMADs, LACP) - * 1 - Ethernet data - */ -MLXSW_ITEM32(tx_v1, hdr, ctl, 0x00, 26, 2); - -/* tx_v1_hdr_proto - * Packet protocol type. Must be set to 1 (Ethernet). - */ -MLXSW_ITEM32(tx_v1, hdr, proto, 0x00, 21, 3); - -/* tx_v1_hdr_swid - * Switch partition ID. Must be set to 0. - */ -MLXSW_ITEM32(tx_v1, hdr, swid, 0x00, 12, 3); - -/* tx_v1_hdr_control_tclass - * Indicates if the packet should use the control TClass and not one - * of the data TClasses. - */ -MLXSW_ITEM32(tx_v1, hdr, control_tclass, 0x00, 6, 1); - -/* tx_v1_hdr_port_mid - * Destination local port for unicast packets. - * Destination multicast ID for multicast packets. - * - * Control packets are directed to a specific egress port, while data - * packets are transmitted through the CPU port (0) into the switch partition, - * where forwarding rules are applied. - */ -MLXSW_ITEM32(tx_v1, hdr, port_mid, 0x04, 16, 16); - -/* tx_v1_hdr_type - * 0 - Data packets - * 6 - Control packets - */ -MLXSW_ITEM32(tx_v1, hdr, type, 0x0C, 0, 4); - -static void -mlxsw_sib_tx_v1_hdr_construct(struct sk_buff *skb, - const struct mlxsw_tx_info *tx_info) -{ - char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); - - memset(txhdr, 0, MLXSW_TXHDR_LEN); - - mlxsw_tx_v1_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); - mlxsw_tx_v1_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); - mlxsw_tx_v1_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); - mlxsw_tx_v1_hdr_swid_set(txhdr, 0); - mlxsw_tx_v1_hdr_control_tclass_set(txhdr, 1); - mlxsw_tx_v1_hdr_port_mid_set(txhdr, tx_info->local_port); - mlxsw_tx_v1_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); -} - -static int mlxsw_sib_hw_id_get(struct mlxsw_sib *mlxsw_sib) -{ - char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; - int err; - - err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(spad), spad_pl); - if (err) - return err; - mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sib->hw_id); - return 0; -} - -static int -mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port *mlxsw_sib_port, - bool is_up) -{ - struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib; - char paos_pl[MLXSW_REG_PAOS_LEN]; - - mlxsw_reg_paos_pack(paos_pl, mlxsw_sib_port->local_port, - is_up ? MLXSW_PORT_ADMIN_STATUS_UP : - MLXSW_PORT_ADMIN_STATUS_DOWN); - return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(paos), paos_pl); -} - -static int mlxsw_sib_port_mtu_set(struct mlxsw_sib_port *mlxsw_sib_port, - u16 mtu) -{ - struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib; - char pmtu_pl[MLXSW_REG_PMTU_LEN]; - int max_mtu; - int err; - - mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, 0); - err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl); - if (err) - return err; - max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); - - if (mtu > max_mtu) - return -EINVAL; - - mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, mtu); - return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl); -} - -static int mlxsw_sib_port_set(struct mlxsw_sib_port *mlxsw_sib_port, u8 port) -{ - struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib; - char plib_pl[MLXSW_REG_PLIB_LEN] = {0}; - int err; - - mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sib_port->local_port); - mlxsw_reg_plib_ib_port_set(plib_pl, port); - err = mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(plib), plib_pl); - return err; -} - -static int mlxsw_sib_port_swid_set(struct mlxsw_sib_port *mlxsw_sib_port, - u8 swid) -{ - struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib; - char pspa_pl[MLXSW_REG_PSPA_LEN]; - - mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sib_port->local_port); - return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pspa), pspa_pl); -} - -static int mlxsw_sib_port_module_info_get(struct mlxsw_sib *mlxsw_sib, - u8 local_port, u8 *p_module, - u8 *p_width) -{ - char pmlp_pl[MLXSW_REG_PMLP_LEN]; - int err; - - mlxsw_reg_pmlp_pack(pmlp_pl, local_port); - err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmlp), pmlp_pl); - if (err) - return err; - *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); - *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); - return 0; -} - -static int mlxsw_sib_port_speed_set(struct mlxsw_sib_port *mlxsw_sib_port, - u16 speed, u16 width) -{ - struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib; - char ptys_pl[MLXSW_REG_PTYS_LEN]; - - mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sib_port->local_port, speed, - width); - return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(ptys), ptys_pl); -} - -static bool mlxsw_sib_port_created(struct mlxsw_sib *mlxsw_sib, u8 local_port) -{ - return mlxsw_sib->ports[local_port] != NULL; -} - -static int __mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port, - u8 module, u8 width) -{ - struct mlxsw_sib_port *mlxsw_sib_port; - int err; - - mlxsw_sib_port = kzalloc(sizeof(*mlxsw_sib_port), GFP_KERNEL); - if (!mlxsw_sib_port) - return -ENOMEM; - mlxsw_sib_port->mlxsw_sib = mlxsw_sib; - mlxsw_sib_port->local_port = local_port; - mlxsw_sib_port->mapping.module = module; - - err = mlxsw_sib_port_swid_set(mlxsw_sib_port, 0); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set SWID\n", - mlxsw_sib_port->local_port); - goto err_port_swid_set; - } - - /* Expose the IB port number as it's front panel name */ - err = mlxsw_sib_port_set(mlxsw_sib_port, module + 1); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set IB port\n", - mlxsw_sib_port->local_port); - goto err_port_ib_set; - } - - /* Supports all speeds from SDR to FDR (bitmask) and support bus width - * of 1x, 2x and 4x (3 bits bitmask) - */ - err = mlxsw_sib_port_speed_set(mlxsw_sib_port, - MLXSW_REG_PTYS_IB_SPEED_EDR - 1, - BIT(3) - 1); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set speed\n", - mlxsw_sib_port->local_port); - goto err_port_speed_set; - } - - /* Change to the maximum MTU the device supports, the SMA will take - * care of the active MTU - */ - err = mlxsw_sib_port_mtu_set(mlxsw_sib_port, MLXSW_IB_DEFAULT_MTU); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set MTU\n", - mlxsw_sib_port->local_port); - goto err_port_mtu_set; - } - - err = mlxsw_sib_port_admin_status_set(mlxsw_sib_port, true); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to change admin state to UP\n", - mlxsw_sib_port->local_port); - goto err_port_admin_set; - } - - mlxsw_core_port_ib_set(mlxsw_sib->core, mlxsw_sib_port->local_port, - mlxsw_sib_port); - mlxsw_sib->ports[local_port] = mlxsw_sib_port; - return 0; - -err_port_admin_set: -err_port_mtu_set: -err_port_speed_set: -err_port_ib_set: - mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT); -err_port_swid_set: - kfree(mlxsw_sib_port); - return err; -} - -static int mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port, - u8 module, u8 width) -{ - int err; - - err = mlxsw_core_port_init(mlxsw_sib->core, local_port, - module + 1, false, 0, false, 0, - mlxsw_sib->hw_id, sizeof(mlxsw_sib->hw_id)); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to init core port\n", - local_port); - return err; - } - err = __mlxsw_sib_port_create(mlxsw_sib, local_port, module, width); - if (err) - goto err_port_create; - - return 0; - -err_port_create: - mlxsw_core_port_fini(mlxsw_sib->core, local_port); - return err; -} - -static void __mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port) -{ - struct mlxsw_sib_port *mlxsw_sib_port = mlxsw_sib->ports[local_port]; - - mlxsw_core_port_clear(mlxsw_sib->core, local_port, mlxsw_sib); - mlxsw_sib->ports[local_port] = NULL; - mlxsw_sib_port_admin_status_set(mlxsw_sib_port, false); - mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT); - kfree(mlxsw_sib_port); -} - -static void mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port) -{ - __mlxsw_sib_port_remove(mlxsw_sib, local_port); - mlxsw_core_port_fini(mlxsw_sib->core, local_port); -} - -static void mlxsw_sib_ports_remove(struct mlxsw_sib *mlxsw_sib) -{ - int i; - - for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++) - if (mlxsw_sib_port_created(mlxsw_sib, i)) - mlxsw_sib_port_remove(mlxsw_sib, i); - kfree(mlxsw_sib->ports); -} - -static int mlxsw_sib_ports_create(struct mlxsw_sib *mlxsw_sib) -{ - size_t alloc_size; - u8 module, width; - int i; - int err; - - alloc_size = sizeof(struct mlxsw_sib_port *) * MLXSW_PORT_MAX_IB_PORTS; - mlxsw_sib->ports = kzalloc(alloc_size, GFP_KERNEL); - if (!mlxsw_sib->ports) - return -ENOMEM; - - for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++) { - err = mlxsw_sib_port_module_info_get(mlxsw_sib, i, &module, - &width); - if (err) - goto err_port_module_info_get; - if (!width) - continue; - err = mlxsw_sib_port_create(mlxsw_sib, i, module, width); - if (err) - goto err_port_create; - } - return 0; - -err_port_create: -err_port_module_info_get: - for (i--; i >= 1; i--) - if (mlxsw_sib_port_created(mlxsw_sib, i)) - mlxsw_sib_port_remove(mlxsw_sib, i); - kfree(mlxsw_sib->ports); - return err; -} - -static void -mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port *mlxsw_sib_port, - enum mlxsw_reg_pude_oper_status status) -{ - if (status == MLXSW_PORT_OPER_STATUS_UP) - pr_info("ib link for port %d - up\n", - mlxsw_sib_port->mapping.module + 1); - else - pr_info("ib link for port %d - down\n", - mlxsw_sib_port->mapping.module + 1); -} - -static void mlxsw_sib_pude_event_func(const struct mlxsw_reg_info *reg, - char *pude_pl, void *priv) -{ - struct mlxsw_sib *mlxsw_sib = priv; - struct mlxsw_sib_port *mlxsw_sib_port; - enum mlxsw_reg_pude_oper_status status; - u8 local_port; - - local_port = mlxsw_reg_pude_local_port_get(pude_pl); - mlxsw_sib_port = mlxsw_sib->ports[local_port]; - if (!mlxsw_sib_port) { - dev_warn(mlxsw_sib->bus_info->dev, "Port %d: Link event received for non-existent port\n", - local_port); - return; - } - - status = mlxsw_reg_pude_oper_status_get(pude_pl); - mlxsw_sib_pude_ib_event_func(mlxsw_sib_port, status); -} - -static const struct mlxsw_listener mlxsw_sib_listener[] = { - MLXSW_EVENTL(mlxsw_sib_pude_event_func, PUDE, EMAD), -}; - -static int mlxsw_sib_taps_init(struct mlxsw_sib *mlxsw_sib) -{ - int i; - int err; - - for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) { - err = mlxsw_core_trap_register(mlxsw_sib->core, - &mlxsw_sib_listener[i], - mlxsw_sib); - if (err) - goto err_rx_listener_register; - } - - return 0; - -err_rx_listener_register: - for (i--; i >= 0; i--) { - mlxsw_core_trap_unregister(mlxsw_sib->core, - &mlxsw_sib_listener[i], - mlxsw_sib); - } - - return err; -} - -static void mlxsw_sib_traps_fini(struct mlxsw_sib *mlxsw_sib) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) { - mlxsw_core_trap_unregister(mlxsw_sib->core, - &mlxsw_sib_listener[i], mlxsw_sib); - } -} - -static int mlxsw_sib_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) -{ - char htgt_pl[MLXSW_REG_HTGT_LEN]; - - mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, - MLXSW_REG_HTGT_INVALID_POLICER, - MLXSW_REG_HTGT_DEFAULT_PRIORITY, - MLXSW_REG_HTGT_DEFAULT_TC); - mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS); - mlxsw_reg_htgt_local_path_rdq_set(htgt_pl, - MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD); - return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); -} - -static int mlxsw_sib_init(struct mlxsw_core *mlxsw_core, - const struct mlxsw_bus_info *mlxsw_bus_info, - struct netlink_ext_ack *extack) -{ - struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core); - int err; - - mlxsw_sib->core = mlxsw_core; - mlxsw_sib->bus_info = mlxsw_bus_info; - - err = mlxsw_sib_hw_id_get(mlxsw_sib); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Failed to get switch HW ID\n"); - return err; - } - - err = mlxsw_sib_ports_create(mlxsw_sib); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Failed to create ports\n"); - return err; - } - - err = mlxsw_sib_taps_init(mlxsw_sib); - if (err) { - dev_err(mlxsw_sib->bus_info->dev, "Failed to set traps\n"); - goto err_traps_init_err; - } - - return 0; - -err_traps_init_err: - mlxsw_sib_ports_remove(mlxsw_sib); - return err; -} - -static void mlxsw_sib_fini(struct mlxsw_core *mlxsw_core) -{ - struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core); - - mlxsw_sib_traps_fini(mlxsw_sib); - mlxsw_sib_ports_remove(mlxsw_sib); -} - -static const struct mlxsw_config_profile mlxsw_sib_config_profile = { - .used_max_system_port = 1, - .max_system_port = 48000, - .used_max_ib_mc = 1, - .max_ib_mc = 27, - .used_max_pkey = 1, - .max_pkey = 32, - .swid_config = { - { - .used_type = 1, - .type = MLXSW_PORT_SWID_TYPE_IB, - } - }, -}; - -static struct mlxsw_driver mlxsw_sib_driver = { - .kind = mlxsw_sib_driver_name, - .priv_size = sizeof(struct mlxsw_sib), - .init = mlxsw_sib_init, - .fini = mlxsw_sib_fini, - .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set, - .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct, - .txhdr_len = MLXSW_TXHDR_LEN, - .profile = &mlxsw_sib_config_profile, -}; - -static struct mlxsw_driver mlxsw_sib2_driver = { - .kind = mlxsw_sib2_driver_name, - .priv_size = sizeof(struct mlxsw_sib), - .init = mlxsw_sib_init, - .fini = mlxsw_sib_fini, - .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set, - .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct, - .txhdr_len = MLXSW_TXHDR_LEN, - .profile = &mlxsw_sib_config_profile, -}; - -static const struct pci_device_id mlxsw_sib_pci_id_table[] = { - {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB), 0}, - {0, }, -}; - -static struct pci_driver mlxsw_sib_pci_driver = { - .name = mlxsw_sib_driver_name, - .id_table = mlxsw_sib_pci_id_table, -}; - -static const struct pci_device_id mlxsw_sib2_pci_id_table[] = { - {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB2), 0}, - {0, }, -}; - -static struct pci_driver mlxsw_sib2_pci_driver = { - .name = mlxsw_sib2_driver_name, - .id_table = mlxsw_sib2_pci_id_table, -}; - -static int __init mlxsw_sib_module_init(void) -{ - int err; - - err = mlxsw_core_driver_register(&mlxsw_sib_driver); - if (err) - return err; - - err = mlxsw_core_driver_register(&mlxsw_sib2_driver); - if (err) - goto err_sib2_driver_register; - - err = mlxsw_pci_driver_register(&mlxsw_sib_pci_driver); - if (err) - goto err_sib_pci_driver_register; - - err = mlxsw_pci_driver_register(&mlxsw_sib2_pci_driver); - if (err) - goto err_sib2_pci_driver_register; - - return 0; - -err_sib2_pci_driver_register: - mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver); -err_sib_pci_driver_register: - mlxsw_core_driver_unregister(&mlxsw_sib2_driver); -err_sib2_driver_register: - mlxsw_core_driver_unregister(&mlxsw_sib_driver); - return err; -} - -static void __exit mlxsw_sib_module_exit(void) -{ - mlxsw_pci_driver_unregister(&mlxsw_sib2_pci_driver); - mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver); - mlxsw_core_driver_unregister(&mlxsw_sib2_driver); - mlxsw_core_driver_unregister(&mlxsw_sib_driver); -} - -module_init(mlxsw_sib_module_init); -module_exit(mlxsw_sib_module_exit); - -MODULE_LICENSE("Dual BSD/GPL"); -MODULE_AUTHOR("Elad Raz "); -MODULE_DESCRIPTION("Mellanox SwitchIB and SwitchIB-2 driver"); -MODULE_ALIAS("mlxsw_switchib2"); -MODULE_DEVICE_TABLE(pci, mlxsw_sib_pci_id_table); -MODULE_DEVICE_TABLE(pci, mlxsw_sib2_pci_id_table);