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[198.145.21.10]) by mx.google.com with ESMTPS id 13-v6si3056835ple.274.2018.07.04.00.51.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hZB1uZWY; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AA0D6210C125E; Wed, 4 Jul 2018 00:51:29 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 20D8A210C0F74 for ; Wed, 4 Jul 2018 00:51:29 -0700 (PDT) Received: by mail-pf0-x242.google.com with SMTP id v9-v6so2269985pff.9 for ; Wed, 04 Jul 2018 00:51:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2GIue/aybt5tZzjD+BhxHrMBA1bf79ztpczv1tK7EQA=; b=hZB1uZWY2RxkUlvkXmkFz/wuD77L/jx2Tzsw1wKnwn76suQGu7SYfrsJxurs4K1AVg 6fPf61V8CHYfxGhPe7/aKzQSvEeSdYJsm5NDlw77rpcHHh/zG9ncn6AIgqp3SdoRPqQ5 gWG3CzItt41MUmvN1emJgBYKdsALhmRPmmKUI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2GIue/aybt5tZzjD+BhxHrMBA1bf79ztpczv1tK7EQA=; b=SZvQGnoWMBsKal3h7RdVYnWUbbMsDWF+ROyaLgAX/OforeEU3Rp9LZQSAGbDBIKo4Q wNUrKC6+dGMYufP8x8d07MUi3HkYKnHIZ34Ts4QQPhtC7fg2rmrDasfJ3sL0E7TEKDxE 1FuA6tGqBQqD7u/g5Iwpwh30ukn0qfU/n/iiZSci/0YHt/melBEhzrJhJRSSJEo34UyW g2gfjGwb3tIx0Sio83t0NfFisRkCI2h2LwoOUwd8UHPeCIEkwefwsR9ys+H21f9Ay44H s6ivGBturrSIEYa+P4T7CUzxgZyRMa/XC5hmDMyoNx4UMQsBUWxp7xWG8vZv9MTanmaK 2FbQ== X-Gm-Message-State: APt69E1rKhFAgpbKt7PiAefzmwOv2SPoHfTIYMOYIIO0znYegMKWuq8g 1uVM6zf9LbrKXX62m0s5nMCG1g== X-Received: by 2002:a65:4b0f:: with SMTP id r15-v6mr928232pgq.103.1530690688881; Wed, 04 Jul 2018 00:51:28 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:28 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:12 +0800 Message-Id: <20180704075117.7427-2-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The edk2 commit bacfd6e let CpuDxe running latter. CpuDxe is needed by gDS->SetMemorySpaceAttributes, and gDS->SetMemorySpaceAttributes is invoked by some drivers. This issue can solve by adding Depex on gEfiCpuArchProtocolGuid to RealTimeClockLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/D03.fdf | 4 ++++ Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 ++ 2 files changed, 6 insertions(+) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 1383aa1091..73e2b7e958 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -146,6 +146,10 @@ READ_STATUS = TRUE READ_LOCK_CAP = TRUE READ_LOCK_STATUS = TRUE + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + } + INF MdeModulePkg/Core/Dxe/DxeMain.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf index 319c35c724..ae7116dc31 100644 --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf @@ -46,3 +46,5 @@ [Pcd] +[Depex] + gEfiCpuArchProtocolGuid From patchwork Wed Jul 4 07:51:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 141014 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp501675ljj; Wed, 4 Jul 2018 00:51:34 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdrZd0jEvVLV0oksrbQB71bWQ98HAf6vcmCqWATjCun0xHlJCIgbXV34lDKseQ3yr7ONNwI X-Received: by 2002:a65:62d8:: with SMTP id m24-v6mr918819pgv.307.1530690694252; Wed, 04 Jul 2018 00:51:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530690694; cv=none; d=google.com; s=arc-20160816; b=BjFs1SdROkyPm/WWZ1fU5k/0Vq0edklkPp73ILvncuAj5PXfQ6YzdMpfWIS66IXIzx obvoA4OV8/9I5eq4bLW0L/TtCWzVDOj3/Y2ncLr8oo8FLw1pj4u/NKRhoCMHtW4Yh09h LPZfhjbKzY0bpoI7EZi45HXbsEJWD7Xge8TykuR90uhYM46VeDqYEEydVvgOqm4S+uxT BZlc8oljRze+0F/cyghlvzIktr55T5eTYgUa1ogfxCseD3AMfGXVYrSOiJsauYv6IX/d cCiAeFx6ZKQxA914yyRQ3sF67gPBlB0SFBLWcJY7BjbKQV4lak9dBynYofhGAx00hMqQ w/Dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=3SzEOy3RU/mF1NU3LvVBJqPubNYObohh8XdBV+JpBTY=; b=YdH5iK0/GjKpljFpjEJW+zCMx6En//IW2sKT/8ebSBA7+bkkD8ziqrW0n+QNslJX2h 7QojFsfKmbyoY49BMGx5NZMUYNDMCbfx547NdDaCbEBU+0x6gDTb9+CcppxRvGuxuWol T5w5XlCd2sMVzeB/VHJfIhjNhhTOhIgiPbUOH6yoxrBAb0vhHQTnbjlHR4qjdK089dkj PWfvF+IivqzAdujOY5DmX4v6j3RdmtgbqPvP0nf+cPPV82I+Kvqf1UY3hNAYiHLC6qwi xcL4UwsbPCKdvJl2hxzbv1f1HthVj8ej4QXnuymSK+5iaiE7qPxX/yT0ll9LUpLTLUBj skLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aDN19Alq; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id m3-v6si3037988plt.71.2018.07.04.00.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aDN19Alq; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DD905210C42D3; Wed, 4 Jul 2018 00:51:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F0D322098EAC7 for ; Wed, 4 Jul 2018 00:51:32 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id m16-v6so2289668pls.11 for ; Wed, 04 Jul 2018 00:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eVWucS/j26op3zbHs7QzFX1SIKxDy2ASWOJkY2smFgk=; b=aDN19AlqtSnaYjhijcH06XJ3M4U8eCUzLKvXX2B7yt+FLpHjEHqxud324YXKmx5mka BssYTY3Ak87vWJILkJyGaojsKMmzcZFwyc678N/BgHQQnD+x5sJVBWFqtyDigK/xouep nfQz9XDn/B1HLkc4CJD3X0WY9KOHzMNYrF8/w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eVWucS/j26op3zbHs7QzFX1SIKxDy2ASWOJkY2smFgk=; b=kJV1KALn3B1NEFwsjNwizXdFfJSbqvj9vLBCnvjbVTHq2ZOPzlahRTqqrMHguqeiB7 mZfAFkRkSZjunDaTJvjqNusMjhkyS3bu4/TrIpEo3PbRp644IwK08+hMAsCj+AAKppHF axG8DAi86J7L7rSli4g1cprTqVnIxiiq39nwpTKATAWJ8hpf8unSxknKkIj76lizEe7/ ghA3aD9kOAVIzra1kna0EtdbVOvBgtppz/0h0USTLKiYTbFs4wX5iDanmIsbgr09w0Rk uig+G0xVWxYS3el1n/ykPHO/Fq1VN8eD1eDqBHZkJMYC5CTjXTOwuSnuLQhgMIsd28Hj Wn6w== X-Gm-Message-State: APt69E0QIq9NYKAy2emg0XnmQxlQiIiF17LetdhUTsP6byJXighECdgT 1nbdz4bbjdRvZR2U2OZ7eF4uKw== X-Received: by 2002:a17:902:b589:: with SMTP id a9-v6mr1064382pls.140.1530690692674; Wed, 04 Jul 2018 00:51:32 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:32 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:13 +0800 Message-Id: <20180704075117.7427-3-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" From: Jason Zhang 1. During test PCIe mcs9922 UART card, the card can't work because the IO ATU config is overlap by Cfg0/Cfg1 ATU address. 2. After adjust the ATU windows, Cfg0/Cfg1 config as below: Cfg0 is equal to "ECAM + (BusBase, 0, 0)" Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang Signed-off-by: Heyi Guo Signed-off-by: Ming Huang --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 55b80aa4e4..e5f66eaa4a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -640,11 +640,12 @@ void SetAtuConfig0RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; + UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); @@ -666,12 +667,12 @@ void SetAtuConfig1RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; - + UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); From patchwork Wed Jul 4 07:51:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 141015 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp501726ljj; Wed, 4 Jul 2018 00:51:37 -0700 (PDT) X-Google-Smtp-Source: AAOMgpc7jIV6D6Hvw9zP9hluidaICC0cat25YXA98dZ9gUnrx63nCHQBX6a6qInwoZ5GFev4OFMt X-Received: by 2002:a17:902:b589:: with SMTP id a9-v6mr1064638pls.140.1530690697478; Wed, 04 Jul 2018 00:51:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530690697; cv=none; d=google.com; s=arc-20160816; b=Rvdp8fEyOtsowYXGhT2rT6paRhY5pd/BdXKQ7z+YZf3Lf1JxzHwgPsuMbob58BdI0R 70JSPwez3ptA6dc27sEaJ8R8Iq8+ZtnWvZB4fnmgqnJNn27sU57Sg5149oK21GTEEmdB pDxA/9e7OHY+0JdPxyWlj2Jvjp1wKOsJR3Cs3+a6lMgDsjW2akXcvsVnLYpe4V8GpHnV 4MZa8qBV+QreEjQw7sm/SL7vfPJBfo7nnJVf1QIFb+8LZ69hGstElTB5VWuqieWjWsg4 7GEL1w+yJDQCJTdDg1s00A9tK764c1RgKA98ODJ0hWex0Q/qdGTXWSeACDKB7I0Eme+g mPmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=1WImzD11H6Gk60bK2v08yYBSiZjc5Td+wgiz/+WKy7g=; b=vfpuOJqdb0lnJBOSDVE/gBWNyCTwpOe1rRBNBLGwZiceWZFKmg4HBa8gixqQeO9RKV A4OC2qh35Mgg7dYEU+8mI1CvQhhtt3MsubYQMWZexX29WWb2SdNBDXaMp9TpeGKJhj5w Ngb57/qACegP6dB3JBxT85cL8BeMAZEbcWigQzz3VKdxoj+3GlEYWAZw8Ij1jMD62f1P qxalDl0r6/hg/JoBDjjTrG0cFsVsUSa/tfap+W7R8SYjN4vrnGkqTXPdE8607OczzWel +lCrftvjZ3BZXxhLVbeKb5o6nWuLgTKFYSS0KvJGWj7t6Y9c6/hxwnkuXKy0xDReZKUm WvJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dlXJ9IHm; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id e2-v6si2864241pgl.4.2018.07.04.00.51.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dlXJ9IHm; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 21481210D43BC; Wed, 4 Jul 2018 00:51:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 09598210C0F74 for ; Wed, 4 Jul 2018 00:51:36 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id z9-v6so2292834plo.1 for ; Wed, 04 Jul 2018 00:51:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=buApLzbytp/eU+y5SkiUgXplzV/QuA5DH7Tx2BdUVg4=; b=dlXJ9IHmfN0bZMFr+11g5HLUJlLmeKdDAD7W3wg9GbxMZnE0l+wvcKn9C1JWRtz57n QoNhJklY/i6ULLl8u4LZudQr52ccBhAuKiLanNB5giM1p0WzZNouXMhkqIKIx0LUnSnm TVTyPUMErDGu/wWHWCwT3d8Kd7iAs4cKvKkMQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=buApLzbytp/eU+y5SkiUgXplzV/QuA5DH7Tx2BdUVg4=; b=HvN32s/8671WyplK1nvY+xjqKuRnXQArTJZ90D26nQ4XbEI7+LMsa9hCpFvr6n3q2s +rjideNktT28SorHAdWJlRTb7qc3QWUP2SUsZWeOg1iDjwVMe0fxeoyzQIFJwHg0dfq2 xlV5gsaW7wyBGLdh+9SRiKNn2vmypXuFb56stCO7LDTdBRy4I3AxlMXmaaNkJkEE4/so /ihzKreG/XgaphIYbSaGcnYpNXQs4LvBJNX42bJGoDMTGpDJyxi4FkPLffqL7vUXdpgv 8TilDzqAULDnroktDN3DtpECoDKTcf0NexG20vLIZ0QsEyVuZ7LOPsXjkBL/8igARhWe IPSQ== X-Gm-Message-State: APt69E0WUsi/tSBbT0/G00DEYRS3Zepx4f4awSRYUBX5jVWZRGE2iWD1 PLXWfv2EEDFoAMExGL3YNyH5hg== X-Received: by 2002:a17:902:3f81:: with SMTP id a1-v6mr1043784pld.29.1530690695815; Wed, 04 Jul 2018 00:51:35 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:35 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:14 +0800 Message-Id: <20180704075117.7427-4-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The MemLimit is wrong when the Private->BusLimit equal 0xFF. This patch fix enumerating device plug in switch cart failed issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index e5f66eaa4a..3f894e8eec 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -666,7 +666,7 @@ void SetAtuConfig1RW ( ) { UINTN RbPciBase = Private->RbPciBar; - UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; + UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit, 0x1F, 0x07, 0xFFF); UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); From patchwork Wed Jul 4 07:51:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 141016 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp501771ljj; Wed, 4 Jul 2018 00:51:40 -0700 (PDT) X-Google-Smtp-Source: AAOMgpd+iJYRmOEgKYw2tmw44IxELSVOjv0F4fPBQGkEzxfi6ipGYVFmUpj5fVTAFXlYnwf3AvCF X-Received: by 2002:a62:9dcc:: with SMTP id a73-v6mr1014300pfk.249.1530690700689; Wed, 04 Jul 2018 00:51:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530690700; cv=none; d=google.com; s=arc-20160816; b=a4eDWJiw/+TGPvN1rSGAfJni+p/P0gatlRVe3O15Mz/qea0vCfd02X7CiZx/H+cr/2 AC0oaIUj3M+Od4SLLDOO6CHwRx0cImPA6NtY36Jm1ijzyGnWcMvtCAU1ctJh2njHTj+p X/LGgDaaN96b+WMl5FpUH6ir+PWlTNbcqwwyT40wZa9+jDdQGk4lL7+lxnhD8yHQdMIR KbOLcdOSLA5dnL9QsPQzy0oZ8hBQev25D4B7tUfIzu8aGnwUqhh5aK5G+LolpMzgVGz4 vkqlVoUfgwRoUuvltw6V1Hm0C5Cw1ili05l9v7+lXsFX/Oo2i7K/yCZrcIaTZt6iuKbt Ibqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=anecy8izmLdkWxcMLEsvYswgmLqoKK1yXtC29N5YLvU=; b=C59ggtNFh4WTaMZn4eqWva0yCIjxrIKkhEWCImSjPPllsVST2BiQPH1FK/EQKKzw/4 YPg6x3r8pmIOod08SaUhsHHUv3taaSZ2S72vV2M03fXx59vkRe/8eBJf+uHrPMg7f/s6 D5FW2Q0HlZMy2SLcmNJoEy4TLoM/eBVUHRLnfV91OBIYYODCgeoaHVU6up/wUKuWI7gz WgNiaoGyfVLW6WjjdBLi/Li/QRemCDgGlrTE2LKD9iCOMbn0VHPOkDHHUN2QZ8cMuQfJ kiQk5DA7d6mxvBim/ppSON4ZQVVevNTbgK0n6VSdcj3EUH+Gr3QC6tpYwvne8l5T2JWK hu4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=X11TnKQu; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id 2-v6si3037460ple.192.2018.07.04.00.51.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=X11TnKQu; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 510A1210D6CEC; Wed, 4 Jul 2018 00:51:40 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::243; helo=mail-pg0-x243.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 35C9B210C6688 for ; Wed, 4 Jul 2018 00:51:39 -0700 (PDT) Received: by mail-pg0-x243.google.com with SMTP id y5-v6so2155674pgv.1 for ; Wed, 04 Jul 2018 00:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0sRNz9lxXBn4Ds0xXco2Q9Ksha2Xik1Bw4rce6YWnMg=; b=X11TnKQupmt+xF+kSvdDuRJHgcmE4JK54b7sy6Wy0fsTFQt/oVq1hoW95QxTsqKXS8 7v7xDV0AOzGUi+M/Ch9V69yFUwEBMKLTtMbm/QFIS+oOY89Dc3ZnudDypoRY0RuHrv9i 2mbWgW1LpYjlh6HG+SSy1LaOha2n7ikGPWqGg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0sRNz9lxXBn4Ds0xXco2Q9Ksha2Xik1Bw4rce6YWnMg=; b=cNhjdZURc3JrLq2rFldK0dVtPg03Wp6rJ2Sc3t8LNas+4BXIwzASydC9ccIYva/PgE sbBbFqrpdLldSp1Xcd/88nOVwEhaqe6cHZPjnAGmw7dhZEOiuDJuNTAoqAteR+QRouVs C2IZoWYHdg8NRwfD/+u9pb3cg37NZ6qjci8FQwI/ZNzB2QJ48hrbT/fPi/3y/G8Q6OAS 5/hLnMNtcKMLR1+hUthEmZqBWq3pZJWx7dbfYB1DwLv2/0yYL0CSdMfkYpukRlQy3Y5Q UUZbm9154IAqmTnVtq1nZNVqy99l3dBaZ9VxxYeQixRvBcCH8P0iZht19pJ5Wbx5EuF7 vjug== X-Gm-Message-State: APt69E1rNMCwJVCfcccfFsz9XulCpiJbGTUlffIskXqINQBnqqUeCpgF 9QU9Pi31YgmO1I/8UccxpjHstg== X-Received: by 2002:a63:bf08:: with SMTP id v8-v6mr905419pgf.3.1530690698840; Wed, 04 Jul 2018 00:51:38 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:38 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:15 +0800 Message-Id: <20180704075117.7427-5-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 4/6] Hisilicon/D05: Add PlatformMiscDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Fix the issue of onboard Nic not work kerenl with AMD GPU and NVME SSD in board. The GPU don't support 64 MSI, so need to allocate INTx, but the default interrupt number 255 is invalid, so Change all the PCI Device interrupt number to 0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 ++++++++++++++++++++ Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++++++++++ 4 files changed, 148 insertions(+) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b6e1a9d98a..0e6d5912a0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -629,6 +629,7 @@ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf # # Memory test diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 4503776d63..61e8d907f9 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -354,6 +354,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c new file mode 100644 index 0000000000..8519b7139d --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c @@ -0,0 +1,99 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include + +VOID +SetIntLine ( + ) +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 INTLine; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Fun; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); + gBS->FreePool ((VOID *)HandleBuffer); + return; + } + + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + Status = gBS->HandleProtocol ( + HandleBuffer[HandleIndex], + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + continue; + } + + INTLine = 0; + (VOID)PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + PCI_INT_LINE_OFFSET, + 1, + &INTLine); + (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun); + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device, Fun)); + } + + gBS->FreePool ((VOID *)HandleBuffer); + return; +} + +EFI_STATUS +EFIAPI +PlatformMiscDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SetIntLine, + NULL, + &gEfiEventReadyToBootGuid, + &Event + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status)); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf new file mode 100644 index 0000000000..0b365e7a53 --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformMiscDxe + FILE_GUID = a48f7a09-253f-468b-87c6-caf78baf47bb + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformMiscDxeEntry + +[Sources.common] + PlatformMiscDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[Guids] + gEfiEventReadyToBootGuid + +[Protocols] + gEfiPciIoProtocolGuid + +[LibraryClasses] + BaseLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + +[Depex] + TRUE From patchwork Wed Jul 4 07:51:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 141017 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp501836ljj; Wed, 4 Jul 2018 00:51:44 -0700 (PDT) X-Google-Smtp-Source: AAOMgpejmVoF8hJRhXaZq2YhyBZfBtxhy6nzcqPl/Q5Pjrc+ayXK9gSLRbAJrszmNVvwJQyYhC1V X-Received: by 2002:a62:e106:: with SMTP id q6-v6mr1075142pfh.75.1530690704126; Wed, 04 Jul 2018 00:51:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530690704; cv=none; d=google.com; s=arc-20160816; b=yqRFqx89MiKisarwCWEYhav5a8e+zhTLg57+fMXQV8nhscWajXvwba+zutbYLeMx7x mbKvXDGho8MfaV3A9LlBi1CNRVa38VPxyKBXIt9ePmswgwd19cSfuagZoXL6O7B/Bh7j uAhoRc2JTFiQyP8LO2ez9vJe7OXJ3x8Z5avfHkFStR2PNWjaBzOdoxAMuuhLf6BT0SLW ADk4IUkOiPnWNNRGngF8bfDjqhGCE2HJHDHDTLoZ4R4AG2VBSAnyOSBqTxoP5WCt3O7P CyFB3bygheiMxAaOQrwjNPhNchF5wiqRophyvm9VP3TnKGgU0fWfivRwKuK6DGl7CHKx jHew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=X4NWRTzCoKf5gHorEzHWWkUeZgjQpfnMOLoX9sccH+M=; b=j28EvWxTbAdgaj6Rdy0MNXHLoMorniRgVxKWA8JicbqHZQ6hCLpJ5WZNviYcDS2PXD qLwljjhw8oKu5xmjRf+lqQttKgkE64F+bqedcX9eee8fPboJ8/uAANq0r+1Poye2aYHA ibadDaPB9V0zlygR0XyR+lZRWahNvKkPCTW4qhefEEzwZLTk4DyhyVV7aKyK0gqm9TQV FrNzbV79iZ8VgJIWKWQRAiOCFmDusiK+oCvYyvUhpXpH1EdvinyGR2Kg7TK0yDte38uf yEaD3MBL8XCTeejbPl1nV7wEGbAJPpxWbdQRFrovzKMUwsUQQ1SdrUuXAHu+scCVZkGd IhNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LCwwortI; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id w12-v6si2648035pgr.428.2018.07.04.00.51.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LCwwortI; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7F8E0210D93BC; Wed, 4 Jul 2018 00:51:43 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 51739210D8514 for ; Wed, 4 Jul 2018 00:51:42 -0700 (PDT) Received: by mail-pf0-x244.google.com with SMTP id a11-v6so2265444pff.8 for ; Wed, 04 Jul 2018 00:51:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A+M5+sAEB/cNqK92kBnSQlZCLUxo1R5kCvkAL13vgDY=; b=LCwwortIoepSJqK/uqM+34GgCphx4m+M67t6YHYaslMhvmEllwS5W2LdniuzO79kux vTLQh2a+VTUGgY8MSAQhYkBZiH/915Rv5mIIbpFDaiD9CvUMFC8yeo4poEX89ys/1ujz THHv03HWdRqNpu7xOFAdiZtuWaE3EKvIPNu3s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A+M5+sAEB/cNqK92kBnSQlZCLUxo1R5kCvkAL13vgDY=; b=bPSgPSiT8qcwcsz0XUEK/AwPmMMVZrIXkF6iOb90vGdlT710XXOufootVHQGQlxKsc lCFdabwy9pt5eHYV1HxGab0fNnV8Y5iK0DXOA0dhkq8Yd8jn/YKLmzc3dXR9Vc/0wrt1 F2F6dMcyOU6dWqfjxruxx8Inh4H81utMCTZXCUKVrVec106F4yew0jiOLqpZR/GBEfNO 8zy2xsCQFPth1oVC4pfPRuyuCiUjOTZd094HCQrNDH/f1JO43r7BvR7tMy28C/Zb+ZCu cVHryKJilV1ZbkiiprbiPL6raxrmrTp9VKKwqaqDHxtNPuw8BmYnoyFB50j6J8iilntq 5UVw== X-Gm-Message-State: APt69E0/hcEkqn7BlZ/J6X99+lCA/fOcfk21wnWzz32xxAak9I0zG6sj i5ywNpXju52EN2//IMc3QQICYg== X-Received: by 2002:a65:62cd:: with SMTP id m13-v6mr929211pgv.280.1530690701845; Wed, 04 Jul 2018 00:51:41 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:41 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:16 +0800 Message-Id: <20180704075117.7427-6-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 5/6] Hisilicon/D05/Pcie: optimize two pcie ports space X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Optimize pcie space for promoting usage rate.Change regions order of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion can satisfy the requirement of larger address alignment. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 12 ++++---- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 8 ++--- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 ++++++++++---------- 5 files changed, 34 insertions(+), 34 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 0e6d5912a0..ab7c5caf86 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -305,13 +305,13 @@ gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 @@ -336,10 +336,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 @@ -353,10 +353,10 @@ gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000 - gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000 + gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000 gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000 gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000 - gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000 + gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000 gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000 diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index 57283a1053..ed6c4ac321 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 2 */ { PCI_HB0RB2_ECAM_BASE, - 0x80, //BusBase - 0x87, //BusLimit + 0xF8, //BusBase + 0xFF, //BusLimit PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB2_IO_BASE), //IOBase @@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 5 */ { PCI_HB0RB5_ECAM_BASE,//ecam - 0x0, //BusBase - 0x7, //BusLimit + 0x78, //BusBase + 0x7F, //BusLimit PCI_HB0RB5_CPUMEMREGIONBASE, //Membase PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit (PCI_HB0RB5_IO_BASE), //IoBase diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 50ccac1b06..9955f6dbeb 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -412,9 +412,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 -[0004] Input base : 00008000 +[0004] Input base : 0000f800 [0004] ID Count : 00000800 -[0004] Output Base : 00008000 +[0004] Output Base : 0000f800 [0004] Output Reference : 00000064 [0004] Flags (decoded below) : 00000000 Single Mapping : 0 @@ -469,9 +469,9 @@ [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 -[0004] Input base : 00000000 +[0004] Input base : 00007800 [0004] ID Count : 00000800 -[0004] Output Base : 00000000 +[0004] Output Base : 00007800 [0004] Output Reference : 0000007c [0004] Flags (decoded below) : 00000000 Single Mapping : 0 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index b47cfec7bd..64807b1714 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0xa0000000, //Base Address 0x2, //Segment Group Number - 0x80, //Start Bus Number - 0x87, //End Bus Number + 0xF8, //Start Bus Number + 0xFF, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe0 @@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { 0x8b0000000, //Base Address 0x5, //Segment Group Number - 0x0, //Start Bus Number - 0x7, //End Bus Number + 0x78, //Start Bus Number + 0x7F, //End Bus Number 0x00000000, //Reserved }, //1p NB PCIe2 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 122e4f072c..3f09e5e568 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -89,15 +89,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex - Name(_BBN, 0x80) // Base Bus Number + Name(_BBN, 0xF8) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x80, // AddressMinimum - Minimum Bus Number - 0x87, // AddressMaximum - Maximum Bus Number + 0xF8, // AddressMinimum - Minimum Bus Number + 0xFF, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -109,8 +109,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xa8800000, // Min Base Address - 0xaffeffff, // Max Base Address + 0xa8000000, // Min Base Address + 0xaf7effff, // Max Base Address 0x0, // Translate 0x77f0000 // Length ) @@ -123,7 +123,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0xafff0000, // Translate + 0xaf7f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -165,7 +165,7 @@ Scope(_SB) { Name (_HID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff] }) Method (_STA, 0x0, NotSerialized) { @@ -280,15 +280,15 @@ Scope(_SB) Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 5) // Segment of this Root complex - Name(_BBN, 0x0) // Base Bus Number + Name(_BBN, 0x78) // Base Bus Number Name(_CCA, 1) Method (_CRS, 0, Serialized) { // Root complex resources Name (RBUF, ResourceTemplate () { WordBusNumber ( // Bus numbers assigned to this root ResourceProducer, MinFixed, MaxFixed, PosDecode, 0, // AddressGranularity - 0x0, // AddressMinimum - Minimum Bus Number - 0x7, // AddressMaximum - Maximum Bus Number + 0x78, // AddressMinimum - Minimum Bus Number + 0x7f, // AddressMaximum - Maximum Bus Number 0, // AddressTranslation - Set to 0 0x8 // RangeLength - Number of Busses ) @@ -300,8 +300,8 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0xb0800000, // Min Base Address - 0xb7feffff, // Max Base Address + 0xb0000000, // Min Base Address + 0xb77effff, // Max Base Address 0x800000000, // Translate 0x77f0000 // Length ) @@ -314,7 +314,7 @@ Scope(_SB) 0x0, // Granularity 0x0, // Min Base Address 0xffff, // Max Base Address - 0x8b7ff0000, // Translate + 0x8b77f0000, // Translate 0x10000 // Length ) }) // Name(RBUF) @@ -593,7 +593,7 @@ Scope(_SB) 0x0, // Translate 0x800000 // Length ) - QwordMemory ( //ECAM space for [bus 0-7] + QwordMemory ( //ECAM space for [bus 78-7f] ResourceConsumer, PosDecode, MinFixed, @@ -601,8 +601,8 @@ Scope(_SB) NonCacheable, ReadWrite, 0x0, // Granularity - 0x8b0000000, // Min Base Address - 0x8b07fffff, // Max Base Address + 0x8b7800000, // Min Base Address + 0x8b7ffffff, // Max Base Address 0x0, // Translate 0x800000 // Length ) From patchwork Wed Jul 4 07:51:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Huang X-Patchwork-Id: 141018 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp501878ljj; Wed, 4 Jul 2018 00:51:47 -0700 (PDT) X-Google-Smtp-Source: AAOMgpc5LWJQhFqsy6QKbUOuEljzYBGSaYYA5/AaMiaxnbr5iPPDnsh20wGVSlbM9aCxt8sGOOV6 X-Received: by 2002:a62:9bc5:: with SMTP id e66-v6mr1073836pfk.84.1530690707490; Wed, 04 Jul 2018 00:51:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530690707; cv=none; d=google.com; s=arc-20160816; b=PsmyRQQ59XoLlbfYEXYJEyfCflEhUM3cunm/Wc+Sh5rqxUow1gzj15n8AQWE+pUfR7 FTWMqflFEA5p2UlbClQshwrX2KFHLBWw4zDbac5xUfiAexFC3DOzHrj0KZwqzyZ0SdAY lDsqY3t1uwkidvGwGk/Pr0+RfSWzLQnN2uAzJFrD+ChQ5ylRanpSnDznJg1wYUX9pwgL N4U17x5FHr9yi6FEOeTZUAGVmX1udRcZ6ju5FkNCcbeAndZpe3+fNBHi3QTiBJ88eICU b2vcwv0clT5BwYcPpbW/Yw/xrzGECSpSKTYb5K4Y3JtRqPCEwrG96OJ+FwFNWSuH178e M+fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=FGeLksboXOCjYBzn2ojOL7D5kDRbzXSQWr+BpVxHRA8=; b=k0lx8fW32yyPSrV3ALqDHZSkhRfHGSlkAswcJWTLkWyhrowz1QDvNZzv7EPTa/eTvh ZXOGR6JCWmRDkxVmvcH/B+UDW8a48uBcws+nu2aJV1H7lDisaz/Tjb9cpSmMLBvgDFkc TUBN7MjKtcltxvwRtSYe5dais4i9l58/Dcy2aSR6BDM9UdFG3A1F59WRgzXrTkBhywTQ /1fKW43dHYSEsjtyuCn3r8gBVFjh3gbksuaE15hGMQKEakCaQyirPC6fCIYrjNhPZdLc 6bVn9HO8MiZ/Ea2qhPdt9AoS2CsWKdptc23wvYYLZ/yM3eXFHe2G1be1rk1vJD7/ZKeR lJmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JydfNG8B; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id n59-v6si2893960plb.198.2018.07.04.00.51.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 00:51:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JydfNG8B; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id ABECF210D93B7; Wed, 4 Jul 2018 00:51:45 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07403210C0F74 for ; Wed, 4 Jul 2018 00:51:45 -0700 (PDT) Received: by mail-pf0-x244.google.com with SMTP id j17-v6so2272699pfn.5 for ; Wed, 04 Jul 2018 00:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xWLk29EGw3s9NQWq/MONaz7B4FkrWLi4cB3eyEnsuv8=; b=JydfNG8Bcr4r/y5A6JYof5J6x1tq2r76ct85iyR3xMf4oiQy17QTtE3e8XZQGNJAOC cUU0NMaWZjftc0uRQkcS1LbpaDIMM4t7Yv6x7zhew8C14i6vA0Oeg1ALIni7xMhzmZ1q qJpRPNy9PLE/i/wCb+0vwwWGIUhDWyg2Xc748= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xWLk29EGw3s9NQWq/MONaz7B4FkrWLi4cB3eyEnsuv8=; b=jjZbCuKTHgwyhtjWY7Rmne9YsD9Hy5Od1QOzSPacRkTFUNqT6ojQ4uV3Q6gzwSA3Rp jw2JtTUYT7Q0SM2Z36YKutR8Wk99bVu2TRqfsCRpOR0c5orGCiHMhSAhKL8MM5n91Jdn ecdIc6038DaAV8lda7JUxYEB9jsbSqoXhLP9QwXGEUgEbBU2i5NPjiGJt+RIBXZBuf+B 1iVixjkgwC77A6NiK0zkDS8Lm9f8dL9zWiwQkg23NtOA9f1fGsZnHQywqA6ByUaynNG3 n+3s8bwcdwXLYhFVo6NDGTcr2wVNAwPo7PmoyBHZ1KAKlIl2IbVr5RDJrIP+q0mJDxlW FNAQ== X-Gm-Message-State: APt69E0huHeo3iLtbTgTtD7ID0hZQmjAroD8H23M6GtGi9ca7AYRGc/Q 7BFc95Fa82aTWfuTACGbKFFFow== X-Received: by 2002:a63:2d45:: with SMTP id t66-v6mr889120pgt.381.1530690704788; Wed, 04 Jul 2018 00:51:44 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id d9-v6sm4803219pge.68.2018.07.04.00.51.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Jul 2018 00:51:44 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 4 Jul 2018 15:51:17 +0800 Message-Id: <20180704075117.7427-7-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180704075117.7427-1-ming.huang@linaro.org> References: <20180704075117.7427-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 6/6] Hisilicon/D0x: Correct smbios product name X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The product name getting from BMC is not suitable. It may cause ambiguity. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c | 1 - 1 file changed, 1 deletion(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c index fcefe2442c..5e965c996c 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c +++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c @@ -86,7 +86,6 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer) TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION); HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL); } - UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME), ProductNameType01); UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumType01); UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER), SystemManufacturerType01);