From patchwork Thu May 20 19:13:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 444855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42D31C433B4 for ; Thu, 20 May 2021 19:14:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A66461363 for ; Thu, 20 May 2021 19:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237504AbhETTPz (ORCPT ); Thu, 20 May 2021 15:15:55 -0400 Received: from smtp-34-i2.italiaonline.it ([213.209.12.34]:33395 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235907AbhETTPs (ORCPT ); Thu, 20 May 2021 15:15:48 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jo6clK7DY5WrZjo6llTD7d; Thu, 20 May 2021 21:13:26 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621538006; bh=hqdToKdXep6rD2t3+5/OUkGokVRGwUGIXwri9qp4guU=; h=From; b=hUnDQhl5+FF2LtbPN7uCikaowH+8P7C86snzpG/1Tf+vWsTDBsuRKVHvoQ2aOYMES 4Z2S0V67pN6sKF/K5z916FF6y0aBSe8EvnqEhhi0j9g+2O5OiKIX1uKE4HbtXzc+cK NxX+/xlDORmR+cmI53zMRmFPCI5rVxUnpVuBfX/t6sF4R2MVWnKB7oE2UDieaWjDXf wZRaBhSwoiB2n9Q+b2Pc4UKO0d9qWODS68PSXin9PE8ShklA3jzdQ5AJ0WEtkj710S ehZHG6D6SzfL/nIm+k1QrJ47oMsmFO+IL3fatKy1N87f6jz/BWHyWkqOEvp5zRmZms Sf9ll4JMJYslQ== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6b4d6 cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=VwQbUJbxAAAA:8 a=IXkOJODCewQtKEFu2i4A:9 a=5yUOnwQy5QICz8m5uxDm:22 a=AjGcO6oz07-iQ99wixmX:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Lee Jones , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tero Kristo , Michael Turquette , Stephen Boyd , Dario Binacchi , Tony Lindgren , Rob Herring , devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v6 2/5] dt-bindings: ti: dpll: add spread spectrum support Date: Thu, 20 May 2021 21:13:02 +0200 Message-Id: <20210520191306.21711-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520191306.21711-1-dariobin@libero.it> References: <20210520191306.21711-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfAzkv4+WDkc+LoumzzdwPTDPiSFA5uUBkTMVOM508MuLoM3Q2faBmN1k+QAdcgNX5NOGEVjg9tBcmIYTRSroXmcdEK7zPo/tefGJnvExs3j74OUKiFJh Ut89JdsOoowGPe2maxf5Uj3uJjyJwyRh5NdjcfhWRTt6dYJAz9AnIhD1sfLvyvaOsGY5JcGbM4vVhg28za2vyC4a6AteHt7IYNp0mZefo+YyPWXvwIdYVAiF v0E+QoC/uRqbuHNXQkJh0ni8ab/04nzQHC74xiUH3QBpoJp/ckvQusGqkSMoTYGWXzvItNGSNXoDyl1oijHoTbBCV5eqB8eDjSRsMhJf6/ZGgjrP7WyM8qHq 7twrMKZU+Sn58oKkxsJVLNuqHg1amTwwFPkSHr//5XtLON4HnkxP8+VAhUCpzewqhwT3gat0QwDSxitp0TiS7cF+tEGMV8rGSh9r0V2YGEk8GM2Gu65a45zT dKkKSrWuLrQTEnBhTM5p9b/6W+7LkZf83wc6TUhzGAyq4+ZZMoqNPB7D1dvP4QD5yndEDvN/NRv5HyEc9jiyVhyVBTwzx4opwITSi/4BOEh1Lg+xzhxlcmfy 1fo= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org DT bindings for enabling and adjusting spread spectrum clocking have been added. Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring --- (no changes since v4) Changes in v4: - Add Rob Herring review tag. Changes in v3: - Add '-hz' suffix to "ti,ssc-modfreq" binding. .../devicetree/bindings/clock/ti/dpll.txt | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt index df57009ff8e7..37a7cb6ad07d 100644 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt @@ -42,6 +42,11 @@ Required properties: "idlest" - contains the idle status register base address "mult-div1" - contains the multiplier / divider register base address "autoidle" - contains the autoidle register base address (optional) + "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains + the frequency spreading register base address (optional) + "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains + the modulation frequency register base address + (optional) ti,am3-* dpll types do not have autoidle register ti,omap2-* dpll type does not support idlest / autoidle registers @@ -51,6 +56,14 @@ Optional properties: - ti,low-power-stop : DPLL supports low power stop mode, gating output - ti,low-power-bypass : DPLL output matches rate of parent bypass clock - ti,lock : DPLL locks in programmed rate + - ti,min-div : the minimum divisor to start from to round the DPLL + target rate + - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency + spreading in permille (10th of a percent) + - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread + spectrum modulation frequency + - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean + to enable the downspread feature Examples: dpll_core_ck: dpll_core_ck@44e00490 { @@ -83,3 +96,10 @@ Examples: clocks = <&sys_ck>, <&sys_ck>; reg = <0x0500>, <0x0540>; }; + + dpll_disp_ck: dpll_disp_ck { + #clock-cells = <0>; + compatible = "ti,am3-dpll-no-gate-clock"; + clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; + }; From patchwork Thu May 20 19:13:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 443450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBE1DC433ED for ; Thu, 20 May 2021 19:14:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A0D62613B9 for ; Thu, 20 May 2021 19:14:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237315AbhETTP4 (ORCPT ); Thu, 20 May 2021 15:15:56 -0400 Received: from smtp-34-i2.italiaonline.it ([213.209.12.34]:38405 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237285AbhETTPv (ORCPT ); Thu, 20 May 2021 15:15:51 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jo6clK7DY5WrZjo6olTD8k; Thu, 20 May 2021 21:13:27 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621538007; bh=3Paw2xB98b+SDuV2alDurkaGEspLbA4rwbMXsFizNMM=; h=From; b=G2iS9HJO6Ysq4n5NwXUz0P0CG3jT+RshkULeAq+fxD31UfE/cFFy80I46QyrXuDGg 605NZzMxDkDHrT31BU36vhTg67GNpuKTohnXLyWmUnnZUXom7mmtPDwFbeXptCZiwi HrnC7xvzTcIDMKZ4QVaHJj0/zZe+Hox1QvwOitvHpKtB9MIKDhqodRyq1OscRWYNuJ ZcDgcQJdRDregvi9wZU3HXv5G+lbbO99pdUgfQmp7TThpuUppfvQSF6yBYlBa4CG5h 37ZPzgIrYJHnKaxBzvDTiA/8ciyID7NRuf8jLkrYlTh3QD83/W2xoJ8oIwwLOHc8u3 Wn5hHicbn0leg== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6b4d7 cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=2KMo9-giAAAA:8 a=4mKMOZvguhLedlVR2KsA:9 a=2pGyGSWy5nf2n_rBi4rp:22 a=UeCTMeHK7YUBiLmz_SX7:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Lee Jones , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tero Kristo , Michael Turquette , Stephen Boyd , Dario Binacchi , Tony Lindgren , Rob Herring , devicetree@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v6 3/5] ARM: dts: am33xx-clocks: add spread spectrum support Date: Thu, 20 May 2021 21:13:03 +0200 Message-Id: <20210520191306.21711-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520191306.21711-1-dariobin@libero.it> References: <20210520191306.21711-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfCKKQ3/eQ89KdiBEt5W6BtCqUtO4ajIEXh1sso9w5esB447P6nUuZkK/dzWp3Yq1LqBYvx+cONwhGMQPUw4Xk6sKcifXuDGkZqu1T39bHEwOZ/5W0tkW om7buNCEeeVqYKYs7ooGDV/L4Gw0CP+rBQH1guOAFp6OuD1YQIPsHDwHhMDXoEdzASdJNztx7kXGSaKlinhTbSTcgLyNA+FsfdUqLzpHDzSfJqOxOZg3mBjc 6jTVejzK/nHoqPV8MXY/Gwi1pMpXta/DXIbzcxoIldivpx8Mv0Wjt8LF1qAl13BHBA7D0TEpB6rYPOyqz2K5EQEDbAFLAh/kTZdU76RDsXFtHjNu1a68kdWR HfNuz8NfMDyrLwpTeNmGj8yEQcEJkpqkaYHmr2xuTyTSh4av8UcFhEc0x48vG3j5tHKFX06LfzH9/5SIUmp4oQzu2XRHOvXk+hIGBrUnwGUJ2eupMdsjJNQo BoyMe9pbHh42V5Rf/OSgOQjdp8mbN6ig513RB1nAQfmah3XS6SIsJqO1W3NFkJ53nw2XC0Dhkqenzd9HygB3R4qUcH/03E3i5BaktsYFCewDfVTHj9ptWNeK 2QU= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruh73x RM, SSC is supported only for LCD and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP). Signed-off-by: Dario Binacchi Acked-by: Tony Lindgren --- (no changes since v4) Changes in v4: - Add SSC registers for CORE, DDR and PER PLLs. - Update commit message. Changes in v3: - Add Tony Lindgren acked tag. Changes in v2: - Remove SSC registers from dpll_core_ck@490 node (SSC is not supported) - Add SSC registers to dpll_mpu_ck@488 node. arch/arm/boot/dts/am33xx-clocks.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index dced92a8970e..b7b7106f2dee 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -164,7 +164,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; + reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { @@ -220,7 +220,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; + reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { @@ -244,7 +244,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { @@ -261,7 +261,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; + reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; dpll_per_m2_ck: dpll_per_m2_ck@4ac { From patchwork Thu May 20 19:13:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 443451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCFD1C43460 for ; Thu, 20 May 2021 19:13:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C41E9613B9 for ; Thu, 20 May 2021 19:13:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236935AbhETTOx (ORCPT ); Thu, 20 May 2021 15:14:53 -0400 Received: from smtp-34.italiaonline.it ([213.209.10.34]:36588 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236841AbhETTOw (ORCPT ); Thu, 20 May 2021 15:14:52 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jo6clK7DY5WrZjo6plTD8z; Thu, 20 May 2021 21:13:30 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621538010; bh=PPTo8GvjIIsaEKU5B1TIF8N7cm5fuyUf7SEXiLKXv5E=; h=From; b=NCeFT0a0nEAKInyX/QskClahvicdc/d9j3ukQ15BUUFr/Yg/rsU4jQM3lCdBe1gG4 79OtmjsmuVOkHjVKtpOIgKU8JZ1SPQrwMPfG/UDNCPcHr+eN9rpSe6kCg34vX0qoMl XKCsRNDvWGxYItyWasGTZQ4RAWumDa+dc1wM/aNAbGcTnm4Bame10ApTWtrDDZekEc LH2LMusz8PsVTSmLzs54HRThz+aXYsg0ORLEZ6tzTIz9bOOS9cKAq2CRMQ8UUL7G2e fBv/4uAIFNt8Wb3hobmUf+Y72Nc3uTiTVjj2bWkDChiuoTe/jXRSlLwFxYi9w8RYkN tQru74qiB/Kug== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6b4da cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=2OX5x-OEy5pyK2UBO5QA:9 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Lee Jones , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tero Kristo , Michael Turquette , Stephen Boyd , Dario Binacchi , Tony Lindgren , Rob Herring , devicetree@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v6 4/5] ARM: dts: am43xx-clocks: add spread spectrum support Date: Thu, 20 May 2021 21:13:04 +0200 Message-Id: <20210520191306.21711-5-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520191306.21711-1-dariobin@libero.it> References: <20210520191306.21711-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfKFqPfFrm9NguM98g1PGePGjdLAxOgmqBsKdOo6VzMURxaUNiApycFskdgIi/4Y2BJ+RHGvjJZB+UQ0XHjY6hv124Cx++UIh4AMaWVb6odeJysE+Alzt lVfVcDuUugjHeNo83ptAt2VbT84lesy3N0AIqawi34ezcteXgeYk2jEdY56G/WLk7QNC4fEZcQ2DeXdmimzlfAWF5GXKseD5EmoyjLiI6jdhlUZqNgFZDUe6 BgV/hNSspke2GALjWhyl1G0Qogj/c0UIMhKERPD6BWHjyoRcX0xzYQVAjqOGxUWOvPj4p+/MgmEu899VTDXAKYUrKZWpNqBc/ns1Sg56kbj58jpHx1aFA6oE UBuT6A4NbMTRQcysUiSfoC3Em26/4o+6OZ9rQneBDdc2yZJzZh4h1YZ2O+dBaXWEyvFU/8KZKnsLkpKhobGmlkXWlmWtbi08T/SCAbdShbk2NELxLf6PX5Zk bKOvC3AGwEOnu7A0w9p1S4fJ1SR61axM2aiRK+SN8ZUP0pQewg11CcRoDRaYRcRjdX2DI/RH92NCCzKnxBoMYLvQHoeMkLfMqM4XGSetnFsvNAleYoXt+ORA TFM= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruhl7x RM, SSC is supported only for LCD and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP, EXTDEV). Signed-off-by: Dario Binacchi Acked-by: Tony Lindgren --- (no changes since v1) arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index c726cd8dbdf1..314fc5975acb 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -250,7 +250,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { @@ -276,7 +276,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; + reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { @@ -294,7 +294,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { @@ -313,7 +313,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; + reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; dpll_per_m2_ck: dpll_per_m2_ck@2df0 { @@ -557,7 +557,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {