From patchwork Thu May 20 20:27:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 443575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C415EC433B4 for ; Thu, 20 May 2021 20:27:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A2F5360FE3 for ; Thu, 20 May 2021 20:27:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235990AbhETU3R (ORCPT ); Thu, 20 May 2021 16:29:17 -0400 Received: from smtp-34.italiaonline.it ([213.209.10.34]:55772 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S238545AbhETU3Q (ORCPT ); Thu, 20 May 2021 16:29:16 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jpGWlKVEa5WrZjpGqlTUNb; Thu, 20 May 2021 22:27:52 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621542472; bh=o/VOXlmBh1ZPZnnDv+64KXqpTUEGPerJE1a/PoV9LoU=; h=From; b=h+mYj61r2xOt1YhNmBxJpHL+MEu5uTWM9JEshHiHXHgKd2RJCbGXEVHZTgBjZKLJx MrRhmRkF0LQNxRNxY0mLgv1YJWqE1hniHZYFqeNY8pPx7SKJXtAwM+966MCwLj1xPx DObtLPpYi/ct5fcL4DtBdvKi3DznMOLJNTKnlsvH1VRP3dfp6ck8ugE13ZXaunllTh +6tyk6UPIzNeLBSUmFAnizce9J94YRznIbC3vjm/Dt9HgoA3fvZS/LvFvYTXP9jEdH 83xoHKJhoK1Ndmfar3IBiDWffx4yKLXrNBYijq7Ue2CoVxHZHtjcpyUafO6P2O3Gtt RJle74aI88PRQ== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6c648 cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=SMixqbvZskzAqJ1qg7QA:9 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Tony Lindgren , Drew Fustini , Linus Walleij , Andy Shevchenko , Jonathan Corbet , linux-doc@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v3 1/3] docs/pinctrl: update `pins' description under debugfs Date: Thu, 20 May 2021 22:27:28 +0200 Message-Id: <20210520202730.4444-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520202730.4444-1-dariobin@libero.it> References: <20210520202730.4444-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfC4IQyqC8yCTSZda7J5PnkJEZPbrYTBhBMpEICGiISDhj3SIApr58H3eUSX81XdpOeXFDgL4V8j6laxA6ZXoeDcOKIUSg9cKw9BjupDw/smTuSgUSlBr souIJhr6BvMOTnSpF4hwcJZS2Wqo/yklxTVGnC3TB8HlcSbXC3rsDCkzKfsgd1p6638feX3hC6nWXWDZcvgmMmXO3wW/tFtS6uaEKFqgATGlgZOQ+hSrwAFe Et0byIGpu8McQQG78e6hnTxI1qp0Hg5AJyXexs7/jTHJityWfH/4UoeKEZstSCnwPQViTVNeGaHRmyeyanWUEgGxPVIsL+OXs7edxmOzRXv6HYa85nOVaQeK bGX30ln9MURWLXnNh4dLXP7lZkgCY/DjJkMTBi5F6HuPhDWw7XKwz5i57vxVJ7KS0zSz3ZdI34sAT0LyKluvUvBb1Q0ldjgiY7+QdDLqmhghcrhdhytYHtq4 /Hf8Cn07xvWV+J06QPnjBubUpIFRw2ZizMnkwg== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Optionally the `pins' file created inside the `/sys/kernel/debug/pinctrl' subdirectory of each pin controller device now allows you to set the mux register of a pin. Signed-off-by: Dario Binacchi --- (no changes since v1) Documentation/driver-api/pin-control.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index e2474425fb0c..3d8192fa45a3 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -1447,6 +1447,9 @@ controller device containing these files: - ``pins``: prints a line for each pin registered on the pin controller. The pinctrl driver may add additional information such as register contents. + Optionally writes the mux register for the selected pin. + e.g. to write the value 0x73 in the mux register of pin 19: + echo 19 0x73 >/sys/kernel/debug/pinctrl/pins - ``gpio-ranges``: print ranges that map gpio lines to pins on the controller From patchwork Thu May 20 20:27:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 443574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33923C433B4 for ; Thu, 20 May 2021 20:28:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C714613AF for ; Thu, 20 May 2021 20:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237029AbhETUaQ (ORCPT ); Thu, 20 May 2021 16:30:16 -0400 Received: from smtp-34.italiaonline.it ([213.209.10.34]:42121 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236249AbhETUaP (ORCPT ); Thu, 20 May 2021 16:30:15 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jpGWlKVEa5WrZjpGqlTUNp; Thu, 20 May 2021 22:27:53 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621542473; bh=Z3x++lNl1KUyMjHgJXYz6ViHhU+nTnNfaQmFUS1eWNs=; h=From; b=wOvc1XmJnM+BC4bu8KsxcvKqRExh4/8BlbUWDbsHNJmYoZdNLFuD7zIcO4+Id+9pW qf0Tb5vF0THakHnduzVs53hZWgDUgjfBrkG4gb5UpvRAfmXaokxL950PZ/Pm+gBH0n EjVsLpHQ+OtgXdx/RW9+btqoxq18UzMEPMiXDDcWIvyax7FFuBlMhMTk4qWEla2Fdz qdiZsSRaR7n4PVdi3ujbHm826Wkgl8/IH0xNSHxjWUK38lUqlUI4IeERQ+h6/vAPqp /4duDt5dRkhn1qQqF3r0DptmuIfHEStm8DKd7O1+KJxw1+99L7sVyTK1RMcSvM3dEk 7AiG6cK4dzMYA== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6c649 cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=LmjiRsjZlzoeE_K0hIMA:9 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Tony Lindgren , Drew Fustini , Linus Walleij , Andy Shevchenko , linux-gpio@vger.kernel.org Subject: [PATCH v3 2/3] pinctrl: core: configure pinmux from pins debug file Date: Thu, 20 May 2021 22:27:29 +0200 Message-Id: <20210520202730.4444-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520202730.4444-1-dariobin@libero.it> References: <20210520202730.4444-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfIUmEvQVxqvsNff7Mc8QYZVUGolb2h3/P3PFxHG5VygqL5T5I2Ja4Gf6GxfDvt86ebJJBjztbv5sXiNyvfP+xIQSoF/FbWpQM26jzirtbxbau2MWod9W UOEccBj3hn6Gx6MDH7rRmXfpc6BzHDXVB1cP6HMk7lJoBw135Ob69lr3RVd8sCzO6y5F2aMHk8sBKDDFiBvbOKwcsoWzvoXFI+c1ZKn6Sc+PyYo4T0LnpzUY cLoOb0YebtPSw+pYyEx1J4UKXZe3khwc8w0q7i7lk576L7/O6PENlxVRWSeBVeT2pZGDr61EfQII2SciVc91tN7G4vNgyztif9O2P5yG0qZJYGtJmJhjBnTa x7osxmPoVmrpzm/waqAfYe6IifhG0IzEnh+MG8e303s+X7IQx3Hit/Y2GAnZAbui5RKCC5pKDAPJ/CxzAbHrrhd8vFzXbg== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The MPUs of some architectures (e.g AM335x) must be in privileged operating mode to write on the pinmux registers. In such cases, where writes will not work from user space, now it can be done from the pins debug file if the platform driver exports the pin_dbg_set() helper among the registered operations. Signed-off-by: Dario Binacchi --- Changes in v3: - Use strncpy_from_user() instead of copy_from_user(). - Do not shadow the error code returned by kstrtouint(). - Change pin_dbg_set() interface (char *buf --> unsigned int val). - Describe pin_dbg_set(). drivers/pinctrl/core.c | 63 +++++++++++++++++++++++++++++++-- include/linux/pinctrl/pinctrl.h | 4 +++ 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index a4ac87c8b4f8..ab832044a0c3 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1620,6 +1620,53 @@ EXPORT_SYMBOL_GPL(pinctrl_pm_select_idle_state); #ifdef CONFIG_DEBUG_FS +static ssize_t pinctrl_pins_write(struct file *file, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct seq_file *s = file->private_data; + struct pinctrl_dev *pctldev = s->private; + const struct pinctrl_ops *ops = pctldev->desc->pctlops; + char buf[32]; + char *c = &buf[0]; + char *token; + int ret; + unsigned int i, pin, val; + + if (!ops->pin_dbg_set) + return -EFAULT; + + ret = strncpy_from_user(buf, user_buf, sizeof(buf)); + if (ret == 0 || ret == sizeof(buf)) + ret = -ERANGE; + + if (ret < 0) + return ret; + + token = strsep(&c, " "); + ret = kstrtouint(token, 0, &pin); + if (ret) + return ret; + + token = strsep(&c, " "); + ret = kstrtouint(token, 0, &val); + if (ret) + return ret; + + for (i = 0; i < pctldev->desc->npins; i++) { + if (pin != pctldev->desc->pins[i].number) + continue; + + ret = ops->pin_dbg_set(pctldev, pin, val); + if (ret) + return ret; + + return count; + } + + return -EINVAL; +} + static int pinctrl_pins_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; @@ -1677,7 +1724,11 @@ static int pinctrl_pins_show(struct seq_file *s, void *what) return 0; } -DEFINE_SHOW_ATTRIBUTE(pinctrl_pins); + +static int pinctrl_pins_open(struct inode *inode, struct file *file) +{ + return single_open(file, pinctrl_pins_show, inode->i_private); +} static int pinctrl_groups_show(struct seq_file *s, void *what) { @@ -1886,6 +1937,14 @@ static int pinctrl_show(struct seq_file *s, void *what) } DEFINE_SHOW_ATTRIBUTE(pinctrl); +static const struct file_operations pinctrl_pins_fops = { + .open = pinctrl_pins_open, + .read = seq_read, + .write = pinctrl_pins_write, + .llseek = seq_lseek, + .release = single_release, +}; + static struct dentry *debugfs_root; static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) @@ -1915,7 +1974,7 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) dev_name(pctldev->dev)); return; } - debugfs_create_file("pins", 0444, + debugfs_create_file("pins", 0644, device_root, pctldev, &pinctrl_pins_fops); debugfs_create_file("pingroups", 0444, device_root, pctldev, &pinctrl_groups_fops); diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 70b45d28e7a9..7ae8aca3dfa5 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -75,6 +75,8 @@ struct pinctrl_gpio_range { * group selector @pins, and the size of the array in @num_pins * @pin_dbg_show: optional debugfs display hook that will provide per-device * info for a certain pin in debugfs + * @pin_dbg_set: optional debugfs set hook that will write per-device pinmux + * register for a certain pin in debugfs * @dt_node_to_map: parse a device tree "pin configuration node", and create * mapping table entries for it. These are returned through the @map and * @num_maps output parameters. This function is optional, and may be @@ -95,6 +97,8 @@ struct pinctrl_ops { unsigned *num_pins); void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset); + int (*pin_dbg_set) (struct pinctrl_dev *pctldev, unsigned int offset, + unsigned int val); int (*dt_node_to_map) (struct pinctrl_dev *pctldev, struct device_node *np_config, struct pinctrl_map **map, unsigned *num_maps); From patchwork Thu May 20 20:27:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 444905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC527C43460 for ; Thu, 20 May 2021 20:28:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CCC8160FE3 for ; Thu, 20 May 2021 20:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237986AbhETUaQ (ORCPT ); Thu, 20 May 2021 16:30:16 -0400 Received: from smtp-34.italiaonline.it ([213.209.10.34]:55772 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237353AbhETUaP (ORCPT ); Thu, 20 May 2021 16:30:15 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jpGWlKVEa5WrZjpGrlTUNw; Thu, 20 May 2021 22:27:53 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621542473; bh=iriFGB7/8coo66GVgaP8apTtH6WPOPW8oKA7OvT/6CM=; h=From; b=liNACm8XkWyLia6tBpy2xyV77bu0I86JYRzafaSXLH48DfJlipaGRF/+zQrNYaEnm iUKNehj82KlKaICmXp3GNYHsb0+sy3eQSpl1wvj2tWJmDszbJeqx7pll6jIdkWkbI4 dJDuQHIIVK4IUPxk6PuBkxxnua09KRIuKkpUQwrh6nAGZD4Lxcu4kjdiPHBdNPnNQ2 c9/yTYrwpxYsgYvsFEJZxZNbu4XNHk9fJNm7DxjZVs4PuPq2n+7tJrYQXeZTFATouZ h4o5lMCm8w0LK2TuCclW3Pw78UfKqDRDYcqp02VNW426oiIiVBQ33RrCzxcXTRSIM0 hh3sc5xRZ2Q2A== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6c649 cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=sozttTNsAAAA:8 a=EdIpBv2ybtxptObV3yYA:9 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Tony Lindgren , Drew Fustini , Linus Walleij , Andy Shevchenko , Haojian Zhuang , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v3 3/3] pinctrl: single: set pinmux from pins debug file Date: Thu, 20 May 2021 22:27:30 +0200 Message-Id: <20210520202730.4444-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520202730.4444-1-dariobin@libero.it> References: <20210520202730.4444-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfIUmEvQVxqvsNff7Mc8QYZVUGolb2h3/P3PFxHG5VygqL5T5I2Ja4Gf6GxfDvt86ebJJBjztbv5sXiNyvfP+xIQSoF/FbWpQM26jzirtbxbau2MWod9W UOEccBj3hn6Gx6MDH7rRmXfpc6BzHDXVB1cP6HMk7lJoBw135Ob69lr3pU7vmKn4KEXvB7CLJw+Dp+HBq9oLxWXYi83Cb+uIzRIYu44MIEdopXRcaNi0M3Ra fonCq7tbAyLXYaiosCoQMIEbq98pPvyRlWFKFsXPmKw9oQnocT3JBEHRopuEHSSZ+RcQ+QSjlTIxAxhYmZCtkRqH7F56XQ30QdwNu1WkmDFrqpFaGJkyuDse lYFXr0Rb0iIlpeanzljf6aoUiJiUfjvBXyg98WoSwgb/W9DebHfNwUVLXceOupyuUPHtwkK1FFotmW6+7T0EcB+/hILoRvXmOstmDlETIO6InIupEwU8rvbh pctqDbbP9T4mVHoKTqowPQUyNv2FkMQqpo8Rz9qPno5u97gqNd0lNgMa7m2vUcX6oodbXu1ZNwY/F2MvznICvq4gFnApRxcb3D9hg+sOAk+Zxeag6sL7v5zx Yhs= Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org As described in section 9.1 of the TI reference manual for AM335x [1], "For writing to the control module registers, the MPU will need to be in privileged mode of operation and writes will not work from user mode". By adding the pin_dbg_set helper to pcs_pinctrl_ops it will be possible to write these registers from the pins debug: cd /sys/kernel/debug/pinctrl/44e10800.pinmux-pinctrl-single/ echo >pins [1] https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf Signed-off-by: Dario Binacchi --- Changes in v3: - Remove CONFIG_DEV_MEM dependency. - Change pcs_pin_dbg_set() interface (char *buf -> unsigned int val). Changes in v2: - Remove CONFIG_SOC_AM33XX dependency. drivers/pinctrl/pinctrl-single.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 2c9c9835f375..1b75236563cf 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -313,6 +313,18 @@ static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); } +static int pcs_pin_dbg_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned int val) +{ + struct pcs_device *pcs; + unsigned int mux_bytes; + + pcs = pinctrl_dev_get_drvdata(pctldev); + mux_bytes = pcs->width / BITS_PER_BYTE; + pcs->write(val, pcs->base + pin * mux_bytes); + return 0; +} + static void pcs_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { @@ -331,6 +343,7 @@ static const struct pinctrl_ops pcs_pinctrl_ops = { .get_group_name = pinctrl_generic_get_group_name, .get_group_pins = pinctrl_generic_get_group_pins, .pin_dbg_show = pcs_pin_dbg_show, + .pin_dbg_set = pcs_pin_dbg_set, .dt_node_to_map = pcs_dt_node_to_map, .dt_free_map = pcs_dt_free_map, };