From patchwork Thu May 20 19:13:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 445021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10B9FC43460 for ; Thu, 20 May 2021 19:14:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E83BF613B4 for ; Thu, 20 May 2021 19:14:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237206AbhETTPq (ORCPT ); Thu, 20 May 2021 15:15:46 -0400 Received: from smtp-34-i2.italiaonline.it ([213.209.12.34]:37658 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S235392AbhETTPo (ORCPT ); Thu, 20 May 2021 15:15:44 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jo6clK7DY5WrZjo6ilTD6m; Thu, 20 May 2021 21:13:22 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621538002; bh=hBVv0EIDOJPnyshBY6NoCuTaYvUzw/b0onSPeL7WQcQ=; h=From; b=lt4OD/JCm71jSEWWf5waabOJ1A5yDTb0T62Qfp4OylOw45X9verM1HoM+Oa0juTJC m2SLz9q8azaefBRgv++QQfatV7cNg7yWCiCITZ9C3CxIz2g1GYtHJ/QdaVt/YpLQvZ ggmjfjDyvt6CZRFY/nKq01rQU4NXq4sxPzep3PHJ54bkQ83LOrFBARKvUa1V1AJOsS EDCrvoPwoyuXw7Oorf8EdPm9VcFa7TGv5MLpL8/QgNHxbwX7bXjEMMe3Y1MBBo5hHl VLAeTHNX1XnKoiVtjdGnFpGzyKor0bpk485AMxsaSl8JvCCRGyis/0UOqV/g7zNsCZ DM9E+gafNxj9w== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6b4d2 cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=VwQbUJbxAAAA:8 a=Bl6OLPU8nqzXNm5YYFQA:9 a=AjGcO6oz07-iQ99wixmX:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Lee Jones , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tero Kristo , Michael Turquette , Stephen Boyd , Dario Binacchi , Tony Lindgren , linux-clk@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v6 1/5] clk: ti: fix typo in routine description Date: Thu, 20 May 2021 21:13:01 +0200 Message-Id: <20210520191306.21711-2-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520191306.21711-1-dariobin@libero.it> References: <20210520191306.21711-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfAQR7MsSMyb1ZKg3ZEfotApon7KhAUuSBROKP6UOUbsI6+xVOxtvRx2rdXf8G7tVDoCjUsXcDvvCGkwz/nGT52Yy8lTAyhidgINviB1g7ju5oDNdyZXS HW3IvnQf+MGnDgucHzfgP5d6OceEspgfgM0o3Yq/0JLxbzgnWNJ5lV7XRtLbgk0gWgMH5Dghu2WXW7cgQMTWbCFRO1lV6A+teltIHwOfNwLqvMbf9L2ERWbe C5dxVvGR3jXaBZvOn3W96xuXHdyX5aGWkp645heRcZR2E4SHhJRcvFMfjhNZ3fGt50UtgR/rjR/AwSIOrwd+3hHcg0EQPPTJCUBE+d593BeIwa/fIzchBb+W lEm5aRISF2jWIUovlA2ijBADWcNDK0RFTK26I3MWrtxM1e2Zb+eTgT68QLmHqW4lxhUHYWVloSgLWZU1zlmRgzyrbQMIqkhFHV+1eLtwW/szHqpWqvNNokSg ThA6XG7Nu49QiiFnmD244X+OFGqicKmr1ACbmsT8o0DD/X3t07gbfCCz8EDw0vSdYmJ/UX6WFeZqoE/ZjRlVU2bASAwKS7K6Ydjfsg== Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Replace _omap3_noncore_dpll_program with omap3_noncore_dpll_program. Signed-off-by: Dario Binacchi Reviewed-by: Stephen Boyd --- (no changes since v4) Changes in v4: - Add Stephen Boyd review tag. drivers/clk/ti/dpll3xxx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 6097b099a5df..94d5b5fe9a2b 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -292,7 +292,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) } /** - * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly + * omap3_noncore_dpll_program - set non-core DPLL M,N values directly * @clk: struct clk * of DPLL to set * @freqsel: FREQSEL value to set * From patchwork Thu May 20 19:13:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 443690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD440C433B4 for ; Thu, 20 May 2021 19:14:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9078B61074 for ; Thu, 20 May 2021 19:14:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237355AbhETTP5 (ORCPT ); Thu, 20 May 2021 15:15:57 -0400 Received: from smtp-34-i2.italiaonline.it ([213.209.12.34]:53932 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S237292AbhETTPv (ORCPT ); Thu, 20 May 2021 15:15:51 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jo6clK7DY5WrZjo6olTD8k; Thu, 20 May 2021 21:13:27 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621538007; bh=3Paw2xB98b+SDuV2alDurkaGEspLbA4rwbMXsFizNMM=; h=From; b=G2iS9HJO6Ysq4n5NwXUz0P0CG3jT+RshkULeAq+fxD31UfE/cFFy80I46QyrXuDGg 605NZzMxDkDHrT31BU36vhTg67GNpuKTohnXLyWmUnnZUXom7mmtPDwFbeXptCZiwi HrnC7xvzTcIDMKZ4QVaHJj0/zZe+Hox1QvwOitvHpKtB9MIKDhqodRyq1OscRWYNuJ ZcDgcQJdRDregvi9wZU3HXv5G+lbbO99pdUgfQmp7TThpuUppfvQSF6yBYlBa4CG5h 37ZPzgIrYJHnKaxBzvDTiA/8ciyID7NRuf8jLkrYlTh3QD83/W2xoJ8oIwwLOHc8u3 Wn5hHicbn0leg== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6b4d7 cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=2KMo9-giAAAA:8 a=4mKMOZvguhLedlVR2KsA:9 a=2pGyGSWy5nf2n_rBi4rp:22 a=UeCTMeHK7YUBiLmz_SX7:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Lee Jones , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tero Kristo , Michael Turquette , Stephen Boyd , Dario Binacchi , Tony Lindgren , Rob Herring , devicetree@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v6 3/5] ARM: dts: am33xx-clocks: add spread spectrum support Date: Thu, 20 May 2021 21:13:03 +0200 Message-Id: <20210520191306.21711-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520191306.21711-1-dariobin@libero.it> References: <20210520191306.21711-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfCKKQ3/eQ89KdiBEt5W6BtCqUtO4ajIEXh1sso9w5esB447P6nUuZkK/dzWp3Yq1LqBYvx+cONwhGMQPUw4Xk6sKcifXuDGkZqu1T39bHEwOZ/5W0tkW om7buNCEeeVqYKYs7ooGDV/L4Gw0CP+rBQH1guOAFp6OuD1YQIPsHDwHhMDXoEdzASdJNztx7kXGSaKlinhTbSTcgLyNA+FsfdUqLzpHDzSfJqOxOZg3mBjc 6jTVejzK/nHoqPV8MXY/Gwi1pMpXta/DXIbzcxoIldivpx8Mv0Wjt8LF1qAl13BHBA7D0TEpB6rYPOyqz2K5EQEDbAFLAh/kTZdU76RDsXFtHjNu1a68kdWR HfNuz8NfMDyrLwpTeNmGj8yEQcEJkpqkaYHmr2xuTyTSh4av8UcFhEc0x48vG3j5tHKFX06LfzH9/5SIUmp4oQzu2XRHOvXk+hIGBrUnwGUJ2eupMdsjJNQo BoyMe9pbHh42V5Rf/OSgOQjdp8mbN6ig513RB1nAQfmah3XS6SIsJqO1W3NFkJ53nw2XC0Dhkqenzd9HygB3R4qUcH/03E3i5BaktsYFCewDfVTHj9ptWNeK 2QU= Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruh73x RM, SSC is supported only for LCD and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP). Signed-off-by: Dario Binacchi Acked-by: Tony Lindgren --- (no changes since v4) Changes in v4: - Add SSC registers for CORE, DDR and PER PLLs. - Update commit message. Changes in v3: - Add Tony Lindgren acked tag. Changes in v2: - Remove SSC registers from dpll_core_ck@490 node (SSC is not supported) - Add SSC registers to dpll_mpu_ck@488 node. arch/arm/boot/dts/am33xx-clocks.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index dced92a8970e..b7b7106f2dee 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -164,7 +164,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; + reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { @@ -220,7 +220,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; + reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { @@ -244,7 +244,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { @@ -261,7 +261,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; + reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; dpll_per_m2_ck: dpll_per_m2_ck@4ac { From patchwork Thu May 20 19:13:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 445022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF4ECC433B4 for ; Thu, 20 May 2021 19:13:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B3EEC61358 for ; Thu, 20 May 2021 19:13:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236750AbhETTOy (ORCPT ); Thu, 20 May 2021 15:14:54 -0400 Received: from smtp-34.italiaonline.it ([213.209.10.34]:36002 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236863AbhETTOw (ORCPT ); Thu, 20 May 2021 15:14:52 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jo6clK7DY5WrZjo6plTD8z; Thu, 20 May 2021 21:13:30 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621538010; bh=PPTo8GvjIIsaEKU5B1TIF8N7cm5fuyUf7SEXiLKXv5E=; h=From; b=NCeFT0a0nEAKInyX/QskClahvicdc/d9j3ukQ15BUUFr/Yg/rsU4jQM3lCdBe1gG4 79OtmjsmuVOkHjVKtpOIgKU8JZ1SPQrwMPfG/UDNCPcHr+eN9rpSe6kCg34vX0qoMl XKCsRNDvWGxYItyWasGTZQ4RAWumDa+dc1wM/aNAbGcTnm4Bame10ApTWtrDDZekEc LH2LMusz8PsVTSmLzs54HRThz+aXYsg0ORLEZ6tzTIz9bOOS9cKAq2CRMQ8UUL7G2e fBv/4uAIFNt8Wb3hobmUf+Y72Nc3uTiTVjj2bWkDChiuoTe/jXRSlLwFxYi9w8RYkN tQru74qiB/Kug== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6b4da cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=2OX5x-OEy5pyK2UBO5QA:9 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Lee Jones , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tero Kristo , Michael Turquette , Stephen Boyd , Dario Binacchi , Tony Lindgren , Rob Herring , devicetree@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v6 4/5] ARM: dts: am43xx-clocks: add spread spectrum support Date: Thu, 20 May 2021 21:13:04 +0200 Message-Id: <20210520191306.21711-5-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520191306.21711-1-dariobin@libero.it> References: <20210520191306.21711-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfKFqPfFrm9NguM98g1PGePGjdLAxOgmqBsKdOo6VzMURxaUNiApycFskdgIi/4Y2BJ+RHGvjJZB+UQ0XHjY6hv124Cx++UIh4AMaWVb6odeJysE+Alzt lVfVcDuUugjHeNo83ptAt2VbT84lesy3N0AIqawi34ezcteXgeYk2jEdY56G/WLk7QNC4fEZcQ2DeXdmimzlfAWF5GXKseD5EmoyjLiI6jdhlUZqNgFZDUe6 BgV/hNSspke2GALjWhyl1G0Qogj/c0UIMhKERPD6BWHjyoRcX0xzYQVAjqOGxUWOvPj4p+/MgmEu899VTDXAKYUrKZWpNqBc/ns1Sg56kbj58jpHx1aFA6oE UBuT6A4NbMTRQcysUiSfoC3Em26/4o+6OZ9rQneBDdc2yZJzZh4h1YZ2O+dBaXWEyvFU/8KZKnsLkpKhobGmlkXWlmWtbi08T/SCAbdShbk2NELxLf6PX5Zk bKOvC3AGwEOnu7A0w9p1S4fJ1SR61axM2aiRK+SN8ZUP0pQewg11CcRoDRaYRcRjdX2DI/RH92NCCzKnxBoMYLvQHoeMkLfMqM4XGSetnFsvNAleYoXt+ORA TFM= Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruhl7x RM, SSC is supported only for LCD and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP, EXTDEV). Signed-off-by: Dario Binacchi Acked-by: Tony Lindgren --- (no changes since v1) arch/arm/boot/dts/am43xx-clocks.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index c726cd8dbdf1..314fc5975acb 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d20>, <0x2d24>, <0x2d2c>; + reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -250,7 +250,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2d60>, <0x2d64>, <0x2d6c>; + reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { @@ -276,7 +276,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2da0>, <0x2da4>, <0x2dac>; + reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { @@ -294,7 +294,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e20>, <0x2e24>, <0x2e2c>; + reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { @@ -313,7 +313,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2de0>, <0x2de4>, <0x2dec>; + reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>; }; dpll_per_m2_ck: dpll_per_m2_ck@2df0 { @@ -557,7 +557,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x2e60>, <0x2e64>, <0x2e6c>; + reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>; }; dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { From patchwork Thu May 20 19:13:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 443691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CA9CC43461 for ; Thu, 20 May 2021 19:13:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70B52613BA for ; Thu, 20 May 2021 19:13:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236859AbhETTO5 (ORCPT ); Thu, 20 May 2021 15:14:57 -0400 Received: from smtp-34-i2.italiaonline.it ([213.209.12.34]:37658 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S236972AbhETTO4 (ORCPT ); Thu, 20 May 2021 15:14:56 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([82.60.150.250]) by smtp-34.iol.local with ESMTPA id jo6clK7DY5WrZjo6slTD9e; Thu, 20 May 2021 21:13:32 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621538012; bh=NTRyHVQakJ7HbxsvPHLac4pXGhyYyUqXNfzgdmxqOpc=; h=From; b=uw0vC90iPXNlgBBfx7uYiCvuBZSElnBWIF2dlfKAQIVSobFlj3J0OLadzUFMdhzqL lxHdIuDJkMoWB8I4bdFwxkLcBjWzGcDJQ0Z07jONfFms4rQIrzfxRDkO5Wxgjpn1yZ Q2KFAnPWHo1g449uFp374+wKG85EIDlGS0tUWFLXIa5QrgD9wNk4KySK25RR/56FQI ebsdd0okXeX8/J/XFIjaTRWdKOqpaesxMs8mhb0ZxklZPr63sGohTCb+9ho0A3YC0J bVHOc6tJfJ3C6eCX54zxUFkMVZ+A3gGgmMf8V/GIeUrRJ+Ca9T6x1c+OYYG1uVWbIo krUA4Ulr4wFxg== X-CNFS-Analysis: v=2.4 cv=W4/96Tak c=1 sm=1 tr=0 ts=60a6b4dc cx=a_exe a=QSJ1svMVA5tvcuOEAX2Bgw==:117 a=QSJ1svMVA5tvcuOEAX2Bgw==:17 a=IkcTkHD0fZMA:10 a=VwQbUJbxAAAA:8 a=o_rbLAqdoS-kjYQczG8A:9 a=QEXdDO2ut3YA:10 a=5yUOnwQy5QICz8m5uxDm:22 a=AjGcO6oz07-iQ99wixmX:22 a=pHzHmUro8NiASowvMSCR:22 a=xoEH_sTeL_Rfw54TyV31:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Lee Jones , =?utf-8?q?Beno=C3=AEt_Cousson?= , Rob Herring , Tero Kristo , Michael Turquette , Stephen Boyd , Dario Binacchi , Tony Lindgren , linux-clk@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v6 5/5] clk: ti: add am33xx/am43xx spread spectrum clock support Date: Thu, 20 May 2021 21:13:05 +0200 Message-Id: <20210520191306.21711-6-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210520191306.21711-1-dariobin@libero.it> References: <20210520191306.21711-1-dariobin@libero.it> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfAPM6ZRb6svY/nWH8qORf9XFgGs/4yr24H/9Qr+yRyj+8avX1F++T0TG44RavE5Eqq/thtXhLk6Ma9wAbiQOmNYgQ5uKiW8flkQy+eBhxBgb/JsqD4ZJ KuFuPC8uMlXXLBKkYmM3HGtaZdYpx3XDGIkgiBN59Cv39eLGMkiN6zoIpo5T6g/TpRpNFzyrqy37nfwar5ErA7Qrj1bJzYzA+LHfkgHVgmhiyDRxyeZdWtBs 7fvd9ct6YZuMqDi+PNx47BLBdm/I69l6GVXdAqLJ/C3v4sZW8uDdvosdG29A/0tJPGd7FJyO8yVMhETKnYqoRZL90fw/abxrmcSdI2BZSZwvPwG3lt5ezUj4 c+fGZBo/lj6NCgoRvXWws00mnPuft3IAK3ar4gcazxCgf9Au4w6Pu0qLGQ8EVGb8ezAKL/7hFdY9fgS0zwI55gL7C1jTXLbch0OdwnKqoEBUZWEXb0bLkas+ gXbxWd9MWmb7HWTJRepeVCe8n4RNkJ+ncEUPqryFwpk+9s73F1d8E9g9dcmz/PJjUDVgkIc3SKAgC44rbeitE1O0tSZUJbKVoVIiCw== Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs. As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for DDR, PER, and CORE PLLs. Calculating the required values and setting the registers accordingly was taken from the set_mpu_spreadspectrum routine contained in the arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project. In locked condition, DPLL output clock = CLKINP *[M/N]. In case of SSC enabled, the reference manual explains that there is a restriction of range of M values. Since the omap2_dpll_round_rate routine attempts to select the minimum possible N, the value of M obtained is not guaranteed to be within the range required. With the new "ti,min-div" parameter it is possible to increase N and consequently M to satisfy the constraint imposed by SSC. Signed-off-by: Dario Binacchi Reviewed-by: Tero Kristo --- Changes in v6: - Add Tero Kristo review tag. Changes in v5: - Remove ssc_ack_mask field from dpll_data structure. It was not used. - Change ssc_downspread type from u8 to bool in dpll_data structure. Changes in v4: - Update commit message. Changes in v3: - Use "ti,ssc-modfreq-hz" binding instead of "ti,ssc-modfreq". Changes in v2: - Move the DT changes to the previous patch in the series. drivers/clk/ti/dpll.c | 39 ++++++++++++++++++ drivers/clk/ti/dpll3xxx.c | 85 +++++++++++++++++++++++++++++++++++++++ include/linux/clk/ti.h | 22 ++++++++++ 3 files changed, 146 insertions(+) diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index d6f1ac5b53e1..e9f9aee936ae 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -290,7 +290,9 @@ static void __init of_ti_dpll_setup(struct device_node *node, struct clk_init_data *init = NULL; const char **parent_names = NULL; struct dpll_data *dd = NULL; + int ssc_clk_index; u8 dpll_mode = 0; + u32 min_div; dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL); clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); @@ -345,6 +347,27 @@ static void __init of_ti_dpll_setup(struct device_node *node, if (dd->autoidle_mask) { if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) goto cleanup; + + ssc_clk_index = 4; + } else { + ssc_clk_index = 3; + } + + if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask && + dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) { + if (ti_clk_get_reg_addr(node, ssc_clk_index++, + &dd->ssc_deltam_reg)) + goto cleanup; + + if (ti_clk_get_reg_addr(node, ssc_clk_index++, + &dd->ssc_modfreq_reg)) + goto cleanup; + + of_property_read_u32(node, "ti,ssc-modfreq-hz", + &dd->ssc_modfreq); + of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam); + dd->ssc_downspread = + of_property_read_bool(node, "ti,ssc-downspread"); } if (of_property_read_bool(node, "ti,low-power-stop")) @@ -356,6 +379,10 @@ static void __init of_ti_dpll_setup(struct device_node *node, if (of_property_read_bool(node, "ti,lock")) dpll_mode |= 1 << DPLL_LOCKED; + if (!of_property_read_u32(node, "ti,min-div", &min_div) && + min_div > dd->min_divider) + dd->min_divider = min_div; + if (dpll_mode) dd->modes = dpll_mode; @@ -585,8 +612,14 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) const struct dpll_data dd = { .idlest_mask = 0x1, .enable_mask = 0x7, + .ssc_enable_mask = 0x1 << 12, + .ssc_downspread_mask = 0x1 << 14, .mult_mask = 0x7ff << 8, .div1_mask = 0x7f, + .ssc_deltam_int_mask = 0x3 << 18, + .ssc_deltam_frac_mask = 0x3ffff, + .ssc_modfreq_mant_mask = 0x7f, + .ssc_modfreq_exp_mask = 0x7 << 8, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, @@ -645,8 +678,14 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node) const struct dpll_data dd = { .idlest_mask = 0x1, .enable_mask = 0x7, + .ssc_enable_mask = 0x1 << 12, + .ssc_downspread_mask = 0x1 << 14, .mult_mask = 0x7ff << 8, .div1_mask = 0x7f, + .ssc_deltam_int_mask = 0x3 << 18, + .ssc_deltam_frac_mask = 0x3ffff, + .ssc_modfreq_mant_mask = 0x7f, + .ssc_modfreq_exp_mask = 0x7 << 8, .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 94d5b5fe9a2b..e32b3515f9e7 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -291,6 +291,88 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) *sd_div = sd; } +/** + * omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers + * @clk: struct clk * of DPLL to set + * + * Enable the DPLL spread spectrum clocking if frequency modulation and + * frequency spreading have been set, otherwise disable it. + */ +static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk) +{ + struct dpll_data *dd = clk->dpll_data; + unsigned long ref_rate; + u32 v, ctrl, mod_freq_divider, exponent, mantissa; + u32 deltam_step, deltam_ceil; + + ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); + + if (dd->ssc_modfreq && dd->ssc_deltam) { + ctrl |= dd->ssc_enable_mask; + + if (dd->ssc_downspread) + ctrl |= dd->ssc_downspread_mask; + else + ctrl &= ~dd->ssc_downspread_mask; + + ref_rate = clk_hw_get_rate(dd->clk_ref); + mod_freq_divider = + (ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq); + if (dd->ssc_modfreq > (ref_rate / 70)) + pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n", + __clk_get_name(clk->hw.clk), ref_rate / 70); + + exponent = 0; + mantissa = mod_freq_divider; + while ((mantissa > 127) && (exponent < 7)) { + exponent++; + mantissa /= 2; + } + if (mantissa > 127) + mantissa = 127; + + v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg); + v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask); + v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask); + v |= exponent << __ffs(dd->ssc_modfreq_exp_mask); + ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg); + + deltam_step = dd->last_rounded_m * dd->ssc_deltam; + deltam_step /= 10; + if (dd->ssc_downspread) + deltam_step /= 2; + + deltam_step <<= __ffs(dd->ssc_deltam_int_mask); + deltam_step /= 100; + deltam_step /= mod_freq_divider; + if (deltam_step > 0xFFFFF) + deltam_step = 0xFFFFF; + + deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >> + __ffs(dd->ssc_deltam_int_mask); + if (deltam_step & dd->ssc_deltam_frac_mask) + deltam_ceil++; + + if ((dd->ssc_downspread && + ((dd->last_rounded_m - (2 * deltam_ceil)) < 20 || + dd->last_rounded_m > 2045)) || + ((dd->last_rounded_m - deltam_ceil) < 20 || + (dd->last_rounded_m + deltam_ceil) > 2045)) + pr_warn("clock: SSC multiplier of DPLL %s is out of range\n", + __clk_get_name(clk->hw.clk)); + + v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg); + v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask); + v |= deltam_step << __ffs(dd->ssc_deltam_int_mask | + dd->ssc_deltam_frac_mask); + ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg); + } else { + ctrl &= ~dd->ssc_enable_mask; + } + + ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg); +} + /** * omap3_noncore_dpll_program - set non-core DPLL M,N values directly * @clk: struct clk * of DPLL to set @@ -390,6 +472,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) ti_clk_ll_ops->clk_writel(v, &dd->control_reg); } + if (dd->ssc_enable_mask) + omap3_noncore_dpll_ssc_program(clk); + /* We let the clock framework set the other output dividers later */ /* REVISIT: Set ramp-up delay? */ diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index c62f6fa6763d..3486f20a3753 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -63,6 +63,17 @@ struct clk_omap_reg { * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs + * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading + * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency + * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg + * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg + * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg + * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in + * @control_reg + * @ssc_modfreq: the DPLL SSC frequency modulation in kHz + * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent) + * @ssc_downspread: require the only low frequency spread of the DPLL in SSC + * mode * @flags: DPLL type/features (see below) * * Possible values for @flags: @@ -110,6 +121,17 @@ struct dpll_data { u8 auto_recal_bit; u8 recal_en_bit; u8 recal_st_bit; + struct clk_omap_reg ssc_deltam_reg; + struct clk_omap_reg ssc_modfreq_reg; + u32 ssc_deltam_int_mask; + u32 ssc_deltam_frac_mask; + u32 ssc_modfreq_mant_mask; + u32 ssc_modfreq_exp_mask; + u32 ssc_enable_mask; + u32 ssc_downspread_mask; + u32 ssc_modfreq; + u32 ssc_deltam; + bool ssc_downspread; u8 flags; };