From patchwork Thu May 27 13:16:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 449670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32CBDC4708B for ; Thu, 27 May 2021 13:16:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 16CF3610FC for ; Thu, 27 May 2021 13:16:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236380AbhE0NSZ (ORCPT ); Thu, 27 May 2021 09:18:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236369AbhE0NSY (ORCPT ); Thu, 27 May 2021 09:18:24 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C614C061760; Thu, 27 May 2021 06:16:50 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id j10so792438edw.8; Thu, 27 May 2021 06:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bJxa6D61sNyoVcUGq0JgZ9RhtqSvpqxNVEv5UpFQHpA=; b=e1jtJrfvCnON7Zgry3taHlpF2S7Ok7Wps42CM9sF8A1X+sidOqveg1wBeTO/2446u0 AvKeUwT1HI336OPftLTxktnKtqpMZfAv4N8UYTf8xbhq4x7uaaK9vOuARa4I+YMok4we kOYEs8JbbO0qg/7u36OEVq+28T++BBWN038cm9W3/PHlz92yg4dEb3s9gEAu1rjNMLbu X7E9E3xtEPqD3WED5Kh2KqykNKGpRDkaLBj8/0rU4/OXC+SgBcvu8lAAKVdiUQyLHVAk ERWQDkYNNSQOqzRv+nj96mYrVGn7es9ssW3qsOHk3wz4fqLn8Iv3qixF6pklYMkQ+dBn HWZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bJxa6D61sNyoVcUGq0JgZ9RhtqSvpqxNVEv5UpFQHpA=; b=D4ok19iNKIEreYmESYKfqeK+TnbnDDMwwLbd2q9PYZuBsPB368f/qwS2IHUnCMQKKs pHa0Lc5zdKqICG3Gtuz/s/8HV2FRiXXWPOZSSJd3PMGAcwg/u6M4LQvFs2reUuAANd3Y DeUSaQj9FRBegBwqqbai+OzlcdjydTLtQybJJqJHR/6HIkRj0VcC5aSOhujKdAiaIxP2 BA75TEIiiPBYVGgoA1OiIKNi37bsHFYQEYmGiAvMX0peAj0XhQq4e4/WNlU4Km9UU0w6 FNUghMa8V1ZOOfnda2At1SiV9YPKW4T9GM3Hjv8B/XMOJhs5aOfjP15k3OsK7cm7YFF7 pS5A== X-Gm-Message-State: AOAM533KuWJx+YDuHl/HFjmhBQzIVXfDyMPcE9S0yHFMdY1/VFKcP5xh avuu5/JU5jWBwhmwF9mLsSJlc3c+Bjg= X-Google-Smtp-Source: ABdhPJzFuBN1+LhAPjeaQrdY/nYNobVtmWAtIzt6XqXwol07HBpqkSFkn/XCqv/slWM0wKn5n9PNPg== X-Received: by 2002:a50:ff16:: with SMTP id a22mr4037741edu.143.1622121408643; Thu, 27 May 2021 06:16:48 -0700 (PDT) Received: from localhost.localdomain ([188.24.140.160]) by smtp.gmail.com with ESMTPSA id r23sm1104206edq.59.2021.05.27.06.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 06:16:48 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/6] clk: actions: Fix UART clock dividers on Owl S500 SoC Date: Thu, 27 May 2021 16:16:39 +0300 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v2: - Added Reviewed-by from Mani drivers/clk/actions/owl-s500.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 61bb224f6330..75b7186185b0 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -305,7 +305,7 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, @@ -317,31 +317,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), - OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), + OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, From patchwork Thu May 27 13:16:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 448990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C620EC4707F for ; Thu, 27 May 2021 13:16:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AEAFF6128B for ; Thu, 27 May 2021 13:16:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236384AbhE0NS1 (ORCPT ); Thu, 27 May 2021 09:18:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236379AbhE0NSZ (ORCPT ); Thu, 27 May 2021 09:18:25 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52794C0613CE; Thu, 27 May 2021 06:16:51 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id e12so52961ejt.3; Thu, 27 May 2021 06:16:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=crig0bzSf2SgCM+EYnsItW6y8m075yiQFudfhyHny3Y=; b=r3zXf9PXJyaSQoeJL0J7o4RLGNp5T8/of+o46r92qRwQKZ1BWDPxsELPIOQGpGmiqe J6HLZ9bdg6F1GGSvs72BLDYYzV7pyCsY5BkYsMQITnRb2/Wad4ntcqUDG4JpYvGZG59u UkqdNJqpw8IuRywypTBg2tXJ4Ef627VrmCDxiBf+OBtCMUz6mW7A6L0EvX2GR1Mqub72 iVVLFi0s+1IRBTKOdT9FBAQLB5lDnV7NkZx9E/DqUfUFSbqewPdBwhlv+vVX0Z8YDVqp 6HVFjptIyTqPIuHTfaJMAY40nyumpfu7pR+TEQ+2c5q1UaDt08p5v661Eyf+g1UYslRN Y3TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=crig0bzSf2SgCM+EYnsItW6y8m075yiQFudfhyHny3Y=; b=F0AClPp1NhjckdTcZOVIYMqGESwc55p4DGFVbZCOjgMJWoJ4TTn4U3TcoTx/teTYEy /LU1RVcKrBqTjlPnTPnz97ZVebjFNrkHAn3xS+br4sZOV3CHuc/cXmXprc8cVt9tHn6b fvy+l6w+u4JhrlYQUpFSHXjWeTy6zH89u+WRZdUEy4vobiOHakTFXxauJ2uxG96a3cNm 9ogTA9/Yg4XN53qjYs3Gp4jfKBq4SAv17yuZ//HDrGpmikzRUgxLUYrysdmQUx3JYHeO bkE8MTF0glxFBgnhytko+Vd7PkHjKluN5rJs2xI8hBxuDSQ2nElvIahlhm9FIMloIen4 WCIw== X-Gm-Message-State: AOAM5331HZMagK6JovoEtdzUadmkStmMAfrKGz622pizeGmZp6CLC2kE DlHewuNs4H+wyZFlhqAnY9gcwpEscTE= X-Google-Smtp-Source: ABdhPJzWexKK6TMKAp90yIfRFCp6HKY74EqmgszOQNQRVH1ZHIm9OHCpUKYJvMuf5POc2v8mscTVgA== X-Received: by 2002:a17:906:3715:: with SMTP id d21mr3883315ejc.34.1622121409962; Thu, 27 May 2021 06:16:49 -0700 (PDT) Received: from localhost.localdomain ([188.24.140.160]) by smtp.gmail.com with ESMTPSA id r23sm1104206edq.59.2021.05.27.06.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 06:16:49 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/6] clk: actions: Fix SD clocks factor table on Owl S500 SoC Date: Thu, 27 May 2021 16:16:40 +0300 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Drop the unsupported entries in the factor table used for the SD[0-2] clocks definitions on the Actions Semi Owl S500 SoC. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v2: - Re-added entry "{ 24, 1, 25 }" to sd_factor_table, according to the datasheet (V1.8+), this is a valid divider drivers/clk/actions/owl-s500.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 75b7186185b0..42abdf964044 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -127,8 +127,7 @@ static struct clk_factor_table sd_factor_table[] = { { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 }, { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 }, { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 }, - { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 }, - { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 }, + { 24, 1, 25 }, /* bit8: /128 */ { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 }, @@ -137,8 +136,7 @@ static struct clk_factor_table sd_factor_table[] = { { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 }, { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 }, { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 }, - { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 }, - { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 }, + { 280, 1, 25 * 128 }, { 0, 0, 0 }, }; From patchwork Thu May 27 13:16:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 449669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09B0CC4708F for ; Thu, 27 May 2021 13:16:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E138A611AE for ; Thu, 27 May 2021 13:16:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236389AbhE0NS2 (ORCPT ); Thu, 27 May 2021 09:18:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235996AbhE0NS0 (ORCPT ); Thu, 27 May 2021 09:18:26 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ADB7C06138A; Thu, 27 May 2021 06:16:52 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id g7so816596edm.4; Thu, 27 May 2021 06:16:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ulSg/i7gd6RTh8QJ8jOfropMdLv/b3cGBvHL1IErnoo=; b=g3J4cgHio4vsbIZucBQnjwlG734pqs3X3lsRI1bnvJZywWO9L2QF7hr/cbf12z0L5/ XH1JfmZ1Y+L8CYAk8A6IFa78iKiRJfaNz2q4m/6h5cFT9u2oli3u3M2z9RuA+JKBRAsS gpC7yTkGnTSCOw0BeQdeFW++CapQ9FhIBPQc0YppbmDUhkUL6DxtvYgaKaT7OP0yHnif eZfU8ekeFcv1JpzDbBAjbfWQtH35WdHsReIPbMm+RNWFe+7KLpx6GgqAcVLtDoizg6Bt gM2FBGPrnyFd+HFAflguEZZ70gOFzAWjM4A/nGo87wUuuzATjbFTdeo9waDSnRswummK wmmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ulSg/i7gd6RTh8QJ8jOfropMdLv/b3cGBvHL1IErnoo=; b=fOINlGCW7mXx/UnfIqEMUkW+TjNzGaaOP7jZ5VQPYP/lWyzBXInvDAt1O+PZsn9jkV ETlNR616PvdMuuekpFwpiQtuznCwhmAKdGSRZ7CAnQhTboffFhT8/f4wGpu/s/M8/ECn NNLthn/FIC/H2Sa/tR9P8eEGjClczJIdE/Gdl7LWG8nEwgt1VY2XNep9G4XrIJbJhzZE it0Tc/TjOwE3FJpJN5KSxYrHC7wc9WXneASlTmgJDcOo23M5gswgME6ICdNKjwEWEJP8 6TnABtWypgyYLJm/WMXV64n8NGqihMUXfuBwoY2NLzhfdE7ex+kV610UACZjiAjXqKwQ HdgQ== X-Gm-Message-State: AOAM530oBHyiFT9T0yRUiEK6ovdpWBiI+0dwciph09q8bWZ3JPMZ/AQ1 PSbgMwx4ABkr+LtRO5+RWrw= X-Google-Smtp-Source: ABdhPJw1+cQGW1kZHgbPN8hgvc86gnCqSumGYxtyk8LAT/fpJ+G/7LYxpr/DfN1fy1sD/50qgpp9rQ== X-Received: by 2002:a05:6402:1d39:: with SMTP id dh25mr4071249edb.113.1622121411213; Thu, 27 May 2021 06:16:51 -0700 (PDT) Received: from localhost.localdomain ([188.24.140.160]) by smtp.gmail.com with ESMTPSA id r23sm1104206edq.59.2021.05.27.06.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 06:16:50 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/6] clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoC Date: Thu, 27 May 2021 16:16:41 +0300 Message-Id: <288f7a0a677a6bd8a3007b8b126f5a4637ec772e.1622119892.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The following clocks of the Actions Semi Owl S500 SoC have been defined to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE, VDE, BISP, SENSOR[0-1] There are several issues involved in this approach: * 'bisp_factor_table[]' describes the configuration of a regular 8-rates divider, so its usage is redundant. Additionally, judging by the BISP clock context, it is incomplete since it maps only 8 out of 12 possible entries. * The clocks mentioned above are not identical in terms of the available rates, therefore cannot rely on the same factor table. Specifically, BISP and SENSOR* are standard 12-rate dividers so their configuration should rely on a proper clock div table, while VCE and VDE require a factor table that is a actually a subset of the one needed for DE[1-2] clocks. Let's fix this by implementing the following: * Add new factor tables 'de_factor_table' and 'hde_factor_table' to properly handle DE[1-2], VCE and VDE clocks. * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1] clocks converted to OWL_COMP_DIV. * Drop the now unused 'bisp_factor_table[]'. Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since there is no reason to always keep ON those clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v2: - Re-added OWL_GATE_HW to SENSOR[0-1], according to the datasheet they are gated, even though the vendor implementation states the opposite drivers/clk/actions/owl-s500.c | 44 ++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 42abdf964044..42d6899755e6 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -140,9 +140,16 @@ static struct clk_factor_table sd_factor_table[] = { { 0, 0, 0 }, }; -static struct clk_factor_table bisp_factor_table[] = { - { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 }, - { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 }, +static struct clk_factor_table de_factor_table[] = { + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, + { 8, 1, 12 }, + { 0, 0, 0 }, +}; + +static struct clk_factor_table hde_factor_table[] = { + { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, + { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, { 0, 0, 0 }, }; @@ -156,6 +163,13 @@ static struct clk_div_table rmii_ref_div_table[] = { { 0, 0 }, }; +static struct clk_div_table std12rate_div_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, + { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, + { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, + { 0, 0 }, +}; + static struct clk_div_table i2s_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, @@ -191,39 +205,39 @@ static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNE /* factor clocks */ static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0); -static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0); -static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0); +static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0); +static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), - OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table), + OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), - OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table), + OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), 0); -static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p, +static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p, OWL_MUX_HW(CMU_BISPCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table), + OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table), 0); -static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, +static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table), - CLK_IGNORE_UNUSED); + OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table), + 0); -static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, +static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), - OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table), - CLK_IGNORE_UNUSED); + OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table), + 0); static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD0CLK, 9, 1), From patchwork Thu May 27 13:16:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 448989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB225C4708A for ; Thu, 27 May 2021 13:16:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 981DE613D1 for ; Thu, 27 May 2021 13:16:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236421AbhE0NSb (ORCPT ); Thu, 27 May 2021 09:18:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236375AbhE0NS1 (ORCPT ); Thu, 27 May 2021 09:18:27 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE227C061760; Thu, 27 May 2021 06:16:53 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id e24so722046eds.11; Thu, 27 May 2021 06:16:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QcmFmBVnSnD2tbZxnT4h9jKt0idY/F3KyHEdb6MSBsw=; b=oJ0iLczWf4eZuaHoL7tZS2LoUrhyj6CAVRTV0v323hwoOv76Vufe8zxV6wNc0/yNvJ EsOOUH6YFWkvi8zVxTFESKsM9YawhiaT3jnE6PNG61NsPsTXggzOnaLURn2fqOWCDbLr 8eA2m9FQbz42drScgFJ4ww3l65k5rWGIF7uzcskiiVkDBFZbAIOyLn01/M08UXDY3Kh4 Nx0sk8NLNNp6HkY3xO05wFYYwkw8D4RTWCzKzQ3iXrNuE1AmdRYic3vXl5m6aejNIQf0 CnHBYTZ4eEMBc+IVlor9u0XryzWSnXQakJp1VHzPx7OA10Tq+EeTLyg1lUaQD94J/FGx yzig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QcmFmBVnSnD2tbZxnT4h9jKt0idY/F3KyHEdb6MSBsw=; b=YKDwaZFC29UJk0eoqoBm+qaldZ+EF1JcMzz4/3paLS6BlqDZfxUpBABygr8GULbA/b ItScUQOE0Wid8+wyu+wlr/hnUB1Gj/qQOIclzNqNwQBVk7KZYTbd2zsK5bbEP+qSpqW8 kElHhVwD9iIt/BYxJ9SQ3l1ota54X6oABn8vUb+zCZnqcaG5EK51gAIsuS2WlIoZ2CUs 1hdcoXlEV5WK25nqAGNT8PeokhqADET2K8pUcZ8leg66GyrL9/oJ9aU5mGEb3nB4Cekg H9GWtnlzAM0x8f+7ukE/0MWgo8I/ZMRLEqCRVQStf1apynMqf/WKWS9yE9b4apG1vOVH fTyQ== X-Gm-Message-State: AOAM533H63DHwUtjOM0XXFIY63Gvc5SqIPbeH8fZ5RRwgVzYQEPV2BfZ eF5ZCbN4yKIao4X3pe4618U= X-Google-Smtp-Source: ABdhPJyk49pY9W9zEZpUEEZqUfetKa2dcWj2MrSsrk/DyOLArCQT27PkU+BRwqnYTnkoPPhi8Gp/dQ== X-Received: by 2002:a05:6402:128d:: with SMTP id w13mr4013434edv.253.1622121412443; Thu, 27 May 2021 06:16:52 -0700 (PDT) Received: from localhost.localdomain ([188.24.140.160]) by smtp.gmail.com with ESMTPSA id r23sm1104206edq.59.2021.05.27.06.16.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 06:16:52 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoC Date: Thu, 27 May 2021 16:16:42 +0300 Message-Id: <107776b4a4e752ef83b143114d2baf52bf8c4107.1622119892.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are a few issues with the setup of the Actions Semi Owl S500 SoC's clock chain involving AHPPREDIV, H and AHB clocks: * AHBPREDIV clock is defined as a muxer only, although it also acts as a divider. * H clock is using a wrong divider register offset * AHB is defined as a multi-rate factor clock, but it is actually just a fixed pass clock. Let's provide the following fixes: * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition. * Use the correct register shift value in the OWL_DIVIDER definition for H clock * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an ungated OWL_COMP_FIXED_FACTOR definition. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea --- Changes in v2: - Reverted the addition of the clock div table for H clock to support the '1' divider (according to the datasheet), even though the vendor implementation marks it as reserved drivers/clk/actions/owl-s500.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 42d6899755e6..257923bd5386 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -153,11 +153,6 @@ static struct clk_factor_table hde_factor_table[] = { { 0, 0, 0 }, }; -static struct clk_factor_table ahb_factor_table[] = { - { 1, 1, 2 }, { 2, 1, 3 }, - { 0, 0, 0 }, -}; - static struct clk_div_table rmii_ref_div_table[] = { { 0, 4 }, { 1, 10 }, { 0, 0 }, @@ -186,7 +181,6 @@ static struct clk_div_table nand_div_table[] = { /* mux clock */ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); -static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); /* gate clocks */ static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0); @@ -199,16 +193,25 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0); static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); /* divider clocks */ -static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0); +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0); static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); /* factor clocks */ -static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0); static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0); static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ +static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, + OWL_MUX_HW(CMU_BUSCLK1, 8, 3), + { 0 }, + OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL), + 0); + +static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk", + { 0 }, + 1, 1, CLK_SET_RATE_PARENT); + static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), From patchwork Thu May 27 13:16:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 449668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90353C47089 for ; Thu, 27 May 2021 13:17:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7312061019 for ; Thu, 27 May 2021 13:17:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236429AbhE0NSc (ORCPT ); Thu, 27 May 2021 09:18:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236405AbhE0NS3 (ORCPT ); Thu, 27 May 2021 09:18:29 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DF62C061763; Thu, 27 May 2021 06:16:55 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id s22so7961390ejv.12; Thu, 27 May 2021 06:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S3aHrQGf4p/xVmD0XaAfsGhbFbf6GNiuGUtg3eCRd38=; b=k5xrEDxj0gWeyBttAbhARWTKhiJLjrhEsqtg0tqVCqyE1iu/C4cIFNGZQTUdfGSNP1 OyetBFAHOZg51L+UvkPFPZEyPVNj6WQGdIijLNJg96YWwlFTkZ/HlDBTWuX9mLtC0WAc RPsVmZmkK63gx2kAhJJjw42tw8/EZXmz0QHFx1RoDPaLFKaBFENXn40wiQ1ch0gtXa/H I63FpIfAAvcwb8hN4/GvCoXFAIj5yxUefaxEUzUgKHPC+BkCMw8FrbrBHIWxQcJN+971 S8hYc7/VuvadNwohY74U0sZXb4ktBmLJq4n+OQuLsB+rH4Q5q5n/7TX7T7clURmTXuJU z1hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S3aHrQGf4p/xVmD0XaAfsGhbFbf6GNiuGUtg3eCRd38=; b=tjmwPlcAkbTM1m72dq+Rae/dWnj28PTBOzL1y6+2EEtaKsNp5FfndZqWE6El0KYRCy qmvxe7t7K4DpIYw/SE24xCaIf1g3KCnY00a5VIll4/dnEn/I6X6USijroqS8Qni7Dk25 /O1ytZA2gKJsSCPH5wb0CFSkkr1LIgLuNh5ZVnjPbv7nz3VGPxpnFvvwVTRTuLkqOMpm WpC0/UI0ol2JKj/UTlx/7lbU7jqu3UERMbZztaW1YWoK78LTWH6a353FQlKKbDtj8a0g kwGgl6P13RN/TKdw4TELnoGwyBNqbnh1/jxyuUlvZ9JvSfaaq72AKIrayoApwOFfqn/i +CcQ== X-Gm-Message-State: AOAM53361E+LYvmsfGi7/ua0893DA1iMMBPtmnQTw8mYwlZnfIQNdKAB SjdjAFlvcDrsg16ORq0Jmqg= X-Google-Smtp-Source: ABdhPJwoP+XikdfWtRTxbQfXgf0nNJBGWOQ24EoA5v5gK2F7Zz6+w2udwJoS57XOVcmVg4YLguYnBQ== X-Received: by 2002:a17:906:dfc1:: with SMTP id jt1mr3753762ejc.473.1622121413958; Thu, 27 May 2021 06:16:53 -0700 (PDT) Received: from localhost.localdomain ([188.24.140.160]) by smtp.gmail.com with ESMTPSA id r23sm1104206edq.59.2021.05.27.06.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 06:16:53 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v2 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoC Date: Thu, 27 May 2021 16:16:43 +0300 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the missing NIC and ETHERNET clock bindings constants for Actions Semi Owl S500 SoC. Signed-off-by: Cristian Ciocaltea Acked-by: Rob Herring Reviewed-by: Manivannan Sadhasivam --- Changes in v2: - Added Acked-by from Rob include/dt-bindings/clock/actions,s500-cmu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h index a250a52a6192..a237eb26accb 100644 --- a/include/dt-bindings/clock/actions,s500-cmu.h +++ b/include/dt-bindings/clock/actions,s500-cmu.h @@ -74,10 +74,12 @@ #define CLK_RMII_REF 54 #define CLK_GPIO 55 -/* system clock (part 2) */ +/* additional clocks */ #define CLK_APB 56 #define CLK_DMAC 57 +#define CLK_NIC 58 +#define CLK_ETHERNET 59 -#define CLK_NR_CLKS (CLK_DMAC + 1) +#define CLK_NR_CLKS (CLK_ETHERNET + 1) #endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */ From patchwork Thu May 27 13:16:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 448988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35020C4708A for ; Thu, 27 May 2021 13:17:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15DCA61019 for ; Thu, 27 May 2021 13:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236464AbhE0NSk (ORCPT ); Thu, 27 May 2021 09:18:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236416AbhE0NSb (ORCPT ); Thu, 27 May 2021 09:18:31 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1C4FC06138C; Thu, 27 May 2021 06:16:56 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id l1so22736ejb.6; Thu, 27 May 2021 06:16:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qDp+pjL8u9TTvxzEepWTwup8whUcX1eXB/WptTlt9e0=; b=s0fnsdwLr45qkf4CZn1JxS4nBDV5pSTUnd82Xj/SCH/G3U+MGcDcZYtSIabAsJUh+c b96jp2GcWbWp/UaN34T319qvzF1H6nPqSwu9S774nyR8pcuJ3DDcuu09pQWq0ofAoz8J vyvuZQXnh99+EuAtDR4PzAc6KkK8N5ORKS3uyL3xq8eF2GD/FIl0+Rdqdo+nrrGPtU46 w6OKJNpfTte/NEWkC/Srmk5tZw0BF0LMqUX1TYzX7JgVJ4n7FocjgPLByOqZ3gmkQvS0 d/LgsDV7UiUEWS25jEsGwAsKcqi0QG3bKRrY43p6K728tCZNDiSDtuMwHkHFgTmmn6Lk bn6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qDp+pjL8u9TTvxzEepWTwup8whUcX1eXB/WptTlt9e0=; b=B6nNspzZFjmT3eBcIouVHKzDvOIREX/vx6eUeOiWtVBbQoa1KCNVtkfZ3xY/5kmaio rLIlFi+AacjrMs4i22JYkjVOeW3KD1bYbx0U5paxxF43I2oQeKaBGg8bv8oH8u5fyaXQ PnyU0wOQRQesvF7bhArHDZe792zo476q/TV2R8RxutjfH9WEdjJf+neHYE/rHzeEgNAY tmErHhgSTWssq93kBphrWjWTBwRM448Fijl6umQWs88taWH3T2mpAHJaB86O0Fnhe+Uw /CEVrn7Zt5awlg8Yy8skX+hUZcSCV04jDo3orS7LBBvKf+uSr2dE/1I2BWYHPo+Z+t3Y DQ/g== X-Gm-Message-State: AOAM5325Nq6QOqDfQWA2dsJ8VdDO8LduqXr2Grqeq3t70YqH+fCVtqyo jOaTt1FFLj9VPJvh5lksvnE= X-Google-Smtp-Source: ABdhPJyUbuiCDS8W6AcHzx60wAAVddrQEg39dMErk3zlG0aQPtEDEGUEaJpjSD5TRhw+TNVswGhWgQ== X-Received: by 2002:a17:906:4c54:: with SMTP id d20mr3812329ejw.513.1622121415293; Thu, 27 May 2021 06:16:55 -0700 (PDT) Received: from localhost.localdomain ([188.24.140.160]) by smtp.gmail.com with ESMTPSA id r23sm1104206edq.59.2021.05.27.06.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 May 2021 06:16:54 -0700 (PDT) From: Cristian Ciocaltea To: Stephen Boyd , Rob Herring , Manivannan Sadhasivam , =?utf-8?q?A?= =?utf-8?q?ndreas_F=C3=A4rber?= , Michael Turquette , Edgar Bernardi Righi Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 6/6] clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoC Date: Thu, 27 May 2021 16:16:44 +0300 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the missing NIC and ETHERNET clocks in the Actions Semi Owl S500 SoC clock driver. Additionally, change APB clock parent from AHB to the newly added NIC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Manivannan Sadhasivam --- Changes in v2: - Reordered "nic_clk_mux_p" after "ahbprediv_clk_mux_p" to follow the reg field ordering drivers/clk/actions/owl-s500.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 257923bd5386..a9c7e06ebcd6 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -113,6 +113,7 @@ static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" }; static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" }; static const char * const pwm_clk_mux_p[] = { "losc", "hosc" }; static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; +static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" }; static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" }; static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" }; static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" }; @@ -194,7 +195,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); /* divider clocks */ static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0); -static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); +static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); /* factor clocks */ @@ -202,6 +203,12 @@ static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ +static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p, + OWL_MUX_HW(CMU_BUSCLK1, 4, 3), + { 0 }, + OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL), + 0); + static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, OWL_MUX_HW(CMU_BUSCLK1, 8, 3), { 0 }, @@ -317,6 +324,10 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 1, 5, 0); +static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk", + OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), + 1, 20, 0); + static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), @@ -451,6 +462,8 @@ static struct owl_clk_common *s500_clks[] = { &apb_clk.common, &dmac_clk.common, &gpio_clk.common, + &nic_clk.common, + ðernet_clk.common, }; static struct clk_hw_onecell_data s500_hw_clks = { @@ -510,6 +523,8 @@ static struct clk_hw_onecell_data s500_hw_clks = { [CLK_APB] = &apb_clk.common.hw, [CLK_DMAC] = &dmac_clk.common.hw, [CLK_GPIO] = &gpio_clk.common.hw, + [CLK_NIC] = &nic_clk.common.hw, + [CLK_ETHERNET] = ðernet_clk.common.hw, }, .num = CLK_NR_CLKS, };