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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 01/22] x86/sev: shorten GHCB terminate macro names Date: Wed, 2 Jun 2021 09:03:55 -0500 Message-Id: <20210602140416.23573-2-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; 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+ sev_es_terminate(GHCB_SEV_ES_PROT_UNSUPPORTED); if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; @@ -175,7 +175,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) enum es_result result; if (!boot_ghcb && !early_setup_sev_es()) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); result = vc_init_em_ctxt(&ctxt, regs, exit_code); @@ -202,5 +202,5 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) if (result == ES_OK) vc_finish_insn(&ctxt); else if (result != ES_RETRY) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 629c3df243f0..11b7d9cea775 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -54,8 +54,8 @@ (((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \ ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS)) -#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0 -#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1 +#define GHCB_SEV_ES_GEN_REQ 0 +#define GHCB_SEV_ES_PROT_UNSUPPORTED 1 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 6ec8b3bfd76e..14198075ff8b 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -207,7 +207,7 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) fail: /* Terminate the guest */ - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); } static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt, diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 9578c82832aa..460717e3f72d 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1383,7 +1383,7 @@ DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication) show_regs(regs); /* Ask hypervisor to sev_es_terminate */ - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); /* If that fails and we get here - just panic */ panic("Returned from Terminate-Request to Hypervisor\n"); @@ -1416,7 +1416,7 @@ bool __init handle_vc_boot_ghcb(struct pt_regs *regs) /* Do initial setup or terminate the guest */ if (unlikely(boot_ghcb == NULL && !sev_es_setup_ghcb())) - sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST); + sev_es_terminate(GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); From patchwork Wed Jun 2 14:03:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3166C4709B for ; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 02/22] x86/sev: Define the Linux specific guest termination reasons Date: Wed, 2 Jun 2021 09:03:56 -0500 Message-Id: <20210602140416.23573-3-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:41 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dbdacf02-317b-4f14-6551-08d925cf5e5a X-MS-TrafficTypeDiagnostic: SA0PR12MB4512: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0HljAJUMv2piUD3WlQBYqwoZaFrVUmgMOgIMTf/ZHpSFDAZQolPY6V/EhRsuE4n5bZkFhKF94FcetQx63vBf2RQfkO3qxOrJMG1DTcs1L0S9xpCvn/ehZy7JXAkDAKJCC4md4yAKHLKEOKKzUT5oy0kPbEP9LwKCcuYGyewIH/whTJ209nii7qlGHOxyBHgRHU0kOqNk+0ug6lSn630DTTnZiU8yVVfj0ALRA2noeIUiV2W/6YNcUS7dDC+6chULzCGVxt6PqL4Tup39KH1XHacTG6eGBRj0AODVpOdHv4V3Rpr66/c7blDYcvFaeYjGGLr6u7t/Q5J8vbOlHCYiMUh4xqEyQjlTxHpCOKejkDiB9IzdvI8UtCbXB77TGYt/F+nP6aQrmZOIFBNR8qg7qF4cGpsFZ3kkwmLFW8n6k+RYOTbG6xPkaeD7AQLvct6gJMC4p3tQeuROBme0sey1zkle5hSZrbtEztMGP8yb+QJeWLMsLrHO1l0bhqBlHSdAhrxIesgWTJRhf0JwXo5UePxiF1f80w9Cfu7hKYmg+TsBnRNjsdqsdPS8B3sPd59tkmbz/MO08KXcYeSmLnIaFc9hA2ZNA37aa+5A3uNG+u0xItaXQLOkTRTPP7xpQcFMZXiFVd5j/6+qkN6ZqCcleBjacrk7GqoEWX3TMsJdWRk= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(39860400002)(136003)(6666004)(44832011)(7416002)(26005)(2906002)(8676002)(6486002)(7696005)(52116002)(38100700002)(478600001)(956004)(66556008)(186003)(1076003)(36756003)(8936002)(16526019)(66946007)(83380400001)(38350700002)(5660300002)(2616005)(54906003)(4326008)(86362001)(66476007)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: lRapv/AGxDDbJbsx9eWs2It0XxN/sDgroLQdPPLY4ywbCnILkfsBZMqEzeykEObcdv1NjrNqtAnEsbEOPW4EZEPElacWP8GmRBpPkdSD8ys0w9+CYHpeBwviGyelKsExYqhajpuBMMlfe0Fu27NyM1dWn+0zYomfUGSOiAO4VHJ1wBSbe6gKMJH8Pfl+YdGGS06p/QhEMvXyhtptMKD2/QIqzgJV97zBeGfxHor/rZ1ifY8pDBH9X1AFpLedGpgGOKI4igqziXvw3l7AdpWk2gJV6zlyu9pcV2fwmGwIIzns//90a10oL9+L7/tS89HsFtu6cUjo34PC39LhLQRljGFBL/FTo/UM7asZi7aFNUZ5JUJxsA78hE4AP3zxgXx6+YHSjSIMSe1YNqSjuTgKBu7DBw7+BvYXUtcgcs7+axlNTVED2mqQgRTbvCcosnJ9ZDemb4gS/zenZiiAesmRiRKTQMwJhe5Uf+CUC0/CVz5wnsYqLgfIPkx8o+B4q78D4Gw3SlWkxdCy0jYvajLFEpiTF4h48/YFHINDtnt5fDZigJL+DamfcBdhzKK9tynQS215lL+9lgm3M9XZ2qdpEnPGgv952fZmV88Tyym0LhgNCV4gqy6ZoNTV9Ibs+XsUYPtpMduiPOwNyhKFitnlL1nGJ9nDDC+/1Z3YGzlYBwi8gYpwgqrYwY7F77/+cN1nv/IGmF2LNn0jdoZuk2elGeS+DP8JA9tXInWEZRBjgNClG1NvvU69bs8ExjhIhvNYvL8TBuPWPgF13oart/sV1xG9N9CV3OjgplbkRYODo3fkBTNo6mLgCaPI0bi8qI9eVyOlhSYYnAKcPdygyCXFmccBPhGz/MgD84qf9Qo9O+nJ03sHGPJK252gg1+0aIXibUeIJeD2vNvSfTQ50d1jCIICg31rEY/a0sCS3u/S0y5Cd5h8gektxC6r/agQk/gpJ9btleHEko7scr/BNGg97bhOvxTAe6RV1uM/haEW9ZQdVF2Sn906icJjIVk3C330cthEiCcGE3wGJizB7BGmVgrPOsyQhXugi6tDInLZoRpKbyEkhvWfFKkRt0v4ggnIKhv98TI2EmwkQQX6y53cT+uVmhXn8qDP1xwGdVmJ2dEemPB/TQb2TFOEYrnDK3U7vjZ7onAuyfrfHP8JDrv9o6hSiOaMkPOm7pKP/pDjrm+yNSOfYRX+zLZw8bXxhCC0Y+x5eQePm0A5UtNugMvbiqA40eCNhqr+qmN3nq/4HyYHqcLtgfvLkcL8KzT2yUcAA6iVMELWOKrbiqska09HyIbtQNo/Eem58xxnKIKnHJ3bvUzTXPH671AqPwOGGuru X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: dbdacf02-317b-4f14-6551-08d925cf5e5a X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:42.3115 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: sMkzeT5jv+LZP/Rixi2qLwXMPWBmEjSEFnC/OZU+DtTFfWrwmsNir4hCtYNBx1kaaGEksqzoP+cMSaOAIx+w6w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4512 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org GHCB specification defines the reason code for reason set 0. The reason codes defined in the set 0 do not cover all possible causes for a guest to request termination. The reason set 1 to 255 is reserved for the vendor-specific codes. Reseve the reason set 1 for the Linux guest. Define an error codes for reason set 1. While at it, change the sev_es_terminate() to accept the reason set parameter. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 6 +++--- arch/x86/include/asm/sev-common.h | 5 +++++ arch/x86/kernel/sev-shared.c | 6 +++--- arch/x86/kernel/sev.c | 4 ++-- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 28bcf04c022e..87621f4e4703 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -122,7 +122,7 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, static bool early_setup_sev_es(void) { if (!sev_es_negotiate_protocol()) - sev_es_terminate(GHCB_SEV_ES_PROT_UNSUPPORTED); + sev_es_terminate(0, GHCB_SEV_ES_PROT_UNSUPPORTED); if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; @@ -175,7 +175,7 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) enum es_result result; if (!boot_ghcb && !early_setup_sev_es()) - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(0, GHCB_SEV_ES_GEN_REQ); vc_ghcb_invalidate(boot_ghcb); result = vc_init_em_ctxt(&ctxt, regs, exit_code); @@ -202,5 +202,5 @@ void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code) if (result == ES_OK) vc_finish_insn(&ctxt); else if (result != ES_RETRY) - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(0, GHCB_SEV_ES_GEN_REQ); } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 11b7d9cea775..f1e2aacb0d61 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -59,4 +59,9 @@ #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) +/* Linux specific reason codes (used with reason set 1) */ +#define GHCB_TERM_REGISTER 0 /* GHCB GPA registration failure */ +#define GHCB_TERM_PSC 1 /* Page State Change failure */ +#define GHCB_TERM_PVALIDATE 2 /* Pvalidate failure */ + #endif diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 14198075ff8b..de0e7e6c52b8 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -24,7 +24,7 @@ static bool __init sev_es_check_cpu_features(void) return true; } -static void __noreturn sev_es_terminate(unsigned int reason) +static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) { u64 val = GHCB_MSR_TERM_REQ; @@ -32,7 +32,7 @@ static void __noreturn sev_es_terminate(unsigned int reason) * Tell the hypervisor what went wrong - only reason-set 0 is * currently supported. */ - val |= GHCB_SEV_TERM_REASON(0, reason); + val |= GHCB_SEV_TERM_REASON(set, reason); /* Request Guest Termination from Hypvervisor */ sev_es_wr_ghcb_msr(val); @@ -207,7 +207,7 @@ void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) fail: /* Terminate the guest */ - sev_es_terminate(GHCB_SEV_ES_GEN_REQ); + sev_es_terminate(0, GHCB_SEV_ES_GEN_REQ); } static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt, diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 460717e3f72d..77a754365ba9 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1383,7 +1383,7 @@ DEFINE_IDTENTRY_VC_SAFE_STACK(exc_vmm_communication) show_regs(regs); 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Cache the negotiated GHCB version so that it can be used later. Signed-off-by: Brijesh Singh Reviewed-by: Venu Busireddy --- arch/x86/include/asm/sev.h | 2 +- arch/x86/kernel/sev-shared.c | 15 ++++++++++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index fa5cd05d3b5b..7ec91b1359df 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -12,7 +12,7 @@ #include #include -#define GHCB_PROTO_OUR 0x0001UL +#define GHCB_PROTOCOL_MIN 1ULL #define GHCB_PROTOCOL_MAX 1ULL #define GHCB_DEFAULT_USAGE 0ULL diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index de0e7e6c52b8..70f181f20d92 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -14,6 +14,13 @@ #define has_cpuflag(f) boot_cpu_has(f) #endif +/* + * Since feature negotiation related variables are set early in the boot + * process they must reside in the .data section so as not to be zeroed + * out when the .bss section is later cleared. + */ +static u16 ghcb_version __section(".data"); + static bool __init sev_es_check_cpu_features(void) { if (!has_cpuflag(X86_FEATURE_RDRAND)) { @@ -54,10 +61,12 @@ static bool sev_es_negotiate_protocol(void) if (GHCB_MSR_INFO(val) != GHCB_MSR_SEV_INFO_RESP) return false; - if (GHCB_MSR_PROTO_MAX(val) < GHCB_PROTO_OUR || - GHCB_MSR_PROTO_MIN(val) > GHCB_PROTO_OUR) + if (GHCB_MSR_PROTO_MAX(val) < GHCB_PROTOCOL_MIN || + GHCB_MSR_PROTO_MIN(val) > GHCB_PROTOCOL_MAX) return false; + ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX); + return true; } @@ -101,7 +110,7 @@ static enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, enum es_result ret; /* Fill in protocol and format specifiers */ - ghcb->protocol_version = GHCB_PROTOCOL_MAX; + ghcb->protocol_version = ghcb_version; ghcb->ghcb_usage = GHCB_DEFAULT_USAGE; ghcb_set_sw_exit_code(ghcb, exit_code); From patchwork Wed Jun 2 14:03:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C2D0C47098 for ; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 04/22] x86/mm: Add sev_feature_enabled() helper Date: Wed, 2 Jun 2021 09:03:58 -0500 Message-Id: <20210602140416.23573-5-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:43 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d9df45f8-bd74-4bd9-89f6-08d925cf5faf X-MS-TrafficTypeDiagnostic: SA0PR12MB4512: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W4qCUcga+1tm5RIcQH19v9or1lxTOh2BVJq4Obmb2116FrM5PQm/SQwXjKB3UKEqP0JBaIdwJlaCVBd41e05L7Vs0c1Vbk/SmW9cPDUKdO6f1jPL6mlQZAUeM+quN6sWfMPF520pr22MvcvyN2cg0vL/PPV/U6BqpRMk1DDQ3Kixyn872LRbomsHn07QnEdOYLPAodAkqJXOLHH/kvrXLxzWscqt5nlxqkxTN6jslfW7oxuZ+7UNwiK5IooWBl5XC07wQpEYj34EgYai//kvuXrYnm01xYDisAwvQqwp2dHoVK+KgWV91D2OZ/3mnAHt2a36PC+Eo94HSNrJVToVma9apijlrSwN6fud+qHQLjNeMbH0KvjFu3FuRzt/R5a7lUdWh6iwYbTE6AwuZPqBp3oVgK7siLyhDw1B+WC3igE86ugq0t7qZR//c7JKHQwGCXFiZf72MJDBiS3NIRTFgsG4ljCUf6pFGX/pUZe3g6kH6lCYgRnMnQaHcq+cq3S6KFjnhkWXPtYdTTmsExAj6STV3nUJA3/McDtvPU9inxznmxdgt32KXJqDT1dbq96zJt/KXhBQq8uX4azGoXnG12qpvQbFddmaxmb6mTLGyCTNbU+rjG0GM2y6ZNUDCt2ApstPRKwEfLyWr/Pq6SAIeA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(39860400002)(136003)(6666004)(44832011)(7416002)(26005)(2906002)(8676002)(6486002)(7696005)(52116002)(38100700002)(478600001)(956004)(66556008)(186003)(1076003)(36756003)(8936002)(16526019)(66946007)(38350700002)(5660300002)(2616005)(54906003)(4326008)(86362001)(66476007)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: sQmOus0PIkuB+UUfBy3b5b4U/fKErMpKFPgXiATbmAiziausYTNHITNm33eHhGKybDdp4hhyFiePYlbsd68PGYVZlYznCPAgpzSPx5xgyM+3qBqev6S5F/dhV3O0vKM9wH3tIMgdn1jUSRaKxO42hHE3niyRgWQIXpxTOkR32VCBTixmiDfBOseAMONJ9bgDdkuPTmNulg4MfFzGIAMlq8f0segOkGbtWcj/jcJ+5iIUEw3+9qrV3baU0T/riYBtMuyyeDdC6eq90UNhYdGeF+GfSZFyjieIC8KeXx/27ZRJqsFy0gRQ9vMkf7bK2lwF/IPkelSI6Kwy5BEoykNSYqJnu3Uvoif0/1itCtP8GKaSSTtlvt+IIz9oCaJqZ9v1ODMyaU3QT//n6wUYdzuMJwSQh6KCSQsmfbbq+oMU7TQMi6lLp66RxDdlqG/Zgt+z8CmCg7pEU03Nx5KDHai9bDWd7KwRgEBxmlF/x7ISncKgyDBQNSEfX16KMgj4GbQMhdBM4P96whUQ3I138w4dTcF5swSHWWBI+5dA7YO7Bbl8rkbU3nmqUrgORNZfCaKnk65yqnkYddynmAJrTfXtlpje/698U7s9p7f8t/N6TZdtECnOF8RTtjYOncqu0W4J1iI6a6qni3fOi09WBAbuhVm1yYGq2uZ1EA+C8GlKvuxusComeLZHCuAPqqddXKGeIUE3/dke7LZBi7I/CJXIl3D5PownzliZyMrvql4jzRIFaD/kw78psfqmzLFQ+aFNkuGp/L3Udd2AhadjBlvVhui8ZlkpGlJDMFdL7ZIWXPtCJcU39tq0jL8rrWFaQPug0fhQ9kT4W7CD4fEu88c2SKCnItFaW9uPffcIZCupGO/BBJSVgmrwzqpOauJyTM5x5+PbCsWIj1Q5PnaKZdeBfsNXx1iAttgnGoJMXgabBa01RKKfdekYDqCgtAhPS0aAN1FnVpNMUEDDOuqrE48bNeMk7ahyKBLktMs5KFihW8DC9WBPB0V7mZlpMBGl8rF3Xyu6nPqNdGkVKzVL3NRSG6xFlTC9Gsz+/RE9ssnNpPr7csl9U+RTTBbIE7pV4jk651Ldhsn0JL+B9yGTv2444wcliboZLzUrXjjsjEfq3hEA3OH3yqZ+JrGHj+7j0X5U456wkTlnY7thn/Jji3t2k6Urg0/KjDAFTuvAXpQCFfUjCfZ7vLkjG6dr0wUAxP0ch34pvnlMpzVJ4RX1yEO8gnIjBDuPRPi8bK5EfuFjc0evrGNt9XMd9XFzrQn2/w85HnP3ZJw3bF4Bio55faUih2Ns2h191fksXx9kcsJltZcFEeUOPGP+1NLEOsyh4MYv X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d9df45f8-bd74-4bd9-89f6-08d925cf5faf X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:44.5582 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lWwtlS5vwExEVvI3ord/e1blSOBoaqF/6JTb00W7keg0+BOFR9HlP/5BdLFN8EOWpduhMCP6YDwmcy/NjLPz5w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4512 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The sev_feature_enabled() helper can be used by the guest to query whether the SNP - Secure Nested Paging feature is active. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/mem_encrypt.h | 9 +++++++++ arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/mm/mem_encrypt.c | 14 ++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h index 9c80c68d75b5..bcc00d0d7c20 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -16,6 +16,12 @@ #include +enum sev_feature_type { + SEV, + SEV_ES, + SEV_SNP +}; + #ifdef CONFIG_AMD_MEM_ENCRYPT extern u64 sme_me_mask; @@ -53,6 +59,7 @@ void __init sev_es_init_vc_handling(void); bool sme_active(void); bool sev_active(void); bool sev_es_active(void); +bool sev_feature_enabled(unsigned int feature_type); #define __bss_decrypted __section(".bss..decrypted") @@ -78,6 +85,7 @@ static inline void sev_es_init_vc_handling(void) { } static inline bool sme_active(void) { return false; } static inline bool sev_active(void) { return false; } static inline bool sev_es_active(void) { return false; } +static inline bool sev_snp_active(void) { return false; } static inline int __init early_set_memory_decrypted(unsigned long vaddr, unsigned long size) { return 0; } @@ -85,6 +93,7 @@ static inline int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size) { return 0; } static inline void mem_encrypt_free_decrypted_mem(void) { } +static bool sev_feature_enabled(unsigned int feature_type) { return false; } #define __bss_decrypted diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 211ba3375ee9..69ce50fa3565 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -481,8 +481,10 @@ #define MSR_AMD64_SEV 0xc0010131 #define MSR_AMD64_SEV_ENABLED_BIT 0 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 +#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) +#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index ff08dc463634..63e7799a9a86 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -389,6 +389,16 @@ bool noinstr sev_es_active(void) return sev_status & MSR_AMD64_SEV_ES_ENABLED; } +bool sev_feature_enabled(unsigned int type) +{ + switch (type) { + case SEV: return sev_status & MSR_AMD64_SEV_ENABLED; + case SEV_ES: return sev_status & MSR_AMD64_SEV_ES_ENABLED; + case SEV_SNP: return sev_status & MSR_AMD64_SEV_SNP_ENABLED; + default: return false; + } +} + /* Override for DMA direct allocation check - ARCH_HAS_FORCE_DMA_UNENCRYPTED */ bool force_dma_unencrypted(struct device *dev) { @@ -461,6 +471,10 @@ static void print_mem_encrypt_feature_info(void) if (sev_es_active()) pr_cont(" SEV-ES"); + /* Secure Nested Paging */ + if (sev_feature_enabled(SEV_SNP)) + pr_cont(" SEV-SNP"); + pr_cont("\n"); } From patchwork Wed Jun 2 14:03:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 453585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCA27C47092 for ; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 05/22] x86/sev: Add support for hypervisor feature VMGEXIT Date: Wed, 2 Jun 2021 09:03:59 -0500 Message-Id: <20210602140416.23573-6-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:44 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bf98b167-3851-475a-225c-08d925cf6060 X-MS-TrafficTypeDiagnostic: SA0PR12MB4512: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MThO5AXiJl1+pIa/2heopZBBVy+VWG61ljYuNkNAflXoR2N4irKSbK/uya/DtRPTRwlALZbWeNNOju2eFuQlZYltayRU5n0mYQsUUoiEz/0itEES7QegJnG0yMkBcLaUvtBYGTgDs1VL8hrv6uggANT4zBtP+odJUFXaabSTSG6z6X84xV6NcRCqVVWYIMnmovf4jArwUW6FLDEK6+BXojtEpn9NTL1DkfO7Oxqhg+VPP8hK6CMz/9el1d1zgh+cJxZuvaeJAUEN5AQml+FwRW5URANcfwBAL1PNSvjMlkriEPI/if1nCr6OsZiH0nSqaINaLBfYWE82nG+/+CvDZg0EeTiKKggy2Gq2hlH8y01S/k/1PvYgov0IRgGnha8I+HFbRCZwgvtfY6n3S21rGwOWY1xP7wHvkNKJzhzNLn/kTM/T9TbXu36v7G3lEQMzZFi/ya6z4W1/LlvNC07VQg1iE0EsuOWqFcuaxov818PIzHHryKG6Gc+CkpETAHWLXTN7EXnOBkmYHeWa6jGLQzyI7LSjoUiEYBFMlknWcIHfvCMpq/pkRgIIXOXhfEDgIctNB0g+lZHUUgMvGLkYB3VyOIfc0oTstRKNeEMN/S2f1/UQTl6nMvAQ4BxzzFkGxfc+NJVj8iGnLpxHGuPMhQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(39860400002)(136003)(6666004)(44832011)(7416002)(26005)(2906002)(8676002)(6486002)(7696005)(52116002)(38100700002)(478600001)(956004)(66556008)(186003)(1076003)(36756003)(8936002)(16526019)(66946007)(83380400001)(38350700002)(5660300002)(2616005)(54906003)(4326008)(86362001)(66476007)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: asaLTQzU+n5OkbM/bOqpG0waJeqVvFYR58RKAXAVxq+na03noRDwWQqtOPcmqTdM1LFXiElFjxmvaTsP366ICfq66vHVrk+cn6KtDCqtJ8zLs4BUPiA/oAAnC04ZZ+UoqpVHiEjY1GwuZFPqDdIiDxsLYB61E+/WI75Jx2P7rRauZCjtFWW5edVGGytHSvpZGBd5z9NOxX+Vo7Ur3B6+ssQHXrWdXjZb2hpkOdj3pWimFN0oEvj8Lx62FtirXluOJr/6lvkwbCVKl1O30WAZuPhDMJEyxeQjHAzHumxPtNcnWj+t4+kkLlcJSA5zRxGpz4Pa9u62XZ5blfB2Dw6Tt053+DuynoR+k/j2hjAcIYXTHVSfWRKh7cs6b/RmX7Ky7yXZBbSqk22d1dp9Ax/QM2Ig/VBSYryQ7B/YRRlcEluP9tCN1hSDYzaO6ZYQwK6kCqGeJhpkulcYmR52aq3GEvOaKvvCqzvswZXnp9PvySyHaXTSgacIo4bKQofTe3Us96qZz8kNx3H5Kl13BCgEOOjb0gSHyji2KAkeTck+R8c5KPen4gLftQTHfgSMOAIjAcSteZ1WU5eF1LFaq5WL53H4hhnNYOdth7p85InfoOYsQuOvUv6VSOgkXl4a6T4k8wLhLPm4ZjIy/QtucfLBxWKpSow/p0PMNr4l0Eyzr6gMF/VsNDlhly0emmRwMAJYDfW3D828/FvKck/FQAaJC8f/BVdGfMNd8XeuxDqGwZJ7dR6VOzH2XIyvVFYVT0mTPA2mEOtMCIfDJVzO/Rzg0qG1S+JIX5bE4zRbrXW/A2DH/e92/tdr7M7GwoqUPxhC2O004Emk1j+nslIm5zw7U1n9T4vYFACw0jO15wVAaldsZhstLyJZzXFLc+0M+0LvCnZ2v94g9RSwDgROqPYHbsHqHba7GEAU2GYJ7NE1I+nC3dvWSZf1pCAHObb3SmraAFeMSH+/Kl5gKyIE31psfdUr/Drtp9ajfKcVjqrPUyC5HUYH9ua6MY4ZDzbhZ1EU9EPYYOyBTPeoSSuAT1R3lhzXWPTj3yOJKV/gY8dDuGWdeMa3kI7GeC018miVA2P+FO6XjEhYNbnvnngEqclBwKEmutY2I4qY8+0DzKH8ntS2wSh6giJ0wZsYqHmUbOigcaeG+S/DV2GVssKS4wO3QoGOI0tVFZJd/AJoSV117kQoV8nC96tU307Egk8SyarcwxLAzY1rjX+FkpiQb2ZoOuSdVKQx9fvoAvLm0Blpk+VRxqP0BsIy4dI0619AeWva703rWlAqhDgmhmoUo6MRQ6KRJwNi/tbeFu5RFnymL0Hw5Upp9XUX4HkoZ+q7/Ywl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf98b167-3851-475a-225c-08d925cf6060 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:45.6915 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9Qd19yKsuzEICjeM1hhxFnw1p7EjJAyFMrdrcCk7CtbpJYou8svrsioqe51vqTOzvLjp8rBp7uTzdhMmJu1low== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4512 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org Version 2 of GHCB specification introduced advertisement of a features that are supported by the hypervisor. Define the GHCB MSR protocol and NAE for the hypervisor feature request and query the feature during the GHCB protocol negotitation. See the GHCB specification for more details. Version 2 of GHCB specification adds several new NAEs, most of them are optional except the hypervisor feature. Now that hypervisor feature NAE is implemented, so bump the GHCB maximum support protocol version. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 9 +++++++++ arch/x86/include/asm/sev.h | 2 +- arch/x86/kernel/sev-shared.c | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index f1e2aacb0d61..981fff2257b9 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -45,6 +45,15 @@ (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) +/* GHCB Hypervisor Feature Request */ +#define GHCB_MSR_HV_FT_REQ 0x080 +#define GHCB_MSR_HV_FT_RESP 0x081 +#define GHCB_MSR_HV_FT_POS 12 +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) + +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ + (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7ec91b1359df..134a7c9d91b6 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -13,7 +13,7 @@ #include #define GHCB_PROTOCOL_MIN 1ULL -#define GHCB_PROTOCOL_MAX 1ULL +#define GHCB_PROTOCOL_MAX 2ULL #define GHCB_DEFAULT_USAGE 0ULL #define VMGEXIT() { asm volatile("rep; vmmcall\n\r"); } diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 70f181f20d92..94957c5bdb51 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -20,6 +20,7 @@ * out when the .bss section is later cleared. */ static u16 ghcb_version __section(".data"); +static u64 hv_features __section(".data"); static bool __init sev_es_check_cpu_features(void) { @@ -49,6 +50,22 @@ static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) asm volatile("hlt\n" : : : "memory"); } +static bool get_hv_features(void) +{ + u64 val; + + sev_es_wr_ghcb_msr(GHCB_MSR_HV_FT_REQ); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + if (GHCB_RESP_CODE(val) != GHCB_MSR_HV_FT_RESP) + return false; + + hv_features = GHCB_MSR_HV_FT_RESP_VAL(val); + + return true; +} + static bool sev_es_negotiate_protocol(void) { u64 val; @@ -67,6 +84,10 @@ static bool sev_es_negotiate_protocol(void) ghcb_version = min_t(size_t, GHCB_MSR_PROTO_MAX(val), GHCB_PROTOCOL_MAX); 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If hypervisor supports the SEV-SNP then it must set the SEV-SNP features bit to indicate that the base SEV-SNP is supported. Check the SEV-SNP feature while establishing the GHCB, if failed, terminate the guest. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 22 ++++++++++++++++++++++ arch/x86/include/asm/sev-common.h | 3 +++ arch/x86/kernel/sev-shared.c | 11 +++++++++++ arch/x86/kernel/sev.c | 4 ++++ 4 files changed, 40 insertions(+) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 87621f4e4703..0745ea61d32e 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -25,6 +25,7 @@ struct ghcb boot_ghcb_page __aligned(PAGE_SIZE); struct ghcb *boot_ghcb; +static u64 msr_sev_status; /* * Copy a version of this function here - insn-eval.c can't be used in @@ -119,11 +120,32 @@ static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, /* Include code for early handlers */ #include "../../kernel/sev-shared.c" +static inline bool sev_snp_enabled(void) +{ + unsigned long low, high; + + if (!msr_sev_status) { + asm volatile("rdmsr\n" + : "=a" (low), "=d" (high) + : "c" (MSR_AMD64_SEV)); + msr_sev_status = (high << 32) | low; + } + + return msr_sev_status & MSR_AMD64_SEV_SNP_ENABLED; +} + static bool early_setup_sev_es(void) { if (!sev_es_negotiate_protocol()) sev_es_terminate(0, GHCB_SEV_ES_PROT_UNSUPPORTED); + /* + * If SEV-SNP is enabled, then check if the hypervisor supports the SEV-SNP + * features. + */ + if (sev_snp_enabled() && !sev_snp_check_hypervisor_features()) + sev_es_terminate(0, GHCB_SEV_ES_SNP_UNSUPPORTED); + if (set_page_decrypted((unsigned long)&boot_ghcb_page)) return false; diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 981fff2257b9..3ebf00772f26 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -51,6 +51,8 @@ #define GHCB_MSR_HV_FT_POS 12 #define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) +#define GHCB_HV_FT_SNP BIT_ULL(0) + #define GHCB_MSR_HV_FT_RESP_VAL(v) \ (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) @@ -65,6 +67,7 @@ #define GHCB_SEV_ES_GEN_REQ 0 #define GHCB_SEV_ES_PROT_UNSUPPORTED 1 +#define GHCB_SEV_ES_SNP_UNSUPPORTED 2 #define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 94957c5bdb51..b8312ad66120 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -32,6 +32,17 @@ static bool __init sev_es_check_cpu_features(void) return true; } +static bool __init sev_snp_check_hypervisor_features(void) +{ + if (ghcb_version < 2) + return false; + + if (!(hv_features & GHCB_HV_FT_SNP)) + return false; + + return true; +} + static void __noreturn sev_es_terminate(unsigned int set, unsigned int reason) { u64 val = GHCB_MSR_TERM_REQ; diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 77a754365ba9..9b70b7332614 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -609,6 +609,10 @@ static bool __init sev_es_setup_ghcb(void) if (!sev_es_negotiate_protocol()) return false; + /* If SNP is active, make sure that hypervisor supports the feature. */ + if (sev_feature_enabled(SEV_SNP) && !sev_snp_check_hypervisor_features()) + sev_es_terminate(0, GHCB_SEV_ES_SNP_UNSUPPORTED); + /* * Clear the boot_ghcb. The first exception comes in before the bss * section is cleared. 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 07/22] x86/sev: Add a helper for the PVALIDATE instruction Date: Wed, 2 Jun 2021 09:04:01 -0500 Message-Id: <20210602140416.23573-8-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; 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Upon completion, a return code is stored in EAX and rFLAGS bits are set based on the return code. If the instruction completed successfully, the CF indicates if the content of the RMP were changed or not. See AMD APM Volume 3 for additional details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 134a7c9d91b6..1b7a172b832b 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -59,6 +59,9 @@ extern void vc_no_ghcb(void); extern void vc_boot_ghcb(void); extern bool handle_vc_boot_ghcb(struct pt_regs *regs); +/* Software defined (when rFlags.CF = 1) */ +#define PVALIDATE_FAIL_NOUPDATE 255 + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); @@ -81,12 +84,29 @@ static __always_inline void sev_es_nmi_complete(void) __sev_es_nmi_complete(); } extern int __init sev_es_efi_map_ghcbs(pgd_t *pgd); +static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) +{ + bool no_rmpupdate; + int rc; + + asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFF\n\t" + CC_SET(c) + : CC_OUT(c) (no_rmpupdate), "=a"(rc) + : "a"(vaddr), "c"(rmp_psize), "d"(validate) + : "memory", "cc"); + + if (no_rmpupdate) + return PVALIDATE_FAIL_NOUPDATE; + + return rc; +} #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { return 0; } static inline void sev_es_nmi_complete(void) { } static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; } +static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) { return 0; } #endif #endif From patchwork Wed Jun 2 14:04:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 453580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85E55C47096 for ; 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dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4512.namprd12.prod.outlook.com (2603:10b6:806:71::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.21; Wed, 2 Jun 2021 14:04:51 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:04:51 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 08/22] x86/compressed: Add helper for validating pages in the decompression stage Date: Wed, 2 Jun 2021 09:04:02 -0500 Message-Id: <20210602140416.23573-9-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:48 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5ee8f10f-f9eb-42f6-0a4b-08d925cf626d X-MS-TrafficTypeDiagnostic: SA0PR12MB4512: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nVZJtB8mHDlOZbULrnkGt0Hb8JSr9uhdZt1ObMwDglxpBeDoCn/QDHCZAVqyKaKsZxjFVqth32eEV2tms3eG1jafzKKPDAyhGYxrnouJELkrkqjChkk6ye/FTgttkWCSyAEcF3oMGsI2gW4ET/JBUkx9aMvjFKB60FCy9kU2aZkKi5cWeql97HlQFxmy8TGeSAEtOaiAZsspKtUE6c25mQ8YVPb23PgC2285muzcS3ds/r74YnK1bVn/0NK0hCrEFh1tqWl39xOisE43xqEHbsmLOc40DgNZn/xdkpo2wbraNDWkFHvVi8Uauz48xjj32x7v9inq8Xwm2nHz1mob/YWnQMh4sRPFOsUhlvjms+NIC/LZNo3sL+s9VLdy1XacLdZRziEh6id4EsKfgqqwJ3I0pS7CzcAXHoT4FUuNa0eBkG00bkL3RJUq0oOsDUbtNC/7MJMmv3Dpr5eWhYkvcCUrPrcw/tG3vst8CnFWar9PwOiSlTc3aGhMmivX/Y2Zw9HdOivkFqLTeKshhGRCqRkDW6n9mjRdjPk5IjJ6oNFLOUWwd2AeqJrg5QTjMn9xgy9TRDklrJzJOvRf6fdh373OKZHG99qBYMjuXct47/CeEBCN7q9qzcmU2jPOPrFmVgdCvjVsNyDgkg4Niyi1Aw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(39860400002)(136003)(6666004)(44832011)(7416002)(26005)(2906002)(8676002)(6486002)(7696005)(52116002)(38100700002)(478600001)(956004)(66556008)(186003)(1076003)(36756003)(8936002)(16526019)(66946007)(83380400001)(38350700002)(5660300002)(2616005)(54906003)(4326008)(86362001)(66476007)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: uLMakkphVov1r07YfUnuZs7g7UESZkczmIofTcASYK5LeEdP41BZ+ZIxrGUNphJLnIx0eJgXzb7uPvokIhstfoQxn74c4mzoF9byMLPiJBzpNBeP6RO2zWEVJOzwhq9B2W8wS0O1tW1By/qZ8nSPVUG4qLbM2m14r7HsQaGux+uV+I6e3Qb7S0TJx2ccnpYXIF2LQPIgGDHdCw7DOGpFeuHa3AAamdE7B3oXEtakhgbnGVKOtV55NkGnsRWfhP03aN8nqRoa3D/as6aTT3kTomeEkvMEcem7s32vyArboqN3YfTQImuFeWaehP70IpRwIeFfZEmGqWpRLqn709lO4IUWBaFJ4+th3W8QBlVcNXVFCKvMEcXVNqtTIO6m6tBdjMhguvKjAv2W0cdX/qnCiNNvfmfVTRExrxcHlExRgzDeg+iluCr6wD0U6cJIdn9VbCYcttHtUjvSsNk85Pddq489lC6tSaikPBkXAvi6BuE01vBpElPsfRfz1pbk3a50g9Hs32gFR+/3+LLra6nEK8L1AtX+iQWFJbDqaNn5alY3glWm3f0Hr9SkqIIA7v/wY2CFCf7MCMWj5scLwzonowqeF/f6dGhlCvROwicNyJi5SWLksLY2t5+5EVeZkTk262fPoxltHQdefpO+uOOr4wXL3tLE4SdagvEfAxO7hqCqfVaEPVA+gNqoOIuMCOsvLQbV7fXZdU2bI+/sSlZ57AfpmVkEOnm93995aTMAzLgiNUobFsZURvT7amUdBbHhMq+d4ieOZHKKXB9m5dWhHMV69rdppgDFQXsAe+B1PafgV+uWBN7eIrCtJ8ikYcO5AOV5AFCEEj3oj0k+JYPCF9maT+e4sMhuezeZLYaMkNLGoWnUmPGT1XdhmyzD1EtIKCM1izkMQhNt+cplGSkqa7p/11KLTvCc66g0AubA9esW1/amYs8/uZIVFKDlFH6apLKH9/G3anuDNsQxKZv9P6bUiH+wc6/rdsSatqOI0kjXk4erPtlZ8Xoon70zH86ttekCPx0z27v+Qw4LazorYKGY1wHcpnxmq7iA4jbgZo81oIAQh+O7OVbMV7n2WnEPRo1unjW+eAFz6NGrOsm+xBENxpq29yBZVuS+67M4/2lhRnwiW/tWvwQljIk6HYw1ApRe3w80mI8XKAG5y6JDoVoWepRW139cr19PUKwgOQdKxZKya0E5E2ZCUpMGyAZ0RoUYaF5tEG5rpLawzUhCEwPYdEE9k3rmKOUk51m1bMCb4c7pNySTb26ZRPYNRs9Wx8CfkNm+Zo/zCchsWxzLnjw8Aqcl4AI1Ltrcbk7Fiq9mm7Gr3hXJ7ArIh2xtIDG7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ee8f10f-f9eb-42f6-0a4b-08d925cf626d X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:50.4288 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gux3QjWOJjWqxMP2mWCEUFWyF3i1l8H5lI1cIAiLulbqiKwcx756f0sGtJ9h76WZDaWlqfrAN9lPtKWFd0YKog== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4512 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org Many of the integrity guarantees of SEV-SNP are enforced through the Reverse Map Table (RMP). Each RMP entry contains the GPA at which a particular page of DRAM should be mapped. The VMs can request the hypervisor to add pages in the RMP table via the Page State Change VMGEXIT defined in the GHCB specification. Inside each RMP entry is a Validated flag; this flag is automatically cleared to 0 by the CPU hardware when a new RMP entry is created for a guest. Each VM page can be either validated or invalidated, as indicated by the Validated flag in the RMP entry. Memory access to a private page that is not validated generates a #VC. A VM must use PVALIDATE instruction to validate the private page before using it. To maintain the security guarantee of SEV-SNP guests, when transitioning pages from private to shared, the guest must invalidate the pages before asking the hypervisor to change the page state to shared in the RMP table. After the pages are mapped private in the page table, the guest must issue a page state change VMGEXIT to make the pages private in the RMP table and validate it. On boot, BIOS should have validated the entire system memory. During the kernel decompression stage, the VC handler uses the set_memory_decrypted() to make the GHCB page shared (i.e clear encryption attribute). And while exiting from the decompression, it calls the set_page_encrypted() to make the page private. Add sev_snp_set_page_{private,shared}() helper that is used by the set_memory_{decrypt,encrypt}() to change the page state in the RMP table. Signed-off-by: Brijesh Singh --- Hi Boris, As you pointed in the v2 feedback, the RMP_PG_SIZE_4K macro is later moved from sev-common.h to generic header file. You wanted to avoid the move and define the macro in generic from the get go. But that generic file is not included in part1 of the series so I kept the macro definition in sev-common.h and later moved to generic in part2 series. This is mainly to make sure that part1 compiles independently. -Brijesh arch/x86/boot/compressed/ident_map_64.c | 17 ++++++++- arch/x86/boot/compressed/misc.h | 6 ++++ arch/x86/boot/compressed/sev.c | 46 +++++++++++++++++++++++++ arch/x86/include/asm/sev-common.h | 19 ++++++++++ arch/x86/include/asm/sev.h | 3 ++ 5 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/x86/boot/compressed/ident_map_64.c b/arch/x86/boot/compressed/ident_map_64.c index f7213d0943b8..59befc610993 100644 --- a/arch/x86/boot/compressed/ident_map_64.c +++ b/arch/x86/boot/compressed/ident_map_64.c @@ -274,16 +274,31 @@ static int set_clr_page_flags(struct x86_mapping_info *info, /* * Changing encryption attributes of a page requires to flush it from * the caches. + * + * If the encryption attribute is being cleared, then change the page + * state to shared in the RMP table. */ - if ((set | clr) & _PAGE_ENC) + if ((set | clr) & _PAGE_ENC) { clflush_page(address); + if (clr) + snp_set_page_shared(pte_pfn(*ptep) << PAGE_SHIFT); + } + /* Update PTE */ pte = *ptep; pte = pte_set_flags(pte, set); pte = pte_clear_flags(pte, clr); set_pte(ptep, pte); + /* + * If the encryption attribute is being set, then change the page state to + * private in the RMP entry. The page state must be done after the PTE + * is updated. + */ + if (set & _PAGE_ENC) + snp_set_page_private(pte_pfn(*ptep) << PAGE_SHIFT); + /* Flush TLB after changing encryption attribute */ write_cr3(top_level_pgt); diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h index e5612f035498..49a2a5848eec 100644 --- a/arch/x86/boot/compressed/misc.h +++ b/arch/x86/boot/compressed/misc.h @@ -121,12 +121,18 @@ void set_sev_encryption_mask(void); #ifdef CONFIG_AMD_MEM_ENCRYPT void sev_es_shutdown_ghcb(void); extern bool sev_es_check_ghcb_fault(unsigned long address); +void snp_set_page_private(unsigned long paddr); +void snp_set_page_shared(unsigned long paddr); + #else static inline void sev_es_shutdown_ghcb(void) { } static inline bool sev_es_check_ghcb_fault(unsigned long address) { return false; } +static inline void snp_set_page_private(unsigned long paddr) { } +static inline void snp_set_page_shared(unsigned long paddr) { } + #endif /* acpi.c */ diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 0745ea61d32e..808fe1f6b170 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -134,6 +134,52 @@ static inline bool sev_snp_enabled(void) return msr_sev_status & MSR_AMD64_SEV_SNP_ENABLED; } +static void __page_state_change(unsigned long paddr, int op) +{ + u64 val; + + if (!sev_snp_enabled()) + return; + + /* + * If private -> shared then invalidate the page before requesting the + * state change in the RMP table. + */ + if ((op == SNP_PAGE_STATE_SHARED) && pvalidate(paddr, RMP_PG_SIZE_4K, 0)) + goto e_pvalidate; + + /* Issue VMGEXIT to change the page state in RMP table. */ + sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op)); + VMGEXIT(); + + /* Read the response of the VMGEXIT. */ + val = sev_es_rd_ghcb_msr(); + if ((GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP) || GHCB_MSR_PSC_RESP_VAL(val)) + sev_es_terminate(1, GHCB_TERM_PSC); + + /* + * Now that page is added in the RMP table, validate it so that it is + * consistent with the RMP entry. + */ + if ((op == SNP_PAGE_STATE_PRIVATE) && pvalidate(paddr, RMP_PG_SIZE_4K, 1)) + goto e_pvalidate; + + return; + +e_pvalidate: + sev_es_terminate(1, GHCB_TERM_PVALIDATE); +} + +void snp_set_page_private(unsigned long paddr) +{ + __page_state_change(paddr, SNP_PAGE_STATE_PRIVATE); +} + +void snp_set_page_shared(unsigned long paddr) +{ + __page_state_change(paddr, SNP_PAGE_STATE_SHARED); +} + static bool early_setup_sev_es(void) { if (!sev_es_negotiate_protocol()) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 3ebf00772f26..1424b8ffde0b 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -56,6 +56,25 @@ #define GHCB_MSR_HV_FT_RESP_VAL(v) \ (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) +#define GHCB_HV_FT_SNP BIT_ULL(0) + +/* SNP Page State Change */ +#define GHCB_MSR_PSC_REQ 0x014 +#define SNP_PAGE_STATE_PRIVATE 1 +#define SNP_PAGE_STATE_SHARED 2 +#define GHCB_MSR_PSC_GFN_POS 12 +#define GHCB_MSR_PSC_GFN_MASK GENMASK_ULL(39, 0) +#define GHCB_MSR_PSC_OP_POS 52 +#define GHCB_MSR_PSC_OP_MASK 0xf +#define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ + (((unsigned long)((op) & GHCB_MSR_PSC_OP_MASK) << GHCB_MSR_PSC_OP_POS) | \ + ((unsigned long)((gfn) & GHCB_MSR_PSC_GFN_MASK) << GHCB_MSR_PSC_GFN_POS) | \ + GHCB_MSR_PSC_REQ) + +#define GHCB_MSR_PSC_RESP 0x015 +#define GHCB_MSR_PSC_ERROR_POS 32 +#define GHCB_MSR_PSC_RESP_VAL(val) ((val) >> GHCB_MSR_PSC_ERROR_POS) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 1b7a172b832b..c41c786d69fe 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -62,6 +62,9 @@ extern bool handle_vc_boot_ghcb(struct pt_regs *regs); /* Software defined (when rFlags.CF = 1) */ #define PVALIDATE_FAIL_NOUPDATE 255 +/* RMP page size */ +#define RMP_PG_SIZE_4K 0 + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); From patchwork Wed Jun 2 14:04:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37BB2C47097 for ; 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dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4512.namprd12.prod.outlook.com (2603:10b6:806:71::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.21; Wed, 2 Jun 2021 14:04:53 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:04:53 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 09/22] x86/compressed: Register GHCB memory when SEV-SNP is active Date: Wed, 2 Jun 2021 09:04:03 -0500 Message-Id: <20210602140416.23573-10-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:52 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e162c06a-b768-48a7-0d1e-08d925cf64ab X-MS-TrafficTypeDiagnostic: SA0PR12MB4512: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 53LdoIBVatvIqBpZpkPWHqRAhhtnsZjeU8wMC3hfxm9gXU80nPxJmyvLjWpDr6e5keIxG88VQ7nG3w1ewmp9gjhJ1BgtM32Jy/1wite37OoX34r7ZCOuFu4Xua2Hw2BTUChBF78jpeHXkKFAafsFS5TMIt6l6cXArCVexhqNzVlq0eKu18kX8PT/ArrhV2L/WwdECAPf1HfzjVRE52u5H+5Xz8izpe+Hv6mCzHETW6nlg9PJhn29CTx/+Qa9E4mBjJnVWrA/MswMIbTHLRxrvENGIki31dg1aqQNCLGbMB8PFA8WfEFZAXiITAdSE4UMmgi0sPcl5+2fgXXM6MKOcIb93329jGrlfw5PJMB/1VKS99Ir2202+Nli8Pil6LQyRby0u+tQZXW1CAmxnVCWqBd4fJQMPvuWQ6k4s0hLjZXx4sYz5A815GO9jqwQ7qXYtSH+z3uMMCfz1rhIZk5cTMpSR7mIlXr2L5korkw3KcV5tOaVfA1mK2Jgjv2vbOnKbvpx9FVlCHrdLUCDz9ryVDQzA1GeJTCgVyyjSZSiDG2X2ncmRjYtcjNEvkdxNocMbZczuoGfW7iWVXykmf2VGWDKkHQymu8uW+O8jbVZr/2/kMhBwkVKpWNlQaRX1M50dy2Y5hWZ5Ly5m0P7e7h51Q== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(39860400002)(136003)(6666004)(44832011)(7416002)(26005)(2906002)(8676002)(6486002)(7696005)(52116002)(38100700002)(478600001)(956004)(66556008)(186003)(1076003)(36756003)(8936002)(16526019)(66946007)(38350700002)(5660300002)(2616005)(54906003)(4326008)(86362001)(66476007)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: GyhB7dMrnoJv+W3ZiAMKrRPUzYcFP1uvEnc6EB/cA24K7hHgl7dmtXOgnUtfA1CTyzQVf9PROi5V6zaZ37e4aXfVYg+mbpjD80pwM4IkOZOVKaOnWEoor/nODTra0+LUCqXu/i4qH51v2svqqDJVRGJEVtcNjlH/ss7VR0UlYxKnc199QGK9Vi1xUwJs3Vj3N2flGWjaSIWNl7kpk77w65gvrpe+5JZwYMIsBt4uqZciA4UopAz6POg+5GEYetCEUSGnCuhffXnx6uaZk1Ntoyu7YAkB1hmbd9v5M1pSarj1Ah4zG9ENCwlbmiR6nDL2ww5eIXsgHERsvbO/Cbyspl1f4RA9ElKMUQn/dkHa8Exh0neBdEPTigiOGTyZ4NCB4z5m4xVp//m6cWSgnghu6DkONg7KZmAbXO2fCNxTIbouOPPLCws242Aya9smNcoylUn9DPVuQq8q2p8aPIJ9CCwR5Dp3wMfTiA4tnSFFtO2xpJWR8/Muwv8deHPEEAmvTrjYFRGTZUOxhigEwa/pJxVcEQPO9ti3fndXA7Z28AZsi7bkw44xW7TtEZ3d5VWWIAlBhKgOgET5JE04vhr6qB9QOUvrTO6rLG4qEYHaMn8kIsrcbqjygx6g/Bw8t4Y3VhmA4qdUyqp2FZHyyFWR/q5gzMsLObA3dVIcKEHV24G3q/P8M2lRWfxtBVvjOncVgDLtJdSLAjIQB2MLs75oWR9kawdO00pty3QfJ7wZRVCIzA9AM+aijN8roCG1ETRgr4SUnGl3aqI6EPkpQ6zqZ4njOYL5kiwi9aWMUPh0BOTRcIOrzq0oBLKXCrgAuYSCWN7ze4hsaYrZmzacfSyGsQIUOVX+whpUKcgKkF7kJ4171sn6IfTMdie37/yP+O8U0rTBH0iCvh3hbR8Mblu3LN/ITV9WOciSukzsUjSVuEFYlhtyfMzWdPOkRWQE08Tq64lIIjVHTEggNSVA2KKICllxbkQ30o9UE06HL5rkCph58W1rPwnfEOs7QY64gdGCwDHl7fXaMN8CzqVpLhJXPIxQvb3TVYxGTeBxKULyF8U1on5A+jsOueK5TPZ80f8HNTFe1uWok/uGMWFEB7HULkvcaMS6W5NszHPqqvfV9732qX+e0qla5kaQfL57DfYnQeFXY24PSmFtzSSuveLYr4rYEkU1XFJg1xFKtuiGghJbvAWqgSYBoRckk2Uhj2acpHxadQGXEzIBzjSAC8Qb9g5nMQQxngdDTFY/6m+TrkQ+H8zqWFKLO+Bg0gFpsx2JSkr/TA7uvOxrHh5/XIv0c9Fe7Zq5QoCtlN8sJkbi3TcMgGvGfsxwE3wVdL0/3zSC X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e162c06a-b768-48a7-0d1e-08d925cf64ab X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:52.8674 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7RMZMdqDJ4t/ckVhG0fYH5vmeC9TldAMhVxpJwU/8GPlPAEv9SH1Kj6LkCcuxjPGh5pvWwPRXSGRJUvjcsz7zQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4512 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The SEV-SNP guest is required to perform GHCB GPA registration. This is because the hypervisor may prefer that a guest use a consistent and/or specific GPA for the GHCB associated with a vCPU. For more information, see the GHCB specification. If hypervisor can not work with the guest provided GPA then terminate the guest boot. Signed-off-by: Brijesh Singh --- arch/x86/boot/compressed/sev.c | 4 ++++ arch/x86/include/asm/sev-common.h | 11 +++++++++++ arch/x86/kernel/sev-shared.c | 16 ++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 808fe1f6b170..4acade02267b 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -203,6 +203,10 @@ static bool early_setup_sev_es(void) /* Initialize lookup tables for the instruction decoder */ inat_init_tables(); + /* SEV-SNP guest requires the GHCB GPA must be registered */ + if (sev_snp_enabled()) + snp_register_ghcb_early(__pa(&boot_ghcb_page)); + return true; } diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 1424b8ffde0b..ae99a8a756fe 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -75,6 +75,17 @@ #define GHCB_MSR_PSC_ERROR_POS 32 #define GHCB_MSR_PSC_RESP_VAL(val) ((val) >> GHCB_MSR_PSC_ERROR_POS) +/* GHCB GPA Register */ +#define GHCB_MSR_GPA_REG_REQ 0x012 +#define GHCB_MSR_GPA_REG_VALUE_POS 12 +#define GHCB_MSR_GPA_REG_GFN_MASK GENMASK_ULL(51, 0) +#define GHCB_MSR_GPA_REQ_GFN_VAL(v) \ + (((unsigned long)((v) & GHCB_MSR_GPA_REG_GFN_MASK) << GHCB_MSR_GPA_REG_VALUE_POS)| \ + GHCB_MSR_GPA_REG_REQ) + +#define GHCB_MSR_GPA_REG_RESP 0x013 +#define GHCB_MSR_GPA_REG_RESP_VAL(v) ((v) >> GHCB_MSR_GPA_REG_VALUE_POS) + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index b8312ad66120..b62226bf51b9 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -77,6 +77,22 @@ static bool get_hv_features(void) return true; } +static void snp_register_ghcb_early(unsigned long paddr) +{ + unsigned long pfn = paddr >> PAGE_SHIFT; + u64 val; + + sev_es_wr_ghcb_msr(GHCB_MSR_GPA_REQ_GFN_VAL(pfn)); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + + /* If the response GPA is not ours then abort the guest */ + if ((GHCB_RESP_CODE(val) != GHCB_MSR_GPA_REG_RESP) || + (GHCB_MSR_GPA_REG_RESP_VAL(val) != pfn)) + sev_es_terminate(1, GHCB_TERM_REGISTER); +} + static bool sev_es_negotiate_protocol(void) { u64 val; From patchwork Wed Jun 2 14:04:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 453584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E6BC47093 for ; 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This is because the hypervisor may prefer that a guest use a consistent and/or specific GPA for the GHCB associated with a vCPU. For more information, see the GHCB specification section GHCB GPA Registration. During the boot, init_ghcb() allocates a per-cpu GHCB page. On very first VC exception, the exception handler switch to using the per-cpu GHCB page allocated during the init_ghcb(). The GHCB page must be registered in the current vcpu context. Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev-internal.h | 12 ++++++++++++ arch/x86/kernel/sev.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 arch/x86/kernel/sev-internal.h diff --git a/arch/x86/kernel/sev-internal.h b/arch/x86/kernel/sev-internal.h new file mode 100644 index 000000000000..d23c81013a8e --- /dev/null +++ b/arch/x86/kernel/sev-internal.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Forward declarations for sev-shared.c + * + * Author: Brijesh Singh + */ + +#ifndef _ARCH_X86_KERNEL_SEV_INTERNAL_H + +static void snp_register_ghcb_early(unsigned long paddr); + +#endif /* _ARCH_X86_KERNEL_SEV_INTERNAL_H */ diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 9b70b7332614..455c09a9b2c2 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -32,6 +32,8 @@ #include #include +#include "sev-internal.h" + #define DR7_RESET_VALUE 0x400 /* For early boot hypervisor communication in SEV-ES enabled guests */ @@ -88,6 +90,13 @@ struct sev_es_runtime_data { * is currently unsupported in SEV-ES guests. */ unsigned long dr7; + + /* + * SEV-SNP requires that the GHCB must be registered before using it. + * The flag below will indicate whether the GHCB is registered, if its + * not registered then sev_es_get_ghcb() will perform the registration. + */ + bool snp_ghcb_registered; }; struct ghcb_state { @@ -192,6 +201,16 @@ void noinstr __sev_es_ist_exit(void) this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist); } +static void snp_register_ghcb(struct sev_es_runtime_data *data, unsigned long paddr) +{ + if (data->snp_ghcb_registered) + return; + + snp_register_ghcb_early(paddr); + + data->snp_ghcb_registered = true; +} + static __always_inline struct ghcb *sev_es_get_ghcb(struct ghcb_state *state) { struct sev_es_runtime_data *data; @@ -218,6 +237,10 @@ static __always_inline struct ghcb *sev_es_get_ghcb(struct ghcb_state *state) data->ghcb_active = true; } + /* SEV-SNP guest requires that GHCB must be registered. */ + if (sev_feature_enabled(SEV_SNP)) + snp_register_ghcb(data, __pa(ghcb)); + return ghcb; } @@ -622,6 +645,10 @@ static bool __init sev_es_setup_ghcb(void) /* Alright - Make the boot-ghcb public */ boot_ghcb = &boot_ghcb_page; + /* SEV-SNP guest requires that GHCB GPA must be registered. */ + if (sev_feature_enabled(SEV_SNP)) + snp_register_ghcb_early(__pa(&boot_ghcb_page)); + return true; } @@ -711,6 +738,7 @@ static void __init init_ghcb(int cpu) data->ghcb_active = false; data->backup_ghcb_active = false; + data->snp_ghcb_registered = false; } void __init sev_es_init_vc_handling(void) From patchwork Wed Jun 2 14:04:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 453583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBBAEC47096 for ; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 11/22] x86/sev: Add helper for validating pages in early enc attribute changes Date: Wed, 2 Jun 2021 09:04:05 -0500 Message-Id: <20210602140416.23573-12-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:55 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 24b83349-d104-4a69-7f3c-08d925cf6683 X-MS-TrafficTypeDiagnostic: SN6PR12MB2766: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2iyiAwmwxSkly9Lrgpl5y0E3HTFjinuqHOIf1H9uGvCKS7kCPP8Wahx/kcRLepBRvIj6YyiQLI1PJUgNTPDt8ptcb1WvxYwczm9kJIQo1lV1R9isgPuGdnHbecdJH7DFwpbcZpj5Gw+pePiVeorUqTwcL3OF8w7KsOWsDKAj4jOndBA6VGWQKRi45vQLHQJfytg5s3jmd7MQqL5n6OjiRstJqPdlRFQPxrnG+qQ4EWq9jc/9Vija+2ks/AKRu1cHyyndnmpygcFcgfqLcmzzfLtnB0BfGW7/wmX3ForIhbV256BefEAUyUfBdlx2/oIBOlZZvHDzlWths8e11zqXqom66QUVqkPYP6jHyXtZ6XoN5zHs4WZL2CjgYno0Vs5pLjvVlJKe6xPtkFWSzmNMpWxyDgzHSdEc1/DB+2VIASvcg6NWX8EuEE5E+6e48uMXqhjCA96FAzhHMxK9j7MTXd/po1k+l34hMK9MLBa0UeK+GzoH37nhOS4YS2Oqw7xE+gOINxpwaJAyGp1qyzd1gQOcc3f84fIgk+AMUhq/Rz8zCFGRYCuZ6qf4UfuP0k46EWPS7rfxkRBgi0dHIOlEhTb3pVHFQME96FSCzZ/Ua0AMFoOSQ/MGoljVpQjLdktolAAhWBhvqcHJP7n3JJ/W5w== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(396003)(39860400002)(366004)(6486002)(38350700002)(86362001)(66946007)(38100700002)(44832011)(52116002)(36756003)(8676002)(83380400001)(7416002)(26005)(4326008)(2616005)(1076003)(186003)(956004)(16526019)(2906002)(316002)(54906003)(6666004)(66476007)(478600001)(5660300002)(7696005)(66556008)(8936002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: S7zCA1tRwRB2DcTNn1YxxUpawyOT7yqPF7sDqOnU3777a4oUjaS03bowx1Kly8jNiO7hZdjg220dtmznVPOTG1P++IQtNXpK5RQFrIK2DHfWVvUcgOWrvXayX0h+MUbFr6iDk9+FboE69q5VWHgBwrfrBHgqyHkmX5OhirX2AHlQtepJU5Of/a82jsXoK9gitAYNKb5BPMB4TeMKt0srje/9TxSP5/H/aw76bvmMjb1LuXL+vSmJnkuB85Sl2sxA37dsbNHOSO0rCqGP4QoL+QzeQhO7IkmFceYCnK1wqqfyVPM/VuQW7YqRhYQhavaC+CVFySOKu2BVPWXN6Gs1661LpP6wsDzHp9kklJOWh1P4lD4hOZK0qJ+5puKzpXZPGd/Kb6yzc9ZqR7ZIznemJaK83AeE3C7SI9Cuw7hXLKV9RHgrq2u9AhZXZWOSkDl1H9YWy24WDiJbmr/vwMJ+HtFRIqOQdgpyeHo3590dHTSNd8FrYf5J7YRxSVamKGFuZa5gYF6fJnEIs3NKlFao1xEgWes40IsUgtTzmHDCkB8o7Ky9mx9cMH8iaeJ59+xsGMDA64xDgvbFkdSf3eDHQT6Hh5bOpMJry87YwEFtesntlrT1R63rpfu+f+/qbJOisCsLiZa/1GkOAdyTrvsfnw8qUFZtLNQoJNXkf5BqZDiRlQ2xWuy19m/wWZfxKaQGeABT5VJ03QLYu+maF4v0mCdy7CRsUdY8N8mRuW1ZcNfaSf9MiNpDi59n56msywIY+NYQWKnia3Ugs5Oo72ziH9/epccMMwoSAz0h5LBRP0KXmPqn91YAFOlZQ18c+40icDM65GFl1bDQ8F2oxD9JDalGqMGe7iykU/9OaBED+0wMJwIDaqBt3gkg7ESOaXCe3bOYvSszCNblOO4GwKLVgtE5CSO2b8zbyx/U70FikueXqJpR2Ys+5+ik02gmb1gNMcAFcOZBNwcNrSty7hpE+zcpfJVE66j3vX32heTB9x4gOX1q/DfglWNikF8N0C3HKAOpaVeg7AKAOWVr/OK21qZ7M4p8caueszY4TZLjjabmBSUB20fgU9j7crBWIe1UbdcQbH8PuBKRpExx3Vk3FUf6zRwGU0o1m5G7gMgsB765Lc0kKTrh8Q3kvTkq/km3W8BRMwuEwX+PkbK54LkKjZM7WcRiOP43c3fRPfQa/hJhZh9XYCLZwUqkRhJTQk5iPHoOwCx8op/ov85LxjlGlOYpQ4o7WMhW5oUxf/mJmCE63CNxLDwfefgUGZNXCVBkkEa0kGd4IV7uh4K+AD5Wg15yPBskj0WHtXC3GAAVdZx4tsobQIsV6vENFP+qEBjI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 24b83349-d104-4a69-7f3c-08d925cf6683 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:56.5923 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Kwdg7H0mJTVwN854ZJ3gYMcrVVgrhwKbJTMLsVLqdi5TjRcsDxFiDhfLR5sTzO9Rofe/e/SvUd1FZtlqonVgfQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2766 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The early_set_memory_{encrypt,decrypt}() are used for changing the page from decrypted (shared) to encrypted (private) and vice versa. When SEV-SNP is active, the page state transition needs to go through additional steps. If the page is transitioned from shared to private, then perform the following after the encryption attribute is set in the page table: 1. Issue the page state change VMGEXIT to add the page as a private in the RMP table. 2. Validate the page after its successfully added in the RMP table. To maintain the security guarantees, if the page is transitioned from private to shared, then perform the following before clearing the encryption attribute from the page table. 1. Invalidate the page. 2. Issue the page state change VMGEXIT to make the page shared in the RMP table. The early_set_memory_{encrypt,decrypt} can be called before the GHCB is setup, use the SNP page state MSR protocol VMGEXIT defined in the GHCB specification to request the page state change in the RMP table. While at it, add a helper snp_prep_memory() that can be used outside the sev specific files to change the page state for a specified memory range. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 20 +++++++ arch/x86/kernel/sev.c | 105 +++++++++++++++++++++++++++++++++++++ arch/x86/mm/mem_encrypt.c | 47 ++++++++++++++++- 3 files changed, 170 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index c41c786d69fe..7c2cb5300e43 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -65,6 +65,12 @@ extern bool handle_vc_boot_ghcb(struct pt_regs *regs); /* RMP page size */ #define RMP_PG_SIZE_4K 0 +/* Memory opertion for snp_prep_memory() */ +enum snp_mem_op { + MEMORY_PRIVATE, + MEMORY_SHARED +}; + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); @@ -103,6 +109,11 @@ static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) return rc; } +void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, + unsigned int npages); +void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, + unsigned int npages); +void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -110,6 +121,15 @@ static inline int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { ret static inline void sev_es_nmi_complete(void) { } static inline int sev_es_efi_map_ghcbs(pgd_t *pgd) { return 0; } static inline int pvalidate(unsigned long vaddr, bool rmp_psize, bool validate) { return 0; } +static inline void __init +early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, unsigned int npages) +{ +} +static inline void __init +early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned int npages) +{ +} +static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op) { } #endif #endif diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 455c09a9b2c2..6e9b45bb38ab 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -532,6 +532,111 @@ static u64 get_jump_table_addr(void) return ret; } +static void pvalidate_pages(unsigned long vaddr, unsigned int npages, bool validate) +{ + unsigned long vaddr_end; + int rc; + + vaddr = vaddr & PAGE_MASK; + vaddr_end = vaddr + (npages << PAGE_SHIFT); + + while (vaddr < vaddr_end) { + rc = pvalidate(vaddr, RMP_PG_SIZE_4K, validate); + if (WARN(rc, "Failed to validate address 0x%lx ret %d", vaddr, rc)) + sev_es_terminate(1, GHCB_TERM_PVALIDATE); + + vaddr = vaddr + PAGE_SIZE; + } +} + +static void __init early_set_page_state(unsigned long paddr, unsigned int npages, int op) +{ + unsigned long paddr_end; + u64 val; + + paddr = paddr & PAGE_MASK; + paddr_end = paddr + (npages << PAGE_SHIFT); + + while (paddr < paddr_end) { + /* + * Use the MSR protocol because this function can be called before the GHCB + * is established. + */ + sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op)); + VMGEXIT(); + + val = sev_es_rd_ghcb_msr(); + + if (GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP) + goto e_term; + + if (WARN(GHCB_MSR_PSC_RESP_VAL(val), + "Failed to change page state to '%s' paddr 0x%lx error 0x%llx\n", + op == SNP_PAGE_STATE_PRIVATE ? "private" : "shared", + paddr, GHCB_MSR_PSC_RESP_VAL(val))) + goto e_term; + + paddr = paddr + PAGE_SIZE; + } + + return; + +e_term: + sev_es_terminate(1, GHCB_TERM_PSC); +} + +void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, + unsigned int npages) +{ + if (!sev_feature_enabled(SEV_SNP)) + return; + + /* Ask hypervisor to add the memory pages in RMP table as a 'private'. */ + early_set_page_state(paddr, npages, SNP_PAGE_STATE_PRIVATE); + + /* Validate the memory pages after they've been added in the RMP table. */ + pvalidate_pages(vaddr, npages, 1); +} + +void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, + unsigned int npages) +{ + if (!sev_feature_enabled(SEV_SNP)) + return; + + /* + * Invalidate the memory pages before they are marked shared in the + * RMP table. + */ + pvalidate_pages(vaddr, npages, 0); + + /* Ask hypervisor to make the memory pages shared in the RMP table. */ + early_set_page_state(paddr, npages, SNP_PAGE_STATE_SHARED); +} + +void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op) +{ + unsigned long vaddr, npages; + + vaddr = (unsigned long)__va(paddr); + npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + + switch (op) { + case MEMORY_PRIVATE: { + early_snp_set_memory_private(vaddr, paddr, npages); + return; + } + case MEMORY_SHARED: { + early_snp_set_memory_shared(vaddr, paddr, npages); + return; + } + default: + break; + } + + WARN(1, "invalid memory op %d\n", op); +} + int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { u16 startup_cs, startup_ip; diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 63e7799a9a86..45d9feb0151a 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "mm_internal.h" @@ -48,6 +49,34 @@ EXPORT_SYMBOL_GPL(sev_enable_key); /* Buffer used for early in-place encryption by BSP, no locking needed */ static char sme_early_buffer[PAGE_SIZE] __initdata __aligned(PAGE_SIZE); +/* + * When SNP is active, changes the page state from private to shared before + * copying the data from the source to destination and restore after the copy. + * This is required because the source address is mapped as decrypted by the + * caller of the routine. + */ +static inline void __init snp_memcpy(void *dst, void *src, size_t sz, + unsigned long paddr, bool decrypt) +{ + unsigned long npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + + if (!sev_feature_enabled(SEV_SNP) || !decrypt) { + memcpy(dst, src, sz); + return; + } + + /* + * If the paddr needs to be accessed decrypted, mark the page + * shared in the RMP table before copying it. + */ + early_snp_set_memory_shared((unsigned long)__va(paddr), paddr, npages); + + memcpy(dst, src, sz); + + /* Restore the page state after the memcpy. */ + early_snp_set_memory_private((unsigned long)__va(paddr), paddr, npages); +} + /* * This routine does not change the underlying encryption setting of the * page(s) that map this memory. It assumes that eventually the memory is @@ -96,8 +125,8 @@ static void __init __sme_early_enc_dec(resource_size_t paddr, * Use a temporary buffer, of cache-line multiple size, to * avoid data corruption as documented in the APM. */ - memcpy(sme_early_buffer, src, len); - memcpy(dst, sme_early_buffer, len); + snp_memcpy(sme_early_buffer, src, len, paddr, enc); + snp_memcpy(dst, sme_early_buffer, len, paddr, !enc); early_memunmap(dst, len); early_memunmap(src, len); @@ -277,9 +306,23 @@ static void __init __set_clr_pte_enc(pte_t *kpte, int level, bool enc) else sme_early_decrypt(pa, size); + /* + * If page is getting mapped decrypted in the page table, then the page state + * change in the RMP table must happen before the page table updates. + */ + if (!enc) + early_snp_set_memory_shared((unsigned long)__va(pa), pa, 1); + /* Change the page encryption mask. */ new_pte = pfn_pte(pfn, new_prot); set_pte_atomic(kpte, new_pte); + + /* + * If page is set encrypted in the page table, then update the RMP table to + * add this page as private. + */ + if (enc) + early_snp_set_memory_private((unsigned long)__va(pa), pa, 1); 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Wed, 2 Jun 2021 14:04:59 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 12/22] x86/kernel: Make the bss.decrypted section shared in RMP table Date: Wed, 2 Jun 2021 09:04:06 -0500 Message-Id: <20210602140416.23573-13-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:57 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 086a58ba-9ae5-4089-dccc-08d925cf6793 X-MS-TrafficTypeDiagnostic: SN6PR12MB2766: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: n/qmT3VUUaHs/FG0ISKZANvVC4j+NE03guJ7pAe9gQ8BYj1r0h4Wfg4l0Sl9m+bTkH24xmvjpdHasq0Zrr1J1+u0+bo6IOtJR3f/h/L6oKdHyA27/DgpyQYMvKnvLOuQvgVldwAM/ewgpVJ59MvAiWNyTWug0IgkCxuPnvcqyYXXrAnBb3GRlCauFYgdYI1EkvNGpYAcy9A0HLt7hZuGIay6oIsE8AiwyUeENOYwzgj4+uBBT1WtJPfdprnH3pLRcO3W9GqtLDr0DvnGhVQOy14wEdn+d/pqqgcdi4WPSoPpUTGwHEkz+NvNzK9NosD5RjdimXiSd3GZOZy20aNtF5uLrjt1qj/jXbYX/CSWrAaPgd6kjAM+DKSphxtkTE2ux5usZ2+adisL8BPo+lnz88hk1Bv0vyex08ObuyloLRL2KrafYG3GKsOyJ9H8B5JTHX/pZoIIZuKxNV/tK7vJusumHtpdNY1A2eyRkPCiPL4iYyZwmUHV/ITNnJ3Z+hIVCN5Wu1GG05F73ipOcan6YTtxROA9YHuveJKtp6DJF64JMxzpGCvJu/xriqycbGmIN8wn575ZszP+Tc9UG04pUWOKUs7lET5L/b/3bU7t+zHUqcH+ZLz1Z3NgJOMHsr9Z3QA+/5pexl05zVBzFboIeA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(396003)(39860400002)(366004)(6486002)(38350700002)(86362001)(66946007)(38100700002)(44832011)(52116002)(36756003)(8676002)(83380400001)(7416002)(26005)(4326008)(2616005)(1076003)(186003)(956004)(16526019)(2906002)(316002)(54906003)(6666004)(66476007)(478600001)(5660300002)(7696005)(66556008)(8936002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: t/LfuCVb4vBYxe2e4KhvjRl6+HhUnbRDxLo8zu9TKLCrlLEn7v9CSilt+DEBq82/Cek43bkRv8zXeMuRsdi2zc/KfYi6GlLP0twLmQL6GILD8lj1LpXiaWExEzg2VKS9NqS03HreP45MUClYXJVKTRjswZscPgQ2pC1bIDtlezCMN1F4LZjTLnVD0zKDm5LX5OpEoJpRtT47BYNOSQbfDHXW0FCgErjHWTJPJhyoOYq+ENwuzgf1RXIZSsy3reEBUW2MH5vPBLX7larvabUD+1sJnyQHFjqwg2RdJOpQrVYMzV3+IzMQujQ6AQqYAfeYF+DMypWrBRFhgV1ZgK0J9WeUTkBpF75r6kwpaiEw2HmGd9ytFGSTuNLWMt++jI1sV5tYEzCUihraufc/mxMFXqFWvUeMHElHAkqc4AzWJ2lb/l5FTa6T8HRgjL17Tn57IrJmIjqRoRqwde7fjFBwrfQUFlSLS0BvX9ueXldiHHmf8w3buL1tEp1KUbffCHW0zsy9FE9qxL2gLyH/q9TZfy3agDEUIhT6eXLfw1LNnx0lne7IFo82h1jNbbolyefdg673dgerRBZbQOklQtyXW2kRRHmLwe9nTohRUV0N9Hyk7R/V2FrS4DPj59EFZoMzKxAa8F6L1ptLF0egzLJfMMcbwX4qAQq2F7MxyXmy/YfNktZDdStB3mqNDAVh6ZowQpgAAHIwWINUWv8riW6PmCzL/haj1xkMhsgepZ686vCtl3wi1XwHuuzZf53+yAZJMAwSCE1dVnjuplQ3WAVr+PU6IFDSt2CJGHpmUfTK7f0o7yXHiL7zwsyAEBt4ECKvVKWVhRjtz8I1z4dZf2l1DmpV/xRrRRzr0w+AIrGj2cc891vTATiN7QqUIuCw6hWZ9AOAWJLJwqqFRg+fPzVSCQ3aSkNvmC2W8qBmEayGJh2uMQqPXahP0RxTqZWvdUlL6vWy7Zm/v7blvL7DB8zEFQPlyqPsm+kc0HSY19kuxto1I5MqxdiTMqzbpeR8yQplvqqo6RBMy8AdqEwNyG/RJNBNgb/o2dIowOfBRlnymdu6JtlT9Ig9aKi87yxtAWJ0fS68dVa50TXySHlVApsD0QQINN5X47MkY6urC9fTTCK6bCLXIg3TMX2j9Iv8qV2ZffiOnnlhqa58ErF7SM4JAqP2Xa7D/CJALiib7+21Y3EO7Am9Iw+9hQ6FAEdn02jrkaYHxE/xLPtRch1y07VdChpOUBefXtWTcgiEactC76Fi7ib2t9cHurRoKkk2TY6PJjrmFOLTNBp6LRa4a2MV/tZKA+KzjSd+GzM7sFOlCkQGm0ScS9CgFmZAxB+rV+k6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 086a58ba-9ae5-4089-dccc-08d925cf6793 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:04:58.8170 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: J5wic2EQO1WWU6+jTNCGsluTK7GyeVhiME3lEIlMHlQinTrsCP9vuTVqcds2BI423fcxHHueUZg/bKFEDkve7Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2766 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The encryption attribute for the bss.decrypted region is cleared in the initial page table build. This is because the section contains the data that need to be shared between the guest and the hypervisor. When SEV-SNP is active, just clearing the encryption attribute in the page table is not enough. The page state need to be updated in the RMP table. Signed-off-by: Brijesh Singh --- arch/x86/kernel/head64.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index de01903c3735..f4c3e632345a 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -288,7 +288,14 @@ unsigned long __head __startup_64(unsigned long physaddr, if (mem_encrypt_active()) { vaddr = (unsigned long)__start_bss_decrypted; vaddr_end = (unsigned long)__end_bss_decrypted; + for (; vaddr < vaddr_end; vaddr += PMD_SIZE) { + /* + * When SEV-SNP is active then transition the page to shared in the RMP + * table so that it is consistent with the page table attribute change. + */ + early_snp_set_memory_shared(__pa(vaddr), __pa(vaddr), PTRS_PER_PMD); + i = pmd_index(vaddr); pmd[i] -= sme_get_me_mask(); } From patchwork Wed Jun 2 14:04:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9B08C47093 for ; Wed, 2 Jun 2021 14:07:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D0E5060FE4 for ; Wed, 2 Jun 2021 14:07:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230438AbhFBOJF (ORCPT ); Wed, 2 Jun 2021 10:09:05 -0400 Received: from mail-mw2nam12on2085.outbound.protection.outlook.com ([40.107.244.85]:36984 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230377AbhFBOHv (ORCPT ); Wed, 2 Jun 2021 10:07:51 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=i/mBHPiurMftLFKfySTyalzs0PEBTKqClLubMhvtohk7hmKjG0c0vFzPqa+gPdBLZp3NJy8NTLwdcu4WMgkbAZjLf//LOpJt9aa5Dq4oZFVh4t54s1jsVRGG7lgTF4RQYC3zzTCXzT5Zf3PNLeeDNhXQAE5Kp+2F+WIgyPaOhYKnSFAoyeI2XHi0eJKTAnBXSamyVpzLE7Oiy+wshyfzpj7fy3qIFAvYQ4US9te7vXbflK4AKX5HpJMwYptnm/i1iDImo8cosxTXtsD/X6weWCqFOXdL7K4/i/jOQ80WhptToXUwg7goksb5DRXtYp6b0KQyudtWuGuLlqdjcLgLCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iBYwKWM1e2f6h3Bx093S/ZsTxx9S/8/Wr0mKLor3GzE=; b=Yb5f6xVHNfroGTC9sVwdhBb17Ai6u9gqVMF4DweX2sLM4mXEZmoNS8TavY4STJZRiccgyvlAlseUmXkfuJIhp35QMl6+ACEDHY3YLRj18BwM7xpBMUkqNf9EpJ6ZE1wd6jsX5CbwQYMi/+5MO5CLBX1r9Cifmml7iPIIB9av7rMbT0D128+1aBUuHL87is1+MUshcc2O+4+fLLe3yEWFsbZ/+GrSbZXF/OaDc+pHZEJHgiWBoJ/qvPTs9lXy9uuZBKnSiH3ADpnS4RobB7DJXgH/PHjPqQxbg9phYmjjVn5c2zEeYpREZ/Z8cHOTMWfi+d89szUfInX9Mw/6jaOhTg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iBYwKWM1e2f6h3Bx093S/ZsTxx9S/8/Wr0mKLor3GzE=; b=cF8nLsfPWGx/jbtiqAGO2Pbkrs/4xMxo/frF7b/+JCxNz6HDb3k2qVUu1NKprOigiO4GdlyIPTaPz+nXWmFPKYiTiWQXT8QOEXDAsEykqIzxXsxW6Rv5mS6FmHhPMKNGrHrs7Fcn8QOCurxEvYnH1TzJZutuSjLMuUoxiKA8O7E= Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2766.namprd12.prod.outlook.com (2603:10b6:805:78::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.22; Wed, 2 Jun 2021 14:05:00 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:05:00 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 13/22] x86/kernel: Validate rom memory before accessing when SEV-SNP is active Date: Wed, 2 Jun 2021 09:04:07 -0500 Message-Id: <20210602140416.23573-14-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:04:59 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7bd03a4-6a6b-4711-f548-08d925cf68dc X-MS-TrafficTypeDiagnostic: SN6PR12MB2766: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ts37rTnYNg1nyIuRjqFKaG6HCJPdV5cqH/WSR1o/q0DchoER6eNkcxsvh1CI8/YHukm9urdE0uz7VdINMGRDS+m1Odhs2y/1YshwegpJBXTRxQacX5YBdFPNanVq7MFMSW89oOf1cYUFzHfmDJeDVj0Id+bfd0PhPGyC3NeHhNJcBp2X8MXdTB/4ODlIpgnEYmvd6NPt+ZXkeLSPXn1QsFH1tjM5b2qzJVhFDplkA8jxNAjygVufIYDyVgoagMU6vXYpPwOApyPns+pgsa0QGjHVSYQH/x2yf+HggePx6ahWcTMgk0AKLdrNFeuh2THUr4YhYZDOEMS+o1ItRSMdToOxudyrZ8nfQZqXW5gpWi4iVE9PLuQXXigpnNVRfKxFLxQEvPjmrAIZgf11vM4dV/H2rxk7c/LbsKgAgyJxrjXkrdHMc/EZdxW3Im663/VALLsJWyY8Eer7FLNiYexrORLJVHoSvIPYyuN+STznpGCa80QuOofKYB2Q89TkRh9kpxkY/l2j4q8fKXQehYiRcEXPwvZNN29I17s8h/qJtPUDzHLexwfPyTOFmFuBLNq1jkFBuREJUHAqJhngkJtVsBZfsne+4Kwi9t5DURizHaEBNrNuP73Sq0basQf9SQbP++shjGjbGE/9SBgNMop3cg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(396003)(39860400002)(366004)(6486002)(38350700002)(86362001)(66946007)(38100700002)(44832011)(52116002)(36756003)(8676002)(83380400001)(7416002)(26005)(4326008)(2616005)(1076003)(186003)(956004)(16526019)(2906002)(316002)(54906003)(6666004)(66476007)(15650500001)(478600001)(5660300002)(7696005)(66556008)(8936002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: XzlLhSQV+R6HHd1W8+cMp1U2Wm63s6SO//gMAWJYnDHtb8n3uhLGpENnTUaamVCrTI6cuZUtAgsAiLPtvHFP2qACmP+4+4EIxnKlNOMGyjv8mGytqJsf0qONRvkbsIqznNYKAoZDoUs8fPMXwv9mCKPolppK+7WEHNRvuT4R/QaNgql2DBxff6/MWsqSqG6u40svy7njiugwXxq+dmc99ubRRka5j8oF2ZgiHK8hDun/Dyfi86MhAtaI78iJtaVWkpTS428e6eTRcHf8hMxSrCS1fJvthrh2UBzbd1jgd2OzMz7Si2U9/nFluXhml9M4liu68BHu5jZa5tK313GzjvatupxRvmwla5SaHcWiAQjg+A+ju6UcnDh2om+jF65rnkaK2kULDBaXKZEGwU3VYk7Slnkof/ITyoPHUwubB+U0sK/7DH2b+sOVfcWjtPKZUHajplr9rfNV90xHNIrebbSw7RnHPbVcCVc1ronQPSa1XOes0zestZ5FpoQZuTkpajm0rIreDDirplPJlguwFYh7TctCGKNK7AjgZ/pezE3csYbk0zmOD7HNnsOTsFf8TMwRPGzhQXWPq2+JZ61g1e4hyikTT3jUvtJ6pKNUwwR7iaS9JboI91hcTj7rd0P/hOH65HgTkXTtLmZwlTJ/4qoyaC6xKnyxq/xrdFboIVPUGJ7HndFQ/4+1aaAZOHJEUUYdEy/30BEFYusFElzY8lxISOQFRJ6V9S65qyp2cQWAGcdi8HMc271Lci7av5424NdEyxOl+DkWyuOF5ywxnfUIaAqulOO16U7RK/usjmwFGDVaJKXTxXNX+DXIQKWBNXCW5Xo/kpZQJ7V4MqOKpNZeouZIaig6+rfycUwqfWF6Vm2SetpztToo4a4s1VghZs7hKczRP5JmLDkVyzhzbeLoS0UDB+jGWrHDB9bUIOKhxsrQcl0V5MB3bHKrSOtdvQP1UxwZWE8n3MTUe7ilvOtMKFwO6yiBzZRf/hMY7jbNs2bkGMSP9uRGot6DuKmeoxfVpit+dw8UfbNjrQ4/knXwe7+idB4U9+Ilg+Nfm2wlkDlSLLxI/x9kREqWFgnsHI8+okRgCYnMC1aFoGirAfGOLtdcVAfJbH3SFWxqRwJBhEUuwYLSo5TOOcEqMNSqZr40AqZ185/JCPGNn9nLugxHmmQSi0Zixk21PfZK9E7ri/zUW5wZeJHoRQe2kzJmxdZyMcXONApMIUY0gA1ru7sM2GrQ6pPOVQXkeDsQja0igzPWowGf60PIaei1lI3FJXFTA+h6tsznRa9CCCOPBK/zHRza6MJd4qxCbDYj7c62I3yJm5s3R71fX7mt2Q/p X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7bd03a4-6a6b-4711-f548-08d925cf68dc X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:05:00.2212 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LoNWDRdWWMdR1Czh7wk0I5F8SAFcC4tHTUDP7mcAfeZmLsTbiMsocUZylB+giNA8Yw2nGQKZBQ5HAc7Ukw/4sA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2766 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The probe_roms() access the memory range (0xc0000 - 0x10000) to probe various ROMs. The memory range is not part of the E820 system RAM range. The memory range is mapped as private (i.e encrypted) in page table. When SEV-SNP is active, all the private memory must be validated before the access. The ROM range was not part of E820 map, so the guest BIOS did not validate it. An access to invalidated memory will cause a VC exception. The guest does not support handling not-validated VC exception yet, so validate the ROM memory regions before it is accessed. Signed-off-by: Brijesh Singh --- arch/x86/kernel/probe_roms.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/probe_roms.c b/arch/x86/kernel/probe_roms.c index 9e1def3744f2..04b59ee77e42 100644 --- a/arch/x86/kernel/probe_roms.c +++ b/arch/x86/kernel/probe_roms.c @@ -21,6 +21,7 @@ #include #include #include +#include static struct resource system_rom_resource = { .name = "System ROM", @@ -197,11 +198,21 @@ static int __init romchecksum(const unsigned char *rom, unsigned long length) void __init probe_roms(void) { - const unsigned char *rom; unsigned long start, length, upper; + const unsigned char *rom; unsigned char c; int i; + /* + * The ROM memory is not part of the E820 system RAM and is not pre-validated + * by the BIOS. The kernel page table maps the ROM region as encrypted memory, + * the SEV-SNP requires the encrypted memory must be validated before the + * access. Validate the ROM before accessing it. + */ + snp_prep_memory(video_rom_resource.start, + ((system_rom_resource.end + 1) - video_rom_resource.start), + MEMORY_PRIVATE); + /* video rom */ upper = adapter_rom_resources[0].start; for (start = video_rom_resource.start; start < upper; start += 2048) { From patchwork Wed Jun 2 14:04:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 453578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8B04C47092 for ; Wed, 2 Jun 2021 14:08:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D1CDF613E4 for ; Wed, 2 Jun 2021 14:08:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231423AbhFBOJx (ORCPT ); Wed, 2 Jun 2021 10:09:53 -0400 Received: from mail-mw2nam12on2072.outbound.protection.outlook.com ([40.107.244.72]:37216 "EHLO NAM12-MW2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S230386AbhFBOIM (ORCPT ); Wed, 2 Jun 2021 10:08:12 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Hu3C8XNTb7KbgZx3cGlt26Zrd4wHYSaNZEoZejp2R8AewFaFx3sICfh4A0opvXRLn0A2SxVTqd97M2QrxSVOJTmQXNa1S0nc2MbfubxjMdD7wkz1J8W12k+FGwqftSsByh2ZDUC+qqU6xpWQS0/y8BM02De60AZt+eJBmmV1KRRJv9DKyRqFq74Naj9KokN0UAAqiYXLAEikUdAz4mG79XvaI+6iClq4Ll0JAhCsYOKrMfYlcl/MFIp0vLwfzEejcPfjdwEi3ACbGz9SLXF/09eJhsF/M5W3jy6YCir7HLvFzty+og8PhOWIqXY5UdWMtnK3ANjtmumGJq5okf4zZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V7ZFKwoMevA3mMgIn1B+sT8tzfenkuPQ+1aptZ11G9Q=; b=fdw1oNFYCWiIUiPziErRNXP9NChNwsni7RRwuXtMfEx9wCqLHUov+XMkFZPg3B0C098kHyoVnC7j3SbAAP5sLF+Pf0r8jDSEiNymEvGC71k0p6a4MDfCu4tXs41hjf53xE0uMytCmXbrPdDfDDnr83iLzrg4pl8v5ffTDxAJKPX5Tn+XMIk0+1MKxJwwmttGEMSAyPikSop41KQB6fie/yHxrsUGQYvbsdEoBZInCSwyCh/3gG+WFPg67JUYyzwNpJ5uZiZuoNPaMTi16ejpMVPxn+qviXAQ14RKt6Nc/HDNGttltqMqr6M/cDEsXngiZAdpTqmwBBQk6yqLvr+1jg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V7ZFKwoMevA3mMgIn1B+sT8tzfenkuPQ+1aptZ11G9Q=; b=hMtkvWSLsYKkUJsznO+CFwIjdLJXtmx/CUOCdRChCA+raxCWbzKPHlheH8USdJV3AaIG3eTdQAr24uL7bUOgXgqsxKUGjferNLNVtME7gbACiMKVaSG7TAObrFvtBODRpUBj5S0/AZFcwF+1aW56pYO/16suXIMrBudVaOP/OOo= Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2766.namprd12.prod.outlook.com (2603:10b6:805:78::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.22; Wed, 2 Jun 2021 14:05:02 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:05:02 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 14/22] x86/mm: Add support to validate memory when changing C-bit Date: Wed, 2 Jun 2021 09:04:08 -0500 Message-Id: <20210602140416.23573-15-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:05:01 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2b6babd7-b186-4cd1-16bc-08d925cf6a22 X-MS-TrafficTypeDiagnostic: SN6PR12MB2766: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: X/2Oe0rMTHbuQdyKCN/Zw6cBpX0LLWMKmgtjGAdzHXGd40KxcDvvW/ZwjZ64q5QqYNNhZneyKIMRG4l1DllRffGHLoFJRFX4AxvhXQ6gz5mY4TvU0mvdUEgvE8GAh9iRiECOGXPu7mE9nMVjWyOOuxVi09a0Vk8xoI3YBCbrL00RqyykSRAWhcHSpSXc1exOFXCxXWomii7CMHZgSI4eNAt710gmHfeVMtsCDmhUlOT9YosiAa/B1jUOsllMUTVkGM+wo0Wen5etFNCTJ1SwadfOcUGsEAzAwTKAj7Py+VUaR8w8aYDsS3fY9zO3UhwEbMEPO6uPiThY/B8/4R+xo40XpkWfrn8HnYUjmmFTTLTNMrYeRJFO3djXTQyutCOHlqMQIXRjniqjfx+Xh29DkehptVgePFPFX/IjzbjrxmSBbZibtpFB95e83YwtLLB4PTK47MBUkt29uwiTu3XKlEX5YITHIpnxeSc5AqrCw1BKRfcCiQNV7wAiylhN+FDrRDufli1k0TavuQcox8juY8qt1+3OvTLi3swHhkByoaQTmp/IT8bmyiwXqZ360N6qaRl9cpya4OlwrqNKQ8P5MWpdqBjv2KN0+Gm7Q1KEOFonGKR+ELXEL031DagJqHFtLR5RGOHY+xwHieRbPmOlDg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(396003)(39860400002)(366004)(6486002)(38350700002)(86362001)(66946007)(38100700002)(44832011)(52116002)(36756003)(8676002)(83380400001)(7416002)(26005)(4326008)(2616005)(1076003)(186003)(956004)(16526019)(2906002)(316002)(54906003)(66476007)(15650500001)(478600001)(5660300002)(7696005)(66556008)(8936002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: 02J8ThA/mmJ21nvCqksivziAhYC+svOZV3MqFMLz1TzJJqiQnqEeyacfwDTXK9/so9n6gKuv865z6cVkrNLKSfM0J82ZkMJqRVpuRVX3rA2rOiBb1I8oCHBAVFY1mNv8EQLtl/c5LrLQfBu2lfBTfkUTM3+YYSafpsFwNh4PuaxxKqm28Ph6791DZBUxlITXiVwi5ngDHFLj7JzEuEMb9MTkVc4KHpSm1jYtsf1q+mcp+m5Px6Hu+tz6qTb5L2Trct80t3/mrEi861J0dymArMTbl72uqHf1ib0ceehAc+La3I8NsVvTfaLEE8jjXV1ntXf2cTRtlb1vZ6f8JORfjniXXYXF14Gilg9VGOspzlJ0O/ve3a0TG91sJ4Wp4VQaPuhJNh9GjCy0AfezSZk7fEo2i7JrwWscMN3q3wGw7As6+tQ9XTyoCvprmOI9ih8OXE7GNhi3bpMaA+tjGCAncZN4+xJ86D/ELCuRfI6zSycOu4jhgsfAQr+8mta/aEiOt7g09WJq43DNZdKPHe1cwMWHc83PYXIt4W2IQp6L+k/6vEMb6uJr/myXrrXX7pUhgqTr5wh7gPUx3O8JUoqqCE/mRd0LAvPgjXtvAPISnZl/4pYutttMSLMky5+3P0nifndoH0eF7kwH/juKnvz5uCEiAnBAfB5WMofXL53u4mtkRRNAu1jiAlReTT/d7AAY8HpRKT7KJdFZngWuEYZE6HKOYvPX/rWd6A03W+ftznQcEYrU52l5uPkfkUvmXhrPGKwbZcVweCZsH9wdkM49ByZyhs3Q72g2g9Wh3wyjgChJ7xooBZOTQPYSIf40VkUyQfZk486jtViwn8RNevYo85+3U90g2mOSLKuVDOcYMdoT8zsXGE4Aqi/X55ZL5YPxTM2l28xnz3S/fQPZ+pw9yGw+KKr4xtDfnuPhWuk/j8vdesK1mfgxBf9K6VpLx5qJA6tHW96PTnwC7Gg30f42FSh3bZV8MAMF/H/SibHacfOeOAzlaeuLHQMUDVLZHWc4vqV1hOICXyRF+jyiNWh8dLpC2YxmAxIMo2cuW9W+5s0GsYUZ/aPlrpBx58x68tqF5YS7HUO+BJYki56+5EIElX1QhJqsjZ1gZQpOiEFM3xwbJIj81d483Dt8ePy69HKWH+1s4IBBnCbVQJYGWIBZpzfCRGlhNRivarFL1wD1MB+bD0uAWiQcpNDEesnVjjQ8NiLw1cdj6tob8zw0Ut//p3Fgcg69kHQ1pv4TSuezFwRrIKi1RN6zpsCkE4AOq6Nf6NgRuJqpOpoVH8ZdNrBtV5lZYh3Rza9vMPCDJwHPOeE/5L7Qi8pY3RskGcNWxRKi X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2b6babd7-b186-4cd1-16bc-08d925cf6a22 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:05:02.0621 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Mtw2O/0DjWCV1lDJloWXdsLWiMV1y1UG9+BjG+AFcInqkRWvtmtgv6frYVGn6UTT8pdNyo4DpUtRgpvMJLah2w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2766 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The set_memory_{encrypt,decrypt}() are used for changing the pages from decrypted (shared) to encrypted (private) and vice versa. When SEV-SNP is active, the page state transition needs to go through additional steps. If the page is transitioned from shared to private, then perform the following after the encryption attribute is set in the page table: 1. Issue the page state change VMGEXIT to add the memory region in the RMP table. 2. Validate the memory region after the RMP entry is added. To maintain the security guarantees, if the page is transitioned from private to shared, then perform the following before encryption attribute is removed from the page table: 1. Invalidate the page. 2. Issue the page state change VMGEXIT to remove the page from RMP table. To change the page state in the RMP table, use the Page State Change VMGEXIT defined in the GHCB specification. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 24 +++++++ arch/x86/include/asm/sev.h | 4 ++ arch/x86/include/uapi/asm/svm.h | 2 + arch/x86/kernel/sev.c | 107 ++++++++++++++++++++++++++++++ arch/x86/mm/pat/set_memory.c | 14 ++++ 5 files changed, 151 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index ae99a8a756fe..86bb185b5ec1 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -62,6 +62,8 @@ #define GHCB_MSR_PSC_REQ 0x014 #define SNP_PAGE_STATE_PRIVATE 1 #define SNP_PAGE_STATE_SHARED 2 +#define SNP_PAGE_STATE_PSMASH 3 +#define SNP_PAGE_STATE_UNSMASH 4 #define GHCB_MSR_PSC_GFN_POS 12 #define GHCB_MSR_PSC_GFN_MASK GENMASK_ULL(39, 0) #define GHCB_MSR_PSC_OP_POS 52 @@ -86,6 +88,28 @@ #define GHCB_MSR_GPA_REG_RESP 0x013 #define GHCB_MSR_GPA_REG_RESP_VAL(v) ((v) >> GHCB_MSR_GPA_REG_VALUE_POS) +/* SNP Page State Change NAE event */ +#define VMGEXIT_PSC_MAX_ENTRY 253 + +struct __packed snp_page_state_header { + u16 cur_entry; + u16 end_entry; + u32 reserved; +}; + +struct __packed snp_page_state_entry { + u64 cur_page : 12, + gfn : 40, + operation : 4, + pagesize : 1, + reserved : 7; +}; + +struct __packed snp_page_state_change { + struct snp_page_state_header header; + struct snp_page_state_entry entry[VMGEXIT_PSC_MAX_ENTRY]; +}; + #define GHCB_MSR_TERM_REQ 0x100 #define GHCB_MSR_TERM_REASON_SET_POS 12 #define GHCB_MSR_TERM_REASON_SET_MASK 0xf diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7c2cb5300e43..e2141fc28058 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -114,6 +114,8 @@ void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long padd void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned int npages); void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op); +void snp_set_memory_shared(unsigned long vaddr, unsigned int npages); +void snp_set_memory_private(unsigned long vaddr, unsigned int npages); #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -130,6 +132,8 @@ early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned i { } static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op) { } +static inline void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) { } +static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npages) { } #endif #endif diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index 554f75fe013c..41573cf44470 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -108,6 +108,7 @@ #define SVM_VMGEXIT_AP_JUMP_TABLE 0x80000005 #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 +#define SVM_VMGEXIT_PSC 0x80000010 #define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff #define SVM_EXIT_ERR -1 @@ -215,6 +216,7 @@ { SVM_VMGEXIT_NMI_COMPLETE, "vmgexit_nmi_complete" }, \ { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ + { SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 6e9b45bb38ab..4847ac81cca3 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -637,6 +637,113 @@ void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op) WARN(1, "invalid memory op %d\n", op); } +static int page_state_vmgexit(struct ghcb *ghcb, struct snp_page_state_change *data) +{ + struct snp_page_state_header *hdr; + int ret = 0; + + hdr = &data->header; + + /* + * As per the GHCB specification, the hypervisor can resume the guest before + * processing all the entries. The loop checks whether all the entries are + * processed. If not, then keep retrying. + */ + while (hdr->cur_entry <= hdr->end_entry) { + + ghcb_set_sw_scratch(ghcb, (u64)__pa(data)); + + ret = sev_es_ghcb_hv_call(ghcb, NULL, SVM_VMGEXIT_PSC, 0, 0); + + /* Page State Change VMGEXIT can pass error code through exit_info_2. */ + if (WARN(ret || ghcb->save.sw_exit_info_2, + "SEV-SNP: page state change failed ret=%d exit_info_2=%llx\n", + ret, ghcb->save.sw_exit_info_2)) + return 1; + } + + return 0; +} + +static void set_page_state(unsigned long vaddr, unsigned int npages, int op) +{ + struct snp_page_state_change *data; + struct snp_page_state_header *hdr; + struct snp_page_state_entry *e; + unsigned long vaddr_end; + struct ghcb_state state; + struct ghcb *ghcb; + int idx; + + vaddr = vaddr & PAGE_MASK; + vaddr_end = vaddr + (npages << PAGE_SHIFT); + + ghcb = sev_es_get_ghcb(&state); + if (unlikely(!ghcb)) + panic("SEV-SNP: Failed to get GHCB\n"); + + data = (struct snp_page_state_change *)ghcb->shared_buffer; + hdr = &data->header; + + while (vaddr < vaddr_end) { + e = data->entry; + memset(data, 0, sizeof(*data)); + + for (idx = 0; idx < VMGEXIT_PSC_MAX_ENTRY; idx++, e++) { + unsigned long pfn; + + if (is_vmalloc_addr((void *)vaddr)) + pfn = vmalloc_to_pfn((void *)vaddr); + else + pfn = __pa(vaddr) >> PAGE_SHIFT; + + e->gfn = pfn; + e->operation = op; + hdr->end_entry = idx; + + /* + * The GHCB specification provides the flexibility to + * use either 4K or 2MB page size in the RMP table. + * The current SNP support does not keep track of the + * page size used in the RMP table. To avoid the + * overlap request, use the 4K page size in the RMP + * table. + */ + e->pagesize = RMP_PG_SIZE_4K; + vaddr = vaddr + PAGE_SIZE; + + if (vaddr >= vaddr_end) + break; + } + + /* Terminate the guest on page state change failure. */ + if (page_state_vmgexit(ghcb, data)) + sev_es_terminate(1, GHCB_TERM_PSC); + } + + sev_es_put_ghcb(&state); +} + +void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) +{ + if (!sev_feature_enabled(SEV_SNP)) + return; + + pvalidate_pages(vaddr, npages, 0); + + set_page_state(vaddr, npages, SNP_PAGE_STATE_SHARED); +} + +void snp_set_memory_private(unsigned long vaddr, unsigned int npages) +{ + if (!sev_feature_enabled(SEV_SNP)) + return; + + set_page_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE); + + pvalidate_pages(vaddr, npages, 1); +} + int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { u16 startup_cs, startup_ip; diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c index 156cd235659f..20cd5ebc972f 100644 --- a/arch/x86/mm/pat/set_memory.c +++ b/arch/x86/mm/pat/set_memory.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "../mm_internal.h" @@ -2009,8 +2010,21 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc) */ cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT)); + /* + * To maintain the security guarantees of SEV-SNP guest, invalidate + * the memory before clearing the encryption attribute. + */ + if (!enc) + snp_set_memory_shared(addr, numpages); + ret = __change_page_attr_set_clr(&cpa, 1); + /* + * Now that memory is marked encrypted in the page table, validate it. + */ + if (!ret && enc) + snp_set_memory_private(addr, numpages); + /* * After changing the encryption attribute, we need to flush TLBs again * in case any speculative TLB caching occurred (but no need to flush From patchwork Wed Jun 2 14:04:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 453577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A495AC4708F for ; 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dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2766.namprd12.prod.outlook.com (2603:10b6:805:78::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.22; Wed, 2 Jun 2021 14:05:03 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:05:03 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. 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While at it, update the dump_vmcb() to log the VMPL level. See APM2 Table 15-34 and B-4 for more details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 6 ++++-- arch/x86/kvm/svm/svm.c | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 772e60efe243..fb38fae3d5ab 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -230,7 +230,8 @@ struct vmcb_save_area { struct vmcb_seg ldtr; struct vmcb_seg idtr; struct vmcb_seg tr; - u8 reserved_1[43]; + u8 reserved_1[42]; + u8 vmpl; u8 cpl; u8 reserved_2[4]; u64 efer; @@ -295,7 +296,8 @@ struct vmcb_save_area { u64 sw_exit_info_1; u64 sw_exit_info_2; u64 sw_scratch; - u8 reserved_11[56]; + u64 sev_features; + u8 reserved_11[48]; u64 xcr0; u8 valid_bitmap[16]; u64 x87_state_gpa; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 05eca131eaf2..2acf187a3100 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3186,8 +3186,8 @@ static void dump_vmcb(struct kvm_vcpu *vcpu) "tr:", save01->tr.selector, save01->tr.attrib, save01->tr.limit, save01->tr.base); - pr_err("cpl: %d efer: %016llx\n", - save->cpl, save->efer); + pr_err("vmpl: %d cpl: %d efer: %016llx\n", + save->vmpl, save->cpl, save->efer); pr_err("%-15s %016llx %-13s %016llx\n", "cr0:", save->cr0, "cr2:", save->cr2); pr_err("%-15s %016llx %-13s %016llx\n", From patchwork Wed Jun 2 14:04:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C337C47083 for ; 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dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4512.namprd12.prod.outlook.com (2603:10b6:806:71::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.21; Wed, 2 Jun 2021 14:05:05 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:05:04 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 16/22] KVM: SVM: Create a separate mapping for the SEV-ES save area Date: Wed, 2 Jun 2021 09:04:10 -0500 Message-Id: <20210602140416.23573-17-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:05:03 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ae15e75f-5293-4e6c-5450-08d925cf6b86 X-MS-TrafficTypeDiagnostic: SA0PR12MB4512: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bsqa5w+wMXrMF0lXtIqUv8zH13VKM3gc+xoMK0sVUkJwkRptKCQvPTP8sypqPF4z7tp8c7CDz4iUwADMHDOhvMXWRJJcAJDbZ6G9Qd7/+XU677XSYxbF5r5kvwSLHQ+2kRO2djSmp1o4lFySrAYUJpgXGp+qokFyaz9jEH/dMEi5Oz5Nck58isT9oUJZ3rdXzstiQvIM1s27I97z194i7zBU7JVb1vWUheVJehpgCyIrAZe9uD/oS2fV6t9LfjoVAf+Yly6lVzv7aKy9jmsWgtIjJjNmpWRrSxtCvVcSOz9s62aAMEuvrLpMJZo32R3g+c11RiZ5Vn5MLdT2vs3ZjKTx4hTtXssifv/ClLRPxcoKZKUbweCcUKHRYPrCk3aSIT65HTk+H6cm42j3lba7KAy95AmRxlxwMAwA3KUWVKYAXhx18emQDEw2Chv1YHYgy15DntiQ14wkFOOK1Xnta0mc8gfY5YBlfJAA+613lTBCax+StU7YRU4JlQjqrpzM+k1jm/fiNUchzYiD34rtcxk+D11fty14CZ/ssT7uPyT1Gbn8xdqCH/FJPjrImb26O41dkmmxWKCYXubnRBA2Tk/vNoSUV7wAmbR7ovw3OrZVn4b0mfnS/cHSFSJqf125rHh/dyxIQPqP4RNP+uED8Q== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(346002)(396003)(39860400002)(136003)(6666004)(44832011)(7416002)(26005)(2906002)(8676002)(6486002)(7696005)(52116002)(38100700002)(478600001)(956004)(66556008)(186003)(1076003)(36756003)(8936002)(16526019)(66946007)(83380400001)(38350700002)(5660300002)(2616005)(54906003)(4326008)(86362001)(66476007)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: daKOspSpvUq1XmPQodoYcQuE8yQqiJfn6yDrOiabv029p95ZIRLDg+33xMKlrMDTzmSJravq/G+58jCI7Sf2SnBgW/xNZEQGIqX6gli4sCX0BWXW7ZQz/wpAM4+72N1BMPY+a7Q0qMFE3VnazeeTjaFecIjAZrFfugdrXL3MaL6CpL4Bei5ut7m4iEK5LVPTmHpEE7olWmeQ1Mg7+mvSzgZgqHCBaQxkz3bOtUnIeFkVGSvnuhR7oXx/GVzViHQfMjqKUcBnv2s44nfqsGGHpVqD1eQDannQNIUA51qCREa3yb8tqcn+zMjQu/pIb1SdgSaf7C8KOST2ZPsTNj8hcgQn4vt08ylE6hMCiDLYKKMdDlV/e5OMwq5fZz/wpUMCpV+l5MZehekr0jdTD1ri3gRyACtNwIQomvCAwA4a+7S1e+o7oX0cq0nvsG/0YJC0D0IE9dA1dnnjoGnPwXa+j9l6b11R9rZj/XqOZe0Etq2e7gWGQEmj7QOb/JZL3PxNx8IFARPEMrzfXGkT+35kz2s4CkOIHVeV5SfYFzwgz03MNlmGnSvO1v2pvpV7LmQZfEmT+ir5MA/pbgPl8UcFI/q9GohaSi5ebdzORx+uzu07mHZqVe8RmG5I9Ss9XOBPHTXQEv4wMQYm17FB6Hz3O0WPkSYgs8IK06TAqrKc4fnvOHS040Kuwy1ZeFBe2glnJmLwgv+7DvYu7fRl26WGU5HyHI0del/JVrFcti6TMHaCPlmRNH+WnPtzQV+kA4SWKq0h9znUd1hT5OAJk7Dr2KWU5sq2JTSAwRkGW4DEhUQSUa15rBV8BYlNMdOSNjtvnPFKeA8NF2Cr+pUkp2uQgwnDQoHit1/mA9Jt61OsEUN/2OzYxfQq1H5GYA4Pa/++q+p3MWQL5RP0z70NDODTAPP3BqhZTtdlBzRyabpJdsr4ZD5fAfmU/Eb5TjeL5BvOeRU0IFtmtD4Z4xm2/mK+QHJSER7jzpZ/9mWUH49oT1gR84ImN/Rr4/DWVSo07ffen/R+YlCA4Adyxs+PqzrE7dUumy3p33dq8Ci5w8WGs2OPT8otjDPPRTx51GSyuMiSWAAL2zUBsYv+0zZ9/OPrHPTqhFOniJ14t3195DshEmVqRPAvPc7isO2gJCwLz80MwqJdXJigd8KfgonH4dXK50VlJr3gYP5U5u9ipoQdPp5gDtybVaq/HAv8JgrIht1F/XYbYRf/EOEkGvycre9PovwOzelYD9VvRHKZMMsRs9eudkrYLc6v/YP/65lvS9x3S9RfWeZGjAbqeTX2yf53NNn2aRyEGgIqCsCOAG4FcP/ALr9jol1hw4g3qlDnid1D X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ae15e75f-5293-4e6c-5450-08d925cf6b86 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:05:04.4857 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YqZ8wMYqc8+moxJI2Lq0ecVzDmCXTflSjmLAZHGMwwS06AZHXkFwFumh+OlMCSHHYZQHH6ypAcrth8q0F8jS+Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4512 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org From: Tom Lendacky The save area for SEV-ES/SEV-SNP guests, as used by the hardware, is different from the save area of a non SEV-ES/SEV-SNP guest. This is the first step in defining the multiple save areas to keep them separate and ensuring proper operation amongst the different types of guests. Create an SEV-ES/SEV-SNP save area and adjust usage to the new save area definition where needed. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 83 +++++++++++++++++++++++++++++--------- arch/x86/kvm/svm/sev.c | 24 +++++------ arch/x86/kvm/svm/svm.h | 2 +- 3 files changed, 77 insertions(+), 32 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index fb38fae3d5ab..482fb20104da 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -219,6 +219,7 @@ struct vmcb_seg { u64 base; } __packed; +/* Save area definition for legacy and SEV-MEM guests */ struct vmcb_save_area { struct vmcb_seg es; struct vmcb_seg cs; @@ -235,8 +236,58 @@ struct vmcb_save_area { u8 cpl; u8 reserved_2[4]; u64 efer; + u8 reserved_3[112]; + u64 cr4; + u64 cr3; + u64 cr0; + u64 dr7; + u64 dr6; + u64 rflags; + u64 rip; + u8 reserved_4[88]; + u64 rsp; + u64 s_cet; + u64 ssp; + u64 isst_addr; + u64 rax; + u64 star; + u64 lstar; + u64 cstar; + u64 sfmask; + u64 kernel_gs_base; + u64 sysenter_cs; + u64 sysenter_esp; + u64 sysenter_eip; + u64 cr2; + u8 reserved_5[32]; + u64 g_pat; + u64 dbgctl; + u64 br_from; + u64 br_to; + u64 last_excp_from; + u64 last_excp_to; + u8 reserved_6[72]; + u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ +} __packed; + +/* Save area definition for SEV-ES and SEV-SNP guests */ +struct sev_es_save_area { + struct vmcb_seg es; + struct vmcb_seg cs; + struct vmcb_seg ss; + struct vmcb_seg ds; + struct vmcb_seg fs; + struct vmcb_seg gs; + struct vmcb_seg gdtr; + struct vmcb_seg ldtr; + struct vmcb_seg idtr; + struct vmcb_seg tr; + u8 reserved_1[43]; + u8 cpl; + u8 reserved_2[4]; + u64 efer; u8 reserved_3[104]; - u64 xss; /* Valid for SEV-ES only */ + u64 xss; u64 cr4; u64 cr3; u64 cr0; @@ -264,22 +315,14 @@ struct vmcb_save_area { u64 br_to; u64 last_excp_from; u64 last_excp_to; - - /* - * The following part of the save area is valid only for - * SEV-ES guests when referenced through the GHCB or for - * saving to the host save area. - */ - u8 reserved_7[72]; - u32 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ - u8 reserved_7b[4]; + u8 reserved_7[80]; u32 pkru; - u8 reserved_7a[20]; - u64 reserved_8; /* rax already available at 0x01f8 */ + u8 reserved_9[20]; + u64 reserved_10; /* rax already available at 0x01f8 */ u64 rcx; u64 rdx; u64 rbx; - u64 reserved_9; /* rsp already available at 0x01d8 */ + u64 reserved_11; /* rsp already available at 0x01d8 */ u64 rbp; u64 rsi; u64 rdi; @@ -291,21 +334,21 @@ struct vmcb_save_area { u64 r13; u64 r14; u64 r15; - u8 reserved_10[16]; + u8 reserved_12[16]; u64 sw_exit_code; u64 sw_exit_info_1; u64 sw_exit_info_2; u64 sw_scratch; u64 sev_features; - u8 reserved_11[48]; + u8 reserved_13[48]; u64 xcr0; u8 valid_bitmap[16]; u64 x87_state_gpa; } __packed; struct ghcb { - struct vmcb_save_area save; - u8 reserved_save[2048 - sizeof(struct vmcb_save_area)]; + struct sev_es_save_area save; + u8 reserved_save[2048 - sizeof(struct sev_es_save_area)]; u8 shared_buffer[2032]; @@ -315,13 +358,15 @@ struct ghcb { } __packed; -#define EXPECTED_VMCB_SAVE_AREA_SIZE 1032 +#define EXPECTED_VMCB_SAVE_AREA_SIZE 740 +#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 272 #define EXPECTED_GHCB_SIZE PAGE_SIZE static inline void __unused_size_checks(void) { BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); + BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE); BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); } @@ -392,7 +437,7 @@ struct vmcb { /* GHCB Accessor functions */ #define GHCB_BITMAP_IDX(field) \ - (offsetof(struct vmcb_save_area, field) / sizeof(u64)) + (offsetof(struct sev_es_save_area, field) / sizeof(u64)) #define DEFINE_GHCB_ACCESSORS(field) \ static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 5bc887e9a986..d93a1c368b61 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -542,12 +542,20 @@ static int sev_launch_update_data(struct kvm *kvm, struct kvm_sev_cmd *argp) static int sev_es_sync_vmsa(struct vcpu_svm *svm) { - struct vmcb_save_area *save = &svm->vmcb->save; + struct sev_es_save_area *save = svm->vmsa; /* Check some debug related fields before encrypting the VMSA */ - if (svm->vcpu.guest_debug || (save->dr7 & ~DR7_FIXED_1)) + if (svm->vcpu.guest_debug || (svm->vmcb->save.dr7 & ~DR7_FIXED_1)) return -EINVAL; + /* + * SEV-ES will use a VMSA that is pointed to by the VMCB, not + * the traditional VMSA that is part of the VMCB. Copy the + * traditional VMSA as it has been built so far (in prep + * for LAUNCH_UPDATE_VMSA) to be the initial SEV-ES state. + */ + memcpy(save, &svm->vmcb->save, sizeof(svm->vmcb->save)); + /* Sync registgers */ save->rax = svm->vcpu.arch.regs[VCPU_REGS_RAX]; save->rbx = svm->vcpu.arch.regs[VCPU_REGS_RBX]; @@ -574,14 +582,6 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->pkru = svm->vcpu.arch.pkru; save->xss = svm->vcpu.arch.ia32_xss; - /* - * SEV-ES will use a VMSA that is pointed to by the VMCB, not - * the traditional VMSA that is part of the VMCB. Copy the - * traditional VMSA as it has been built so far (in prep - * for LAUNCH_UPDATE_VMSA) to be the initial SEV-ES state. - */ - memcpy(svm->vmsa, save, sizeof(*save)); - return 0; } @@ -2598,7 +2598,7 @@ void sev_es_create_vcpu(struct vcpu_svm *svm) void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu) { struct svm_cpu_data *sd = per_cpu(svm_data, cpu); - struct vmcb_save_area *hostsa; + struct sev_es_save_area *hostsa; /* * As an SEV-ES guest, hardware will restore the host state on VMEXIT, @@ -2608,7 +2608,7 @@ void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu) vmsave(__sme_page_pa(sd->save_area)); /* XCR0 is restored on VMEXIT, save the current host value */ - hostsa = (struct vmcb_save_area *)(page_address(sd->save_area) + 0x400); + hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400); hostsa->xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); /* PKRU is restored on VMEXIT, save the current host value */ diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 2c9ece618b29..0b89aee51b74 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -170,7 +170,7 @@ struct vcpu_svm { } shadow_msr_intercept; /* SEV-ES support */ - struct vmcb_save_area *vmsa; + struct sev_es_save_area *vmsa; struct ghcb *ghcb; struct kvm_host_map ghcb_map; bool received_first_sipi; From patchwork Wed Jun 2 14:04:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBC32C47083 for ; Wed, 2 Jun 2021 14:05:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A123C613EA for ; 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However, the save area for SEV-ES has changed within the hardware causing the relation between the SEV-ES save area to change relative to the GHCB save area. This is the second step in defining the multiple save areas to keep them separate and ensuring proper operation amongst the different types of guests. Create a GHCB save area that matches the GHCB specification. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 48 +++++++++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 482fb20104da..f5edfc552240 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -346,9 +346,49 @@ struct sev_es_save_area { u64 x87_state_gpa; } __packed; +struct ghcb_save_area { + u8 reserved_1[203]; + u8 cpl; + u8 reserved_2[116]; + u64 xss; + u8 reserved_3[24]; + u64 dr7; + u8 reserved_4[16]; + u64 rip; + u8 reserved_5[88]; + u64 rsp; + u8 reserved_6[24]; + u64 rax; + u8 reserved_7[264]; + u64 rcx; + u64 rdx; + u64 rbx; + u8 reserved_8[8]; + u64 rbp; + u64 rsi; + u64 rdi; + u64 r8; + u64 r9; + u64 r10; + u64 r11; + u64 r12; + u64 r13; + u64 r14; + u64 r15; + u8 reserved_9[16]; + u64 sw_exit_code; + u64 sw_exit_info_1; + u64 sw_exit_info_2; + u64 sw_scratch; + u8 reserved_10[56]; + u64 xcr0; + u8 valid_bitmap[16]; + u64 x87_state_gpa; +} __packed; + struct ghcb { - struct sev_es_save_area save; - u8 reserved_save[2048 - sizeof(struct sev_es_save_area)]; + struct ghcb_save_area save; + u8 reserved_save[2048 - sizeof(struct ghcb_save_area)]; u8 shared_buffer[2032]; @@ -359,6 +399,7 @@ struct ghcb { #define EXPECTED_VMCB_SAVE_AREA_SIZE 740 +#define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 272 #define EXPECTED_GHCB_SIZE PAGE_SIZE @@ -366,6 +407,7 @@ struct ghcb { static inline void __unused_size_checks(void) { BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE); + BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE); BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE); BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE); BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE); @@ -437,7 +479,7 @@ struct vmcb { /* GHCB Accessor functions */ #define GHCB_BITMAP_IDX(field) \ - (offsetof(struct sev_es_save_area, field) / sizeof(u64)) + (offsetof(struct ghcb_save_area, field) / sizeof(u64)) #define DEFINE_GHCB_ACCESSORS(field) \ static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \ From patchwork Wed Jun 2 14:04:12 2021 Content-Type: text/plain; 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Wed, 2 Jun 2021 14:05:10 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 18/22] KVM: SVM: Update the SEV-ES save area mapping Date: Wed, 2 Jun 2021 09:04:12 -0500 Message-Id: <20210602140416.23573-19-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:05:08 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7a1f731-6dde-4120-d883-08d925cf6e87 X-MS-TrafficTypeDiagnostic: SA0PR12MB4446: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: azoIlvM90dIUYYvu9EgjNvJmVAXVh3hums+CkhXa8X+mRw0o8/MZjn0s9k68NTVjR/01lMBePBrbtEzDTtaF3rUTNoTrX7Fhunot1AqeQ5DaCj1cb2G4/0JkmoeCMlXlXBLIvQ7dWa1KCDRXxLs87KpZ+bTAP5lK7ZuPDUeuER30jhLH+oWp2H7MygLCL+8VcCuzGBe7UV8rZf7UBvWYjyRIjPU7NkQliYNcHTLpIMktF/T+e56ouzZX85lsmmpExmbIldwu0yxO/j5VPbY8VpydBu3nLPQbRVhwLmFp9pQeZY1wlGjVkYRFqbf+UFYoFJGljXPALXqce08NPZvCTmMcxe6MSUPpwGAH9AFEjk1NAIWR8LuVkHGVt8YYbjzWKlJkzBuq2BqCBMAKrdLZ4NXBAhlwnYs+sdTGolFZafWYx+vSN0xBi0BYoDuYJGciaGy3lGWXctNBT4uBk2OOfSXOTeXjKgp1GGG76enG4rTbEmW02nNRVKR9CLZ3CQQPh3wx6XwgRmDjwOISwYJO78nyx55mbdqpz/vGjJyep9hAYpRijq+gkV4EZhCM/+8j7YUG6BaeLpOR9WDBYAGbnerJUnTxWfj4KTuZ3tBRrGksBhIzaj+JNQywGlyHJWVRhAsQT2TRkO1aBlQ+O+t4gQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(366004)(396003)(346002)(136003)(39860400002)(478600001)(8936002)(7416002)(16526019)(44832011)(66476007)(186003)(66946007)(4326008)(8676002)(7696005)(52116002)(1076003)(86362001)(83380400001)(38350700002)(6486002)(15650500001)(316002)(6666004)(5660300002)(54906003)(38100700002)(26005)(66556008)(36756003)(2616005)(956004)(2906002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: PuX2D00Oq5LoPU88p42woyigAKrolJ3K7QdfjsVSzfzRdHaYlMZc1uvEIA35SCYo31fh+aR5C19SAbs9XwxGMjZA0f/ndsTy48w5R0iC5mkLG6MdoUR9fWrpZ2wqB/6HKVwvFiaLu5csIOWgKwyiTmCZC+J8bh/FkELg2HcOzEfekd43xXXwmgNH/sOaBR6armIuP+PzJW+OIElac5Vw01ruYovE2LKARh/+Dsjxmob72iBnZY2o4TVgS7LDvsUfX+e00uLGBsJ/U2ivWp6QJVzJJj78vHH0kcGo14Gex341c+YWVMiGHla96Nc7uKsGudS2u+zSmDI1GPt6cUIXGEj4PXAGiVNru2UzXO/SLaJ2h2PzgSvOfKfI81mFjLHs38RQ0U4r7Xp84CTmGY3KB6wMsJu5Pymad6xleT8BjxhfAJVGIzQXo+9XsSH9afg/Yt4L7T1ltONOLQH7aNdnx9q1ZDnnk5fa0zmQCguxfTay4/bwjLlDb0hQqILA01stb+WDM1e8Gvp5ooWKdoyE5+6GJ5nm8pk1/cwQtlf2imK0nwRpxj9ZdLBoouNmdVd0MIWIDih8IyumNdhR4v3nvrydVeYzZYf3GQhS96jbNGt/IMKVsXfFIMjyBNkhnM/Vp7kpgGTYxyIerUYEGl9xHz6q5Vfud6qEEbx8YCF6n2K/f0EjxPRCMH0GJ2QUBzDMKzZgnAZYQQKVcaRJYAIjVySZq2TUVO9J7marRtFemdN0urEiYJGy9Mjezf7tYhegYqLULki4zC7m3IYt1PtS6iVxQeFdNIsP6DWDn1R/jHBi01/CfJk1k1qW2KsHKTmMRexKM0eIa/V6TXdDtMyBeGaug3eUTI/0GmH/XgyNeZjE+BcUrJxJqnrchs+UcN6PoJsc0vJKEM0L7WIcC38McuypElFV6SKHdPY+hl4aJmMU9SBnOqDOYCwSuY6Gp8ldRvOiYfKoA3PnQf57oesjTTuRGGLiB+S4Om827BPbTzFdm83De16HoGuXRSYgvBCoKdxzPTaMC9eakSBC9ExhueoH1xW9DqU33AcnwhYpXDpzLYxoXI+t6YsQAy+O4HpmpEKuVvcbc9PFmRDtsIEZ3heKuZ+ElUhfMc60W3sLvEiFxx4M7xCFtFOH1f4Pu6++GfB/kj7k4IdSqBpBt0fpz7ZuRYlTFBSjXXpAklcl4FoaHFU9GjmOxeV8spETaEcVTrXKUWuMFY5XF6bmu/qwaRYcNigR+WeQ7NzmWDxMkZPVW266TnXVTIQ8eYbzdFVI0t4H/vTdRR2VoIdM2C71BV/QX6XvKRAyNmf/ji3K5Bik8QNIzDind3IaHJ7wS26m X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7a1f731-6dde-4120-d883-08d925cf6e87 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:05:10.0555 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +lPhjBSrjCY65HT8dC0Uj4XeD1Ah7/jEpdR357tQkuxVbhdK1QmbjcWu0VR4rNKZ3U98000CjkN3LNC4+GXjuQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4446 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org From: Tom Lendacky This is the final step in defining the multiple save areas to keep them separate and ensuring proper operation amongst the different types of guests. Update the SEV-ES/SEV-SNP save area to match the APM. This save area will be used for the upcoming SEV-SNP AP Creation NAE event support. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/svm.h | 66 +++++++++++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index f5edfc552240..b6f358d6b975 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -282,7 +282,13 @@ struct sev_es_save_area { struct vmcb_seg ldtr; struct vmcb_seg idtr; struct vmcb_seg tr; - u8 reserved_1[43]; + u64 vmpl0_ssp; + u64 vmpl1_ssp; + u64 vmpl2_ssp; + u64 vmpl3_ssp; + u64 u_cet; + u8 reserved_1[2]; + u8 vmpl; u8 cpl; u8 reserved_2[4]; u64 efer; @@ -295,9 +301,19 @@ struct sev_es_save_area { u64 dr6; u64 rflags; u64 rip; - u8 reserved_4[88]; + u64 dr0; + u64 dr1; + u64 dr2; + u64 dr3; + u64 dr0_addr_mask; + u64 dr1_addr_mask; + u64 dr2_addr_mask; + u64 dr3_addr_mask; + u8 reserved_4[24]; u64 rsp; - u8 reserved_5[24]; + u64 s_cet; + u64 ssp; + u64 isst_addr; u64 rax; u64 star; u64 lstar; @@ -308,7 +324,7 @@ struct sev_es_save_area { u64 sysenter_esp; u64 sysenter_eip; u64 cr2; - u8 reserved_6[32]; + u8 reserved_5[32]; u64 g_pat; u64 dbgctl; u64 br_from; @@ -317,12 +333,12 @@ struct sev_es_save_area { u64 last_excp_to; u8 reserved_7[80]; u32 pkru; - u8 reserved_9[20]; - u64 reserved_10; /* rax already available at 0x01f8 */ + u8 reserved_8[20]; + u64 reserved_9; /* rax already available at 0x01f8 */ u64 rcx; u64 rdx; u64 rbx; - u64 reserved_11; /* rsp already available at 0x01d8 */ + u64 reserved_10; /* rsp already available at 0x01d8 */ u64 rbp; u64 rsi; u64 rdi; @@ -334,16 +350,34 @@ struct sev_es_save_area { u64 r13; u64 r14; u64 r15; - u8 reserved_12[16]; - u64 sw_exit_code; - u64 sw_exit_info_1; - u64 sw_exit_info_2; - u64 sw_scratch; + u8 reserved_11[16]; + u64 guest_exit_info_1; + u64 guest_exit_info_2; + u64 guest_exit_int_info; + u64 guest_nrip; u64 sev_features; - u8 reserved_13[48]; + u64 vintr_ctrl; + u64 guest_exit_code; + u64 virtual_tom; + u64 tlb_id; + u64 pcpu_id; + u64 event_inj; u64 xcr0; - u8 valid_bitmap[16]; - u64 x87_state_gpa; + u8 reserved_12[16]; + + /* Floating point area */ + u64 x87_dp; + u32 mxcsr; + u16 x87_ftw; + u16 x87_fsw; + u16 x87_fcw; + u16 x87_fop; + u16 x87_ds; + u16 x87_cs; + u64 x87_rip; + u8 fpreg_x87[80]; + u8 fpreg_xmm[256]; + u8 fpreg_ymm[256]; } __packed; struct ghcb_save_area { @@ -400,7 +434,7 @@ struct ghcb { #define EXPECTED_VMCB_SAVE_AREA_SIZE 740 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 -#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032 +#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 272 #define EXPECTED_GHCB_SIZE PAGE_SIZE From patchwork Wed Jun 2 14:04:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71E45C4708F for ; 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dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2766.namprd12.prod.outlook.com (2603:10b6:805:78::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.22; Wed, 2 Jun 2021 14:05:15 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:05:14 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 19/22] x86/sev-snp: SEV-SNP AP creation support Date: Wed, 2 Jun 2021 09:04:13 -0500 Message-Id: <20210602140416.23573-20-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:05:10 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4312be5c-4e8b-4ee3-90f2-08d925cf6f9b X-MS-TrafficTypeDiagnostic: SN6PR12MB2766: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yW0m1BrRPkSWxshatIcURzsJ1HFmYVpEM3HLDrnh44DrprW+Su9jQcKe14mom9pWldVYqqVOxxsUTPW+AI8KDuoz/cIFJxAWnaJP+qqZkHZynSXaxbyUb0BNYXgZyklJ7RvmTKWkRhiT6cH/voLFVanTDibPrckI4fU6i5Q/6AUFJEyhokZ0st4p2cZBr9xe4cCNvcHDIAws7amGsmdK2VxdVg/0MWfd5ysLuEpzVEoCfWcDIS+DRY+/zrY/POZQtntHrAfdl8Y//jof9r5NYD3Dy+nxHFvgpdjTMs0JdORrWnlNWRXPYzSvRV8/ums9mIItuV764rgPbVCRBUEwdMrPh79UzAMWXpHEwb2FxsVNyT+iJpBRlH7igzahLTUxdS6VTN0TWiHc76Cg0hswGlQ7zxqJ1kChBTEFt1FFo23WgkSELtc7eN+ywYSL5TfE6zomvqOimFPBI6GO3QYxyEl+SBjm7WjdZZPCpJJnuOX1c9aEMUndQ040upGhxt7CsEufrImx54jHzDtYIecjpYjNnihLmF0vFLXJEOW4jy7wkbiI7UIxwdIEWEK8xGXh1VS+R7D/Qznahi9z+2FVMG6G7XXwFpSoPr1kBfamaEPSIT1zjOpLVdV4k6Q0XB0a6Ui9lRO4l+LvKERa2NgyXA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(396003)(39860400002)(366004)(6486002)(38350700002)(86362001)(66946007)(38100700002)(44832011)(52116002)(36756003)(8676002)(83380400001)(7416002)(26005)(4326008)(2616005)(1076003)(186003)(956004)(16526019)(2906002)(316002)(54906003)(66476007)(478600001)(5660300002)(30864003)(7696005)(66556008)(8936002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: AJct5giUYp2c8D2lglFOkKRXId3NI72fKcT9GWgL53XEM3Gw96xxbBP14B/ZyK7FC4eGOR+QRHL7UpaOK2+xvsPByVkwRnseDHI/9os17JYr5xhhm6ko8Gtq1ItL0KqSvTh6Lnuc5ezLuGDbz+k+aMUYGQMMm+Bxq13i3N93ZEQ40A/BK/iqQjZ0BLVhIy3eSyt5sFYeJlUAwqBY1txN7ttoApGcHI19TRF3LEAexpvLIaB0Qmpz5j/+mxcs4sorQLWi1Aa2sSrSC1aPTFUaXzzXJDbEGQbzKcfh3rkkXw6cNa0+uSxNrBxcl5JqldzbiLp9dsmDs/775yCOPDjDIfjIou5givSGsQKczF93ORbKo3GSKyqoe6jFbz99N4/zqZkjklFNlHRgZNlw/8RfqaBva7+uRRKtYeU1ATUQOa6ob9AcheY0XsjlG19NvKbTWBF6tYmMQLwTiZYNTysC4sZ2pa7SlRzroFEB7g/AhDWYfCAEyj/h2AqT7aWaNhfOfPIVQMM3wsQqYwG4UsvMlmsAImu5uMxvc789fJIZuFpUYKFIWCee5RXgyqD3sfVyM4QwMeqgo525BAcUds2+ON6bqnCZvFUfy/eG1Ze9KebSSyIYC9LH9wVCFHwO6e5MEElUopUuXHTyIvBFwZ6EmYOuheBGNCLCwrzZ46kICws1sSvcBytYJ1ZRB19en+UF0a2lAhUN6xiXYX3Vdq3SRd7FEeiliWDuPFwSbrXltYVtdgqaw/b9Cn7sNSBYJGD4Cj9gg5MiJ7TftBsSnZL4vs28xdboN+++311Wbu6+E1o7Gujx+jm8zLCqHEYB99IDW3FIUP12U3H2KQS0m+8J/yMZPZw92rbUPFbkbvMPDOuuCBD8QlRVCd1cJb/EyBaiLlL8RA546rnlHmRkb/G1exj1Rhn6DPVpWhWVXsHNSJM7Q0oCdIoHnrKa0Ya3UgKHiiaeUEejAIvM+0vQOzCJT0RSmKg1V5y413fYu1SeZdNr0NERK2q+ltS2z1LShxHudMYySXEIgwrp30SEJDGYcm+pC8YVM6bgpdb9VWhdGIbq8r3HM1PBW0CkCZC7LhpaI8UZRMOJE9HUzYdlJU0J+8DeEd1K/bI9urfq8EnHvj9+FTL1mD+kqOcNAcQvz5i7x1726VSE5B3/AeFgusa9KqnNFaaE00JlkJv/keTyoHT5Z/x69wTqEudDf8CVel0mKezK4ctE3oZhawKeHqUw/qnJNa9xVUIvjusYRGYvZb2TyptPjOT/OeSiOHwz5W47+MunCYqYq4vYZ9cmags3o0GifqKS+3A5pHsNL/BTebXaz0CTLFdmtF5uLm9AOJtO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4312be5c-4e8b-4ee3-90f2-08d925cf6f9b X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:05:14.8058 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SzL4latpdybniT0QZcXdRzxFvCxypTpKRjpNCb6CRv7V/zqW4+37FX9MpZioVpfnQN3hVUCblFSwu3JQ4IccCw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2766 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org From: Tom Lendacky To provide a more secure way to start APs under SEV-SNP, use the SEV-SNP AP Creation NAE event. This allows for guest control over the AP register state rather than trusting the hypervisor with the SEV-ES Jump Table address. During native_smp_prepare_cpus(), invoke an SEV-SNP function that, if SEV-SNP is active, will set or override apic->wakeup_secondary_cpu. This will allow the SEV-SNP AP Creation NAE event method to be used to boot the APs. Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev-common.h | 1 + arch/x86/include/asm/sev.h | 13 ++ arch/x86/include/uapi/asm/svm.h | 5 + arch/x86/kernel/sev-shared.c | 5 + arch/x86/kernel/sev.c | 206 ++++++++++++++++++++++++++++++ arch/x86/kernel/smpboot.c | 3 + 6 files changed, 233 insertions(+) diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h index 86bb185b5ec1..47aa57bf654a 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -57,6 +57,7 @@ (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) #define GHCB_HV_FT_SNP BIT_ULL(0) +#define GHCB_HV_FT_SNP_AP_CREATION (BIT_ULL(1) | GHCB_HV_FT_SNP) /* SNP Page State Change */ #define GHCB_MSR_PSC_REQ 0x014 diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index e2141fc28058..640108402ae9 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -71,6 +71,13 @@ enum snp_mem_op { MEMORY_SHARED }; +#define RMPADJUST_VMPL_MAX 3 +#define RMPADJUST_VMPL_MASK GENMASK(7, 0) +#define RMPADJUST_VMPL_SHIFT 0 +#define RMPADJUST_PERM_MASK_MASK GENMASK(7, 0) +#define RMPADJUST_PERM_MASK_SHIFT 8 +#define RMPADJUST_VMSA_PAGE_BIT BIT(16) + #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); @@ -116,6 +123,9 @@ void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op); void snp_set_memory_shared(unsigned long vaddr, unsigned int npages); void snp_set_memory_private(unsigned long vaddr, unsigned int npages); + +void snp_setup_wakeup_secondary_cpu(void); + #else static inline void sev_es_ist_enter(struct pt_regs *regs) { } static inline void sev_es_ist_exit(void) { } @@ -134,6 +144,9 @@ early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, unsigned i static inline void __init snp_prep_memory(unsigned long paddr, unsigned int sz, int op) { } static inline void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) { } static inline void snp_set_memory_private(unsigned long vaddr, unsigned int npages) { } + +static inline void snp_setup_wakeup_secondary_cpu(void) { } + #endif #endif diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index 41573cf44470..c0152186a008 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -109,6 +109,10 @@ #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 #define SVM_VMGEXIT_PSC 0x80000010 +#define SVM_VMGEXIT_AP_CREATION 0x80000013 +#define SVM_VMGEXIT_AP_CREATE_ON_INIT 0 +#define SVM_VMGEXIT_AP_CREATE 1 +#define SVM_VMGEXIT_AP_DESTROY 2 #define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff #define SVM_EXIT_ERR -1 @@ -217,6 +221,7 @@ { SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ { SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \ + { SVM_VMGEXIT_AP_CREATION, "vmgexit_ap_creation" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index b62226bf51b9..7139c9ba59b2 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -32,6 +32,11 @@ static bool __init sev_es_check_cpu_features(void) return true; } +static bool snp_ap_creation_supported(void) +{ + return (hv_features & GHCB_HV_FT_SNP_AP_CREATION) == GHCB_HV_FT_SNP_AP_CREATION; +} + static bool __init sev_snp_check_hypervisor_features(void) { if (ghcb_version < 2) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 4847ac81cca3..8f7ef35a25ef 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -31,6 +32,7 @@ #include #include #include +#include #include "sev-internal.h" @@ -106,6 +108,8 @@ struct ghcb_state { static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data); DEFINE_STATIC_KEY_FALSE(sev_es_enable_key); +static DEFINE_PER_CPU(struct sev_es_save_area *, snp_vmsa); + /* Needed in vc_early_forward_exception */ void do_early_exception(struct pt_regs *regs, int trapnr); @@ -744,6 +748,208 @@ void snp_set_memory_private(unsigned long vaddr, unsigned int npages) pvalidate_pages(vaddr, npages, 1); } +static int snp_rmpadjust(void *va, unsigned int vmpl, unsigned int perm_mask, bool vmsa) +{ + unsigned int attrs; + int err; + + attrs = (vmpl & RMPADJUST_VMPL_MASK) << RMPADJUST_VMPL_SHIFT; + attrs |= (perm_mask & RMPADJUST_PERM_MASK_MASK) << RMPADJUST_PERM_MASK_SHIFT; + if (vmsa) + attrs |= RMPADJUST_VMSA_PAGE_BIT; + + /* Perform RMPADJUST */ + asm volatile (".byte 0xf3,0x0f,0x01,0xfe\n\t" + : "=a" (err) + : "a" (va), "c" (0), "d" (attrs) + : "memory", "cc"); + + return err; +} + +static int snp_clear_vmsa(void *vmsa) +{ + /* + * Clear the VMSA attribute for the page: + * RDX[7:0] = 1, Target VMPL level, must be numerically + * higher than current level (VMPL0) + * RDX[15:8] = 0, Target permission mask (not used) + * RDX[16] = 0, Not a VMSA page + */ + return snp_rmpadjust(vmsa, RMPADJUST_VMPL_MAX, 0, false); +} + +static int snp_set_vmsa(void *vmsa) +{ + /* + * To set the VMSA attribute for the page: + * RDX[7:0] = 1, Target VMPL level, must be numerically + * higher than current level (VMPL0) + * RDX[15:8] = 0, Target permission mask (not used) + * RDX[16] = 1, VMSA page + */ + return snp_rmpadjust(vmsa, RMPADJUST_VMPL_MAX, 0, true); +} + +#define INIT_CS_ATTRIBS (SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | SVM_SELECTOR_READ_MASK | SVM_SELECTOR_CODE_MASK) +#define INIT_DS_ATTRIBS (SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | SVM_SELECTOR_WRITE_MASK) + +#define INIT_LDTR_ATTRIBS (SVM_SELECTOR_P_MASK | 2) +#define INIT_TR_ATTRIBS (SVM_SELECTOR_P_MASK | 3) + +static int snp_wakeup_cpu_via_vmgexit(int apic_id, unsigned long start_ip) +{ + struct sev_es_save_area *cur_vmsa; + struct sev_es_save_area *vmsa; + struct ghcb_state state; + struct ghcb *ghcb; + unsigned long flags; + u8 sipi_vector; + u64 cr4; + int cpu; + int ret; + + if (!snp_ap_creation_supported()) + return -ENOTSUPP; + + /* Override start_ip with known SEV-ES/SEV-SNP starting RIP */ + if (start_ip == real_mode_header->trampoline_start) { + start_ip = real_mode_header->sev_es_trampoline_start; + } else { + WARN_ONCE(1, "unsupported SEV-SNP start_ip: %lx\n", start_ip); + return -EINVAL; + } + + /* Find the logical CPU for the APIC ID */ + for_each_present_cpu(cpu) { + if (arch_match_cpu_phys_id(cpu, apic_id)) + break; + } + if (cpu >= nr_cpu_ids) + return -EINVAL; + + cur_vmsa = per_cpu(snp_vmsa, cpu); + vmsa = (struct sev_es_save_area *)get_zeroed_page(GFP_KERNEL); + if (!vmsa) + return -ENOMEM; + + /* CR4 should maintain the MCE value */ + cr4 = native_read_cr4() & ~X86_CR4_MCE; + + /* Set the CS value based on the start_ip converted to a SIPI vector */ + sipi_vector = (start_ip >> 12); + vmsa->cs.base = sipi_vector << 12; + vmsa->cs.limit = 0xffff; + vmsa->cs.attrib = INIT_CS_ATTRIBS; + vmsa->cs.selector = sipi_vector << 8; + + /* Set the RIP value based on start_ip */ + vmsa->rip = start_ip & 0xfff; + + /* Set VMSA entries to the INIT values as documented in the APM */ + vmsa->ds.limit = 0xffff; + vmsa->ds.attrib = INIT_DS_ATTRIBS; + vmsa->es = vmsa->ds; + vmsa->fs = vmsa->ds; + vmsa->gs = vmsa->ds; + vmsa->ss = vmsa->ds; + + vmsa->gdtr.limit = 0xffff; + vmsa->ldtr.limit = 0xffff; + vmsa->ldtr.attrib = INIT_LDTR_ATTRIBS; + vmsa->idtr.limit = 0xffff; + vmsa->tr.limit = 0xffff; + vmsa->tr.attrib = INIT_TR_ATTRIBS; + + vmsa->efer = 0x1000; /* Must set SVME bit */ + vmsa->cr4 = cr4; + vmsa->cr0 = 0x60000010; + vmsa->dr7 = 0x400; + vmsa->dr6 = 0xffff0ff0; + vmsa->rflags = 0x2; + vmsa->g_pat = 0x0007040600070406ULL; + vmsa->xcr0 = 0x1; + vmsa->mxcsr = 0x1f80; + vmsa->x87_ftw = 0x5555; + vmsa->x87_fcw = 0x0040; + + /* + * Set the SNP-specific fields for this VMSA: + * VMPL level + * SEV_FEATURES (matches the SEV STATUS MSR right shifted 2 bits) + */ + vmsa->vmpl = 0; + vmsa->sev_features = sev_status >> 2; + + /* Switch the page over to a VMSA page now that it is initialized */ + ret = snp_set_vmsa(vmsa); + if (ret) { + pr_err("set VMSA page failed (%u)\n", ret); + free_page((unsigned long)vmsa); + + return -EINVAL; + } + + /* Issue VMGEXIT AP Creation NAE event */ + local_irq_save(flags); + + ghcb = sev_es_get_ghcb(&state); + + vc_ghcb_invalidate(ghcb); + ghcb_set_rax(ghcb, vmsa->sev_features); + ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_CREATION); + ghcb_set_sw_exit_info_1(ghcb, ((u64)apic_id << 32) | SVM_VMGEXIT_AP_CREATE); + ghcb_set_sw_exit_info_2(ghcb, __pa(vmsa)); + + sev_es_wr_ghcb_msr(__pa(ghcb)); + VMGEXIT(); + + if (!ghcb_sw_exit_info_1_is_valid(ghcb) || + lower_32_bits(ghcb->save.sw_exit_info_1)) { + pr_alert("SNP AP Creation error\n"); + ret = -EINVAL; + } + + sev_es_put_ghcb(&state); + + local_irq_restore(flags); + + /* Perform cleanup if there was an error */ + if (ret) { + int err = snp_clear_vmsa(vmsa); + + if (err) + pr_err("clear VMSA page failed (%u), leaking page\n", err); + else + free_page((unsigned long)vmsa); + + vmsa = NULL; + } + + /* Free up any previous VMSA page */ + if (cur_vmsa) { + int err = snp_clear_vmsa(cur_vmsa); + + if (err) + pr_err("clear VMSA page failed (%u), leaking page\n", err); + else + free_page((unsigned long)cur_vmsa); + } + + /* Record the current VMSA page */ + cur_vmsa = vmsa; + + return ret; +} + +void snp_setup_wakeup_secondary_cpu(void) +{ + if (!sev_feature_enabled(SEV_SNP)) + return; + + apic->wakeup_secondary_cpu = snp_wakeup_cpu_via_vmgexit; +} + int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) { u16 startup_cs, startup_ip; diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 0ad5214f598a..973145081818 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -82,6 +82,7 @@ #include #include #include +#include #ifdef CONFIG_ACPI_CPPC_LIB #include @@ -1379,6 +1380,8 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) smp_quirk_init_udelay(); speculative_store_bypass_ht_init(); + + snp_setup_wakeup_secondary_cpu(); } void arch_thaw_secondary_cpus_begin(void) From patchwork Wed Jun 2 14:04:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2DE3C4708F for ; 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dkim=none (message not signed) header.d=none; kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4592.namprd12.prod.outlook.com (2603:10b6:806:9b::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.22; Wed, 2 Jun 2021 14:05:21 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:05:21 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 20/22] x86/boot: Add Confidential Computing address to setup_header Date: Wed, 2 Jun 2021 09:04:14 -0500 Message-Id: <20210602140416.23573-21-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; Wed, 2 Jun 2021 14:05:15 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a92c46d9-f8a3-4e3b-21f1-08d925cf7263 X-MS-TrafficTypeDiagnostic: SA0PR12MB4592: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F0cXrhWG18BEahp2Q6dZb4TGGlTTaFzxXdFnj0kA9fEy67BbeOsTX2qqaF1UtLi2EtuOeRE6ai5DtDAZb+dVC0YBMDeMjK9oWaVX6oR9YTxyhy71YGHGoz8RieqPWBcif72MlZikCTCGrXV10/rERjwf57mh1f7nQEq0RCnQt+kMuPgkpf+rBoxiPm+Si1OLOWRzb+fDz4wZaG915Olgx/X7ObVytjFzSVLGT6m3JjcwH2d9WjlyBeowQQRmoP1YousfgXwalJI/UssRKwUXSX6AEPhpzb5l7W+mZmZTFueUD5rBsRWIpMnx+ITUjB8AVsN4gfVNrHpdmNoNCEXSV15vUDjI5s3a5GHbL9xTOCWQHGW/foFt5MsA5IPlpSMIkGitnsx8jeMzUsPtAH4kZBXai861c7elLee6kwApEeWwcH9B3IihVREQ3nr1LPVfI3ehXMckgmRAOQznx9374O3F2u66LzewKdo1PvHtE9uY7/BMfVtrMcNNJZ49etPRHwguFx+KKhCFs3KyjKZmWU2G4LvTLE50lViB7Wv4w03kDFfSWPkzZS75TN8bL6at/w8mvFkbQc/OLWLlBSLksu+Mlu4QLcoYHm3BMdP6dqMiGk10tj4zO0+74okT4oA4Y1lyCSFtUjT3EyJPSmG5ZA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SN6PR12MB2718.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(396003)(346002)(136003)(39860400002)(366004)(376002)(956004)(8936002)(8676002)(36756003)(478600001)(54906003)(83380400001)(1076003)(44832011)(2616005)(38350700002)(38100700002)(5660300002)(66476007)(66556008)(2906002)(66946007)(4326008)(26005)(86362001)(186003)(7696005)(52116002)(16526019)(6486002)(7416002)(316002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: ra33CGRP85fegl8iq9FEQ6oPwIkZoHlHWOMlxpLIzQsVFKBVg0rsmNTVy6MXRumvpjyHRRMrefRQ81C0v1x8RFcAg6YZ570SbAae3e0rEect55eBqswEvQ53cuXwgdtpHaWNLD/OJlwKviMczP5tb9MEukZ8zueOA4u/BG8WpYKTrHzPw+gr/0SJtRn3jhJd6m8JgdpQQp2r8dGVuz4EAyXHAKDdnlOp54tEv8NYyknX2XS9r4go634w3ZLmeD0Q0D1LQDea0xA9KoUvwZkjNikyJftMJyU1P+mAykXhfAj7nP4P1ivWoUCr7F4Oip8iRsIbSrXxm7prrcIBl9lQRssPj6IdIDCh6o1BoYroHajJTBex62/W2A0gsfqDhD5q3M7Fx/CX3Q4gK8SKinjGwtk0AqMhmmUAA8R4pZC3/lyjGRZT9q7+gGvXO8wGwnCmqzl0P7TOwd0d3PDchDp3s5dlI65Mue94idLKwm4RNUD2CCz86w+q7MqtQNNc1cLZzLSlpmg3ba8yiXJq7dvvLuA+UsNVncnE1FVdSyTrna1BlWK2pOGceykWmX18ROSVZGBeFjXQ7oBOeurc/3WOK9UUsgWLa4HCX2QzNf0xkxaK8rXOalAfGSAQIwRd8OqGjoBmkCR+XUIm5bc6FRfkWKLj5E063L6EX9u+VIzNLBiOClIyDNnQDLnubjrk5X3QLjqk2sncxkrBCpCGgvZaBxLrbaPPEN9frS1dwF36LJP7VAKnFbSROL3PNMpcOivkhGn5fNOJdjpnkqRj9TZe1TtPDuXnswJSKBn4bUIQxA7aaswq4xOGcaLN5HW1zRDLQ50D3cty4RZ6aO3kEhv4+0qoZ0eEHSsEUQ9tbfXEYq5448iJ7xQj9FxzFJIpH+1SPKHh7Ty0180fMUPkjatfct7BiSjTxlXz5GR8Dih5LSVVvjEbrcE/v0rnwQoxwmHsH1OKk4XvMx+on2KREDuqdRTY02d3TSYUJDxQSYayhmvtk9pCbe1/rWTC5iqNqpzK93S6FaAxIxEybxTMyy3lvRg4/GEdfiCYM0B/L9sZngEUY0Lt4L6oT3rcH2T/Fo1yayOyr5NLvF0JUv3IVgXtY3TjhtNujSuUcQGFU33KDJ7ay/sQyEoHrZ+MRWjrjFnD00RE8bgXCXjlZAJSDKqxU+k6dKD8MXXNh3yiQzolUMsVhW4fRSoIQpTYsKPVoGwhBXAlEHyDU4SzVLFdLvDhTq2MuIrfSfddriVaHTgT6CpmUX3JBU01OpJNS2ew1tN9gVH1vl1Zdm/n848daIbuz5wHyyFa9Vz6tIoUL2wPGP4xl5oCK9gmUB5pZzsY418u X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a92c46d9-f8a3-4e3b-21f1-08d925cf7263 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2021 14:05:20.9283 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qiBqVOiTMkq+ZLdaQks8jpOvp81eCsojAUjdOo60nP6Mw25+LxwJTUulJQPrO8q4/rbYGPZ4jsK8C8o6AVWrTw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4592 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org While launching the encrypted guests, the hypervisor may need to provide some additional information that will used during the guest boot. In the case of AMD SEV-SNP the information includes the address of the secrets and CPUID pages. The secrets page contains information such as a VM to PSP communication key and CPUID page contain PSP filtered CPUID values. When booting under the EFI based BIOS, the EFI configuration table contains an entry for the confidential computing blob. In order to support booting encrypted guests on non EFI VM, the hypervisor to pass these additional information to the kernel with different method. For this purpose expand the struct setup_header to hold the physical address of the confidential computing blob location. Being zero means it isn't passed. Signed-off-by: Brijesh Singh --- Documentation/x86/boot.rst | 27 +++++++++++++++++++++++++++ arch/x86/boot/header.S | 7 ++++++- arch/x86/include/uapi/asm/bootparam.h | 1 + 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/Documentation/x86/boot.rst b/Documentation/x86/boot.rst index fc844913dece..9b32805617bb 100644 --- a/Documentation/x86/boot.rst +++ b/Documentation/x86/boot.rst @@ -75,6 +75,8 @@ Protocol 2.14 BURNT BY INCORRECT COMMIT DO NOT USE!!! ASSUME SAME AS 2.13. Protocol 2.15 (Kernel 5.5) Added the kernel_info and kernel_info.setup_type_max. + +Protocol 2.16 (Kernel 5.14) Added the confidential computing blob address ============= ============================================================ .. note:: @@ -226,6 +228,7 @@ Offset/Size Proto Name Meaning 0260/4 2.10+ init_size Linear memory required during initialization 0264/4 2.11+ handover_offset Offset of handover entry point 0268/4 2.15+ kernel_info_offset Offset of the kernel_info +026C/4 2.16+ cc_blob_address Physical address of the confidential computing blob =========== ======== ===================== ============================================ .. note:: @@ -1026,6 +1029,30 @@ Offset/size: 0x000c/4 This field contains maximal allowed type for setup_data and setup_indirect structs. +============ ================== +Field name: cc_blob_address +Type: write (optional) +Offset/size: 0x26C/4 +Protocol: 2.16+ +============ ================== + + This field can be set by the boot loader to tell the kernel the physical address + of the confidential computing blob info. + + A value of 0 indicates that either the blob is not provided or use the EFI configuration + table to retrieve the blob location. + + In the case of AMD SEV the blob look like this:: + + struct cc_blob_sev_info { + u32 magic; /* 0x45444d41 (AMDE) */ + u16 version; + u16 reserved; + u64 secrets_phys; /* pointer to secrets page */ + u32 secrets_len; + u64 cpuid_phys; /* pointer to cpuid page */ + u32 cpuid_len; + } The Image Checksum ================== diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S index 6dbd7e9f74c9..b4a014a18f91 100644 --- a/arch/x86/boot/header.S +++ b/arch/x86/boot/header.S @@ -303,7 +303,7 @@ _start: # Part 2 of the header, from the old setup.S .ascii "HdrS" # header signature - .word 0x020f # header version number (>= 0x0105) + .word 0x0210 # header version number (>= 0x0105) # or else old loadlin-1.5 will fail) .globl realmode_swtch realmode_swtch: .word 0, 0 # default_switch, SETUPSEG @@ -577,6 +577,11 @@ pref_address: .quad LOAD_PHYSICAL_ADDR # preferred load addr init_size: .long INIT_SIZE # kernel initialization size handover_offset: .long 0 # Filled in by build.c kernel_info_offset: .long 0 # Filled in by build.c +cc_blob_address: .long 0 # (Header version 0x210 or later) + # If nonzero, a 32-bit pointer to + # the confidential computing blob. + # The blob will contain the information + # used while booting the encrypted VM. # End of setup header ##################################################### diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h index b25d3f82c2f3..210e1a0fb4ce 100644 --- a/arch/x86/include/uapi/asm/bootparam.h +++ b/arch/x86/include/uapi/asm/bootparam.h @@ -102,6 +102,7 @@ struct setup_header { __u32 init_size; __u32 handover_offset; __u32 kernel_info_offset; + __u32 cc_blob_address; } __attribute__((packed)); struct sys_desc_table { From patchwork Wed Jun 2 14:04:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 452793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05510C4708F for ; Wed, 2 Jun 2021 14:06:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DEE7660FE3 for ; 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kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4592.namprd12.prod.outlook.com (2603:10b6:806:9b::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4195.22; Wed, 2 Jun 2021 14:05:23 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4173.030; Wed, 2 Jun 2021 14:05:23 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 21/22] x86/sev: Register SNP guest request platform device Date: Wed, 2 Jun 2021 09:04:15 -0500 Message-Id: <20210602140416.23573-22-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; 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The hypervisor uses the SNP_GUEST_REQUEST command interface provided by the SEV-SNP firmware to forward the guest messages to the PSP. In order to communicate with the PSP, the guest need to locate the secrets page inserted by the hypervisor during the SEV-SNP guest launch. The secrets page contains the communication keys used to send and receive the encrypted messages between the guest and the PSP. The secrets page is located either through the setup_data cc_blob_address or EFI configuration table. Create a platform device that the SNP guest driver can bind to get the platform resources. The SNP guest driver can provide userspace interface to get the attestation report, key derivation etc. The helper snp_issue_guest_request() will be used by the drivers to send the guest message request to the hypervisor. The guest message header contains a message count. The message count is used in the IV. The firmware increments the message count by 1, and expects that next message will be using the incremented count. The helper snp_msg_seqno() will be used by driver to get and message sequence counter, and it will be automatically incremented by the snp_issue_guest_request(). The incremented value is be saved in the secrets page so that the kexec'ed kernel knows from where to begin. See SEV-SNP and GHCB spec for more details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 12 +++ arch/x86/include/uapi/asm/svm.h | 2 + arch/x86/kernel/sev.c | 176 ++++++++++++++++++++++++++++++++ arch/x86/platform/efi/efi.c | 2 + include/linux/efi.h | 1 + include/linux/sev-guest.h | 76 ++++++++++++++ 6 files changed, 269 insertions(+) create mode 100644 include/linux/sev-guest.h diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 640108402ae9..da2f757cd9bc 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -59,6 +59,18 @@ extern void vc_no_ghcb(void); extern void vc_boot_ghcb(void); extern bool handle_vc_boot_ghcb(struct pt_regs *regs); +/* AMD SEV Confidential computing blob structure */ +#define CC_BLOB_SEV_HDR_MAGIC 0x45444d41 +struct cc_blob_sev_info { + u32 magic; + u16 version; + u16 reserved; + u64 secrets_phys; + u32 secrets_len; + u64 cpuid_phys; + u32 cpuid_len; +}; + /* Software defined (when rFlags.CF = 1) */ #define PVALIDATE_FAIL_NOUPDATE 255 diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index c0152186a008..bd64f2b98ac7 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -109,6 +109,7 @@ #define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0 #define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1 #define SVM_VMGEXIT_PSC 0x80000010 +#define SVM_VMGEXIT_GUEST_REQUEST 0x80000011 #define SVM_VMGEXIT_AP_CREATION 0x80000013 #define SVM_VMGEXIT_AP_CREATE_ON_INIT 0 #define SVM_VMGEXIT_AP_CREATE 1 @@ -222,6 +223,7 @@ { SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \ { SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \ { SVM_VMGEXIT_AP_CREATION, "vmgexit_ap_creation" }, \ + { SVM_VMGEXIT_GUEST_REQUEST, "vmgexit_guest_request" }, \ { SVM_EXIT_ERR, "invalid_guest_state" } diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 8f7ef35a25ef..8aae1166f52e 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) "SEV-ES: " fmt +#include #include /* For show_regs() */ #include #include @@ -16,10 +17,13 @@ #include #include #include +#include #include #include +#include #include #include +#include #include #include @@ -33,6 +37,7 @@ #include #include #include +#include /* For struct boot_params */ #include "sev-internal.h" @@ -47,6 +52,8 @@ static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE); */ static struct ghcb __initdata *boot_ghcb; +static unsigned long snp_secrets_phys; + /* #VC handler runtime per-CPU data */ struct sev_es_runtime_data { struct ghcb ghcb_page; @@ -105,6 +112,10 @@ struct ghcb_state { struct ghcb *ghcb; }; +#ifdef CONFIG_EFI +extern unsigned long cc_blob_phys; +#endif + static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data); DEFINE_STATIC_KEY_FALSE(sev_es_enable_key); @@ -1909,3 +1920,168 @@ bool __init handle_vc_boot_ghcb(struct pt_regs *regs) while (true) halt(); } + +static struct resource guest_req_res[0]; +static struct platform_device guest_req_device = { + .name = "snp-guest", + .id = -1, + .resource = guest_req_res, + .num_resources = 1, +}; + +static struct snp_secrets_page_layout *snp_map_secrets_page(void) +{ + u16 __iomem *secrets; + + if (!snp_secrets_phys || !sev_feature_enabled(SEV_SNP)) + return NULL; + + secrets = ioremap_encrypted(snp_secrets_phys, PAGE_SIZE); + if (!secrets) + return NULL; + + return (struct snp_secrets_page_layout *)secrets; +} + +u64 snp_msg_seqno(void) +{ + struct snp_secrets_page_layout *layout; + u64 count; + + layout = snp_map_secrets_page(); + if (layout == NULL) + return 0; + + /* Read the current message sequence counter from secrets pages */ + count = readl(&layout->os_area.msg_seqno_0); + + iounmap(layout); + + /* + * The message sequence counter for the SNP guest request is a 64-bit value + * but the version 2 of GHCB specification defines the 32-bit storage for the + * it. + */ + if ((count + 1) >= INT_MAX) + return 0; + + return count + 1; +} +EXPORT_SYMBOL_GPL(snp_msg_seqno); + +static void snp_gen_msg_seqno(void) +{ + struct snp_secrets_page_layout *layout; + u64 count; + + layout = snp_map_secrets_page(); + if (layout == NULL) + return; + + /* Increment the sequence counter by 2 and save in secrets page. */ + count = readl(&layout->os_area.msg_seqno_0); + count += 2; + + writel(count, &layout->os_area.msg_seqno_0); + iounmap(layout); +} + +static int get_snp_secrets_resource(struct resource *res) +{ + struct setup_header *hdr = &boot_params.hdr; + struct cc_blob_sev_info *info; + unsigned long paddr; + int ret = -ENODEV; + + /* + * The secret page contains the VM encryption key used for encrypting the + * messages between the guest and the PSP. The secrets page location is + * available either through the setup_data or EFI configuration table. + */ + if (hdr->cc_blob_address) { + paddr = hdr->cc_blob_address; + } else if (efi_enabled(EFI_CONFIG_TABLES)) { +#ifdef CONFIG_EFI + paddr = cc_blob_phys; +#else + return -ENODEV; +#endif + } else { + return -ENODEV; + } + + info = memremap(paddr, sizeof(*info), MEMREMAP_WB); + if (!info) + return -ENOMEM; + + /* Verify the header that its a valid SEV_SNP CC header */ + if ((info->magic == CC_BLOB_SEV_HDR_MAGIC) && + info->secrets_phys && + (info->secrets_len == PAGE_SIZE)) { + res->start = info->secrets_phys; + res->end = info->secrets_phys + info->secrets_len; + res->flags = IORESOURCE_MEM; + snp_secrets_phys = info->secrets_phys; + ret = 0; + } + + memunmap(info); + return ret; +} + +static int __init add_snp_guest_request(void) +{ + if (!sev_feature_enabled(SEV_SNP)) + return -ENODEV; + + if (get_snp_secrets_resource(&guest_req_res[0])) + return -ENODEV; + + platform_device_register(&guest_req_device); + dev_info(&guest_req_device.dev, "registered [secret 0x%llx - 0x%llx]\n", + guest_req_res[0].start, guest_req_res[0].end); + + return 0; +} +device_initcall(add_snp_guest_request); + +unsigned long snp_issue_guest_request(int type, struct snp_guest_request_data *input) +{ + struct ghcb_state state; + struct ghcb *ghcb; + unsigned long id; + int ret; + + if (!sev_feature_enabled(SEV_SNP)) + return -ENODEV; + + if (type == GUEST_REQUEST) + id = SVM_VMGEXIT_GUEST_REQUEST; + else + return -EINVAL; + + ghcb = sev_es_get_ghcb(&state); + if (!ghcb) + return -ENODEV; + + vc_ghcb_invalidate(ghcb); + ghcb_set_rax(ghcb, input->data_gpa); + ghcb_set_rbx(ghcb, input->data_npages); + + ret = sev_es_ghcb_hv_call(ghcb, NULL, id, input->req_gpa, input->resp_gpa); + if (ret) + goto e_put; + + if (ghcb->save.sw_exit_info_2) { + ret = ghcb->save.sw_exit_info_2; + goto e_put; + } + + /* Command was successful, increment the message sequence counter. */ + snp_gen_msg_seqno(); + +e_put: + sev_es_put_ghcb(&state); + return ret; +} +EXPORT_SYMBOL_GPL(snp_issue_guest_request); diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c index 8a26e705cb06..2cca9ee6e1d4 100644 --- a/arch/x86/platform/efi/efi.c +++ b/arch/x86/platform/efi/efi.c @@ -57,6 +57,7 @@ static unsigned long efi_systab_phys __initdata; static unsigned long prop_phys = EFI_INVALID_TABLE_ADDR; static unsigned long uga_phys = EFI_INVALID_TABLE_ADDR; static unsigned long efi_runtime, efi_nr_tables; +unsigned long cc_blob_phys; unsigned long efi_fw_vendor, efi_config_table; @@ -66,6 +67,7 @@ static const efi_config_table_type_t arch_tables[] __initconst = { #ifdef CONFIG_X86_UV {UV_SYSTEM_TABLE_GUID, &uv_systab_phys, "UVsystab" }, #endif + {EFI_CC_BLOB_GUID, &cc_blob_phys, "CC blob" }, {}, }; diff --git a/include/linux/efi.h b/include/linux/efi.h index 6b5d36babfcc..75aeb2a56888 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -344,6 +344,7 @@ void efi_native_runtime_setup(void); #define EFI_CERT_SHA256_GUID EFI_GUID(0xc1c41626, 0x504c, 0x4092, 0xac, 0xa9, 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28) #define EFI_CERT_X509_GUID EFI_GUID(0xa5c059a1, 0x94e4, 0x4aa7, 0x87, 0xb5, 0xab, 0x15, 0x5c, 0x2b, 0xf0, 0x72) #define EFI_CERT_X509_SHA256_GUID EFI_GUID(0x3bd2a492, 0x96c0, 0x4079, 0xb4, 0x20, 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed) +#define EFI_CC_BLOB_GUID EFI_GUID(0x067b1f5f, 0xcf26, 0x44c5, 0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42) /* * This GUID is used to pass to the kernel proper the struct screen_info diff --git a/include/linux/sev-guest.h b/include/linux/sev-guest.h new file mode 100644 index 000000000000..51277448a108 --- /dev/null +++ b/include/linux/sev-guest.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD Secure Encrypted Virtualization (SEV) guest driver interface + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + * + */ + +#ifndef __LINUX_SEV_GUEST_H_ +#define __LINUX_SEV_GUEST_H_ + +#include + +enum vmgexit_type { + GUEST_REQUEST, + + GUEST_REQUEST_MAX +}; + +/* + * The secrets page contains 96-bytes of reserved field that can be used by + * the guest OS. The guest OS uses the area to save the message sequence + * number for each VMPL level. + * + * See the GHCB spec section Secret page layout for the format for this area. + */ +struct secrets_os_area { + u32 msg_seqno_0; + u32 msg_seqno_1; + u32 msg_seqno_2; + u32 msg_seqno_3; + u64 ap_jump_table_pa; + u8 rsvd[40]; + u8 guest_usage[32]; +} __packed; + +#define VMPCK_KEY_LEN 32 + +/* See the SNP spec secrets page layout section for the structure */ +struct snp_secrets_page_layout { + u32 version; + u32 imiEn : 1, + rsvd1 : 31; + u32 fms; + u32 rsvd2; + u8 gosvw[16]; + u8 vmpck0[VMPCK_KEY_LEN]; + u8 vmpck1[VMPCK_KEY_LEN]; + u8 vmpck2[VMPCK_KEY_LEN]; + u8 vmpck3[VMPCK_KEY_LEN]; + struct secrets_os_area os_area; + u8 rsvd3[3840]; +} __packed; + +struct snp_guest_request_data { + unsigned long req_gpa; + unsigned long resp_gpa; + unsigned long data_gpa; + unsigned int data_npages; +}; + +#ifdef CONFIG_AMD_MEM_ENCRYPT +unsigned long snp_issue_guest_request(int vmgexit_type, struct snp_guest_request_data *input); +u64 snp_msg_seqno(void); +#else + +static inline unsigned long snp_issue_guest_request(int type, + struct snp_guest_request_data *input) +{ + return -ENODEV; +} +static inline u64 snp_msg_seqno(void) { return 0; } +#endif /* CONFIG_AMD_MEM_ENCRYPT */ +#endif /* __LINUX_SEV_GUEST_H__ */ From patchwork Wed Jun 2 14:04:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 453579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56EF9C4708F for ; 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Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com, Brijesh Singh Subject: [PATCH Part1 RFC v3 22/22] virt: Add SEV-SNP guest driver Date: Wed, 2 Jun 2021 09:04:16 -0500 Message-Id: <20210602140416.23573-23-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602140416.23573-1-brijesh.singh@amd.com> References: <20210602140416.23573-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN6PR05CA0010.namprd05.prod.outlook.com (2603:10b6:805:de::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.9 via Frontend Transport; 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The driver uses snp_issue_guest_request() to issue GHCB SNP_GUEST_REQUEST NAE event. This command constructs a trusted channel between the guest and the PSP firmware. The userspace can use the following ioctls provided by the driver: 1. Request an attestation report that can be used to assume the identity and security configuration of the guest. 2. Ask the firmware to provide a key derived from a root key. See SEV-SNP spec section Guest Messages for more details. Signed-off-by: Brijesh Singh --- drivers/virt/Kconfig | 3 + drivers/virt/Makefile | 1 + drivers/virt/sevguest/Kconfig | 10 + drivers/virt/sevguest/Makefile | 4 + drivers/virt/sevguest/snp.c | 448 +++++++++++++++++++++++++++++++++ drivers/virt/sevguest/snp.h | 63 +++++ include/uapi/linux/sev-guest.h | 56 +++++ 7 files changed, 585 insertions(+) create mode 100644 drivers/virt/sevguest/Kconfig create mode 100644 drivers/virt/sevguest/Makefile create mode 100644 drivers/virt/sevguest/snp.c create mode 100644 drivers/virt/sevguest/snp.h create mode 100644 include/uapi/linux/sev-guest.h diff --git a/drivers/virt/Kconfig b/drivers/virt/Kconfig index 8061e8ef449f..4de714c5ee9a 100644 --- a/drivers/virt/Kconfig +++ b/drivers/virt/Kconfig @@ -36,4 +36,7 @@ source "drivers/virt/vboxguest/Kconfig" source "drivers/virt/nitro_enclaves/Kconfig" source "drivers/virt/acrn/Kconfig" + +source "drivers/virt/sevguest/Kconfig" + endif diff --git a/drivers/virt/Makefile b/drivers/virt/Makefile index 3e272ea60cd9..b2d1a8131c90 100644 --- a/drivers/virt/Makefile +++ b/drivers/virt/Makefile @@ -8,3 +8,4 @@ obj-y += vboxguest/ obj-$(CONFIG_NITRO_ENCLAVES) += nitro_enclaves/ obj-$(CONFIG_ACRN_HSM) += acrn/ +obj-$(CONFIG_SEV_GUEST) += sevguest/ diff --git a/drivers/virt/sevguest/Kconfig b/drivers/virt/sevguest/Kconfig new file mode 100644 index 000000000000..e88a85527bf6 --- /dev/null +++ b/drivers/virt/sevguest/Kconfig @@ -0,0 +1,10 @@ +config SEV_GUEST + tristate "AMD SEV Guest driver" + default y + depends on AMD_MEM_ENCRYPT + help + Provides AMD SNP guest request driver. The driver can be used by the + guest to communicate with the hypervisor to request the attestation report + and more. + + If you choose 'M' here, this module will be called sevguest. diff --git a/drivers/virt/sevguest/Makefile b/drivers/virt/sevguest/Makefile new file mode 100644 index 000000000000..1505df437682 --- /dev/null +++ b/drivers/virt/sevguest/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +sevguest-y := snp.o + +obj-$(CONFIG_SEV_GUEST) += sevguest.o diff --git a/drivers/virt/sevguest/snp.c b/drivers/virt/sevguest/snp.c new file mode 100644 index 000000000000..00d8e8fddf2c --- /dev/null +++ b/drivers/virt/sevguest/snp.c @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AMD Secure Encrypted Virtualization Nested Paging (SEV-SNP) guest request interface + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "snp.h" + +#define DEVICE_NAME "sev-guest" +#define AAD_LEN 48 +#define MSG_HDR_VER 1 + +struct snp_guest_crypto { + struct crypto_aead *tfm; + uint8_t *iv, *authtag; + int iv_len, a_len; +}; + +struct snp_guest_dev { + struct device *dev; + struct miscdevice misc; + + struct snp_guest_crypto *crypto; + struct snp_guest_msg *request, *response; +}; + +static DEFINE_MUTEX(snp_cmd_mutex); + +static inline struct snp_guest_dev *to_snp_dev(struct file *file) +{ + struct miscdevice *dev = file->private_data; + + return container_of(dev, struct snp_guest_dev, misc); +} + +static struct snp_guest_crypto *init_crypto(struct snp_guest_dev *snp_dev, uint8_t *key, + size_t keylen) +{ + struct snp_guest_crypto *crypto; + + crypto = kzalloc(sizeof(*crypto), GFP_KERNEL_ACCOUNT); + if (!crypto) + return NULL; + + crypto->tfm = crypto_alloc_aead("gcm(aes)", 0, 0); + if (IS_ERR(crypto->tfm)) + goto e_free; + + if (crypto_aead_setkey(crypto->tfm, key, keylen)) + goto e_free_crypto; + + crypto->iv_len = crypto_aead_ivsize(crypto->tfm); + if (crypto->iv_len < 12) { + dev_err(snp_dev->dev, "IV length is less than 12.\n"); + goto e_free_crypto; + } + + crypto->iv = kmalloc(crypto->iv_len, GFP_KERNEL_ACCOUNT); + if (!crypto->iv) + goto e_free_crypto; + + if (crypto_aead_authsize(crypto->tfm) > MAX_AUTHTAG_LEN) { + if (crypto_aead_setauthsize(crypto->tfm, MAX_AUTHTAG_LEN)) { + dev_err(snp_dev->dev, "failed to set authsize to %d\n", MAX_AUTHTAG_LEN); + goto e_free_crypto; + } + } + + crypto->a_len = crypto_aead_authsize(crypto->tfm); + crypto->authtag = kmalloc(crypto->a_len, GFP_KERNEL_ACCOUNT); + if (!crypto->authtag) + goto e_free_crypto; + + return crypto; + +e_free_crypto: + crypto_free_aead(crypto->tfm); +e_free: + kfree(crypto->iv); + kfree(crypto->authtag); + kfree(crypto); + + return NULL; +} + +static void deinit_crypto(struct snp_guest_crypto *crypto) +{ + crypto_free_aead(crypto->tfm); + kfree(crypto->iv); + kfree(crypto->authtag); + kfree(crypto); +} + +static int enc_dec_message(struct snp_guest_crypto *crypto, struct snp_guest_msg *msg, + uint8_t *src_buf, uint8_t *dst_buf, size_t len, bool enc) +{ + struct snp_guest_msg_hdr *hdr = &msg->hdr; + struct scatterlist src[3], dst[3]; + DECLARE_CRYPTO_WAIT(wait); + struct aead_request *req; + int ret; + + req = aead_request_alloc(crypto->tfm, GFP_KERNEL); + if (!req) + return -ENOMEM; + + /* + * AEAD memory operations: + * +------ AAD -------+------- DATA -----+---- AUTHTAG----+ + * | msg header | plaintext | hdr->authtag | + * | bytes 30h - 5Fh | or | | + * | | cipher | | + * +------------------+------------------+----------------+ + */ + sg_init_table(src, 3); + sg_set_buf(&src[0], &hdr->algo, AAD_LEN); + sg_set_buf(&src[1], src_buf, hdr->msg_sz); + sg_set_buf(&src[2], hdr->authtag, crypto->a_len); + + sg_init_table(dst, 3); + sg_set_buf(&dst[0], &hdr->algo, AAD_LEN); + sg_set_buf(&dst[1], dst_buf, hdr->msg_sz); + sg_set_buf(&dst[2], hdr->authtag, crypto->a_len); + + aead_request_set_ad(req, AAD_LEN); + aead_request_set_tfm(req, crypto->tfm); + aead_request_set_callback(req, 0, crypto_req_done, &wait); + + aead_request_set_crypt(req, src, dst, len, crypto->iv); + ret = crypto_wait_req(enc ? crypto_aead_encrypt(req) : crypto_aead_decrypt(req), &wait); + + aead_request_free(req); + return ret; +} + +static int encrypt_payload(struct snp_guest_dev *snp_dev, struct snp_guest_msg *msg, + void *plaintext, size_t len) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_guest_msg_hdr *hdr = &msg->hdr; + + memset(crypto->iv, 0, crypto->iv_len); + memcpy(crypto->iv, &hdr->msg_seqno, sizeof(hdr->msg_seqno)); + + return enc_dec_message(crypto, msg, plaintext, msg->payload, len, true); +} + +static int decrypt_payload(struct snp_guest_dev *snp_dev, struct snp_guest_msg *msg, + void *plaintext, size_t len) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_guest_msg_hdr *hdr = &msg->hdr; + + /* Build IV with response buffer sequence number */ + memset(crypto->iv, 0, crypto->iv_len); + memcpy(crypto->iv, &hdr->msg_seqno, sizeof(hdr->msg_seqno)); + + return enc_dec_message(crypto, msg, msg->payload, plaintext, len, false); +} + +static int __handle_guest_request(struct snp_guest_dev *snp_dev, int msg_type, + struct snp_user_guest_request *input, uint8_t *req_buf, + size_t req_sz, uint8_t *resp_buf, size_t resp_sz, size_t *msg_sz) +{ + struct snp_guest_msg *response = snp_dev->response; + struct snp_guest_msg_hdr *resp_hdr = &response->hdr; + struct snp_guest_msg *request = snp_dev->request; + struct snp_guest_msg_hdr *req_hdr = &request->hdr; + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct snp_guest_request_data data; + int ret; + + memset(request, 0, sizeof(*request)); + + /* Populate the request header */ + req_hdr->algo = SNP_AEAD_AES_256_GCM; + req_hdr->hdr_version = MSG_HDR_VER; + req_hdr->hdr_sz = sizeof(*req_hdr); + req_hdr->msg_type = msg_type; + req_hdr->msg_version = input->msg_version; + req_hdr->msg_seqno = snp_msg_seqno(); + req_hdr->msg_vmpck = 0; + req_hdr->msg_sz = req_sz; + + dev_dbg(snp_dev->dev, "request [seqno %lld type %d version %d sz %d]\n", + req_hdr->msg_seqno, req_hdr->msg_type, req_hdr->msg_version, req_hdr->msg_sz); + + /* Encrypt the request message buffer */ + ret = encrypt_payload(snp_dev, request, req_buf, req_sz); + if (ret) + return ret; + + /* Call firmware to process the request */ + data.req_gpa = __pa(request); + data.resp_gpa = __pa(response); + ret = snp_issue_guest_request(GUEST_REQUEST, &data); + input->fw_err = ret; + if (ret) + return ret; + + dev_dbg(snp_dev->dev, "response [msg_seqno %lld msg_type %d msg_version %d msg_sz %d]\n", + resp_hdr->msg_seqno, resp_hdr->msg_type, resp_hdr->msg_version, resp_hdr->msg_sz); + + /* Verify that the sequence counter is incremented by 1 */ + if (unlikely(resp_hdr->msg_seqno != (req_hdr->msg_seqno + 1))) + return -EBADMSG; + + /* Verify response message type and version */ + if ((resp_hdr->msg_type != (req_hdr->msg_type + 1)) || + (resp_hdr->msg_version != req_hdr->msg_version)) + return -EBADMSG; + + /* + * If the message size is greather than our buffer length then return + * an error. + */ + if (unlikely((resp_hdr->msg_sz + crypto->a_len) > resp_sz)) + return -EBADMSG; + + /* Decrypt the payload */ + ret = decrypt_payload(snp_dev, response, resp_buf, resp_hdr->msg_sz + crypto->a_len); + if (ret) + return ret; + + *msg_sz = resp_hdr->msg_sz; + return 0; +} + +static int handle_guest_request(struct snp_guest_dev *snp_dev, int msg_type, + struct snp_user_guest_request *input, void *req_buf, + size_t req_len, void __user *resp_buf, size_t resp_len) +{ + struct snp_guest_crypto *crypto = snp_dev->crypto; + struct page *page; + size_t msg_len; + int ret; + + /* Allocate the buffer to hold response */ + resp_len += crypto->a_len; + page = alloc_pages(GFP_KERNEL_ACCOUNT, get_order(resp_len)); + if (!page) + return -ENOMEM; + + ret = __handle_guest_request(snp_dev, msg_type, input, req_buf, req_len, + page_address(page), resp_len, &msg_len); + if (ret) + goto e_free; + + if (copy_to_user(resp_buf, page_address(page), msg_len)) + ret = -EFAULT; + +e_free: + __free_pages(page, get_order(resp_len)); + + return ret; +} + +static int get_report(struct snp_guest_dev *snp_dev, struct snp_user_guest_request *input) +{ + struct snp_user_report __user *report = (struct snp_user_report *)input->data; + struct snp_user_report_req req; + + if (copy_from_user(&req, &report->req, sizeof(req))) + return -EFAULT; + + return handle_guest_request(snp_dev, SNP_MSG_REPORT_REQ, input, &req.user_data, + sizeof(req.user_data), report->response, sizeof(report->response)); +} + +static int derive_key(struct snp_guest_dev *snp_dev, struct snp_user_guest_request *input) +{ + struct snp_user_derive_key __user *key = (struct snp_user_derive_key *)input->data; + struct snp_user_derive_key_req req; + + if (copy_from_user(&req, &key->req, sizeof(req))) + return -EFAULT; + + return handle_guest_request(snp_dev, SNP_MSG_KEY_REQ, input, &req, sizeof(req), + key->response, sizeof(key->response)); +} + +static long snp_guest_ioctl(struct file *file, unsigned int ioctl, unsigned long arg) +{ + struct snp_guest_dev *snp_dev = to_snp_dev(file); + struct snp_user_guest_request input; + void __user *argp = (void __user *)arg; + int ret = -ENOTTY; + + if (copy_from_user(&input, argp, sizeof(input))) + return -EFAULT; + + mutex_lock(&snp_cmd_mutex); + switch (ioctl) { + case SNP_GET_REPORT: { + ret = get_report(snp_dev, &input); + break; + } + case SNP_DERIVE_KEY: { + ret = derive_key(snp_dev, &input); + break; + } + default: + break; + } + + mutex_unlock(&snp_cmd_mutex); + + if (copy_to_user(argp, &input, sizeof(input))) + return -EFAULT; + + return ret; +} + +static void free_shared_pages(void *buf, size_t sz) +{ + unsigned int npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + + /* If fail to restore the encryption mask then leak it. */ + if (set_memory_encrypted((unsigned long)buf, npages)) + return; + + __free_pages(virt_to_page(buf), get_order(sz)); +} + +static void *alloc_shared_pages(size_t sz) +{ + unsigned int npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; + struct page *page; + int ret; + + page = alloc_pages(GFP_KERNEL_ACCOUNT, get_order(sz)); + if (IS_ERR(page)) + return NULL; + + ret = set_memory_decrypted((unsigned long)page_address(page), npages); + if (ret) { + __free_pages(page, get_order(sz)); + return NULL; + } + + return page_address(page); +} + +static const struct file_operations snp_guest_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = snp_guest_ioctl, +}; + +static int __init snp_guest_probe(struct platform_device *pdev) +{ + struct snp_secrets_page_layout *secrets; + struct device *dev = &pdev->dev; + struct snp_guest_dev *snp_dev; + uint8_t key[VMPCK_KEY_LEN]; + struct miscdevice *misc; + struct resource *res; + void __iomem *base; + int ret; + + snp_dev = devm_kzalloc(&pdev->dev, sizeof(struct snp_guest_dev), GFP_KERNEL); + if (!snp_dev) + return -ENOMEM; + + platform_set_drvdata(pdev, snp_dev); + snp_dev->dev = dev; + + res = platform_get_mem_or_io(pdev, 0); + if (IS_ERR(res)) + return PTR_ERR(res); + + /* Map the secrets page to get the key */ + base = ioremap_encrypted(res->start, resource_size(res)); + if (IS_ERR(base)) + return PTR_ERR(base); + + secrets = (struct snp_secrets_page_layout *)base; + memcpy_fromio(key, secrets->vmpck0, sizeof(key)); + iounmap(base); + + snp_dev->crypto = init_crypto(snp_dev, key, sizeof(key)); + if (!snp_dev->crypto) + return -EIO; + + /* Allocate the shared page used for the request and response message. */ + snp_dev->request = alloc_shared_pages(sizeof(struct snp_guest_msg)); + if (IS_ERR(snp_dev->request)) + return PTR_ERR(snp_dev->request); + + snp_dev->response = alloc_shared_pages(sizeof(struct snp_guest_msg)); + if (IS_ERR(snp_dev->response)) { + ret = PTR_ERR(snp_dev->response); + goto e_free_req; + } + + misc = &snp_dev->misc; + misc->minor = MISC_DYNAMIC_MINOR; + misc->name = DEVICE_NAME; + misc->fops = &snp_guest_fops; + + return misc_register(misc); + +e_free_req: + free_shared_pages(snp_dev->request, sizeof(struct snp_guest_msg)); + return ret; +} + +static int __exit snp_guest_remove(struct platform_device *pdev) +{ + struct snp_guest_dev *snp_dev = platform_get_drvdata(pdev); + + free_shared_pages(snp_dev->request, sizeof(struct snp_guest_msg)); + free_shared_pages(snp_dev->response, sizeof(struct snp_guest_msg)); + deinit_crypto(snp_dev->crypto); + misc_deregister(&snp_dev->misc); + + return 0; +} + +static struct platform_driver snp_guest_driver = { + .remove = __exit_p(snp_guest_remove), + .driver = { + .name = "snp-guest", + }, +}; + +module_platform_driver_probe(snp_guest_driver, snp_guest_probe); + +MODULE_AUTHOR("Brijesh Singh "); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0.0"); +MODULE_DESCRIPTION("AMD SNP Guest Driver"); diff --git a/drivers/virt/sevguest/snp.h b/drivers/virt/sevguest/snp.h new file mode 100644 index 000000000000..930ffc0f4be3 --- /dev/null +++ b/drivers/virt/sevguest/snp.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + * + * SEV-SNP API spec is available at https://developer.amd.com/sev + */ + +#ifndef __LINUX_SNP_GUEST_H_ +#define __LINUX_SNP_GUEST_H_ + +#include + +#define MAX_AUTHTAG_LEN 32 + +/* See SNP spec SNP_GUEST_REQUEST section for the structure */ +enum msg_type { + SNP_MSG_TYPE_INVALID = 0, + SNP_MSG_CPUID_REQ, + SNP_MSG_CPUID_RSP, + SNP_MSG_KEY_REQ, + SNP_MSG_KEY_RSP, + SNP_MSG_REPORT_REQ, + SNP_MSG_REPORT_RSP, + SNP_MSG_EXPORT_REQ, + SNP_MSG_EXPORT_RSP, + SNP_MSG_IMPORT_REQ, + SNP_MSG_IMPORT_RSP, + SNP_MSG_ABSORB_REQ, + SNP_MSG_ABSORB_RSP, + SNP_MSG_VMRK_REQ, + SNP_MSG_VMRK_RSP, + + SNP_MSG_TYPE_MAX +}; + +enum aead_algo { + SNP_AEAD_INVALID, + SNP_AEAD_AES_256_GCM, +}; + +struct snp_guest_msg_hdr { + u8 authtag[MAX_AUTHTAG_LEN]; + u64 msg_seqno; + u8 rsvd1[8]; + u8 algo; + u8 hdr_version; + u16 hdr_sz; + u8 msg_type; + u8 msg_version; + u16 msg_sz; + u32 rsvd2; + u8 msg_vmpck; + u8 rsvd3[35]; +} __packed; + +struct snp_guest_msg { + struct snp_guest_msg_hdr hdr; + u8 payload[4000]; +} __packed; + +#endif /* __LINUX_SNP_GUEST_H__ */ diff --git a/include/uapi/linux/sev-guest.h b/include/uapi/linux/sev-guest.h new file mode 100644 index 000000000000..0a8454631605 --- /dev/null +++ b/include/uapi/linux/sev-guest.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Userspace interface for AMD SEV and SEV-SNP guest driver. + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Brijesh Singh + * + * SEV-SNP API specification is available at: https://developer.amd.com/sev/ + */ + +#ifndef __UAPI_LINUX_SEV_GUEST_H_ +#define __UAPI_LINUX_SEV_GUEST_H_ + +#include + +struct snp_user_report_req { + __u8 user_data[64]; +}; + +struct snp_user_report { + struct snp_user_report_req req; + + /* see SEV-SNP spec for the response format */ + __u8 response[4000]; +}; + +struct snp_user_derive_key_req { + __u8 root_key_select; + __u64 guest_field_select; + __u32 vmpl; + __u32 guest_svn; + __u64 tcb_version; +}; + +struct snp_user_derive_key { + struct snp_user_derive_key_req req; + + /* see SEV-SNP spec for the response format */ + __u8 response[64]; +}; + +struct snp_user_guest_request { + /* Message version number (must be non-zero) */ + __u8 msg_version; + __u64 data; + + /* firmware error code on failure (see psp-sev.h) */ + __u32 fw_err; +}; + +#define SNP_GUEST_REQ_IOC_TYPE 'S' +#define SNP_GET_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x0, struct snp_user_guest_request) +#define SNP_DERIVE_KEY _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x1, struct snp_user_guest_request) + +#endif /* __UAPI_LINUX_SEV_GUEST_H_ */