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[213.113.114.119]) by smtp.gmail.com with ESMTPSA id h192sm1571609lfg.56.2017.05.06.05.11.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 May 2017 05:11:08 -0700 (PDT) From: Linus Walleij To: Tejun Heo , Bartlomiej Zolnierkiewicz , linux-ide@vger.kernel.org Cc: Janos Laube , Paulius Zaleckas , openwrt-devel@openwrt.org, linux-arm-kernel@lists.infradead.org, Hans Ulli Kroll , Florian Fainelli , Linus Walleij , devicetree@vger.kernel.org, John Feng-Hsin Chiang , Greentime Hu Subject: [PATCH 1/4] ata: Add DT bindings for Faraday Technology FTIDE010 Date: Sat, 6 May 2017 14:10:50 +0200 Message-Id: <20170506121053.11554-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Faraday Technology FTIDE010 found in the Storlink/Storm/Cortina Systems Gemini SoC. I am not 100% sure that this part if from Faraday Technology but a lot points in that direction: - A later IDE interface called FTIDE020 exist and share some properties. - The SATA bridge has the same Built In Self Test (BIST) that the Faraday FTSATA100 seems to have, and it has version number 0100 in the device ID register, so this is very likely a FTSATA100 bundled with the FTIDE010. Cc: devicetree@vger.kernel.org Cc: John Feng-Hsin Chiang Cc: Greentime Hu Signed-off-by: Linus Walleij --- Greentime: I think this may be interesting to you since the FTIDE020 will need the same bindings so we can probably just reuse them and maybe make the parser a library if you want to upstream the FTIDE020. Faraday people: I do not have it from a source that this hardware is really FTIDE010 but I would be VERY surprised if it is not. U-Boot has an FTIDE020 IDE controller synthesized in the Andestech platform, and it has a similar yet different register layout, featuring similar timing set-ups: http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/block/ftide020.h http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/block/ftide020.c --- .../devicetree/bindings/ata/faraday,ftide010.txt | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/faraday,ftide010.txt -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Hans Ulli Kroll Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/ata/faraday,ftide010.txt b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt new file mode 100644 index 000000000000..5048408c07c5 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/faraday,ftide010.txt @@ -0,0 +1,63 @@ +* Faraday Technology FTIDE010 PATA controller + +This controller is the first Faraday IDE interface block, used in the +StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini +platform. The controller can do PIO modes 0 through 4, Multi-word DMA +(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6. + +On the Gemini platform, this PATA block is accompanied by a PATA to +SATA bridge in order to support SATA. This is why a phandle to that +controller is compulsory on that platform. + +The timing properties are unique per-SoC, not per-board. + +Required properties: +- compatible: should be one of + "cortina,gemini-pata", "faraday,ftide010" + "faraday,ftide010" +- interrupts: interrupt for the block +- reg: registers and size for the block + + The unit of the below required timings is two clock periods of the ATA + reference clock which is 30 nanoseconds per unit at 66MHz and 20 nanoseconds + per unit at 50 MHz. + +- faraday,pio-active-time: array of 5 elements for T2 timing for Mode 0, + 1, 2, 3 and 4. Range 0..15. +- faraday,pio-recovery-time: array of 5 elements for T2l timing for Mode 0, + 1, 2, 3 and 4. Range 0..15. +- faraday,mdma-50-active-time: array of 4 elements for Td timing for multi + word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15. +- faraday,mdma-50-recovery-time: array of 4 elements for Tk timing for + multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15. +- faraday,mdma-66-active-time: array of 4 elements for Td timing for multi + word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15. +- faraday,mdma-66-recovery-time: array of 4 elements for Tk timing for + multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15. +- faraday,udma-50-setup-time: array of 4 elements for Tvds timing for ultra + DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7. +- faraday,udma-50-hold-time: array of 4 elements for Tdvh timing for + multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7. +- faraday,udma-66-setup-time: array of 4 elements for Tvds timing for multi + word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 50 MHz. Range 0..7. +- faraday,udma-66-hold-time: array of 4 elements for Tdvh timing for + multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 50 MHz. Range 0..7. + +Optional properties: +- clocks: a SoC clock running the peripheral. +- clock-names: should be set to "PCLK" for the peripheral clock. + +Required properties for "cortina,gemini-pata" compatible: +- sata: a phande to the Gemini PATA to SATA bridge, see + cortina,gemini-sata-bridge.txt for details. + +Example: + +ata@63000000 { + compatible = "cortina,gemini-pata", "faraday,ftide010"; + reg = <0x63000000 0x100>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GEMINI_CLK_GATE_IDE>; + clock-names = "PCLK"; + sata = <&sata>; +}; From patchwork Sat May 6 12:10:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 98752 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp549545qge; Sat, 6 May 2017 05:11:20 -0700 (PDT) X-Received: by 10.98.80.69 with SMTP id e66mr23090183pfb.250.1494072680124; Sat, 06 May 2017 05:11:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.114.119]) by smtp.gmail.com with ESMTPSA id h192sm1571609lfg.56.2017.05.06.05.11.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 May 2017 05:11:13 -0700 (PDT) From: Linus Walleij To: Tejun Heo , Bartlomiej Zolnierkiewicz , linux-ide@vger.kernel.org Cc: Janos Laube , Paulius Zaleckas , openwrt-devel@openwrt.org, linux-arm-kernel@lists.infradead.org, Hans Ulli Kroll , Florian Fainelli , Linus Walleij , devicetree@vger.kernel.org, John Feng-Hsin Chiang , Greentime Hu Subject: [PATCH 2/4] ata: Add DT bindings for the Gemini SATA bridge Date: Sat, 6 May 2017 14:10:51 +0200 Message-Id: <20170506121053.11554-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170506121053.11554-1-linus.walleij@linaro.org> References: <20170506121053.11554-1-linus.walleij@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Cortina Systems Gemini PATA to SATA bridge. Cc: devicetree@vger.kernel.org Cc: John Feng-Hsin Chiang Cc: Greentime Hu Signed-off-by: Linus Walleij --- .../bindings/ata/cortina,gemini-sata-bridge.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt b/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt new file mode 100644 index 000000000000..9fe92818b2fb --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt @@ -0,0 +1,55 @@ +* Cortina Systems Gemini SATA Bridge + +The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that +takes two Faraday Technology FTIDE010 PATA controllers and bridges +them in different configurations to two SATA ports. + +Required properties: +- compatible: should be + "cortina,gemini-sata-bridge" +- reg: registers and size for the block +- resets: phandles to the reset lines for both SATA bridges +- reset-names: must be "sata0", "sata1" +- clocks: phandles to the compulsory peripheral clocks +- clock-names: must be "SATA0_PCLK", "SATA1_PCLK" +- syscon: a phandle to the global Gemini system controller +- cortina,gemini-ata-muxmode: tell the desired multiplexing mode for + the ATA controller and SATA bridges. Values 0..3: + Mode 0: ata0 master <-> sata0 + ata1 master <-> sata1 + ata0 slave interface brought out on IDE pads + Mode 1: ata0 master <-> sata0 + ata1 master <-> sata1 + ata1 slave interface brought out on IDE pads + Mode 2: ata1 master <-> sata1 + ata1 slave <-> sata0 + ata0 master and slave interfaces brought out + on IDE pads + Mode 3: ata0 master <-> sata0 + ata1 slave <-> sata1 + ata1 master and slave interfaces brought out + on IDE pads + +Optional boolean properties: +- cortina,gemini-enable-ide-pins: enables the PATA to IDE connection. + The muxmode setting decides whether ATA0 or ATA1 is brought out, + and whether master, slave or both interfaces get brought out. +- cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge + inside the Gemnini SoC. The Muxmode decides what PATA blocks will + be muxed out and how. + +Example: + +sata: sata@46000000 { + compatible = "cortina,gemini-sata-bridge"; + reg = <0x46000000 0x100>; + resets = <&rcon 26>, <&rcon 27>; + reset-names = "sata0", "sata1"; + clocks = <&gcc GEMINI_CLK_GATE_SATA0>, + <&gcc GEMINI_CLK_GATE_SATA1>; + clock-names = "SATA0_PCLK", "SATA1_PCLK"; + syscon = <&syscon>; + cortina,gemini-ata-muxmode = <3>; + cortina,gemini-enable-ide-pins; + cortina,gemini-enable-sata-bridge; +};