From patchwork Mon Jul 23 10:08:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 142560 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5862542ljj; Mon, 23 Jul 2018 03:09:26 -0700 (PDT) X-Google-Smtp-Source: AAOMgpez45G4s7rP1RGIKaGp9YtoPBHP1lqKdjk177bo6kmNHISYFgoC32EhjNigq4b6HxVNWeJc X-Received: by 2002:a17:902:201:: with SMTP id 1-v6mr12478684plc.310.1532340566772; Mon, 23 Jul 2018 03:09:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532340566; cv=none; d=google.com; s=arc-20160816; b=H4zsWuLrLnjVcr7giz6mNq/+YkxwzHAUBJG6syyBVETzKvoJr78it/N5fXOuiDAIgQ RKeJDjqp+HwT8sjwpZAh1gAseFtLxi07T7/GRQigIXpdGcJmlp9Ca+ktgvQrTugVl0KU R0+uTHICXjXLW9TogQEJXU+uiClBQ5u2Xk0sDnWZEnKjs+5eKro9ytALM1aCYLBtnJPY StGPdiDdEalAMtFL9uxFiwBphgcnkqFyMsfVE8nREtMiM5nWgz0ptm5VNdD6Z0AQ5aZp q4MdHTyeX7EYkrMrIBSnFAEalm7vtuCmlaEmanTBJslRfYbK1NfZ9jmnruTbOnDoHT/J MNig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=pgMbW6Ss8duf9bBSciMwtG6e41E2GSRno97Zc3Vq3KI=; b=VD8i4ef7q5x6CI7kJIqWqIzOo9R4CAY+3nH9a1EqPwC9SM6fFTeC7niJYsphK6vNx9 irOLPZk8QtxcGTCpPtIx76FgMEf8xMBi0VdzYkmwAonLrZNTEndYvhjMHPTgjv88vUsO weN6iOjs1895YOAdzsCm5pWovYyK8O+aKmcGMnM5qFTwMdwFuTIJOvW8bWi150qtNtR2 C/3trFPIgg9+LE7H1jCVRt/kFLBCdkwz2fha0Yn9PH3zY9EA6NOmIxLIqvlX+dpWEuhp NzOE5d7+34Q27s8j9QQGHCR7zlGF6eR/yhvwbu66ke78+UK10pheDXOXqQJjvfLPC3Mj BHcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gdVHd0xA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g11-v6si8316899pgf.386.2018.07.23.03.09.26; Mon, 23 Jul 2018 03:09:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gdVHd0xA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388390AbeGWLJu (ORCPT + 31 others); Mon, 23 Jul 2018 07:09:50 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:38720 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388375AbeGWLJu (ORCPT ); Mon, 23 Jul 2018 07:09:50 -0400 Received: by mail-pg1-f195.google.com with SMTP id k3-v6so50640pgq.5 for ; Mon, 23 Jul 2018 03:09:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pgMbW6Ss8duf9bBSciMwtG6e41E2GSRno97Zc3Vq3KI=; b=gdVHd0xA5mzJwbrXBorxwgtSz9aheGhVAti5E+RZ42Vr3oO9RWHJ/lumt+iKt4ZtQr Kf3DRvhfwNuwwLRgoqIhNW1W7zju3l193utHO5EU5puYCFTq7jo6GCUwYN9dOLlporyn +QRpRM4OpAqnMUs8FdA+ryImom2ir6Nq4ADrg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pgMbW6Ss8duf9bBSciMwtG6e41E2GSRno97Zc3Vq3KI=; b=V7pp2BUas1HctT2QMueaCjbaXGsD61I+ZLFsm9mi2cR0nmo5NLf1gGH+810LDNKuhO tDFOoSMfOZM3QS2D24UNhd5H1tH8Ww13CudqF2Yp86rLGhDThoOhwjMtYmWSIhfn2big Si2voZpYqiEQzvRfLzrhKS+mbtzLljR6boU3Ay5v2N0/MRJleSk9fgAIIpykotVdo+yW mQqw6Ef/X/diHzJTQDEZ6RfT0L6fkcc0Vv9Uel5UA2qEVRJQDxH+awTvXCAiDDUqQo7o zApQqmWZPLQGRBjCRZCg6Sere7eF96gl2cJWTbmiCA4BvJB+FvvzuKQjb64pXimaNFoh 0dPw== X-Gm-Message-State: AOUpUlGWLrAiWML9wkqqgcYpRh5vidd2ab7TpB5Ym9kswfNA/DxVZsWr sxi+9EV9wHCPTUCOKw7DRSceJTxCmpePWg== X-Received: by 2002:a63:b213:: with SMTP id x19-v6mr11517985pge.393.1532340562867; Mon, 23 Jul 2018 03:09:22 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm13470698pfk.87.2018.07.23.03.09.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 03:09:21 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , zhang.lyra@gmail.com Subject: [PATCH V4 3/7] mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode Date: Mon, 23 Jul 2018 18:08:24 +0800 Message-Id: <1532340508-8749-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> References: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 90 ++++++++++++++++++++++++++++++++++-------------- drivers/mmc/host/sdhci.h | 15 ++++++-- 2 files changed, 78 insertions(+), 27 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9cb17c0..ce71afa 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -271,6 +271,46 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } +static void sdhci_config_dma(struct sdhci_host *host) +{ + u8 ctrl; + u16 ctrl2; + + if (host->version < SDHCI_SPEC_200) + return; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + + /* + * Always adjust the DMA selection as some controllers + * (e.g. JMicron) can't do PIO properly when the selection + * is ADMA. + */ + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if ((host->flags & SDHCI_REQ_USE_DMA) && + (host->flags & SDHCI_USE_ADMA)) + ctrl |= SDHCI_CTRL_ADMA32; + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + /* + * If v4 mode, all supported DMA can be 64-bit addressing if + * controller supports 64-bit system address, otherwise only + * ADMA can support 64-bit addressing. + */ + if (host->v4_mode) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } else { + if ((host->flags & SDHCI_REQ_USE_DMA) && + (host->flags & SDHCI_USE_ADMA)) + ctrl |= SDHCI_CTRL_ADMA64; + } + } + + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; @@ -916,7 +956,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { - u8 ctrl; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1012,25 +1051,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } } - /* - * Always adjust the DMA selection as some controllers - * (e.g. JMicron) can't do PIO properly when the selection - * is ADMA. - */ - if (host->version >= SDHCI_SPEC_200) { - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); - ctrl &= ~SDHCI_CTRL_DMA_MASK; - if ((host->flags & SDHCI_REQ_USE_DMA) && - (host->flags & SDHCI_USE_ADMA)) { - if (host->flags & SDHCI_USE_64_BIT_DMA) - ctrl |= SDHCI_CTRL_ADMA64; - else - ctrl |= SDHCI_CTRL_ADMA32; - } else { - ctrl |= SDHCI_CTRL_SDMA; - } - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - } + sdhci_config_dma(host); if (!(host->flags & SDHCI_REQ_USE_DMA)) { int flags; @@ -3503,6 +3524,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) +{ + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) + return host->caps & SDHCI_CAN_64BIT_V4; + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3539,7 +3573,7 @@ int sdhci_setup_host(struct sdhci_host *host) override_timeout_clk = host->timeout_clk; - if (host->version > SDHCI_SPEC_300) { + if (host->version > SDHCI_SPEC_420) { pr_err("%s: Unknown controller version (%d). You may experience problems.\n", mmc_hostname(mmc), host->version); } @@ -3574,7 +3608,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_can_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3608,8 +3642,8 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; @@ -3617,7 +3651,13 @@ int sdhci_setup_host(struct sdhci_host *host) } host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; - buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + /* + * Host Controller Version 4.00 or later can support 128-bit + * and 96-bit Descriptor for 64-bit addressing mode. 128-bit + * Descriptor is for v4 mode, and high 32-bit of it is reserved + * according to the specification v4.10. + */ + buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 519d939..23318ff 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -205,6 +206,7 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_SUPPORT_SDR50 0x00000001 @@ -271,6 +273,9 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 +#define SDHCI_SPEC_420 5 /* * End of controller registers. @@ -306,8 +311,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Mon Jul 23 10:08:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 142561 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5862606ljj; Mon, 23 Jul 2018 03:09:31 -0700 (PDT) X-Google-Smtp-Source: AAOMgpedc2u+w9lhMwOflC1O1e/XI5hFfRneun6qCuD8zxDPrPaXp+waYeWRoC1NIb0kAME4M1cI X-Received: by 2002:a62:d842:: with SMTP id e63-v6mr12761246pfg.88.1532340571152; Mon, 23 Jul 2018 03:09:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532340571; cv=none; d=google.com; s=arc-20160816; b=0vkdH4eTp/g0lcjZFfhuvEQ0N+gOODEx7NaEfDU5Ck1PiIWoT8nMvHW4bGMpxRP5Nc iG15Ancz3sX4/2LrH+h66iUNlvm7Ahtu28g8JoWfSoWxnif7L07pZiGv3m2efGCLOS6d yI3aPV34+CaueT/abjwbY2WJ8RtAwiLYrZB9O5K/F0v7TWs0jk6GeAIk3U/DBJ5NSxZE QoUHb1CdEA5yoYJnJcTBlShLDbtXmYo8VTtJ437p43VJ6q9IKNNWRupWkUnsL68TVHxa lXAUzwHh7N3YTPFJAOxe9x5XvJQzrV7FtPgBRz5E4TFXz1MVFCwFl4nvRU6u0bTCFjQg 0jhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Vwl51bqmcDS8wp+lU1pZalSc7Z3bokmXBYlYRayzf+k=; b=RX1277DRMzWA2o61185qA9AV5cQw4XRctBU7jYMB8uXJNgtzC/jkRjt3J+BYAbdkBc XwHkT48y4Ki6SYBC5aHKixjtcKH+rzskfIKDsxho5KokXjDJNEMxxyJdeWmNi6jWea0i Npb+gGOX9geTq1pvDTqyCgQJZbSC9du9n3utgtkTuBCACaPaoJ5sZvBrtw+upUAffRQO Ll/3MCYb9aMcru3OBcb26R/EW8LuOiS8Of5Jq0TkKUIEsCqtLkQbeBoj3Kw13bgoZq95 vuhlVYs9/7pj+rVKl1rn4wAHBKJHWw/2vCDuVka0jzfdWkWQafXBSnJALWGU150A2hOv /noA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aafJerS+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 91-v6si7667286ply.296.2018.07.23.03.09.30; Mon, 23 Jul 2018 03:09:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aafJerS+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388406AbeGWLJy (ORCPT + 31 others); Mon, 23 Jul 2018 07:09:54 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:35609 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388246AbeGWLJy (ORCPT ); Mon, 23 Jul 2018 07:09:54 -0400 Received: by mail-pf1-f196.google.com with SMTP id q7-v6so12376pff.2 for ; Mon, 23 Jul 2018 03:09:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Vwl51bqmcDS8wp+lU1pZalSc7Z3bokmXBYlYRayzf+k=; b=aafJerS+Wy98Bqo54iiJlRRZ4XSAOzDYKbZmcV904pGjNkYIXGPlN5ERHKshAVYb+P rBSye5CXK+IrnLSQNwvnPqy/SrWY9XFvGR96twNi3hVDMB92dIXj8Lp0UzcPOd9Du1z3 ugMc20CHPyUB9xiuV/yTi2YA0W/pcQgkmzycE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vwl51bqmcDS8wp+lU1pZalSc7Z3bokmXBYlYRayzf+k=; b=tmXyUpJQyu5Zk/a67DO6XBv0qtMM/33pISo4OoMzfbhwfzgXC1h/62Gqpq2nLqwTNU VJMxdIJyQQKg9zKwKgaAlUY1baQpx0IZzXkRGwZGSau1dVLxd9Pil8fdku1CtjK6+Dzh bk/Pog8u+QIUz8zOw1DUCVyIQy3XevhnA6AKiiCixEkF3VrJr5byc7jcpv5rn0hY/Jsd 87xKiwZmnyn1XMhHgHyIRdJCqc1P0CZwI0RzCTjAUfzhVR6ejfcopr3oD05qvRtHp0Z7 D3K9WyBknrqOY/i5efSDONScL/Cc+aIiknvM5wbBHKdmSPHxRZFmfI67q7lSFOg1hZPV jVXg== X-Gm-Message-State: AOUpUlErjOen+cimKRYXfPkhds7OwEu52DgCSgtiicwlXQQVYPBX0US5 hcALH1hhohc2KFE9rcL/hT8NBA== X-Received: by 2002:a65:6203:: with SMTP id d3-v6mr11649605pgv.420.1532340567315; Mon, 23 Jul 2018 03:09:27 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm13470698pfk.87.2018.07.23.03.09.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 03:09:26 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , zhang.lyra@gmail.com Subject: [PATCH V4 4/7] mmc: sdhci: add 32-bit block count support for v4 mode Date: Mon, 23 Jul 2018 18:08:25 +0800 Message-Id: <1532340508-8749-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> References: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 15 ++++++++++++++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 15 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ce71afa..5acea3d 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -956,6 +956,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { + u32 reg; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1070,7 +1071,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 16-bit Block Count + * register need to be set to zero, 32-bit Block Count register would + * be selected. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 23318ff..81aae07 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) From patchwork Mon Jul 23 10:08:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 142562 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp5862649ljj; Mon, 23 Jul 2018 03:09:35 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdVMB38bFqWOWi5ib03E99/urQBGRDsTyNFdIeja77tUh7w/UwKbp7KjagtoTzfA/Emskgi X-Received: by 2002:a17:902:ac1:: with SMTP id 59-v6mr3121531plp.18.1532340575337; Mon, 23 Jul 2018 03:09:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532340575; cv=none; d=google.com; s=arc-20160816; b=ptgwtbYcY8iorSk/IAu26TA+wzzwUFb2SrKqUxwOEInVwotjRR6zD4GaUtPcV1i14T AkvHJeNWa5jyNrU0hwGLlWf4lRHEu7PA8UtJmAj6a8QykfpBbyhdUCe7oKTNKnSS5OsU qq9YzDezoHWBFxr1QVb9CtWV2ihuTo0HMDT4F4SLshnXmF1E7cDFzntoh5twqQRNDdH3 AEpxENk6WAU3rrSJWqHdvYDwu2WPbNum1YzGRuTkmZJGt2wZKKZEf7vwozWmsQO1dogI DjlFb8soCr7Yj4DyRpOcQYBeUcL5P6tQDOkPnDoM3l7hLkJFcyGlAiGEnY9PmBRoMHqB OshQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+pDYdrEU5zydj6TS5ZAbh5dlUzb5zJaLCom/C7No0Jg=; b=fQO0pPfAt5TewEjGDZumBNPVuG3eUE7sbkI4lzNbZi5axiMqfJ1RDAwZOPzHqkzS/f ylqH/fzUchfz5dHNHp9ZhGKvF/VPhkvswXJwqd/Z7DiDWGb+UsbPXdXVvoLutlyQx29V gs9mSFFFlueNqzOIvyXP6XHSqaWaPmZclxIKJadoZdP9icxal0BTUg/ozRmhpqBcrrX6 fmm7ZamYGaURuJZS+7UY/VYHbGc42OyqVA8947NH01GIGz6HDJgRvXbQP+9tV45Wx9bv Q14nAv/Ye4K+qHg+JpluBjTo1pifrrNzdoscXJtugi3SQcx2Yql7jD8m3MXd9ubDlAl4 zS3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G0siyRfk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w6-v6si8640385pgb.61.2018.07.23.03.09.35; Mon, 23 Jul 2018 03:09:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G0siyRfk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388426AbeGWLJ7 (ORCPT + 31 others); Mon, 23 Jul 2018 07:09:59 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:44474 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388375AbeGWLJ7 (ORCPT ); Mon, 23 Jul 2018 07:09:59 -0400 Received: by mail-pg1-f196.google.com with SMTP id r1-v6so40946pgp.11 for ; Mon, 23 Jul 2018 03:09:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+pDYdrEU5zydj6TS5ZAbh5dlUzb5zJaLCom/C7No0Jg=; b=G0siyRfkolwXWKyBmUvy2lCI4X+2feBbUMTqQ6wkNeqqQeL/KCJl2Nmkxr3lCw/N/h 5hxVs0UfcC5xN3AqzmilFILJKMPQzrDMfKoCEQdpUiOM3rkDLn9wH9m2gF/2C/WwA9px PQEbMttAA747HAgB42DORmFvQ0HySvq38m81I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+pDYdrEU5zydj6TS5ZAbh5dlUzb5zJaLCom/C7No0Jg=; b=WUK4Yckf4H9bIBNyhKGNXusNZvh1Fw7aKtFR2T3uUDXdwHSx8Z+OUVjUjkQ1TbFCsP hJEMGCIBH5Gm2tkSV2B7B3/7OwY5smIOwNkxgG+VDK3UzppAIDUgYUV4Nk+o183+lqvU x+WP0gw+uGMK68Zn+6N31Lg4Iiyar0ADTEUO6VhPCQJWhy3MsiVm2zDal0uGBb+8q9/F G+zY07DMgTxEoXYo9BhAj2tTUe+wekk6UNAJ1mcZFmHqJxY1NVow8S2PI745gN681M7D 1m4a/yqISKKMjdJMr6pJBDTn05PbdAW6fWOHPEyXMjUiGgF2hyi4BNCLai+1WosnOYC5 XNIw== X-Gm-Message-State: AOUpUlHFaqK42AFCMpeb0jtTh3dv8YgjgEJUQe968sySUvR7d0/sUyUY cE38oCwkTKIcAH+uO9NxSrxA3g== X-Received: by 2002:a62:ccd0:: with SMTP id j77-v6mr12554876pfk.22.1532340572214; Mon, 23 Jul 2018 03:09:32 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm13470698pfk.87.2018.07.23.03.09.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 03:09:31 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , zhang.lyra@gmail.com Subject: [PATCH V4 5/7] mmc: sdhci: add Auto CMD Auto Select support Date: Mon, 23 Jul 2018 18:08:26 +0800 Message-Id: <1532340508-8749-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> References: <1532340508-8749-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 61 +++++++++++++++++++++++++++++++++++++++--------- drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 52 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 5acea3d..5c60590 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -311,6 +311,23 @@ static void sdhci_config_dma(struct sdhci_host *host) sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } +static void sdhci_enable_cmd23(struct sdhci_host *host) +{ + u16 ctrl2; + + /* + * This is used along with "Auto CMD Auto Select" feature, + * which is introduced from v4.10, if card supports CMD23, + * Auto CMD23 should be used instead of Auto CMD12. + */ + if (host->version >= SDHCI_SPEC_410 && + (host->mmc->caps & MMC_CAP_CMD23)) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CMD23_ENABLE; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } +} + static void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; @@ -329,6 +346,8 @@ static void sdhci_init(struct sdhci_host *host, int soft) host->clock = 0; mmc->ops->set_ios(mmc, &mmc->ios); } + + sdhci_enable_cmd23(host); } static void sdhci_reinit(struct sdhci_host *host) @@ -1093,6 +1112,36 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host *host, !mrq->cap_cmd_during_tfr; } +static inline void sdhci_auto_cmd_select(struct sdhci_host *host, + struct mmc_command *cmd, + u16 *mode) +{ + bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && + (cmd->opcode != SD_IO_RW_EXTENDED); + bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); + + /* + * In case of Version 4.10 or later, use of 'Auto CMD Auto + * Select' is recommended rather than use of 'Auto CMD12 + * Enable' or 'Auto CMD23 Enable'. + */ + if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { + *mode |= SDHCI_TRNS_AUTO_SEL; + return; + } + + /* + * If we are sending CMD23, CMD12 never gets sent + * on successful completion (so no Auto-CMD12). + */ + if (use_cmd12) { + *mode |= SDHCI_TRNS_AUTO_CMD12; + } else if (use_cmd23) { + *mode |= SDHCI_TRNS_AUTO_CMD23; + sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); + } +} + static void sdhci_set_transfer_mode(struct sdhci_host *host, struct mmc_command *cmd) { @@ -1119,17 +1168,7 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; - /* - * If we are sending CMD23, CMD12 never gets sent - * on successful completion (so no Auto-CMD12). - */ - if (sdhci_auto_cmd12(host, cmd->mrq) && - (cmd->opcode != SD_IO_RW_EXTENDED)) - mode |= SDHCI_TRNS_AUTO_CMD12; - else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { - mode |= SDHCI_TRNS_AUTO_CMD23; - sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); - } + sdhci_auto_cmd_select(host, cmd, &mode); } if (data->flags & MMC_DATA_READ) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 81aae07..a8f4ec2 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -42,6 +42,7 @@ #define SDHCI_TRNS_BLK_CNT_EN 0x02 #define SDHCI_TRNS_AUTO_CMD12 0x04 #define SDHCI_TRNS_AUTO_CMD23 0x08 +#define SDHCI_TRNS_AUTO_SEL 0x0C #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 @@ -185,6 +186,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000