From patchwork Mon Jun 7 11:38:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 455461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5F80C47082 for ; Mon, 7 Jun 2021 11:39:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C4B136121D for ; Mon, 7 Jun 2021 11:39:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230434AbhFGLlY (ORCPT ); Mon, 7 Jun 2021 07:41:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231435AbhFGLlX (ORCPT ); Mon, 7 Jun 2021 07:41:23 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 173B9C061787 for ; Mon, 7 Jun 2021 04:39:19 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id z26so12854338pfj.5 for ; Mon, 07 Jun 2021 04:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DlAUbwKHHHe65i+U7K3ydnc29EqdXosEre7ru7N+GbE=; b=Al2mbeZLpBHewqO4nzNNMGC7AmYHSvaDvA4nQB48+J+guCAbRkfkixMt97BbMmXrGr uTxIrFZLx9qwECMBWouLgWtFvgjQ+p572SkE0ttZMeTW2MgEo3BLUch25f11/6XMsWkS l5L7UIoLZb5A4cOJAWm4eJVAXFVUv+q4P4DEZG8YfWnGoFiUa1o5jRu6ZDzQJF6d4Xoh t1IMuRDKDg+tfCbweu40oo+jJc7JL2FskCx18GmmNBiGaSier82tlZy0sVl/h2aD+4mF bcv2bja/oH3i7XmaiDTnmqc4hJaRd+RjhBw//9Nt2GKn/RpzW5R48zI9LD2wRW7j2Kru gFHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DlAUbwKHHHe65i+U7K3ydnc29EqdXosEre7ru7N+GbE=; b=HEwZUinJFZtpQZLWLrNFSLW80QBsMVKm45tYfiKl9o2inhk6me2G9dEhjaOPJarvvJ +IiXZFrLlgKgMQjCM/ILE2XOys5zY+VZ4yQ/QDaTfPenGIfit3lHUAKgSZcRTSL9GOyW SUoUFxoKCCs9/raRp17KpicvvvXtOV+aqFH4rkGDlA9zEXWSQSG/hMZoOAIBGNuUlGqh iSGM0ow+tX/kYh/EzOKJkuGzJP6Nx7P2X8MEqNSoc1jizWSQi+D3PG+0k55njGZK5H3J 8m3p2UWDAmWVf6sVIggsaOVMCrTksDJgx3pph633tfr+txw3vkuW8GWlZXnHiWn0w4ok /fwQ== X-Gm-Message-State: AOAM531UUofUkBCJTRyxH5o6+7b3HubH02BBUtlHIRN5psxKSAG5ItRm IdUsNDg9yPLJjaB6K81px8dOKb1k5Xirxw== X-Google-Smtp-Source: ABdhPJx+JA3GA3bvFkAkuQGUzsnkDN8ow3pxo3VkR/8fBNo/FWLxBAnGiKx2f5yDP7DPkOghyThelg== X-Received: by 2002:a65:6911:: with SMTP id s17mr17717276pgq.128.1623065958453; Mon, 07 Jun 2021 04:39:18 -0700 (PDT) Received: from localhost.localdomain.name ([122.177.177.211]) by smtp.gmail.com with ESMTPSA id j7sm7223939pjf.0.2021.06.07.04.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 04:39:18 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Linus Walleij , Liam Girdwood , Mark Brown , Bjorn Andersson , Vinod Koul , Rob Herring , Andy Gross , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH 2/8] dt-bindings: pinctrl: qcom, pmic-gpio: Add compatible for SA8155p-adp Date: Mon, 7 Jun 2021 17:08:34 +0530 Message-Id: <20210607113840.15435-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210607113840.15435-1-bhupesh.sharma@linaro.org> References: <20210607113840.15435-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add pmic-gpio compatible strings for pmm8155au_1 and pmm8155au_2 pmics found on SA8155p-adp board. Cc: Linus Walleij Cc: Liam Girdwood Cc: Mark Brown Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Cc: Andy Gross Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index f6a9760558a6..ee4721f1c477 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -27,6 +27,8 @@ PMIC's from Qualcomm. "qcom,pm660l-gpio" "qcom,pm8150-gpio" "qcom,pm8150b-gpio" + "qcom,pmm8155au-1-gpio" + "qcom,pmm8155au-2-gpio" "qcom,pm8350-gpio" "qcom,pm8350b-gpio" "qcom,pm8350c-gpio" @@ -116,6 +118,9 @@ to specify in a pin configuration subnode: and gpio8) gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7) gpio1-gpio12 for pm8150l (hole on gpio7) + gpio1-gpio10 for pmm8155au-1 (holes on gpio2, gpio5, gpio7 + and gpio8) + gpio1-gpio10 for pmm8155au-2 (holes on gpio2, gpio5, gpio7) gpio1-gpio10 for pm8350 gpio1-gpio8 for pm8350b gpio1-gpio9 for pm8350c From patchwork Mon Jun 7 11:38:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 455285 Delivered-To: patch@linaro.org Received: by 2002:a17:906:72d5:0:0:0:0 with SMTP id m21csp3224513ejl; Mon, 7 Jun 2021 04:40:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy0tpQp9YOzO7OWRlbsIWAUBHSC4j7XJEUAZsz9Xk46JV3FlKG4hKKmMfTKWy1C8hZHfLM4 X-Received: by 2002:a05:6402:1c83:: with SMTP id cy3mr19193472edb.108.1623066042912; Mon, 07 Jun 2021 04:40:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623066042; cv=none; d=google.com; s=arc-20160816; b=Y3jVG5Gbm0HgmQlEeoyuTKPAQg334P9SUrfkADV4u0GiXOUGTa7lh8UFCENyNtIh75 u4xdD7bSW+0kiXIxbDqr7f8W9YiM8Y9A5y7Dq/obVSKR/paui4D9mEwIMvMhYWNbu61G acPbZXJNDFC/V2ZFgEa2TvkTq8kNEjiUjAIzQMCO0TbZMZlWKwUSZsgRtPTHvtRgo2Bo q4LhAQVo+0Cw58vtEFamr1GRFP/42+XOvr9RzZaPOKoTroqUK+MHHS3q/ckvwSgF/7H4 FOuLCs0+sjX+mjXtpvLv9NSvQT0pzXgiwd3o6eY3Uo/cJRnGBmIOhIOgVpKIF4R7MZ0q g0UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KI3tTCluotO+HmvYcfUBTi934M7YmjMqNpLlbV1t4KU=; b=iBcil0/cThEZqVG+4lleYmdCHlc3XO9iQZSq03mP5hnxqz3lyK5gcn/en+PmLzaiHR adRxPoe+Q6l2BidB446MSqN8WjMENYNX9Kk41FLFTFrT1VcGJG38fP4Dni9AUTYwF6eJ dySCwf5W5B9aK0qbcktNI3CzZ41T620QxoupV3DYh1vOh7arnurIf0nlBQi/QXeXKM1J xa2z8DLF5qqmUJhAe/8BCmiR/488za4VC2FOMtrHMIntyAm0UktBTu2D7+H/NqyL4GUI AJdAYz9P783IdSK9QFmMw6YbWtlx2GrEn2p7qUkqjAWdNaRCwE5WUGpm2LVPw3jb3Kte MMrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XaTWaIIY; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The output power management circuits in these regulators include: - FTS510 smps, - HFS510 smps, and - LDO510 linear regulators Cc: Linus Walleij Cc: Liam Girdwood Cc: Mark Brown Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Cc: Andy Gross Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/regulator/qcom-rpmh-regulator.c | 72 +++++++++++++++++++++++++ 1 file changed, 72 insertions(+) -- 2.31.1 diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qcom-rpmh-regulator.c index 22fec370fa61..d0a3c6527568 100644 --- a/drivers/regulator/qcom-rpmh-regulator.c +++ b/drivers/regulator/qcom-rpmh-regulator.c @@ -883,6 +883,70 @@ static const struct rpmh_vreg_init_data pm8150l_vreg_data[] = { {}, }; +static const struct rpmh_vreg_init_data pmm8155au_1_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"), + RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"), + RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l8-l11"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l10"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9"), + RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l1-l8-l11"), + RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9"), + RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l2-l10"), + RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"), + RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l13-l16-l17"), + RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16-l17"), + RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l13-l16-l17"), + RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + {}, +}; + +static const struct rpmh_vreg_init_data pmm8155au_2_vreg_data[] = { + RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"), + RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"), + RPMH_VREG("smps3", "smp%s3", &pmic5_ftsmps510, "vdd-s3"), + RPMH_VREG("smps4", "smp%s4", &pmic5_hfsmps510, "vdd-s4"), + RPMH_VREG("smps5", "smp%s5", &pmic5_hfsmps510, "vdd-s5"), + RPMH_VREG("smps6", "smp%s6", &pmic5_ftsmps510, "vdd-s6"), + RPMH_VREG("smps7", "smp%s7", &pmic5_ftsmps510, "vdd-s7"), + RPMH_VREG("smps8", "smp%s8", &pmic5_ftsmps510, "vdd-s8"), + RPMH_VREG("smps9", "smp%s9", &pmic5_ftsmps510, "vdd-s9"), + RPMH_VREG("smps10", "smp%s10", &pmic5_ftsmps510, "vdd-s10"), + RPMH_VREG("ldo1", "ldo%s1", &pmic5_nldo, "vdd-l1-l8-l11"), + RPMH_VREG("ldo2", "ldo%s2", &pmic5_pldo, "vdd-l2-l10"), + RPMH_VREG("ldo3", "ldo%s3", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + RPMH_VREG("ldo4", "ldo%s4", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + RPMH_VREG("ldo5", "ldo%s5", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + RPMH_VREG("ldo6", "ldo%s6", &pmic5_nldo, "vdd-l6-l9"), + RPMH_VREG("ldo7", "ldo%s7", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo8", "ldo%s8", &pmic5_nldo, "vdd-l1-l8-l11"), + RPMH_VREG("ldo9", "ldo%s9", &pmic5_nldo, "vdd-l6-l9"), + RPMH_VREG("ldo10", "ldo%s10", &pmic5_pldo, "vdd-l2-l10"), + RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"), + RPMH_VREG("ldo12", "ldo%s12", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo13", "ldo%s13", &pmic5_pldo, "vdd-l13-l16-l17"), + RPMH_VREG("ldo14", "ldo%s14", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo15", "ldo%s15", &pmic5_pldo_lv, "vdd-l7-l12-l14-l15"), + RPMH_VREG("ldo16", "ldo%s16", &pmic5_pldo, "vdd-l13-l16-l17"), + RPMH_VREG("ldo17", "ldo%s17", &pmic5_pldo, "vdd-l13-l16-l17"), + RPMH_VREG("ldo18", "ldo%s18", &pmic5_nldo, "vdd-l3-l4-l5-l18"), + {}, +}; + static const struct rpmh_vreg_init_data pm8350_vreg_data[] = { RPMH_VREG("smps1", "smp%s1", &pmic5_ftsmps510, "vdd-s1"), RPMH_VREG("smps2", "smp%s2", &pmic5_ftsmps510, "vdd-s2"), @@ -1143,6 +1207,14 @@ static const struct of_device_id __maybe_unused rpmh_regulator_match_table[] = { .compatible = "qcom,pm8150l-rpmh-regulators", .data = pm8150l_vreg_data, }, + { + .compatible = "qcom,pmm8155au-1-rpmh-regulators", + .data = pmm8155au_1_vreg_data, + }, + { + .compatible = "qcom,pmm8155au-2-rpmh-regulators", + .data = pmm8155au_2_vreg_data, + }, { .compatible = "qcom,pm8350-rpmh-regulators", .data = pm8350_vreg_data, From patchwork Mon Jun 7 11:38:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 455283 Delivered-To: patch@linaro.org Received: by 2002:a17:906:72d5:0:0:0:0 with SMTP id m21csp3224029ejl; Mon, 7 Jun 2021 04:39:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyyPpF5I4vm3l21TaWpVMnJPaGUk6ZCQJ0mlURuQTLg0W4kOiJJPwsTp+PDoKNAoi5oK4p7 X-Received: by 2002:a05:6402:177a:: with SMTP id da26mr19677727edb.40.1623065996639; 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Cc: Linus Walleij Cc: Liam Girdwood Cc: Mark Brown Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Cc: Andy Gross Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.31.1 diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 00870da0c94e..890c44b6e198 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1127,6 +1127,10 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, /* pm8150l has 12 GPIOs with holes on 7 */ { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, + /* pmm8155au-1 has 10 GPIOs with holes on 2, 5, 7 and 8 */ + { .compatible = "qcom,pmm8155au-1-gpio", .data = (void *) 10 }, + /* pmm8155au-2 has 10 GPIOs with holes on 2, 5 and 7 */ + { .compatible = "qcom,pmm8155au-2-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, From patchwork Mon Jun 7 11:38:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 455281 Delivered-To: patch@linaro.org Received: by 2002:a17:906:72d5:0:0:0:0 with SMTP id m21csp3224003ejl; Mon, 7 Jun 2021 04:39:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz8qBA+e00meZG4JJw4vKgIG4aNYCAJiCvzL6ynEvqt3kIcBQuLQ462g5YwLvIYbMP5Oopx X-Received: by 2002:a17:906:a1d9:: with SMTP id bx25mr17101428ejb.363.1623065994516; Mon, 07 Jun 2021 04:39:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623065994; cv=none; d=google.com; s=arc-20160816; b=z3iZT4/7P+7Z7NR2gAXCZRxao1u2z4etDNrbtdtoRQGs4qHqSthK5TV3/3agY91X0i pIxGS33um/bGmmXK2R1vUDBwZJX+7OjVOOo7luMsUXK6hNnYF5kgGGIa7x99y0PXOR5w +F/ivVYQ426Qgu7NzZ/BbplR1grHNLoLKsh5Ru3yPm3OZfpgz0eOpJ5MMkKhEIhuqUY+ AxihxRS7jqaXMmUhz426YrDRVBuixki4tYOkXYq+UhnMQ1SWI9v8IrQaG+Hp49UjzRdR CqMB3kxEdV0t+c6oJ3AM0weUQ/xKM7uMG2sbADvuKFKSkuSzu3pczut2jMTP2bHND1XV /vhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ix3Z3iu5Sdv/B7LYx2J6tZXgGiemwrKhiSlqqq85Tao=; b=Zu6W3uRARfRSSAk7UH8M9Ma1Y59byoRkPJPj9uLFkBIVZuxJHFuND3/LiLTxx16Y1D PYTF/f/abTDBedECsic67LZQZCv4bW2XP6P0pv/i49uyIPQpHRDVesu+MVWn8DxRyX8z AaIraC86w0v0bS76mHIMlqgu3r7tHOYEB1dScnK2b4rXaxL3evTsVM1iaRiTjtKRfmzp D5td7MUMBm3ZMPXPASRDcIsAzHDRjMGcprueVmfvaCmOB4m6HKgp+dFdnNL8g2qE8YoS bmhQ6JoCzkkjTW4kOjDD+SywnZ2OUHABKIyEbFK0JWUAJJAm6ZWc3UD6tBELLGuD66ar ZGjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kTSgf7cp; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w4si8407501edq.419.2021.06.07.04.39.54; Mon, 07 Jun 2021 04:39:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kTSgf7cp; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231462AbhFGLlg (ORCPT + 17 others); Mon, 7 Jun 2021 07:41:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231366AbhFGLlf (ORCPT ); Mon, 7 Jun 2021 07:41:35 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0304C06178B for ; Mon, 7 Jun 2021 04:39:44 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id u7so8494487plq.4 for ; Mon, 07 Jun 2021 04:39:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ix3Z3iu5Sdv/B7LYx2J6tZXgGiemwrKhiSlqqq85Tao=; b=kTSgf7cpzEefZXwj/Gi0pLErE2/d8Xz0i2MKmf7fPxskKtL4Ap66mCqhKSxUMkFVsD e1NCuuSbL2YSOLMHyXqroWjo11J/c274RGqMf+oktKFxpcirue7p9iZxoqvjq5ktINvx QWaT2Nu+IflBUPy5SeuBJjteB6xokggeABOEwvzP/iIEE996+vye1MGS1CeTi/jd4noq Z4aSpIaKzATfZk20ADAtdXhvRwPNsDyW1CpyFsGdR26x+jnmHN0hcVulg0YUd6h3zAJj XuSfh0akC5UQL46cqiWFnHPrU3Zglyj0exMkUsLu2Pxb1ltDxYAJ2Zwd7NyYpnx8hTXQ l+TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ix3Z3iu5Sdv/B7LYx2J6tZXgGiemwrKhiSlqqq85Tao=; b=ci5nqfq55AYXuZJOG3/SGhtqW40Bi2tF+Aws8ywGf0fdRJcMQpFdCwcWygd7Kszffe Vcf0xd/dZsmRWp9+HDZfLCrc0MwrK/PCVv7BmCdo0AQUHLH5L88XkxKwdGYf8eIMZS+U vyIkwtQT9SQZ+HonsXi+9yioo8kBPnuwUKuZWXiIX32SC3ZjjL54JF+I/TLokZLSG6x2 xbpmPZ7SFEEsrNRBYZ2QBtuewNmt07EpIXfESkBWZMLWMGnAPIpVSn4zFrxJJBUqxi94 ZvxtuRvYqaSvDh8btgk/5NrNDW/dICjr6sgofmRSrMRWjDByciygjLVdRrTUUtplb5MS v+zQ== X-Gm-Message-State: AOAM532OBnAs2mmpJ9JmY8r0CHkH6G6cQDV+b25mLG5z7XMXmUCWVyhU p3O3xap73aB/0PYUKrlC4YWH8kzf0vmAeQ== X-Received: by 2002:a17:90b:3ecb:: with SMTP id rm11mr19723250pjb.95.1623065983941; Mon, 07 Jun 2021 04:39:43 -0700 (PDT) Received: from localhost.localdomain.name ([122.177.177.211]) by smtp.gmail.com with ESMTPSA id j7sm7223939pjf.0.2021.06.07.04.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 04:39:43 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, Linus Walleij , Liam Girdwood , Mark Brown , Bjorn Andersson , Vinod Koul , Rob Herring , Andy Gross , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, bhupesh.linux@gmail.com Subject: [PATCH 7/8] arm64: dts: qcom: pmm8155au_2: Add base dts file Date: Mon, 7 Jun 2021 17:08:39 +0530 Message-Id: <20210607113840.15435-8-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210607113840.15435-1-bhupesh.sharma@linaro.org> References: <20210607113840.15435-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add base DTS file for pmm8155au_2 along with GPIOs, power-on, rtc and vadc nodes. Cc: Linus Walleij Cc: Liam Girdwood Cc: Mark Brown Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Cc: Andy Gross Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: bhupesh.linux@gmail.com Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi | 107 ++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi -- 2.31.1 diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi new file mode 100644 index 000000000000..11c0c203a4e2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Limited + */ + +#include +#include +#include + +/ { + thermal-zones { + pmm8155au-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmm8155au_2_temp>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@4 { + compatible = "qcom,pmm8155au-2", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + power-on@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x0800>; + + status = "disabled"; + }; + + pmm8155au_2_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pmm8155au_2_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + + ref-gnd@0 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "ref_gnd"; + }; + + vref-1p25@1 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "vref_1p25"; + }; + + die-temp@6 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "die_temp"; + }; + }; + + pmm8155au_2_gpios: gpio@c000 { + compatible = "qcom,pmm8155au-2-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@5 { + compatible = "qcom,pmm8155au-2", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +};