From patchwork Tue Jul 24 11:45:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 142773 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp7166342ljj; Tue, 24 Jul 2018 04:46:34 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcoS10TKzJBRDE7aCpbriFZlVVzrn9+YIdx56BCt2rJsOkt/Xs9I9Byiu9DcE/0VJob6zL2 X-Received: by 2002:a62:8a83:: with SMTP id o3-v6mr17541133pfk.12.1532432794086; Tue, 24 Jul 2018 04:46:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532432794; cv=none; d=google.com; s=arc-20160816; b=0hqXGNFgR6J1bgEtD5HXn7xX8emOPyUKm3X6qpXXOc40ofRKF3a9IkPjgnarI5e+CF Y6gcQXhwNhTmMUUyht74298UkPPYwWJyfOoO9YjMsyL3+DeVyi8GvHiMfEaNMffxZvQd s3uRHytuL3hgbxUmBszMIq4SmIDFUe18YuvgUrLREFtv8iN2r1NR7otRXzutFlLpm9xG FzSK8F/rVJ1sCiPH99SpLKz2y8ZWqVulqVds7qgTZnBidrYR8P7eExTfLWjdAeSSGTba uQBaXB4UeSWkLSKATu1IWLOkoXWl0ih1lrIp3vt2WvQjTxJU+gkwE/G0na2qGTWwain6 VGWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=pnY+0ROAx/oczEejs5KVoIjyUCqqWa3QKgTalLxYzHE=; b=OMqHWKnVzZDKdw1gcPIN7MsJu3Hqlqx35t7iRkQ/per4XyI/fXYQ9AAAwyL6xd1iuq eDfmWUc2wgJDr2jfnHijgIfx4EL9UwbusmJiwystCg4126Ls87wZBH9PcjTmKUM7iS74 omATTVGtTOa8RYxQONRZaWK1P5qdCv5rVS0n+nbdczlwAfxIa8v1mELlxTwzZki4t4v0 /z4P0RURkKfwRr4JeRpF9doHvLS9p5RgnKxCjepBmtov1KlBFwGn/8WnMRBtxahzlJkw DIPn0DtxD1YiXys+a0eD4KfWeLajr5JytyCLKZy5i1aejoSvWjJ8QuoraVRrsiOxsupk WXvA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p5-v6si11418604pgl.516.2018.07.24.04.46.33; Tue, 24 Jul 2018 04:46:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388422AbeGXMwf (ORCPT + 31 others); Tue, 24 Jul 2018 08:52:35 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:10111 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388256AbeGXMwe (ORCPT ); Tue, 24 Jul 2018 08:52:34 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id D6A62EEBBC833; Tue, 24 Jul 2018 19:46:24 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Tue, 24 Jul 2018 19:46:17 +0800 From: Shameer Kolothum To: , CC: , , , , , , , , , , , Subject: [PATCH v2 1/4] acpi: arm64: add iort support for PMCG Date: Tue, 24 Jul 2018 12:45:12 +0100 Message-ID: <20180724114515.21764-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> References: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Neil Leeder Add support for the SMMU Performance Monitor Counter Group information from ACPI. This is in preparation for its use in the SMMU v3 PMU driver. Signed-off-by: Neil Leeder Signed-off-by: Hanjun Guo Signed-off-by: Shameer Kolothum --- drivers/acpi/arm64/iort.c | 95 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 83 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 7a3a541..ac4d0d6 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -356,7 +356,8 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node, if (map->flags & ACPI_IORT_ID_SINGLE_MAPPING) { if (node->type == ACPI_IORT_NODE_NAMED_COMPONENT || node->type == ACPI_IORT_NODE_PCI_ROOT_COMPLEX || - node->type == ACPI_IORT_NODE_SMMU_V3) { + node->type == ACPI_IORT_NODE_SMMU_V3 || + node->type == ACPI_IORT_NODE_PMCG) { *id_out = map->output_base; return parent; } @@ -394,6 +395,8 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node) } return smmu->id_mapping_index; + case ACPI_IORT_NODE_PMCG: + return 0; default: return -EINVAL; } @@ -1287,6 +1290,63 @@ static bool __init arm_smmu_is_coherent(struct acpi_iort_node *node) return smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK; } +static void __init arm_smmu_common_dma_configure(struct device *dev, + enum dev_dma_attr attr) +{ + /* We expect the dma masks to be equivalent for all SMMUs set-ups */ + dev->dma_mask = &dev->coherent_dma_mask; + + /* Configure DMA for the page table walker */ + acpi_dma_configure(dev, attr); +} + +static int __init arm_smmu_v3_pmu_count_resources(struct acpi_iort_node *node) +{ + struct acpi_iort_pmcg *pmcg; + + /* Retrieve PMCG specific data */ + pmcg = (struct acpi_iort_pmcg *)node->node_data; + + /* + * There are always 2 memory resources. + * If the overflow_gsiv is present then add that for a total of 3. + */ + return pmcg->overflow_gsiv > 0 ? 3 : 2; +} + +static void __init arm_smmu_v3_pmu_init_resources(struct resource *res, + struct acpi_iort_node *node) +{ + struct acpi_iort_pmcg *pmcg; + + /* Retrieve PMCG specific data */ + pmcg = (struct acpi_iort_pmcg *)node->node_data; + + res[0].start = pmcg->page0_base_address; + res[0].end = pmcg->page0_base_address + SZ_4K - 1; + res[0].flags = IORESOURCE_MEM; + res[1].start = pmcg->page1_base_address; + res[1].end = pmcg->page1_base_address + SZ_4K - 1; + res[1].flags = IORESOURCE_MEM; + + if (pmcg->overflow_gsiv) + acpi_iort_register_irq(pmcg->overflow_gsiv, "overflow", + ACPI_EDGE_SENSITIVE, &res[2]); +} + +static struct acpi_iort_node *iort_find_pmcg_ref(struct acpi_iort_node *node) +{ + struct acpi_iort_pmcg *pmcg; + struct acpi_iort_node *ref_node = NULL; + + /* Retrieve PMCG specific data */ + pmcg = (struct acpi_iort_pmcg *)node->node_data; + if (pmcg->node_reference) + ref_node = ACPI_ADD_PTR(struct acpi_iort_node, + iort_table, pmcg->node_reference); + return ref_node; +} + struct iort_dev_config { const char *name; int (*dev_init)(struct acpi_iort_node *node); @@ -1296,6 +1356,8 @@ struct iort_dev_config { struct acpi_iort_node *node); void (*dev_set_proximity)(struct device *dev, struct acpi_iort_node *node); + void (*dev_dma_configure)(struct device *dev, + enum dev_dma_attr attr); }; static const struct iort_dev_config iort_arm_smmu_v3_cfg __initconst = { @@ -1304,23 +1366,38 @@ static const struct iort_dev_config iort_arm_smmu_v3_cfg __initconst = { .dev_count_resources = arm_smmu_v3_count_resources, .dev_init_resources = arm_smmu_v3_init_resources, .dev_set_proximity = arm_smmu_v3_set_proximity, + .dev_dma_configure = arm_smmu_common_dma_configure }; static const struct iort_dev_config iort_arm_smmu_cfg __initconst = { .name = "arm-smmu", .dev_is_coherent = arm_smmu_is_coherent, .dev_count_resources = arm_smmu_count_resources, - .dev_init_resources = arm_smmu_init_resources + .dev_init_resources = arm_smmu_init_resources, + .dev_dma_configure = arm_smmu_common_dma_configure +}; + +static const struct iort_dev_config iort_arm_smmu_v3_pmcg_cfg __initconst = { + .name = "arm-smmu-v3-pmu", + .dev_count_resources = arm_smmu_v3_pmu_count_resources, + .dev_init_resources = arm_smmu_v3_pmu_init_resources }; static __init const struct iort_dev_config *iort_get_dev_cfg( struct acpi_iort_node *node) { + struct acpi_iort_node *ref_node; + switch (node->type) { case ACPI_IORT_NODE_SMMU_V3: return &iort_arm_smmu_v3_cfg; case ACPI_IORT_NODE_SMMU: return &iort_arm_smmu_cfg; + case ACPI_IORT_NODE_PMCG: + /* Check this is associated with SMMUv3 */ + ref_node = iort_find_pmcg_ref(node); + if (ref_node && ref_node->type == ACPI_IORT_NODE_SMMU_V3) + return &iort_arm_smmu_v3_pmcg_cfg; default: return NULL; } @@ -1376,12 +1453,6 @@ static int __init iort_add_platform_device(struct acpi_iort_node *node, if (ret) goto dev_put; - /* - * We expect the dma masks to be equivalent for - * all SMMUs set-ups - */ - pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; - fwnode = iort_get_fwnode(node); if (!fwnode) { @@ -1391,11 +1462,11 @@ static int __init iort_add_platform_device(struct acpi_iort_node *node, pdev->dev.fwnode = fwnode; - attr = ops->dev_is_coherent && ops->dev_is_coherent(node) ? + if (ops->dev_dma_configure) { + attr = ops->dev_is_coherent && ops->dev_is_coherent(node) ? DEV_DMA_COHERENT : DEV_DMA_NON_COHERENT; - - /* Configure DMA for the page table walker */ - acpi_dma_configure(&pdev->dev, attr); + ops->dev_dma_configure(&pdev->dev, attr); + } iort_set_device_domain(&pdev->dev, node); From patchwork Tue Jul 24 11:45:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 142774 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp7166415ljj; Tue, 24 Jul 2018 04:46:38 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf9xA20521ygo0lyoOiReYe9ON0XYVY9AGJFFJGOWR2Ptx5BZY7+qLnDb/NaCFeO95p0QIm X-Received: by 2002:a63:d309:: with SMTP id b9-v6mr15991867pgg.163.1532432797942; Tue, 24 Jul 2018 04:46:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532432797; cv=none; d=google.com; s=arc-20160816; b=DG+uE/swOy1w7Jw3YVQZX4bDqVJyfUA1iHgV7784t1w3eDbizuGyquqZucV5P/SXKg GjFDOb3ICt+z0tXGg+5+Y8RUAyLzzQScrYXbL5hKt7SuZvbx9r1xcvzyJTrcA8OUbDJf aBLgo8E/wKH8XabVLvvJO+cfhfHhtZkZRL8BRvUcGF8seLOiX6oq0Xa+bkwY/XL95TrO xtBKmEURTqXSfuhbFAv87no3MNGuSvJkJ2xm+AZ6EjsgX278WEe3tq1FckEVJ12WyFbm S/hX7s1vLFDZPwIcerSBB/mre9fdGpTDj0xNM2b/4QMp8xRIAbAZ6hubzzRGHKRgelEE UnUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=vUZORpuNv9VcH0DvoRt7GLwotfl01CcNvXZ4dcufeK0=; b=Wam1lntoRyg8l5GzGdLT2ELxOP4lHOOn3wFPy8OrZMP1gPjvsSDIfJfHlocVfWL+Kn 6vQ0Nn2SCPTwJC6R9ClszJOdH8vwrMqRW92hRpMGshZYTyNzccnXwZ8SQL2AeRKnJ2XJ 2zygYKkHCwmD9q4+4tR3N4emfUGi5HMQbE36ZTKFHZrNFvneciKhVPCL8drmjBpXckLQ IJnvrxhGqCJP/kcjDadl/TT0tcI7pe7I7hCgF7jRE0OBOWfHN7wys9hnmM5EevvfeQV8 eILapPR2PTqjvYRliLs2CW4BCpbbawyz4c7HEADJAm0ynXzjb6Uo9h69I5XOznQabZE0 1ulQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l7-v6si11273861pgc.650.2018.07.24.04.46.37; Tue, 24 Jul 2018 04:46:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388449AbeGXMwk (ORCPT + 31 others); Tue, 24 Jul 2018 08:52:40 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:10112 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388370AbeGXMwj (ORCPT ); Tue, 24 Jul 2018 08:52:39 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id DD0AFB580EA43; Tue, 24 Jul 2018 19:46:29 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Tue, 24 Jul 2018 19:46:21 +0800 From: Shameer Kolothum To: , CC: , , , , , , , , , , , Subject: [PATCH v2 2/4] acpi: arm64: iort helper to find the associated smmu of pmcg node Date: Tue, 24 Jul 2018 12:45:13 +0100 Message-ID: <20180724114515.21764-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> References: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds an helper to retrieve the smmuv3 dev(if any) associated with the PMCG node. This will be used in subsequent SMMUv3 PMU driver patch to name the pmu device. Signed-off-by: Shameer Kolothum --- drivers/acpi/arm64/iort.c | 84 ++++++++++++++++++++++++++++++++++++----------- include/linux/acpi_iort.h | 4 +++ 2 files changed, 69 insertions(+), 19 deletions(-) -- 2.7.4 diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index ac4d0d6..7940080 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -42,6 +42,7 @@ struct iort_fwnode { struct list_head list; struct acpi_iort_node *iort_node; struct fwnode_handle *fwnode; + struct platform_device *pdev; }; static LIST_HEAD(iort_fwnode_list); static DEFINE_SPINLOCK(iort_fwnode_lock); @@ -52,12 +53,14 @@ static DEFINE_SPINLOCK(iort_fwnode_lock); * * @node: IORT table node associated with the IOMMU * @fwnode: fwnode associated with the IORT node + * @pdev: platform dev associated with the IORT node if any * * Returns: 0 on success * <0 on failure */ static inline int iort_set_fwnode(struct acpi_iort_node *iort_node, - struct fwnode_handle *fwnode) + struct fwnode_handle *fwnode, + struct platform_device *pdev) { struct iort_fwnode *np; @@ -69,6 +72,7 @@ static inline int iort_set_fwnode(struct acpi_iort_node *iort_node, INIT_LIST_HEAD(&np->list); np->iort_node = iort_node; np->fwnode = fwnode; + np->pdev = pdev; spin_lock(&iort_fwnode_lock); list_add_tail(&np->list, &iort_fwnode_list); @@ -78,6 +82,31 @@ static inline int iort_set_fwnode(struct acpi_iort_node *iort_node, } /** + * iort_get_pdev() - Retrieve pdev associated with an IORT node + * + * @node: IORT table node to be looked-up + * + * Returns: platform dev pointer on success, NULL on failure + */ +static inline struct platform_device *iort_get_pdev( + struct acpi_iort_node *node) +{ + struct iort_fwnode *curr; + struct platform_device *pdev = NULL; + + spin_lock(&iort_fwnode_lock); + list_for_each_entry(curr, &iort_fwnode_list, list) { + if (curr->iort_node == node) { + pdev = curr->pdev; + break; + } + } + spin_unlock(&iort_fwnode_lock); + + return pdev; +} + +/** * iort_get_fwnode() - Retrieve fwnode associated with an IORT node * * @node: IORT table node to be looked-up @@ -1347,6 +1376,32 @@ static struct acpi_iort_node *iort_find_pmcg_ref(struct acpi_iort_node *node) return ref_node; } +/** + * iort_find_pmcg_ref_smmu - helper to retrieve SMMUv3 associated with PMCG + * @dev: PMCG device + * + * Returns: smmu dev associated with the PMCG on success, NULL on failure + */ +struct device *iort_find_pmcg_ref_smmu(struct device *dev) +{ + struct acpi_iort_node *node; + struct acpi_iort_node *ref_node = NULL; + struct platform_device *pdev = NULL; + + node = iort_get_iort_node(dev->fwnode); + if (!node || node->type != ACPI_IORT_NODE_PMCG) + return NULL; + + ref_node = iort_find_pmcg_ref(node); + if (ref_node && ref_node->type == ACPI_IORT_NODE_SMMU_V3) + pdev = iort_get_pdev(ref_node); + + if (pdev) + return &pdev->dev; + + return NULL; +} + struct iort_dev_config { const char *name; int (*dev_init)(struct acpi_iort_node *node); @@ -1453,13 +1508,14 @@ static int __init iort_add_platform_device(struct acpi_iort_node *node, if (ret) goto dev_put; - fwnode = iort_get_fwnode(node); - + fwnode = acpi_alloc_fwnode_static(); if (!fwnode) { ret = -ENODEV; goto dev_put; } + iort_set_fwnode(node, fwnode, pdev); + pdev->dev.fwnode = fwnode; if (ops->dev_dma_configure) { @@ -1472,12 +1528,14 @@ static int __init iort_add_platform_device(struct acpi_iort_node *node, ret = platform_device_add(pdev); if (ret) - goto dma_deconfigure; + goto out; return 0; -dma_deconfigure: +out: acpi_dma_deconfigure(&pdev->dev); + iort_delete_fwnode(node); + acpi_free_fwnode_static(fwnode); dev_put: platform_device_put(pdev); @@ -1519,8 +1577,7 @@ static void __init iort_init_platform_devices(void) { struct acpi_iort_node *iort_node, *iort_end; struct acpi_table_iort *iort; - struct fwnode_handle *fwnode; - int i, ret; + int i; bool acs_enabled = false; const struct iort_dev_config *ops; @@ -1547,18 +1604,7 @@ static void __init iort_init_platform_devices(void) ops = iort_get_dev_cfg(iort_node); if (ops) { - fwnode = acpi_alloc_fwnode_static(); - if (!fwnode) - return; - - iort_set_fwnode(iort_node, fwnode); - - ret = iort_add_platform_device(iort_node, ops); - if (ret) { - iort_delete_fwnode(iort_node); - acpi_free_fwnode_static(fwnode); - return; - } + iort_add_platform_device(iort_node, ops); } iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort_node, diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 38cd77b..54ccff2 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -36,6 +36,7 @@ u32 iort_msi_map_rid(struct device *dev, u32 req_id); struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id); void acpi_configure_pmsi_domain(struct device *dev); int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id); +struct device *iort_find_pmcg_ref_smmu(struct device *dev); /* IOMMU interface */ void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size); const struct iommu_ops *iort_iommu_configure(struct device *dev); @@ -48,6 +49,9 @@ static inline struct irq_domain *iort_get_device_domain(struct device *dev, u32 req_id) { return NULL; } static inline void acpi_configure_pmsi_domain(struct device *dev) { } +static inline +struct device *iort_find_pmcg_ref_smmu(struct device *dev) +{ return NULL; } /* IOMMU interface */ static inline void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size) { } From patchwork Tue Jul 24 11:45:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 142776 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp7166480ljj; Tue, 24 Jul 2018 04:46:43 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfPe2swxVl+esy1zy1lIYCpP5+yyQ/BmlnGOHBZePKV+BKu/l8BO6VJjmzQfV3Dq8souxYy X-Received: by 2002:a62:ec41:: with SMTP id k62-v6mr17286274pfh.206.1532432803409; Tue, 24 Jul 2018 04:46:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532432803; cv=none; d=google.com; s=arc-20160816; b=Rp1KOpNLuuxgJcnmj+b427VzjUcrR6Zvs0pA9ks0EKAkdCkk4v/1wVh0YA5nrxMBGX ZcwUF0nGfSMODPDtP1xQgVn0AmnS+aKA5ZZqtGxn4iXzDtxVY5o+T+2h8cR4tn3CnmaO D04LbLBwIxEMuumiSHwM8gTE5Uyc4nII3/LrdZgBvKNUrPRs+vg/w/77n07UXenO1x9M mvCJA/mPDCP0jHSjSBuFBzLQNuZZSvYhpaxAUZwJUW/ca+Jab+/mgp4/o+c0oF3NmXZx 3Hw/hG0DgBmhFhA1yPYHlZDqy2V+Prwn9bLMt1haQN6NmyLmg5Tt1lxgJIdlxsnhLBYR 7kwQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id e12-v6si10798685pfn.322.2018.07.24.04.46.43; Tue, 24 Jul 2018 04:46:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388494AbeGXMwp (ORCPT + 31 others); Tue, 24 Jul 2018 08:52:45 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:10114 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388476AbeGXMwo (ORCPT ); Tue, 24 Jul 2018 08:52:44 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 04571103E3B15; Tue, 24 Jul 2018 19:46:35 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Tue, 24 Jul 2018 19:46:29 +0800 From: Shameer Kolothum To: , CC: , , , , , , , , , , , Subject: [PATCH v2 4/4] perf/smmuv3: Add MSI irq support Date: Tue, 24 Jul 2018 12:45:15 +0100 Message-ID: <20180724114515.21764-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> References: <20180724114515.21764-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds support for MSI based counter overflow interrupt. Signed-off-by: Shameer Kolothum --- drivers/perf/arm_smmuv3_pmu.c | 105 +++++++++++++++++++++++++++++++++--------- 1 file changed, 84 insertions(+), 21 deletions(-) -- 2.7.4 diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index b3dc394..ca69813 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -94,6 +94,10 @@ #define SMMU_PMCG_IRQ_CFG2 0xE64 #define SMMU_PMCG_IRQ_STATUS 0xE68 +/* MSI config fields */ +#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) +#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1 + #define SMMU_COUNTER_RELOAD BIT(31) #define SMMU_DEFAULT_FILTER_SEC 0 #define SMMU_DEFAULT_FILTER_SPAN 1 @@ -657,14 +661,89 @@ static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data) return IRQ_HANDLED; } +static void smmu_pmu_free_msis(void *data) +{ + struct device *dev = data; + + platform_msi_domain_free_irqs(dev); +} + +static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + phys_addr_t doorbell; + struct device *dev = msi_desc_to_dev(desc); + struct smmu_pmu *pmu = dev_get_drvdata(dev); + + doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; + doorbell &= MSI_CFG0_ADDR_MASK; + + writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1); + writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE, + pmu->reg_base + SMMU_PMCG_IRQ_CFG2); +} + +static void smmu_pmu_setup_msi(struct smmu_pmu *pmu) +{ + struct msi_desc *desc; + struct device *dev = pmu->dev; + int ret; + + /* Clear MSI address reg */ + writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); + + /* MSI supported or not */ + if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) + return; + + ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); + if (ret) { + dev_warn(dev, "failed to allocate MSIs\n"); + return; + } + + desc = first_msi_entry(dev); + if (desc) + pmu->irq = desc->irq; + + /* Add callback to free MSIs on teardown */ + devm_add_action(dev, smmu_pmu_free_msis, dev); +} + +static int smmu_pmu_setup_irq(struct smmu_pmu *pmu) +{ + int irq, ret = -ENXIO; + + smmu_pmu_setup_msi(pmu); + + irq = pmu->irq; + if (irq) + ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq, + IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD, + "smmu-v3-pmu", pmu); + return ret; +} + static int smmu_pmu_reset(struct smmu_pmu *smmu_pmu) { + int ret; + /* Disable counter and interrupt */ writeq(smmu_pmu->counter_present_mask, smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0); writeq(smmu_pmu->counter_present_mask, smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0); + ret = smmu_pmu_setup_irq(smmu_pmu); + if (ret) { + dev_err(smmu_pmu->dev, "failed to setup irqs\n"); + return ret; + } + + /* Pick one CPU to be the preferred one to use */ + smmu_pmu->on_cpu = smp_processor_id(); + WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu))); + smmu_pmu_disable(&smmu_pmu->pmu); return 0; } @@ -738,26 +817,8 @@ static int smmu_pmu_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(dev, "Failed to get valid irq for smmu @%pa\n", - &mem_resource_0->start); - return irq; - } - - err = devm_request_irq(dev, irq, smmu_pmu_handle_irq, - IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD, - "smmu-pmu", smmu_pmu); - if (err) { - dev_err(dev, - "Unable to request IRQ%d for SMMU PMU counters\n", irq); - return err; - } - - smmu_pmu->irq = irq; - - /* Pick one CPU to be the preferred one to use */ - smmu_pmu->on_cpu = smp_processor_id(); - WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu))); + if (irq > 0) + smmu_pmu->irq = irq; smmu_pmu->num_counters = get_num_counters(smmu_pmu); smmu_pmu->counter_present_mask = GENMASK(smmu_pmu->num_counters - 1, 0); @@ -765,7 +826,9 @@ static int smmu_pmu_probe(struct platform_device *pdev) SMMU_PMCG_CFGR_SIZE_MASK) >> SMMU_PMCG_CFGR_SIZE_SHIFT; smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0); - smmu_pmu_reset(smmu_pmu); + err = smmu_pmu_reset(smmu_pmu); + if (err) + return err; err = cpuhp_state_add_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);