From patchwork Tue Jun 8 22:34:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 456228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4ED64C48BCD for ; Tue, 8 Jun 2021 22:38:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33E6B60551 for ; Tue, 8 Jun 2021 22:38:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235260AbhFHWkn (ORCPT ); Tue, 8 Jun 2021 18:40:43 -0400 Received: from mail-qv1-f53.google.com ([209.85.219.53]:39445 "EHLO mail-qv1-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235258AbhFHWkl (ORCPT ); Tue, 8 Jun 2021 18:40:41 -0400 Received: by mail-qv1-f53.google.com with SMTP id u14so8861694qvq.6 for ; Tue, 08 Jun 2021 15:38:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6eqeLtF2wYve+NaCkqrhAPj7GJ7t1Uc8cbMldYDNzmc=; b=Mv8h0zAZa85cNE9rseThVvwjyYB9knu4rn7uHCkg2DyvdR4N0DgMPfSC2MUZIYsKXq cwsYs8ghRN5iRdKbbAZQmYUAiu3UXsL4BY3APai3695aXktzGG5oQfiBGIbf9hgRvrmW 8bnAlUTjlJXWUuvdx2cptBdIF5bbC1FqYf1xX3iHnONXVoqf8mZZjMtRt8eTQ941Duuu mv42q6l9VQHPJqewCJrXtPwf9tzC2UotMDKdaWLxCLiFPRhMVaVfqKx04WucLHRZfDxP TClns7nQ0HIREF6HZAqaRSkgPzzZZocB6Novk0/M+jD2A986HTM2cwjBlUax+mNw+4Ib kPkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6eqeLtF2wYve+NaCkqrhAPj7GJ7t1Uc8cbMldYDNzmc=; b=i0JB8FAzQ0dkD3dWQSHLPwCacP+HlrY9kgaJ+0b2yAboQnArM8ykSfPHG5HKUsFqCI VG+0cSFi4cjaSaYMxGnSXaFq30H1IZyuDsQgi2MpLG2KWU2lF6fi7X4jncA1ZrywKstQ 0rmXwRH/nQt/LZvX/Yj0S8Q8LzzNjA79EuxWW8agJNse/Zo3yqO6AOB2gTGIf4itt9eq /6QtLBf2CCQtew/h2tQsr1hukyu4AadwVIqTWulawbS6YrkW+hyW/wU8PEusw0IKfv5f sVfrrXACZ+3HfbN5q9JxyIuE2R2iYQid+ePC/Vppb+IW7BjnvCcz1YrkxSBJPt2gDkiO Ys9w== X-Gm-Message-State: AOAM531oBCR+IBqz7IdOS9ovVZ1idyBCur2BTaQ5GJ0dvW5Wz+EYvY+J 1sBRC90Jr6Yvz2qVBtyRsNxJiQ== X-Google-Smtp-Source: ABdhPJw1o4lhprHmGw2h3aqoKr10f1XTAfu6jpNt/PApK8tndgV3l+To+BXpyX2phwJl+Iz4K+IdJQ== X-Received: by 2002:a0c:c3d1:: with SMTP id p17mr2654124qvi.44.1623191867886; Tue, 08 Jun 2021 15:37:47 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id m3sm2324266qkh.135.2021.06.08.15.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:37:45 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: robert.foss@linaro.org, andrey.konovalov@linaro.org, Todor Tomov , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , linux-media@vger.kernel.org (open list:QUALCOMM CAMERA SUBSYSTEM DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 02/17] media: camss: csiphy-3ph: disable interrupts Date: Tue, 8 Jun 2021 18:34:51 -0400 Message-Id: <20210608223513.23193-3-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210608223513.23193-1-jonathan@marek.ca> References: <20210608223513.23193-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The driver does nothing with the interrupts, so set the irq mask registers to zero to avoid wasting CPU time for nothing. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 35 ++----------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 5948abdcd2206..783b65295d20b 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -352,38 +352,9 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, else if (csiphy->camss->version == CAMSS_845) csiphy_gen2_config_lanes(csiphy, settle_cnt); - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11)); - - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12)); - - val = 0xfb; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13)); - - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14)); - - val = 0x7f; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15)); - - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16)); - - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17)); - - val = 0xef; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18)); - - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19)); - - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20)); - - val = 0xff; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21)); + /* IRQ_MASK registers - disable all interrupts */ + for (i = 11; i < 22; i++) + writel_relaxed(0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i)); } static void csiphy_lanes_disable(struct csiphy_device *csiphy, From patchwork Tue Jun 8 22:34:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 456226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14650C4743D for ; Tue, 8 Jun 2021 22:39:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 042BB6135D for ; Tue, 8 Jun 2021 22:39:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235423AbhFHWlE (ORCPT ); Tue, 8 Jun 2021 18:41:04 -0400 Received: from mail-qv1-f44.google.com ([209.85.219.44]:45635 "EHLO mail-qv1-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235335AbhFHWky (ORCPT ); Tue, 8 Jun 2021 18:40:54 -0400 Received: by mail-qv1-f44.google.com with SMTP id g12so11737215qvx.12 for ; Tue, 08 Jun 2021 15:38:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h7Ze/0FZcrCZ8/ohSgsWEa3JmZJ0LCpIBTZQMUOgUhU=; b=eamqO/u0HsdTmoA2C+587eGJ/oIlmXzpEBuM4yEYfeq/+5KIr54POJmXjSNQihc0xo FvRcPA7xjYbdstnOkPYSq+ZSg9Zhn9JuBwifgaM99JZHmXVwL/flBt9Hwh/lp53Nz4PE kbmslmWXvmuMZyLYqzCphXQ8ZJoHDNvk5r+QFfE7D1uI7gPntADS6j+Qn4VRJomaG6ZP AqAtOtq1sOEX4vvZzCCMyYP5YHK3INw/4z01UGpgpgetwUjZL5wtj3cgERYHJs3aS4a1 5w33tilvCQwscRsrHM2Qk8TxLfow0LAKbVE0R0ZKqpNE+hLDbpIoM2YEHdtsS2mq+A47 JOsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h7Ze/0FZcrCZ8/ohSgsWEa3JmZJ0LCpIBTZQMUOgUhU=; b=a+m/PMN+7NQ673Vpm0mBBYb5wVwGWt5+KzNqqKJS934gMmHXoF/xHrv7QputpgqHEo 9uqZERIrruwAIpoMSDdwS4ZhiyeTkkk2xJX71Mh422hAWHbqrVfesVhCRDTZBqIChxDq Ekd0faAMLRgOoIjEmzwdBaoV1t1ZnUrb/FxWw4/+4jI6qPbYdoOMy3/lGrr2bdl0XzQ3 xv2rinMh5mh72etyhub8kuTfvDlGTQWSc3+sho+MkiVO7smihCIahxGfN5Sk4PNRubjJ pBoPGf7unnHM+RF17H9qtzl83h7aed9d3T+dmmkx9HzKM3FY8QYhCs/ifu+13e4b8rSk RHfQ== X-Gm-Message-State: AOAM531Qc0kO2+Fm/TMnU4K1XYDpTafCRKkThjqRsLz3DenhCLlWGakO uOA8KwNX55j5MteKt3J3cn8UcQ== X-Google-Smtp-Source: ABdhPJzDHkTFsvO+r15hgBa0ALf0Crvy2Ll+TqLfx+jjBK9zYG3L2pU67agXtLjgoW5GtSl4ohzU6A== X-Received: by 2002:a05:6214:240b:: with SMTP id fv11mr2695139qvb.23.1623191869113; Tue, 08 Jun 2021 15:37:49 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id m3sm2324266qkh.135.2021.06.08.15.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:37:48 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: robert.foss@linaro.org, andrey.konovalov@linaro.org, Todor Tomov , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , linux-media@vger.kernel.org (open list:QUALCOMM CAMERA SUBSYSTEM DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 03/17] media: camss: csiphy-3ph: add support for SM8250 CSI DPHY Date: Tue, 8 Jun 2021 18:34:52 -0400 Message-Id: <20210608223513.23193-4-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210608223513.23193-1-jonathan@marek.ca> References: <20210608223513.23193-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for CSIPHY (2PH/DPHY mode) found on SM8250 hardware. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 147 ++++++++++++++++-- drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 139 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 783b65295d20b..c5b0a91b36f88 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -62,6 +62,7 @@ struct csiphy_reg_t { u32 csiphy_param_type; }; +/* GEN2 1.0 2PH */ static const struct csiphy_reg_t lane_regs_sdm845[5][14] = { { @@ -146,6 +147,121 @@ csiphy_reg_t lane_regs_sdm845[5][14] = { }, }; +/* GEN2 1.2.1 2PH */ +static const struct +csiphy_reg_t lane_regs_sm8250[5][20] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, +}; + static void csiphy_hw_version_read(struct csiphy_device *csiphy, struct device *dev) { @@ -298,13 +414,25 @@ static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy, static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u8 settle_cnt) { - int i, l; + const struct csiphy_reg_t *r; + int i, l, array_size; u32 val; - for (l = 0; l < 5; l++) { - for (i = 0; i < 14; i++) { - const struct csiphy_reg_t *r = &lane_regs_sdm845[l][i]; + switch (csiphy->camss->version) { + case CAMSS_845: + r = &lane_regs_sdm845[0][0]; + array_size = ARRAY_SIZE(lane_regs_sdm845[0]); + break; + case CAMSS_8250: + r = &lane_regs_sm8250[0][0]; + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); + break; + default: + unreachable(); + } + for (l = 0; l < 5; l++) { + for (i = 0; i < array_size; i++, r++) { switch (r->csiphy_param_type) { case CSIPHY_SETTLE_CNT_LOWER_BYTE: val = settle_cnt & 0xff; @@ -325,13 +453,15 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; + bool is_gen2 = (csiphy->camss->version == CAMSS_845 || + csiphy->camss->version == CAMSS_8250); u8 settle_cnt; u8 val; int i; settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); - val = BIT(c->clk.pos); + val = is_gen2 ? BIT(7) : BIT(c->clk.pos); for (i = 0; i < c->num_data; i++) val |= BIT(c->data[i].pos * 2); @@ -346,11 +476,10 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, val = 0x00; writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); - if (csiphy->camss->version == CAMSS_8x16 || - csiphy->camss->version == CAMSS_8x96) - csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); - else if (csiphy->camss->version == CAMSS_845) + if (is_gen2) csiphy_gen2_config_lanes(csiphy, settle_cnt); + else + csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); /* IRQ_MASK registers - disable all interrupts */ for (i = 11; i < 22; i++) diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index dc8b4154f92b3..377e2474a485f 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -69,6 +69,7 @@ enum camss_version { CAMSS_8x96, CAMSS_660, CAMSS_845, + CAMSS_8250, }; struct camss { From patchwork Tue Jun 8 22:34:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 456232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55C64C48BCD for ; Tue, 8 Jun 2021 22:37:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 412BA61351 for ; Tue, 8 Jun 2021 22:37:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235070AbhFHWjr (ORCPT ); Tue, 8 Jun 2021 18:39:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234228AbhFHWjp (ORCPT ); Tue, 8 Jun 2021 18:39:45 -0400 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38B9CC0617A6 for ; Tue, 8 Jun 2021 15:37:51 -0700 (PDT) Received: by mail-qk1-x730.google.com with SMTP id k4so21968640qkd.0 for ; Tue, 08 Jun 2021 15:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pBISRGXcYaTjdyy7zFRwXRZ/Xqtc0LVrOOtyDwss3eg=; b=02f0lZJ5PP3Eiylz/zR/mouRFgBT9n4kVgKwIm5HemxQLen0zBBwqlvzZ7tt3c6jdk 44M3xC65Ss+GGObi0v41j7qIMTbZ4ofRsUSfE6ORIYiC9iSURdabjKZ1ZXSwWRnyw+UE JHdTPrpKfY2MjFPD0aAc3W4tv6gV6uX+WG0nImNQiX51ak7LRj2Dn9ljPVn31qZtacNw DButh6ySOFQlQ/OecgdHyt6HT9kZP+OM5ofR/oIGYd3pk4jCXo9+hSVdI/jX7UsGmPiP FSH4yLiy0wAAJD9Mj37rd2MUFFtyjJSMPMTf6vi4C237AcEHtXTfMeBX8cLEyy5kWG5U kFwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pBISRGXcYaTjdyy7zFRwXRZ/Xqtc0LVrOOtyDwss3eg=; b=hqKcq+AZegz/tphaEhii43odgrrPzfJnFtPUD08wvXyOomJcaYXfotceJILBS3T4A4 UGV780PmVaksh6nHcLU3IeRdE/R6LuCx/8xYn28SZpGoyUQxJOnT4R8CpPZ3HULSkEQ5 nKLepuY4KG9DN+M+0WKLfyiepFRcde//Xe1mquutdrHPVlOCFTCCpR7zDRLdP2Q/u/Ru uwnIygV3th3IMvN6De8BdqWXw++Soky0ACDjuv/G3rguGIj7ehV9JtjM425UKS/E6+7k Olxr1bF+Utz7/SkUvVMkIhwfo4YCttQOjmZaEpemWMeZzRZZClzCN+zGxp7faNYivopi sWlw== X-Gm-Message-State: AOAM532WsIL0+pqe3586w6MFsfl2F4h/xDmaD7EbsPadXWjGmEFhPT04 f2wPYsA99YSue50GBQ7alOMrmQ== X-Google-Smtp-Source: ABdhPJzYn15uMI1dfCue0mox6oIAlMHImpKRCx4PXqnoGK4XIj1dR517BqHINIa26ujrL+u+9S1Fbw== X-Received: by 2002:a37:b3c5:: with SMTP id c188mr24031804qkf.242.1623191870438; Tue, 08 Jun 2021 15:37:50 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id m3sm2324266qkh.135.2021.06.08.15.37.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:37:49 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: robert.foss@linaro.org, andrey.konovalov@linaro.org, Todor Tomov , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , Hans Verkuil , linux-media@vger.kernel.org (open list:QUALCOMM CAMERA SUBSYSTEM DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 04/17] media: camss: csid-170: fix non-10bit formats Date: Tue, 8 Jun 2021 18:34:53 -0400 Message-Id: <20210608223513.23193-5-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210608223513.23193-1-jonathan@marek.ca> References: <20210608223513.23193-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the decode_format/data_type from the "format" struct instead of a hardcoded 10-bit format. Fixes: eebe6d00e9bf ("media: camss: Add support for CSID hardware version Titan 170") Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss --- drivers/media/platform/qcom/camss/camss-csid-170.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-170.c b/drivers/media/platform/qcom/camss/camss-csid-170.c index ac22ff29d2a9f..aa65043c33037 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-170.c +++ b/drivers/media/platform/qcom/camss/camss-csid-170.c @@ -366,7 +366,7 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) val |= input_format->width & 0x1fff << TPG_DT_n_CFG_0_FRAME_WIDTH; writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0)); - val = DATA_TYPE_RAW_10BIT << TPG_DT_n_CFG_1_DATA_TYPE; + val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE; writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0)); val = tg->mode << TPG_DT_n_CFG_2_PAYLOAD_MODE; @@ -382,8 +382,9 @@ static void csid_configure_stream(struct csid_device *csid, u8 enable) val = 1 << RDI_CFG0_BYTE_CNTR_EN; val |= 1 << RDI_CFG0_FORMAT_MEASURE_EN; val |= 1 << RDI_CFG0_TIMESTAMP_EN; + /* note: for non-RDI path, this should be format->decode_format */ val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; - val |= DATA_TYPE_RAW_10BIT << RDI_CFG0_DATA_TYPE; + val |= format->data_type << RDI_CFG0_DATA_TYPE; val |= vc << RDI_CFG0_VIRTUAL_CHANNEL; val |= dt_id << RDI_CFG0_DT_ID; writel_relaxed(val, csid->base + CSID_RDI_CFG0(0)); From patchwork Tue Jun 8 22:34:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 456227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF7C2C48BCD for ; Tue, 8 Jun 2021 22:39:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B513261351 for ; Tue, 8 Jun 2021 22:39:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235351AbhFHWkx (ORCPT ); Tue, 8 Jun 2021 18:40:53 -0400 Received: from mail-qt1-f174.google.com ([209.85.160.174]:45608 "EHLO mail-qt1-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235306AbhFHWku (ORCPT ); Tue, 8 Jun 2021 18:40:50 -0400 Received: by mail-qt1-f174.google.com with SMTP id l17so12408738qtq.12 for ; Tue, 08 Jun 2021 15:38:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MLu63O/FGB3OwQJYCj3q5EMOUKS51/xFISH4Nn/2C/8=; b=NNCx0Pc95kM1qAdnhBuhr8Qi71A0x+RgFhiiW99y4ByAqG7QJz+3TDkoj328ubWj+y ugL5/mZV567+inWIlTXxCSKZnnjVsGzlxqRz9YggP8lwOQ4sEcYw88/+NcyfmhoPyFuL LVZnmuAinEQj2DxOAO1AG2pbd9fLqHhrFHd858l03w94qRVZxgeBXfITet8wxfibqadb nywBSrOMKgEhhDaZpl+FilYr8AZxdIyILYsYrDAjcXH8UlxT4EFXSWmQr9xCzGj6Dtq9 qTgBEsxIjXD8bJOTx74UatsFsB7jRoo+nR7MbLsU9eRL9sI4UyyxJp74G3+rlGRf+Km/ eSFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MLu63O/FGB3OwQJYCj3q5EMOUKS51/xFISH4Nn/2C/8=; b=DyNyLtygDnnkp3yR99FJtlQAM39ndtojAHDGVvPG5JLPcBgAKv+PCvJa/lyj2vloTg imZtmEQrMwB1m83DrK7chC3j3tdRKZ3ipxrc52UYFpX/HZ09IpL/b383Y6IWpamu6CoK soLGzy0XFq4cmUUQBUbDjE3RJEO/hPViGQuOaCWl2gkOMCv7i7f5o9brHsMP8h2rN2ef xwDC5u7gNIbTVbqN9ZVGXZNysGYwe8hl6agPmviyHsVsGSp9OBRxJDQMboP6TB4yqUS8 TVtEDnaiw5wy8/3KWyFxxNc9aU9a9pcViC8CrUqNGC54uvzhK3HQUrKxrgYOqZ097Ikd PUbA== X-Gm-Message-State: AOAM532AwxSPbTzouw1jOdyHMzM5dK109URDKLluwMXp8VP/wgN2d12A 54uoEcByIoqJKr8xliRKSvkqRimzKGcjp0HcCR0bqw== X-Google-Smtp-Source: ABdhPJxqi6iboRcr63hnvz7UyaJR2v9uH5MlRCqu/2mTBGBMLzPY/mDRaMIk8k3lE8sifG4JsZy/TA== X-Received: by 2002:ac8:580b:: with SMTP id g11mr23488425qtg.244.1623191876554; Tue, 08 Jun 2021 15:37:56 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id m3sm2324266qkh.135.2021.06.08.15.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:37:56 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: robert.foss@linaro.org, andrey.konovalov@linaro.org, Todor Tomov , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , linux-media@vger.kernel.org (open list:QUALCOMM CAMERA SUBSYSTEM DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 09/17] media: camss: csid: allow csid to work without a regulator Date: Tue, 8 Jun 2021 18:34:58 -0400 Message-Id: <20210608223513.23193-10-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210608223513.23193-1-jonathan@marek.ca> References: <20210608223513.23193-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org At least for titan HW, CSID don't have an associated regulator. This change is necessary to be able to model this in the CSID resources. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss --- drivers/media/platform/qcom/camss/camss-csid.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index cc11fbfdae132..528674dea06ca 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -162,7 +162,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) return ret; } - ret = regulator_enable(csid->vdda); + ret = csid->vdda ? regulator_enable(csid->vdda) : 0; if (ret < 0) { pm_runtime_put_sync(dev); return ret; @@ -170,14 +170,16 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) ret = csid_set_clock_rates(csid); if (ret < 0) { - regulator_disable(csid->vdda); + if (csid->vdda) + regulator_disable(csid->vdda); pm_runtime_put_sync(dev); return ret; } ret = camss_enable_clocks(csid->nclocks, csid->clock, dev); if (ret < 0) { - regulator_disable(csid->vdda); + if (csid->vdda) + regulator_disable(csid->vdda); pm_runtime_put_sync(dev); return ret; } @@ -188,7 +190,8 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) if (ret < 0) { disable_irq(csid->irq); camss_disable_clocks(csid->nclocks, csid->clock); - regulator_disable(csid->vdda); + if (csid->vdda) + regulator_disable(csid->vdda); pm_runtime_put_sync(dev); return ret; } @@ -197,7 +200,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) } else { disable_irq(csid->irq); camss_disable_clocks(csid->nclocks, csid->clock); - ret = regulator_disable(csid->vdda); + ret = csid->vdda ? regulator_disable(csid->vdda) : 0; pm_runtime_put_sync(dev); } @@ -634,7 +637,9 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, /* Regulator */ - csid->vdda = devm_regulator_get(dev, res->regulator[0]); + csid->vdda = NULL; + if (res->regulator[0]) + csid->vdda = devm_regulator_get(dev, res->regulator[0]); if (IS_ERR(csid->vdda)) { dev_err(dev, "could not get regulator\n"); return PTR_ERR(csid->vdda); From patchwork Tue Jun 8 22:34:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 456229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF0D6C4743F for ; Tue, 8 Jun 2021 22:38:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C84DA6135D for ; Tue, 8 Jun 2021 22:38:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235196AbhFHWkM (ORCPT ); Tue, 8 Jun 2021 18:40:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234915AbhFHWkI (ORCPT ); Tue, 8 Jun 2021 18:40:08 -0400 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CAA5C0617A8 for ; Tue, 8 Jun 2021 15:37:58 -0700 (PDT) Received: by mail-qk1-x733.google.com with SMTP id j189so21955722qkf.2 for ; Tue, 08 Jun 2021 15:37:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZIQt2jCiu8UQ3tm03+YZTLApMSATbTz4nD1zztWDgOQ=; b=qFD9+dYXxnHJRQggT3QcQ/+nrZgr/vhVcXpz1xKDiACbl+FQ3UtSQPQNWA99ebE4cG jvIG3k8cg1xNDk8Be7Gi010k7KRLfaj1RvY0D0R1UUI6K8t4nS6mzJp8oD6UlvGkGibi KB3PdjvRlVaZlRBm1X+tUMRUH55JdW1h/0prncQOe6/oLUyZaQz2YOxAQFJ9RUcb7+KQ AX68gwlxDBal0X9i1gu9NzMlRTYhJT+pbe5lgeAlVhUL/ZPd/MIJYiPnPBriFIMomMJU sPCBR/reUkUUFP8p+znm1LQbJzsRaOVvMPYmaRL8C3VWEplfCdBLlbF8taUXUrtus1OQ RXdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZIQt2jCiu8UQ3tm03+YZTLApMSATbTz4nD1zztWDgOQ=; b=HWlDZ9x06MLH8CEYt+TkLREseC+Vvtbg8kcQvO5hgdG7JXR/tYSXDmUhCUKbOU87rH o8hTFSgW3uKYeWL2l82cMy74MQqnI/SyfAm78xxKskwCNBeKasHDiOUKtM0lYTyKi+La 6sv4l+LmMcsHWDekvPvBb9fUEDg1Np6uxsL82flbUvJM9iyNQ3k2Waa2HD4cu0jvWetj ZCYJgYusf1TVreAwtJlSKDjX0ggKnJWhu58uC5HzDJU+KCUknRtBlTolHTftpxTd9Ks/ 3UIPFxBSQIrr8eCZeL/UtSSlfw7vst0ompaE6kVstNQcYTXTj1v6xp0oWxzvwccow4aZ AMLQ== X-Gm-Message-State: AOAM532m6lZWCEtV0tiUp+08Xkv0Eu6CTQ6ObiHQKr49tnb/SQ30rd4K u+3RQfigA8wuKm50cRwbgdhAyg== X-Google-Smtp-Source: ABdhPJzxpS1UIUw7jyGvjpk0uHBt5n9wjOEIm712XMpbWA+7rKbWITYsJFp9O5jKv2MzZpu+3XH2GA== X-Received: by 2002:a37:8b47:: with SMTP id n68mr23337235qkd.209.1623191877747; Tue, 08 Jun 2021 15:37:57 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id m3sm2324266qkh.135.2021.06.08.15.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:37:57 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: robert.foss@linaro.org, andrey.konovalov@linaro.org, Todor Tomov , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , linux-media@vger.kernel.org (open list:QUALCOMM CAMERA SUBSYSTEM DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 10/17] media: camss: remove vdda-csiN from sdm845 resources Date: Tue, 8 Jun 2021 18:34:59 -0400 Message-Id: <20210608223513.23193-11-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210608223513.23193-1-jonathan@marek.ca> References: <20210608223513.23193-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This isn't used and only works because devm_regulator_get() returns a dummy regulator. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss --- drivers/media/platform/qcom/camss/camss.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index ef100d5f77636..c08d6d6f6f90d 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -542,7 +542,7 @@ static const struct resources csiphy_res_845[] = { static const struct resources csid_res_845[] = { /* CSID0 */ { - .regulator = { "vdda-csi0" }, + .regulator = { NULL }, .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe0", "vfe0_src", "vfe0_cphy_rx", "csi0", @@ -562,7 +562,7 @@ static const struct resources csid_res_845[] = { /* CSID1 */ { - .regulator = { "vdda-csi1" }, + .regulator = { NULL }, .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe1", "vfe1_src", "vfe1_cphy_rx", "csi1", @@ -582,7 +582,7 @@ static const struct resources csid_res_845[] = { /* CSID2 */ { - .regulator = { "vdda-csi2" }, + .regulator = { NULL }, .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe_lite", "vfe_lite_src", "vfe_lite_cphy_rx", "csi2", From patchwork Tue Jun 8 22:35:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 456225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9884C4743F for ; Tue, 8 Jun 2021 22:39:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8CAC961351 for ; Tue, 8 Jun 2021 22:39:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235553AbhFHWlX (ORCPT ); Tue, 8 Jun 2021 18:41:23 -0400 Received: from mail-qk1-f178.google.com ([209.85.222.178]:44679 "EHLO mail-qk1-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235466AbhFHWlK (ORCPT ); Tue, 8 Jun 2021 18:41:10 -0400 Received: by mail-qk1-f178.google.com with SMTP id c18so6825568qkc.11 for ; Tue, 08 Jun 2021 15:39:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WlBPGjiShiO5vfWZbC7KLleHizVDyP7QnDJ5l2ylDCs=; b=KDdwSHTmEoIii9B1U7cHc99/8eKEilpM7aor/MrKzsYRDz8b7EdyPVdW/mtJBjMwJW b/lKtUFSEQeJXqy1qXEESeBtuWBPcySq0sU9FNakJYAX29dz/7q41Sf+JgFDrO1HpUMa +bc8zhm1L5rj9zF4GhMOlTDGfA5RWTgZHYd1U2y5S/kS7h9GKa2XV7vwPjlc2Ttu2cRZ 9ovBasSPSePsDeQgTeO65yACJObPMakupBevibqPrFGqOlBtquIqas+8v1ZP92OpLl4H bDUhfxykuUSPPO2aPuTcbZyAB4e6YgwaO9CyZ8gy/46E2WBbCmrDjXkK8UbEKDKhbsP9 vRvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WlBPGjiShiO5vfWZbC7KLleHizVDyP7QnDJ5l2ylDCs=; b=U+Ku+LXsdVKIrfqLrSBlmQ6Qa4BSFQMV9X/jsw7keZvs1QLGunbXhXDH9fBRz9GFpS 301xtFcIh2bqO1BfAwhla7F+SN+WoFgdI78qASJpeIdAEF75asgEvIGZ3AUKhJjROkO/ WuI5gxBnSpVkKGam98v1fP5XC6owVZQX2QVk0/mIF5/C/9w8Bbm4SRdv+XWHG+sIwbZa GFIdHA/1WDXQO2yz3BQ0IWzZd7QinZlgHx1VGt2pBjbI06LJERNARO/ufYNNdNOtoisw 7iZB8uYZE+5RvnDazSIb0iUMTIw5nt8mc3PBS6yoH+3eDmep0RVEqzkde4ZTHDga1tXr EWFg== X-Gm-Message-State: AOAM533QipR+m5GiN2kB2yW3yWtA80/472s8rp6BNt52wvfrmRD17aOo pNoO6Rb0ZJMuEs9MlbNMda0WPA== X-Google-Smtp-Source: ABdhPJzKiflWQGJ8wqd7z+8aiHAuGCAAktlzmc2Nn2ztRmtC3jPoCoFdtbBEa6GqjLjYdNbA7iRT3Q== X-Received: by 2002:a37:a0d:: with SMTP id 13mr12692417qkk.47.1623191884166; Tue, 08 Jun 2021 15:38:04 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id m3sm2324266qkh.135.2021.06.08.15.38.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:38:03 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: robert.foss@linaro.org, andrey.konovalov@linaro.org, Todor Tomov , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , linux-kernel@vger.kernel.org (open list), linux-media@vger.kernel.org (open list:QUALCOMM CAMERA SUBSYSTEM DRIVER) Subject: [PATCH 14/17] media: camss: Add initial support for VFE hardware version Titan 480 Date: Tue, 8 Jun 2021 18:35:03 -0400 Message-Id: <20210608223513.23193-15-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210608223513.23193-1-jonathan@marek.ca> References: <20210608223513.23193-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for VFE found on SM8250 (Titan 480). This implementation is based on the titan 170 implementation. It supports the normal and lite VFE, and only supports the RDI0 capture path. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-vfe-480.c | 545 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss-vfe.h | 1 + 3 files changed, 547 insertions(+) create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-480.c diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 0752c46ea37b5..81dd56aff0f27 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -15,6 +15,7 @@ qcom-camss-objs += \ camss-vfe-4-7.o \ camss-vfe-4-8.o \ camss-vfe-170.o \ + camss-vfe-480.o \ camss-vfe-gen1.o \ camss-vfe.o \ camss-video.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-480.c b/drivers/media/platform/qcom/camss/camss-vfe-480.c new file mode 100644 index 0000000000000..6e6a4caee0a96 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-480.c @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-vfe-480.c + * + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v480 (SM8250) + * + * Copyright (C) 2020-2021 Linaro Ltd. + * Copyright (C) 2021 Jonathan Marek + */ + +#include +#include +#include +#include + +#include "camss.h" +#include "camss-vfe.h" + +/* VFE 2/3 are lite and have a different register layout */ +#define IS_LITE (vfe->id >= 2 ? 1 : 0) + +#define VFE_HW_VERSION (0x00) + +#define VFE_GLOBAL_RESET_CMD (IS_LITE ? 0x0c : 0x1c) +#define GLOBAL_RESET_HW_AND_REG (IS_LITE ? BIT(1) : BIT(0)) + +#define VFE_REG_UPDATE_CMD (IS_LITE ? 0x20 : 0x34) +#define REG_UPDATE_RDI(n) (IS_LITE ? BIT(n) : BIT(1 + (n))) +#define VFE_IRQ_CMD (IS_LITE ? 0x24 : 0x38) +#define IRQ_CMD_GLOBAL_CLEAR BIT(0) + +#define VFE_IRQ_MASK(n) ((IS_LITE ? 0x28 : 0x3c) + (n) * 4) +#define IRQ_MASK_0_RESET_ACK (IS_LITE ? BIT(17) : BIT(0)) +#define IRQ_MASK_0_BUS_TOP_IRQ (IS_LITE ? BIT(4) : BIT(7)) +#define VFE_IRQ_CLEAR(n) ((IS_LITE ? 0x34 : 0x48) + (n) * 4) +#define VFE_IRQ_STATUS(n) ((IS_LITE ? 0x40 : 0x54) + (n) * 4) + +#define BUS_REG_BASE (IS_LITE ? 0x1a00 : 0xaa00) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x3FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xdc) + +#define VFE_BUS_IRQ_MASK(n) (BUS_REG_BASE + 0x18 + (n) * 4) +#define BUS_IRQ_MASK_0_RDI_RUP(n) (IS_LITE ? BIT(n) : BIT(3 + (n))) +#define BUS_IRQ_MASK_0_COMP_DONE(n) (IS_LITE ? BIT(4 + (n)) : BIT(6 + (n))) +#define VFE_BUS_IRQ_CLEAR(n) (BUS_REG_BASE + 0x20 + (n) * 4) +#define VFE_BUS_IRQ_STATUS(n) (BUS_REG_BASE + 0x28 + (n) * 4) +#define VFE_BUS_IRQ_CLEAR_GLOBAL (BUS_REG_BASE + 0x30) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) +#define WM_CFG_EN (0) +#define WM_CFG_MODE (16) +#define MODE_QCOM_PLAIN (0) +#define MODE_MIPI_RAW (1) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_1(n) (BUS_REG_BASE + 0x210 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) +#define VFE_BUS_WM_HEADER_ADDR(n) (BUS_REG_BASE + 0x220 + (n) * 0x100) +#define VFE_BUS_WM_HEADER_INCR(n) (BUS_REG_BASE + 0x224 + (n) * 0x100) +#define VFE_BUS_WM_HEADER_CFG(n) (BUS_REG_BASE + 0x228 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) + +#define VFE_BUS_WM_SYSTEM_CACHE_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) +#define VFE_BUS_WM_BURST_LIMIT(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) + +/* for titan 480, each bus client is hardcoded to a specific path + * and each bus client is part of a hardcoded "comp group" + */ +#define RDI_WM(n) ((IS_LITE ? 0 : 23) + (n)) +#define RDI_COMP_GROUP(n) ((IS_LITE ? 0 : 11) + (n)) + +static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) +{ + u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION); + + u32 gen = (hw_version >> 28) & 0xF; + u32 rev = (hw_version >> 16) & 0xFFF; + u32 step = hw_version & 0xFFFF; + + dev_dbg(dev, "VFE HW Version = %u.%u.%u\n", gen, rev, step); +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0)); + writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD); +} + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) +{ + struct v4l2_pix_format_mplane *pix = + &line->video_out.active_fmt.fmt.pix_mp; + + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ + + /* no clock gating at bus input */ + writel_relaxed(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + + writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel_relaxed(pix->plane_fmt[0].bytesperline * pix->height, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); + writel_relaxed(WM_IMAGE_CFG_0_DEFAULT_WIDTH, + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel_relaxed(pix->plane_fmt[0].bytesperline, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + writel_relaxed(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* no dropped frames, one irq per frame */ + writel_relaxed(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel_relaxed(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + writel_relaxed(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel_relaxed(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE, + vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ + writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ + writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) +{ + vfe->reg_update |= REG_UPDATE_RDI(line_id); + writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + vfe->reg_update &= ~REG_UPDATE_RDI(line_id); +} + +static void vfe_enable_irq_common(struct vfe_device *vfe) +{ + /* enable only the IRQs used: rup and comp_done irqs for RDI0 */ + writel_relaxed(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ, + vfe->base + VFE_IRQ_MASK(0)); + writel_relaxed(BUS_IRQ_MASK_0_RDI_RUP(0) | BUS_IRQ_MASK_0_COMP_DONE(RDI_COMP_GROUP(0)), + vfe->base + VFE_BUS_IRQ_MASK(0)); +} + +static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id); +static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm); + +/* + * vfe_isr - VFE module interrupt handler + * @irq: Interrupt line + * @dev: VFE device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t vfe_isr(int irq, void *dev) +{ + struct vfe_device *vfe = dev; + u32 status; + + status = readl_relaxed(vfe->base + VFE_IRQ_STATUS(0)); + writel_relaxed(status, vfe->base + VFE_IRQ_CLEAR(0)); + writel_relaxed(IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD); + + if (status & IRQ_MASK_0_RESET_ACK) + vfe_isr_reset_ack(vfe); + + if (status & IRQ_MASK_0_BUS_TOP_IRQ) { + u32 status = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(0)); + writel_relaxed(status, vfe->base + VFE_BUS_IRQ_CLEAR(0)); + writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL); + + if (status & BUS_IRQ_MASK_0_RDI_RUP(0)) + vfe_isr_reg_update(vfe, 0); + + if (status & BUS_IRQ_MASK_0_COMP_DONE(RDI_COMP_GROUP(0))) + vfe_isr_wm_done(vfe, 0); + } + + return IRQ_HANDLED; +} + +/* + * vfe_halt - Trigger halt on VFE module and wait to complete + * @vfe: VFE device + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +static int vfe_get_output(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output; + unsigned long flags; + int wm_idx; + + spin_lock_irqsave(&vfe->output_lock, flags); + + output = &line->output; + if (output->state != VFE_OUTPUT_OFF) { + dev_err(vfe->camss->dev, "Output is running\n"); + goto error; + } + + output->wm_num = 1; + + wm_idx = vfe_reserve_wm(vfe, line->id); + if (wm_idx < 0) { + dev_err(vfe->camss->dev, "Can not reserve wm\n"); + goto error_get_wm; + } + output->wm_idx[0] = wm_idx; + + output->drop_update_idx = 0; + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; + +error_get_wm: + vfe_release_wm(vfe, output->wm_idx[0]); + output->state = VFE_OUTPUT_OFF; +error: + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return -EINVAL; +} + +static int vfe_enable_output(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output = &line->output; + unsigned long flags; + unsigned int i; + + spin_lock_irqsave(&vfe->output_lock, flags); + + vfe_reg_update_clear(vfe, line->id); + + if (output->state != VFE_OUTPUT_OFF) { + dev_err(vfe->camss->dev, "Output is not in reserved state %d\n", + output->state); + spin_unlock_irqrestore(&vfe->output_lock, flags); + return -EINVAL; + } + + WARN_ON(output->gen2.active_num); + + output->state = VFE_OUTPUT_ON; + + output->sequence = 0; + output->wait_reg_update = 0; + reinit_completion(&output->reg_update); + + vfe_wm_start(vfe, output->wm_idx[0], line); + + for (i = 0; i < 2; i++) { + output->buf[i] = vfe_buf_get_pending(output); + if (!output->buf[i]) + break; + output->gen2.active_num++; + vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); + } + + vfe_reg_update(vfe, line->id); + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +static int vfe_disable_output(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output = &line->output; + unsigned long flags; + unsigned int i; + bool done; + int timeout = 0; + + do { + spin_lock_irqsave(&vfe->output_lock, flags); + done = !output->gen2.active_num; + spin_unlock_irqrestore(&vfe->output_lock, flags); + usleep_range(10000, 20000); + + if (timeout++ == 100) { + dev_err(vfe->camss->dev, "VFE idle timeout - resetting\n"); + vfe_reset(vfe); + output->gen2.active_num = 0; + return 0; + } + } while (!done); + + spin_lock_irqsave(&vfe->output_lock, flags); + for (i = 0; i < output->wm_num; i++) + vfe_wm_stop(vfe, output->wm_idx[i]); + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +/* + * vfe_enable - Enable streaming on VFE line + * @line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_enable(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + int ret; + + mutex_lock(&vfe->stream_lock); + + if (!vfe->stream_count) + vfe_enable_irq_common(vfe); + + vfe->stream_count++; + + mutex_unlock(&vfe->stream_lock); + + ret = vfe_get_output(line); + if (ret < 0) + goto error_get_output; + + ret = vfe_enable_output(line); + if (ret < 0) + goto error_enable_output; + + vfe->was_streaming = 1; + + return 0; + +error_enable_output: + vfe_put_output(line); + +error_get_output: + mutex_lock(&vfe->stream_lock); + + vfe->stream_count--; + + mutex_unlock(&vfe->stream_lock); + + return ret; +} + +/* + * vfe_disable - Disable streaming on VFE line + * @line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_disable(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + + vfe_disable_output(line); + + vfe_put_output(line); + + mutex_lock(&vfe->stream_lock); + + vfe->stream_count--; + + mutex_unlock(&vfe->stream_lock); + + return 0; +} + +/* + * vfe_isr_reg_update - Process reg update interrupt + * @vfe: VFE Device + * @line_id: VFE line + */ +static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) +{ + struct vfe_output *output; + unsigned long flags; + + spin_lock_irqsave(&vfe->output_lock, flags); + vfe_reg_update_clear(vfe, line_id); + + output = &vfe->line[line_id].output; + + if (output->wait_reg_update) { + output->wait_reg_update = 0; + complete(&output->reg_update); + } + + spin_unlock_irqrestore(&vfe->output_lock, flags); +} + +/* + * vfe_isr_wm_done - Process write master done interrupt + * @vfe: VFE Device + * @wm: Write master id + */ +static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) +{ + struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]]; + struct camss_buffer *ready_buf; + struct vfe_output *output; + unsigned long flags; + u32 index; + u64 ts = ktime_get_ns(); + + spin_lock_irqsave(&vfe->output_lock, flags); + + if (vfe->wm_output_map[wm] == VFE_LINE_NONE) { + dev_err_ratelimited(vfe->camss->dev, + "Received wm done for unmapped index\n"); + goto out_unlock; + } + output = &vfe->line[vfe->wm_output_map[wm]].output; + + ready_buf = output->buf[0]; + if (!ready_buf) { + dev_err_ratelimited(vfe->camss->dev, + "Missing ready buf %d!\n", output->state); + goto out_unlock; + } + + ready_buf->vb.vb2_buf.timestamp = ts; + ready_buf->vb.sequence = output->sequence++; + + index = 0; + output->buf[0] = output->buf[1]; + if (output->buf[0]) + index = 1; + + output->buf[index] = vfe_buf_get_pending(output); + + if (output->buf[index]) + vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line); + else + output->gen2.active_num--; + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + return; + +out_unlock: + spin_unlock_irqrestore(&vfe->output_lock, flags); +} + +/* + * vfe_pm_domain_off - Disable power domains specific to this VFE. + * @vfe: VFE Device + */ +static void vfe_pm_domain_off(struct vfe_device *vfe) +{ + /* nop */ +} + +/* + * vfe_pm_domain_on - Enable power domains specific to this VFE. + * @vfe: VFE Device + */ +static int vfe_pm_domain_on(struct vfe_device *vfe) +{ + return 0; +} + +/* + * vfe_queue_buffer - Add empty buffer + * @vid: Video device structure + * @buf: Buffer to be enqueued + * + * Add an empty buffer - depending on the current number of buffers it will be + * put in pending buffer queue or directly given to the hardware to be filled. + * + * Return 0 on success or a negative error code otherwise + */ +static int vfe_queue_buffer(struct camss_video *vid, + struct camss_buffer *buf) +{ + struct vfe_line *line = container_of(vid, struct vfe_line, video_out); + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output; + unsigned long flags; + + output = &line->output; + + spin_lock_irqsave(&vfe->output_lock, flags); + + if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) { + output->buf[output->gen2.active_num++] = buf; + vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line); + } else { + vfe_buf_add_pending(output, buf); + } + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +static const struct camss_video_ops vfe_video_ops_480 = { + .queue_buffer = vfe_queue_buffer, + .flush_buffers = vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops = vfe_video_ops_480; + vfe->line_num = 1; +} + +const struct vfe_hw_ops vfe_ops_480 = { + .global_reset = vfe_global_reset, + .hw_version_read = vfe_hw_version_read, + .isr = vfe_isr, + .pm_domain_off = vfe_pm_domain_off, + .pm_domain_on = vfe_pm_domain_on, + .subdev_init = vfe_subdev_init, + .vfe_disable = vfe_disable, + .vfe_enable = vfe_enable, + .vfe_halt = vfe_halt, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index 97a1361996308..e80b482885d4a 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -185,5 +185,6 @@ extern const struct vfe_hw_ops vfe_ops_4_1; extern const struct vfe_hw_ops vfe_ops_4_7; extern const struct vfe_hw_ops vfe_ops_4_8; extern const struct vfe_hw_ops vfe_ops_170; +extern const struct vfe_hw_ops vfe_ops_480; #endif /* QC_MSM_CAMSS_VFE_H */ From patchwork Tue Jun 8 22:35:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 456230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0E9EC4743F for ; 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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id m3sm2324266qkh.135.2021.06.08.15.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jun 2021 15:38:06 -0700 (PDT) From: Jonathan Marek To: linux-arm-msm@vger.kernel.org Cc: robert.foss@linaro.org, andrey.konovalov@linaro.org, Todor Tomov , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , linux-media@vger.kernel.org (open list:QUALCOMM CAMERA SUBSYSTEM DRIVER), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 16/17] media: camss: add support for SM8250 camss Date: Tue, 8 Jun 2021 18:35:05 -0400 Message-Id: <20210608223513.23193-17-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210608223513.23193-1-jonathan@marek.ca> References: <20210608223513.23193-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The Titan 480 camss found on SM8250 has 6 CSIPHY and 4 VFE/CSID. CSID is compatible with the Titan 170 CSID, but the Titan 480 CSID are inside the VFE region (between the "top" and "bus" registers), so a workaround is added to avoid ioremap failure. Signed-off-by: Jonathan Marek Reviewed-by: Robert Foss --- drivers/media/platform/qcom/camss/Makefile | 2 +- .../{camss-csid-170.c => camss-csid-gen2.c} | 2 +- .../media/platform/qcom/camss/camss-csid.c | 28 ++- .../media/platform/qcom/camss/camss-csid.h | 2 +- .../media/platform/qcom/camss/camss-csiphy.c | 8 +- drivers/media/platform/qcom/camss/camss-vfe.c | 9 +- .../media/platform/qcom/camss/camss-video.c | 3 +- drivers/media/platform/qcom/camss/camss.c | 199 ++++++++++++++++-- 8 files changed, 227 insertions(+), 26 deletions(-) rename drivers/media/platform/qcom/camss/{camss-csid-170.c => camss-csid-gen2.c} (99%) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 81dd56aff0f27..4e22223589739 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -6,7 +6,7 @@ qcom-camss-objs += \ camss-csid.o \ camss-csid-4-1.o \ camss-csid-4-7.o \ - camss-csid-170.o \ + camss-csid-gen2.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ camss-csiphy.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-170.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c similarity index 99% rename from drivers/media/platform/qcom/camss/camss-csid-170.c rename to drivers/media/platform/qcom/camss/camss-csid-gen2.c index 9e54d251793fc..abbfbf4488934 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-170.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -594,7 +594,7 @@ static void csid_subdev_init(struct csid_device *csid) csid->testgen.nmodes = CSID_PAYLOAD_MODE_NUM_SUPPORTED_GEN2; } -const struct csid_hw_ops csid_ops_170 = { +const struct csid_hw_ops csid_ops_gen2 = { .configure_stream = csid_configure_stream, .configure_testgen_pattern = csid_configure_testgen_pattern, .hw_version = csid_hw_version, diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 528674dea06ca..b4c068a152f73 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -25,6 +25,10 @@ #include "camss-csid-gen1.h" #include "camss.h" +/* offset of CSID registers in VFE region for VFE 480 */ +#define VFE_480_CSID_OFFSET 0x1200 +#define VFE_480_LITE_CSID_OFFSET 0x200 + #define MSM_CSID_NAME "msm_csid" const char * const csid_testgen_modes[] = { @@ -560,8 +564,9 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, } else if (camss->version == CAMSS_8x96 || camss->version == CAMSS_660) { csid->ops = &csid_ops_4_7; - } else if (camss->version == CAMSS_845) { - csid->ops = &csid_ops_170; + } else if (camss->version == CAMSS_845 || + camss->version == CAMSS_8250) { + csid->ops = &csid_ops_gen2; } else { return -EINVAL; } @@ -569,10 +574,21 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, /* Memory */ - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); - csid->base = devm_ioremap_resource(dev, r); - if (IS_ERR(csid->base)) - return PTR_ERR(csid->base); + if (camss->version == CAMSS_8250) { + /* for titan 480, CSID registers are inside the VFE region, + * between the VFE "top" and "bus" registers. this requires + * VFE to be initialized before CSID + */ + if (id >= 2) /* VFE/CSID lite */ + csid->base = camss->vfe[id].base + VFE_480_LITE_CSID_OFFSET; + else + csid->base = camss->vfe[id].base + VFE_480_CSID_OFFSET; + } else { + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); + csid->base = devm_ioremap_resource(dev, r); + if (IS_ERR(csid->base)) + return PTR_ERR(csid->base); + } /* Interrupt */ diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 814ebc7c29d65..17a50fa426be1 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -205,7 +205,7 @@ extern const char * const csid_testgen_modes[]; extern const struct csid_hw_ops csid_ops_4_1; extern const struct csid_hw_ops csid_ops_4_7; -extern const struct csid_hw_ops csid_ops_170; +extern const struct csid_hw_ops csid_ops_gen2; #endif /* QC_MSM_CAMSS_CSID_H */ diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index f82f1e2aa6883..1d10c816acf5c 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -582,7 +582,8 @@ int msm_csiphy_subdev_init(struct camss *camss, csiphy->ops = &csiphy_ops_3ph_1_0; csiphy->formats = csiphy_formats_8x96; csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96); - } else if (camss->version == CAMSS_845) { + } else if (camss->version == CAMSS_845 || + camss->version == CAMSS_8250) { csiphy->ops = &csiphy_ops_3ph_1_0; csiphy->formats = csiphy_formats_sdm845; csiphy->nformats = ARRAY_SIZE(csiphy_formats_sdm845); @@ -679,7 +680,10 @@ int msm_csiphy_subdev_init(struct camss *camss, if (!strcmp(clock->name, "csiphy0_timer") || !strcmp(clock->name, "csiphy1_timer") || - !strcmp(clock->name, "csiphy2_timer")) + !strcmp(clock->name, "csiphy2_timer") || + !strcmp(clock->name, "csiphy3_timer") || + !strcmp(clock->name, "csiphy4_timer") || + !strcmp(clock->name, "csiphy5_timer")) csiphy->rate_set[i] = true; if (camss->version == CAMSS_660 && diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index b08bded2344e6..48d05ece0dcc1 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -220,7 +220,8 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, } else if (vfe->camss->version == CAMSS_8x96 || vfe->camss->version == CAMSS_660 || - vfe->camss->version == CAMSS_845) + vfe->camss->version == CAMSS_845 || + vfe->camss->version == CAMSS_8250) switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_2X8: { @@ -1278,6 +1279,9 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, case CAMSS_845: vfe->ops = &vfe_ops_170; break; + case CAMSS_8250: + vfe->ops = &vfe_ops_480; + break; default: return -EINVAL; } @@ -1389,7 +1393,8 @@ int msm_vfe_subdev_init(struct camss *camss, struct vfe_device *vfe, l->formats = formats_rdi_8x96; l->nformats = ARRAY_SIZE(formats_rdi_8x96); } - } else if (camss->version == CAMSS_845) { + } else if (camss->version == CAMSS_845 || + camss->version == CAMSS_8250) { l->formats = formats_rdi_845; l->nformats = ARRAY_SIZE(formats_rdi_845); } else { diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c index 54e77d30d452c..5dc1ddbe6d658 100644 --- a/drivers/media/platform/qcom/camss/camss-video.c +++ b/drivers/media/platform/qcom/camss/camss-video.c @@ -1011,7 +1011,8 @@ int msm_video_register(struct camss_video *video, struct v4l2_device *v4l2_dev, video->formats = formats_rdi_8x96; video->nformats = ARRAY_SIZE(formats_rdi_8x96); } - } else if (video->camss->version == CAMSS_845) { + } else if (video->camss->version == CAMSS_845 || + video->camss->version == CAMSS_8250) { video->formats = formats_rdi_845; video->nformats = ARRAY_SIZE(formats_rdi_845); } else { diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index c08d6d6f6f90d..14a1a6e524345 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -662,6 +662,165 @@ static const struct resources vfe_res_845[] = { } }; +static const struct resources csiphy_res_8250[] = { + /* CSIPHY0 */ + { + .regulator = { NULL }, + .clock = { "csiphy0", "csiphy0_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" } + }, + /* CSIPHY1 */ + { + .regulator = { NULL }, + .clock = { "csiphy1", "csiphy1_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" } + }, + /* CSIPHY2 */ + { + .regulator = { NULL }, + .clock = { "csiphy2", "csiphy2_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" } + }, + /* CSIPHY3 */ + { + .regulator = { NULL }, + .clock = { "csiphy3", "csiphy3_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" } + }, + /* CSIPHY4 */ + { + .regulator = { NULL }, + .clock = { "csiphy4", "csiphy4_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy4" }, + .interrupt = { "csiphy4" } + }, + /* CSIPHY5 */ + { + .regulator = { NULL }, + .clock = { "csiphy5", "csiphy5_timer" }, + .clock_rate = { { 400000000 }, + { 300000000 } }, + .reg = { "csiphy5" }, + .interrupt = { "csiphy5" } + } +}; + +static const struct resources csid_res_8250[] = { + /* CSID0 */ + { + .regulator = { NULL }, + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" }, + .clock_rate = { { 400000000 }, + { 400000000 }, + { 350000000, 475000000, 576000000, 720000000 }, + { 100000000, 200000000, 300000000, 400000000 }, + { 0 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" } + }, + /* CSID1 */ + { + .regulator = { NULL }, + .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" }, + .clock_rate = { { 400000000 }, + { 400000000 }, + { 350000000, 475000000, 576000000, 720000000 }, + { 100000000, 200000000, 300000000, 400000000 }, + { 0 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" } + }, + /* CSID2 */ + { + .regulator = { NULL }, + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, + .clock_rate = { { 400000000 }, + { 400000000 }, + { 400000000, 480000000 }, + { 0 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" } + }, + /* CSID3 */ + { + .regulator = { NULL }, + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, + .clock_rate = { { 400000000 }, + { 400000000 }, + { 400000000, 480000000 }, + { 0 } }, + .reg = { "csid3" }, + .interrupt = { "csid3" } + } +}; + +static const struct resources vfe_res_8250[] = { + /* VFE0 */ + { + .regulator = { NULL }, + .clock = { "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0", "vfe0_axi", "cam_hf_axi" }, + .clock_rate = { { 400000000, 480000000 }, + { 0 }, + { 100000000, 200000000, 300000000, 400000000 }, + { 350000000, 475000000, 576000000, 720000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" } + }, + /* VFE1 */ + { + .regulator = { NULL }, + .clock = { "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1", "vfe1_axi", "cam_hf_axi" }, + .clock_rate = { { 400000000, 480000000 }, + { 0 }, + { 100000000, 200000000, 300000000, 400000000 }, + { 350000000, 475000000, 576000000, 720000000 }, + { 0 }, + { 0 } }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" } + }, + /* VFE2 (lite) */ + { + .regulator = { NULL }, + .clock = { "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", "vfe_lite", "cam_hf_axi" }, + .clock_rate = { { 400000000, 480000000 }, + { 0 }, + { 0 }, + { 400000000, 480000000 }, + { 0 } }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" } + }, + /* VFE3 (lite) */ + { + .regulator = { NULL }, + .clock = { "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", "vfe_lite", "cam_hf_axi" }, + .clock_rate = { { 400000000, 480000000 }, + { 0 }, + { 0 }, + { 400000000, 480000000 }, + { 0 } }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" } + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -945,6 +1104,12 @@ static int camss_init_subdevices(struct camss *camss) /* Titan VFEs don't have an ISPIF */ ispif_res = NULL; vfe_res = vfe_res_845; + } else if (camss->version == CAMSS_8250) { + csiphy_res = csiphy_res_8250; + csid_res = csid_res_8250; + /* Titan VFEs don't have an ISPIF */ + ispif_res = NULL; + vfe_res = vfe_res_8250; } else { return -EINVAL; } @@ -960,6 +1125,17 @@ static int camss_init_subdevices(struct camss *camss) } } + /* note: SM8250 requires VFE to be initialized before CSID */ + for (i = 0; i < camss->vfe_num; i++) { + ret = msm_vfe_subdev_init(camss, &camss->vfe[i], + &vfe_res[i], i); + if (ret < 0) { + dev_err(camss->dev, + "Fail to init vfe%d sub-device: %d\n", i, ret); + return ret; + } + } + for (i = 0; i < camss->csid_num; i++) { ret = msm_csid_subdev_init(camss, &camss->csid[i], &csid_res[i], i); @@ -978,16 +1154,6 @@ static int camss_init_subdevices(struct camss *camss) return ret; } - for (i = 0; i < camss->vfe_num; i++) { - ret = msm_vfe_subdev_init(camss, &camss->vfe[i], - &vfe_res[i], i); - if (ret < 0) { - dev_err(camss->dev, - "Fail to init vfe%d sub-device: %d\n", i, ret); - return ret; - } - } - return 0; } @@ -1250,7 +1416,8 @@ static int camss_configure_pd(struct camss *camss) if (camss->version == CAMSS_8x96 || camss->version == CAMSS_660) nbr_pm_domains = PM_DOMAIN_GEN1_COUNT; - else if (camss->version == CAMSS_845) + else if (camss->version == CAMSS_845 || + camss->version == CAMSS_8250) nbr_pm_domains = PM_DOMAIN_GEN2_COUNT; for (i = 0; i < nbr_pm_domains; i++) { @@ -1326,6 +1493,12 @@ static int camss_probe(struct platform_device *pdev) camss->csiphy_num = 4; camss->csid_num = 3; camss->vfe_num = 3; + } else if (of_device_is_compatible(dev->of_node, + "qcom,sm8250-camss")) { + camss->version = CAMSS_8250; + camss->csiphy_num = 6; + camss->csid_num = 4; + camss->vfe_num = 4; } else { ret = -EINVAL; goto err_free; @@ -1457,7 +1630,8 @@ void camss_delete(struct camss *camss) if (camss->version == CAMSS_8x96 || camss->version == CAMSS_660) nbr_pm_domains = PM_DOMAIN_GEN1_COUNT; - else if (camss->version == CAMSS_845) + else if (camss->version == CAMSS_845 || + camss->version == CAMSS_8250) nbr_pm_domains = PM_DOMAIN_GEN2_COUNT; for (i = 0; i < nbr_pm_domains; i++) { @@ -1493,6 +1667,7 @@ static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8996-camss" }, { .compatible = "qcom,sdm660-camss" }, { .compatible = "qcom,sdm845-camss" }, + { .compatible = "qcom,sm8250-camss" }, { } };