From patchwork Thu Jul 26 10:15:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 142947 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp273824ljj; Thu, 26 Jul 2018 03:16:19 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeVjoteRa0WDWjeRbMlJ7H2tzLfwX/BZmjA6oDjuODowc4R8T7xPB11SWjPkZnDLEaZNK9e X-Received: by 2002:a62:864a:: with SMTP id x71-v6mr1501604pfd.252.1532600178992; Thu, 26 Jul 2018 03:16:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532600178; cv=none; d=google.com; s=arc-20160816; b=E7wjuCMmsrAPqpd9g71yxLiHaGHwTpZZyi4JBvRBgrpJ7e0t3gQhLV+wG7dDJU7a7e fYSGwrmZtz0tVJJDQSwOz2l4ghFNV8qJRyeLkoRngt6N3jh0zkxg/xOfA7d2YfSWlz51 7zH8uF2m35J6cSZUK4Pe64wKR8yrzax6WQ7W09CtTjB1OuurUjZBs/FWPFSXWfT5aaT7 tc/NJEuyw3TblxgUcaFrHR7RNkxy4YbYDiMG7QSOixD//EJk4uYHcXj1bP9IIlXakRf1 D22tHabOIoLTeCX2zWhXoPckzRowproKmj/zodBJpuW5LqrvGJET72tCD+hx9vRsZCxm PmlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=s9ggIHlFjOX1GmAyyDslj8PkwmNwq5DhXl20UHGcAF8=; b=u9itaXfMLHOKbVu6AYDqWTTe2nxkxJYRljCVZJMqhIW1pLhpOisSR6pgcN73GQ42OX XyA9XhOjuQ8mfn6IyWXyYnLGIrk8y8taEjZfPScps6EgFjoxHgm5VFnDEhMgFOlepHgt etgYi1PI+UcxpmsbBDfGtBqG5FFDsqXgTTjoqclJZGZH9tIxgS6yddBrqqJrEPNooZQr xLNpB+qH90giLqq1X2c+HuzDEo97/Kh+5Ik/tY+rgu6xUZByl41uMl0T/ZGu5aFxj+Dn F3yO26Jv8Ms8cpTOIr6ZAwW+5JtWWjNd+dzeRSD6ewleiLy86200ErkXAKcv3hxlcQEX hMHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kiu38j8g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i184-v6si935361pge.405.2018.07.26.03.16.18; Thu, 26 Jul 2018 03:16:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kiu38j8g; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729190AbeGZLcZ (ORCPT + 31 others); Thu, 26 Jul 2018 07:32:25 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:39997 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729053AbeGZLcZ (ORCPT ); Thu, 26 Jul 2018 07:32:25 -0400 Received: by mail-wm0-f66.google.com with SMTP id y9-v6so1428784wma.5 for ; Thu, 26 Jul 2018 03:16:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s9ggIHlFjOX1GmAyyDslj8PkwmNwq5DhXl20UHGcAF8=; b=kiu38j8ghlbuHgRXPBTkxa0q3f3oYEDFjIYba/QumdUgE60hlluZOpleJg1gKDi2QM Jaq8+tO/aejAEuSpfb9bEFlW2zj1O+CcOxMhY5+PElt65EBOrYpsNMjJivnXLQnAIUwi lw7/R8KsyXpO1GY/EWKg2MBAeGpm7BVmZzIx8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s9ggIHlFjOX1GmAyyDslj8PkwmNwq5DhXl20UHGcAF8=; b=JF32nW12uifkygoduohMANWmqL56PpOkrnPQJCt4JoCErz5UWAMsrpajTFVsFiIzkG 7XkWX+gWdXUP4mp9Bmcql2j1xCI4a9QLqOmNuWlTyAn3UwcAZxCuZYYzEs+h5CVLrND9 JjBA4xrUNU9ONYKMi/j6s6YFcwJD5GnHWqqnM9s5m7T+pDoeAcKb4O7FMLmXg/PeSeoc lgiL/Uo/T0jZh21UTyXzbJOvkvFKJdBuKAXRfA/geXLRxV7Q/LD9lmg4vHOmM4wXIe2N UH3UjxwJ2zS5ji57+NGOOU3BXrA48RPwu8ec4IJAnn0Z/k7N2HUUXtR49BYDWOuxyoVB ltTA== X-Gm-Message-State: AOUpUlHBqGuoIDLhHoxZUYkqRBXs3HKcsoNgpViQnGi8KoO1hbHG2GMO TqbUa8my9Qj3sB2QrDDxN5w55Q== X-Received: by 2002:a1c:1943:: with SMTP id 64-v6mr1098030wmz.89.1532600173921; Thu, 26 Jul 2018 03:16:13 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:35bd:fbdf:74b5:3f51]) by smtp.gmail.com with ESMTPSA id f6-v6sm957303wrp.30.2018.07.26.03.16.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jul 2018 03:16:13 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org, stanley.chu@mediatek.com, baolin.wang@linaro.org, Sudeep.Holla@arm.com, Sudeep Holla , Thierry Reding , Jonathan Hunter , Santosh Shilimkar , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT), linux-arm-kernel@lists.infradead.org (moderated list:ARM/TEXAS INSTRUMENT KEYSTONE ClOCKSOURCE) Subject: [PATCH 1/7] clocksource/drivers: Set clockevent device cpumask to cpu_possible_mask Date: Thu, 26 Jul 2018 12:15:24 +0200 Message-Id: <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <014f94f9-54d4-1ee0-aa89-67ca5d221989@free.fr> References: <014f94f9-54d4-1ee0-aa89-67ca5d221989@free.fr> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sudeep Holla Currently, quite a few clockevent devices have cpumask set to cpu_all_mask which should be fine. However, cpu_possible_mask is more accurate and if there are any other clockevent devices in the system which have cpumask set to cpu_possible_mask, then having cpu_all_mask may result in issues (mostly boot hang with forever loops in clockevents_notify_released). So, lets replace all the clockevent device cpu_all_mask to cpu_possible_mask in order to prevent above mentioned possible issue. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: Thierry Reding Cc: Jonathan Hunter Cc: Santosh Shilimkar Signed-off-by: Sudeep Holla Signed-off-by: Daniel Lezcano --- drivers/clocksource/tegra20_timer.c | 2 +- drivers/clocksource/timer-atcpit100.c | 2 +- drivers/clocksource/timer-keystone.c | 2 +- drivers/clocksource/zevio-timer.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index c337a81..dabf0a1 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c @@ -230,7 +230,7 @@ static int __init tegra20_init_timer(struct device_node *np) return ret; } - tegra_clockevent.cpumask = cpu_all_mask; + tegra_clockevent.cpumask = cpu_possible_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_config_and_register(&tegra_clockevent, 1000000, 0x1, 0x1fffffff); diff --git a/drivers/clocksource/timer-atcpit100.c b/drivers/clocksource/timer-atcpit100.c index 5e23d7b..b4bd2f5 100644 --- a/drivers/clocksource/timer-atcpit100.c +++ b/drivers/clocksource/timer-atcpit100.c @@ -185,7 +185,7 @@ static struct timer_of to = { .set_state_oneshot = atcpit100_clkevt_set_oneshot, .tick_resume = atcpit100_clkevt_shutdown, .set_next_event = atcpit100_clkevt_next_event, - .cpumask = cpu_all_mask, + .cpumask = cpu_possible_mask, }, .of_irq = { diff --git a/drivers/clocksource/timer-keystone.c b/drivers/clocksource/timer-keystone.c index 0eee032..f5b2eda 100644 --- a/drivers/clocksource/timer-keystone.c +++ b/drivers/clocksource/timer-keystone.c @@ -211,7 +211,7 @@ static int __init keystone_timer_init(struct device_node *np) event_dev->set_state_shutdown = keystone_shutdown; event_dev->set_state_periodic = keystone_set_periodic; event_dev->set_state_oneshot = keystone_shutdown; - event_dev->cpumask = cpu_all_mask; + event_dev->cpumask = cpu_possible_mask; event_dev->owner = THIS_MODULE; event_dev->name = TIMER_NAME; event_dev->irq = irq; diff --git a/drivers/clocksource/zevio-timer.c b/drivers/clocksource/zevio-timer.c index a6a0338..f746893 100644 --- a/drivers/clocksource/zevio-timer.c +++ b/drivers/clocksource/zevio-timer.c @@ -162,7 +162,7 @@ static int __init zevio_timer_add(struct device_node *node) timer->clkevt.set_state_oneshot = zevio_timer_set_oneshot; timer->clkevt.tick_resume = zevio_timer_set_oneshot; timer->clkevt.rating = 200; - timer->clkevt.cpumask = cpu_all_mask; + timer->clkevt.cpumask = cpu_possible_mask; timer->clkevt.features = CLOCK_EVT_FEAT_ONESHOT; timer->clkevt.irq = irqnr; From patchwork Thu Jul 26 10:15:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 142949 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp273934ljj; Thu, 26 Jul 2018 03:16:25 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeqJxOnAv+ZPtpzCC6XiHDTlqMPutW69EGTiWpj/dBpUy0o1WUcnCLhjxNiyIhkwYVNSqPG X-Received: by 2002:a17:902:bc85:: with SMTP id bb5-v6mr1357124plb.229.1532600185826; Thu, 26 Jul 2018 03:16:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532600185; cv=none; d=google.com; s=arc-20160816; b=oHMF/huuNwg9bWrkqh5TuH9Ls6fINcOWblY4jrObYVp/bPZVVLDYarRt0TQRbvFnGJ WnAvALuM5E9C/xrbGk/F3xx44naQDz96qUNs2cMaCrOLE+hGW913IRP6wpkYt+c1W6l8 Ah16icakEVhsd2g/ozKy6e/S4VJ4EpoL7eMgq6LAEXeMy5I4BbbVlNx2v8ZixZM7Wlh/ iPTur+Wvr2JA6uFPg4+EyJ88uueMhtChElCAkkQ0f+6bPRbDWHDQFIKOd3Rj5mx3hhZL Xm9+DKAglBS+n3pkdjF056b0eJ2YDivI0/1v6nDtwNxYIekkvbWMCD8j16rPjQCG1C/s YATg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=UHmo2ehcMWHoYCSeH4q1gNLHdMcPoM5dlEiYM+7Kqeg=; b=SkUUJHfaFlpiGmiT9viVWNDKuejYVPDwQtlp6fV8E1HEB9v9AwVxxVJSlRCu9m97hb qIUeTF01bAbsvqeA6NZY7lqpnGVjVfVeZ6CdvS9b8VHzvpkbgfAK58zdwr/8XzTK6TVL hYuyf4f84GzOej36X/WS1+8tt3+QmCmaQWrFFZgI6a3bcsGT3a6I4Jz2TNtJpItBYejy cLoQW8GLiHNCKURIU5dgfyCCLxyWIkn01P14Se18EGOLJuVyJo/mJfvlo9JCucwaswVP t5btYwfP8YUp+5H67OW/6FnMyY6v3RafBjcN3jYJOh9BgcdVaXa4DrWZQmBwofOcZCMh XmmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B+16ZiiE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l3-v6si917665pld.223.2018.07.26.03.16.25; Thu, 26 Jul 2018 03:16:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B+16ZiiE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729387AbeGZLcc (ORCPT + 31 others); Thu, 26 Jul 2018 07:32:32 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:35804 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729031AbeGZLcb (ORCPT ); Thu, 26 Jul 2018 07:32:31 -0400 Received: by mail-wr1-f65.google.com with SMTP id a3-v6so1144116wrt.2 for ; Thu, 26 Jul 2018 03:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UHmo2ehcMWHoYCSeH4q1gNLHdMcPoM5dlEiYM+7Kqeg=; b=B+16ZiiEOY3xQK+hdptPVoSY9VqIEW0FdvquQu9qkUKkHnH1mri3Pd6AGhL2BkUuWp uc23JJwIkzM0dco9dk14XLfEipCPm4deKOqU4c8E9hP/T3ptHAx67za66tWE+8y69Ia7 sDl9JMGBMWBjAMgVpi29Vkj4AA6c0Fx1cg4dQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UHmo2ehcMWHoYCSeH4q1gNLHdMcPoM5dlEiYM+7Kqeg=; b=Q9uMBPl8IbGFlRB4veRkn1wCVxn2SRAxODqJP3M8ZIuahRkz5ebZDqdrQ8gt/kuhrS prpWIIByGE9Ml6DFRH/EbpncX8mVPM2Q/SJlpCSUVgSPpaGl0ZvmnxbRMx2GENeTFe8D WUFfrzR825lGxUQpFaCyV+ttAKn8ap1j0jbIGDrutIvtFsOqrafZogQRMlFN6cYQbv7L xLubIQIys5RrHBRp/i+Spk4r3jgZjKoORR25WP1J+DAiKbH53ulSrC3SXHpMzJzwHMRp A+uYz5gVbX5TdclLdCISyff3gBwVs4FDIHfBpuvcDwoRdMBY4uffZdicPcg1XWpGqy/b fEdQ== X-Gm-Message-State: AOUpUlFm8S+La934gfGpyZ/Nd3UaBPUKgNn0Efi7fZWTipg8EJZsIh9N W1cszhoIRVbLl87ffVzzi28h+Q== X-Received: by 2002:adf:c44c:: with SMTP id a12-v6mr1127098wrg.20.1532600180521; Thu, 26 Jul 2018 03:16:20 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:35bd:fbdf:74b5:3f51]) by smtp.gmail.com with ESMTPSA id f6-v6sm957303wrp.30.2018.07.26.03.16.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jul 2018 03:16:19 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org, stanley.chu@mediatek.com, baolin.wang@linaro.org, Sudeep.Holla@arm.com, Matthias Brugger , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 3/7] clocksource/drivers/timer-mediatek: Rename mtk_timer to timer-mediatek Date: Thu, 26 Jul 2018 12:15:26 +0200 Message-Id: <1532600131-28168-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> References: <014f94f9-54d4-1ee0-aa89-67ca5d221989@free.fr> <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stanley Chu Rename mtk_timer to timer-mediatek to apply new naming convention in clocksource folder. Signed-off-by: Stanley Chu Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/mtk_timer.c | 268 ----------------------------------- drivers/clocksource/timer-mediatek.c | 268 +++++++++++++++++++++++++++++++++++ 3 files changed, 269 insertions(+), 269 deletions(-) delete mode 100644 drivers/clocksource/mtk_timer.c create mode 100644 drivers/clocksource/timer-mediatek.c -- 2.7.4 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 00caf37..c070cc7 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -49,7 +49,7 @@ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o -obj-$(CONFIG_MTK_TIMER) += mtk_timer.o +obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c deleted file mode 100644 index f9b724f..0000000 --- a/drivers/clocksource/mtk_timer.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Mediatek SoCs General-Purpose Timer handling. - * - * Copyright (C) 2014 Matthias Brugger - * - * Matthias Brugger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define GPT_IRQ_EN_REG 0x00 -#define GPT_IRQ_ENABLE(val) BIT((val) - 1) -#define GPT_IRQ_ACK_REG 0x08 -#define GPT_IRQ_ACK(val) BIT((val) - 1) - -#define TIMER_CTRL_REG(val) (0x10 * (val)) -#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4) -#define TIMER_CTRL_OP_ONESHOT (0) -#define TIMER_CTRL_OP_REPEAT (1) -#define TIMER_CTRL_OP_FREERUN (3) -#define TIMER_CTRL_CLEAR (2) -#define TIMER_CTRL_ENABLE (1) -#define TIMER_CTRL_DISABLE (0) - -#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val))) -#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4) -#define TIMER_CLK_SRC_SYS13M (0) -#define TIMER_CLK_SRC_RTC32K (1) -#define TIMER_CLK_DIV1 (0x0) -#define TIMER_CLK_DIV2 (0x1) - -#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val))) -#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val))) - -#define GPT_CLK_EVT 1 -#define GPT_CLK_SRC 2 - -struct mtk_clock_event_device { - void __iomem *gpt_base; - u32 ticks_per_jiffy; - struct clock_event_device dev; -}; - -static void __iomem *gpt_sched_reg __read_mostly; - -static u64 notrace mtk_read_sched_clock(void) -{ - return readl_relaxed(gpt_sched_reg); -} - -static inline struct mtk_clock_event_device *to_mtk_clk( - struct clock_event_device *c) -{ - return container_of(c, struct mtk_clock_event_device, dev); -} - -static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer) -{ - u32 val; - - val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); - writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base + - TIMER_CTRL_REG(timer)); -} - -static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt, - unsigned long delay, u8 timer) -{ - writel(delay, evt->gpt_base + TIMER_CMP_REG(timer)); -} - -static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt, - bool periodic, u8 timer) -{ - u32 val; - - /* Acknowledge interrupt */ - writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); - - val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); - - /* Clear 2 bit timer operation mode field */ - val &= ~TIMER_CTRL_OP(0x3); - - if (periodic) - val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT); - else - val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT); - - writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR, - evt->gpt_base + TIMER_CTRL_REG(timer)); -} - -static int mtk_clkevt_shutdown(struct clock_event_device *clk) -{ - mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT); - return 0; -} - -static int mtk_clkevt_set_periodic(struct clock_event_device *clk) -{ - struct mtk_clock_event_device *evt = to_mtk_clk(clk); - - mtk_clkevt_time_stop(evt, GPT_CLK_EVT); - mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT); - mtk_clkevt_time_start(evt, true, GPT_CLK_EVT); - return 0; -} - -static int mtk_clkevt_next_event(unsigned long event, - struct clock_event_device *clk) -{ - struct mtk_clock_event_device *evt = to_mtk_clk(clk); - - mtk_clkevt_time_stop(evt, GPT_CLK_EVT); - mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT); - mtk_clkevt_time_start(evt, false, GPT_CLK_EVT); - - return 0; -} - -static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id) -{ - struct mtk_clock_event_device *evt = dev_id; - - /* Acknowledge timer0 irq */ - writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); - evt->dev.event_handler(&evt->dev); - - return IRQ_HANDLED; -} - -static void -__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) -{ - writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); - - writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1, - evt->gpt_base + TIMER_CLK_REG(timer)); - - writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); - - writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); -} - -static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer) -{ - u32 val; - - /* Disable all interrupts */ - writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG); - - /* Acknowledge all spurious pending interrupts */ - writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); - - val = readl(evt->gpt_base + GPT_IRQ_EN_REG); - writel(val | GPT_IRQ_ENABLE(timer), - evt->gpt_base + GPT_IRQ_EN_REG); -} - -static int __init mtk_timer_init(struct device_node *node) -{ - struct mtk_clock_event_device *evt; - struct resource res; - unsigned long rate = 0; - struct clk *clk; - - evt = kzalloc(sizeof(*evt), GFP_KERNEL); - if (!evt) - return -ENOMEM; - - evt->dev.name = "mtk_tick"; - evt->dev.rating = 300; - evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - evt->dev.set_state_shutdown = mtk_clkevt_shutdown; - evt->dev.set_state_periodic = mtk_clkevt_set_periodic; - evt->dev.set_state_oneshot = mtk_clkevt_shutdown; - evt->dev.tick_resume = mtk_clkevt_shutdown; - evt->dev.set_next_event = mtk_clkevt_next_event; - evt->dev.cpumask = cpu_possible_mask; - - evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer"); - if (IS_ERR(evt->gpt_base)) { - pr_err("Can't get resource\n"); - goto err_kzalloc; - } - - evt->dev.irq = irq_of_parse_and_map(node, 0); - if (evt->dev.irq <= 0) { - pr_err("Can't parse IRQ\n"); - goto err_mem; - } - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("Can't get timer clock\n"); - goto err_irq; - } - - if (clk_prepare_enable(clk)) { - pr_err("Can't prepare clock\n"); - goto err_clk_put; - } - rate = clk_get_rate(clk); - - if (request_irq(evt->dev.irq, mtk_timer_interrupt, - IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) { - pr_err("failed to setup irq %d\n", evt->dev.irq); - goto err_clk_disable; - } - - evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); - - /* Configure clock source */ - mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); - clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), - node->name, rate, 300, 32, clocksource_mmio_readl_up); - gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC); - sched_clock_register(mtk_read_sched_clock, 32, rate); - - /* Configure clock event */ - mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); - clockevents_config_and_register(&evt->dev, rate, 0x3, - 0xffffffff); - - mtk_timer_enable_irq(evt, GPT_CLK_EVT); - - return 0; - -err_clk_disable: - clk_disable_unprepare(clk); -err_clk_put: - clk_put(clk); -err_irq: - irq_dispose_mapping(evt->dev.irq); -err_mem: - iounmap(evt->gpt_base); - of_address_to_resource(node, 0, &res); - release_mem_region(res.start, resource_size(&res)); -err_kzalloc: - kfree(evt); - - return -EINVAL; -} -TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init); diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c new file mode 100644 index 0000000..f9b724f --- /dev/null +++ b/drivers/clocksource/timer-mediatek.c @@ -0,0 +1,268 @@ +/* + * Mediatek SoCs General-Purpose Timer handling. + * + * Copyright (C) 2014 Matthias Brugger + * + * Matthias Brugger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPT_IRQ_EN_REG 0x00 +#define GPT_IRQ_ENABLE(val) BIT((val) - 1) +#define GPT_IRQ_ACK_REG 0x08 +#define GPT_IRQ_ACK(val) BIT((val) - 1) + +#define TIMER_CTRL_REG(val) (0x10 * (val)) +#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4) +#define TIMER_CTRL_OP_ONESHOT (0) +#define TIMER_CTRL_OP_REPEAT (1) +#define TIMER_CTRL_OP_FREERUN (3) +#define TIMER_CTRL_CLEAR (2) +#define TIMER_CTRL_ENABLE (1) +#define TIMER_CTRL_DISABLE (0) + +#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val))) +#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4) +#define TIMER_CLK_SRC_SYS13M (0) +#define TIMER_CLK_SRC_RTC32K (1) +#define TIMER_CLK_DIV1 (0x0) +#define TIMER_CLK_DIV2 (0x1) + +#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val))) +#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val))) + +#define GPT_CLK_EVT 1 +#define GPT_CLK_SRC 2 + +struct mtk_clock_event_device { + void __iomem *gpt_base; + u32 ticks_per_jiffy; + struct clock_event_device dev; +}; + +static void __iomem *gpt_sched_reg __read_mostly; + +static u64 notrace mtk_read_sched_clock(void) +{ + return readl_relaxed(gpt_sched_reg); +} + +static inline struct mtk_clock_event_device *to_mtk_clk( + struct clock_event_device *c) +{ + return container_of(c, struct mtk_clock_event_device, dev); +} + +static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer) +{ + u32 val; + + val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); + writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base + + TIMER_CTRL_REG(timer)); +} + +static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt, + unsigned long delay, u8 timer) +{ + writel(delay, evt->gpt_base + TIMER_CMP_REG(timer)); +} + +static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt, + bool periodic, u8 timer) +{ + u32 val; + + /* Acknowledge interrupt */ + writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); + + val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); + + /* Clear 2 bit timer operation mode field */ + val &= ~TIMER_CTRL_OP(0x3); + + if (periodic) + val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT); + else + val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT); + + writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR, + evt->gpt_base + TIMER_CTRL_REG(timer)); +} + +static int mtk_clkevt_shutdown(struct clock_event_device *clk) +{ + mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT); + return 0; +} + +static int mtk_clkevt_set_periodic(struct clock_event_device *clk) +{ + struct mtk_clock_event_device *evt = to_mtk_clk(clk); + + mtk_clkevt_time_stop(evt, GPT_CLK_EVT); + mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT); + mtk_clkevt_time_start(evt, true, GPT_CLK_EVT); + return 0; +} + +static int mtk_clkevt_next_event(unsigned long event, + struct clock_event_device *clk) +{ + struct mtk_clock_event_device *evt = to_mtk_clk(clk); + + mtk_clkevt_time_stop(evt, GPT_CLK_EVT); + mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT); + mtk_clkevt_time_start(evt, false, GPT_CLK_EVT); + + return 0; +} + +static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id) +{ + struct mtk_clock_event_device *evt = dev_id; + + /* Acknowledge timer0 irq */ + writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); + evt->dev.event_handler(&evt->dev); + + return IRQ_HANDLED; +} + +static void +__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) +{ + writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, + evt->gpt_base + TIMER_CTRL_REG(timer)); + + writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1, + evt->gpt_base + TIMER_CLK_REG(timer)); + + writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); + + writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, + evt->gpt_base + TIMER_CTRL_REG(timer)); +} + +static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer) +{ + u32 val; + + /* Disable all interrupts */ + writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG); + + /* Acknowledge all spurious pending interrupts */ + writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); + + val = readl(evt->gpt_base + GPT_IRQ_EN_REG); + writel(val | GPT_IRQ_ENABLE(timer), + evt->gpt_base + GPT_IRQ_EN_REG); +} + +static int __init mtk_timer_init(struct device_node *node) +{ + struct mtk_clock_event_device *evt; + struct resource res; + unsigned long rate = 0; + struct clk *clk; + + evt = kzalloc(sizeof(*evt), GFP_KERNEL); + if (!evt) + return -ENOMEM; + + evt->dev.name = "mtk_tick"; + evt->dev.rating = 300; + evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + evt->dev.set_state_shutdown = mtk_clkevt_shutdown; + evt->dev.set_state_periodic = mtk_clkevt_set_periodic; + evt->dev.set_state_oneshot = mtk_clkevt_shutdown; + evt->dev.tick_resume = mtk_clkevt_shutdown; + evt->dev.set_next_event = mtk_clkevt_next_event; + evt->dev.cpumask = cpu_possible_mask; + + evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer"); + if (IS_ERR(evt->gpt_base)) { + pr_err("Can't get resource\n"); + goto err_kzalloc; + } + + evt->dev.irq = irq_of_parse_and_map(node, 0); + if (evt->dev.irq <= 0) { + pr_err("Can't parse IRQ\n"); + goto err_mem; + } + + clk = of_clk_get(node, 0); + if (IS_ERR(clk)) { + pr_err("Can't get timer clock\n"); + goto err_irq; + } + + if (clk_prepare_enable(clk)) { + pr_err("Can't prepare clock\n"); + goto err_clk_put; + } + rate = clk_get_rate(clk); + + if (request_irq(evt->dev.irq, mtk_timer_interrupt, + IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) { + pr_err("failed to setup irq %d\n", evt->dev.irq); + goto err_clk_disable; + } + + evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); + + /* Configure clock source */ + mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); + clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), + node->name, rate, 300, 32, clocksource_mmio_readl_up); + gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC); + sched_clock_register(mtk_read_sched_clock, 32, rate); + + /* Configure clock event */ + mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); + clockevents_config_and_register(&evt->dev, rate, 0x3, + 0xffffffff); + + mtk_timer_enable_irq(evt, GPT_CLK_EVT); + + return 0; + +err_clk_disable: + clk_disable_unprepare(clk); +err_clk_put: + clk_put(clk); +err_irq: + irq_dispose_mapping(evt->dev.irq); +err_mem: + iounmap(evt->gpt_base); + of_address_to_resource(node, 0, &res); + release_mem_region(res.start, resource_size(&res)); +err_kzalloc: + kfree(evt); + + return -EINVAL; +} +TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init); From patchwork Thu Jul 26 10:15:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 142950 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp273978ljj; Thu, 26 Jul 2018 03:16:28 -0700 (PDT) X-Google-Smtp-Source: AAOMgpecI8rSIeiy41+35G0QG4iJbVbOCLXOgfo+JoQMVwVdEgsOaTrux33cz6LQDHh7T2pnMYL0 X-Received: by 2002:a17:902:b189:: with SMTP id s9-v6mr1372863plr.188.1532600188579; Thu, 26 Jul 2018 03:16:28 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id q2-v6si916880plh.136.2018.07.26.03.16.28; Thu, 26 Jul 2018 03:16:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e05JtHyK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729414AbeGZLce (ORCPT + 31 others); Thu, 26 Jul 2018 07:32:34 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:40326 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729031AbeGZLce (ORCPT ); Thu, 26 Jul 2018 07:32:34 -0400 Received: by mail-wr1-f66.google.com with SMTP id h15-v6so1137548wrs.7 for ; Thu, 26 Jul 2018 03:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NiwYSYcAfjtEfHOWA6PB1+uyUi635B3M3JtOW5fhzOc=; b=e05JtHyKjQ6MjW2fPHTYFEQd/XZF2GHXVXUXTUg7Z+2SiN/WIJ4+HPoB+8cNlhYi4Z n3KjEoIbFKxzjg/yMofz+2xZzosh+Il+RVwyftlApp41xH9iVVP2oYPd4sqWrAMqPEuB Z1biuCF2fK2VgVuexW03y6JMpNZ1oSiNjRX9w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NiwYSYcAfjtEfHOWA6PB1+uyUi635B3M3JtOW5fhzOc=; b=JcRnWduohhanm2ePAsjh3uSHjXxviQCu+lyJ5HIVYbD+cSsaqcIm4vMHkYgmrNN2Oz JYDaSrqvcRyGy9mMuptj+1zPXMf5sLoaRtjnwFLJ9Ni4l4QZPrRLUSeCKQBlbCE6jwYP DgGtaz6jq7o9985Kbm4xidMfz/Ny38VPIYP2f/sgR6Kdu6lXtxUXjyarjUSNvmYqtoaB eLAr3FLBZ7BG6FYWU/+ldHkSWusxFJnr+z+FW/y21aBnl/4bBvTb4MWxXOqXj5cDDMX6 KMtQU91FhkVo1ZcaEbnD9PnctK7gIcreawNGdbtDYF/z3uf4/LHieFdcxX/OMge/UeJH 76+Q== X-Gm-Message-State: AOUpUlGKHN3WdQfboH7OD5WJJ76jz75kPyMXiY/hdO7g7FaWFe96MbX6 WbBFG2p3nouwtwnacfPi10Ov9A== X-Received: by 2002:adf:9527:: with SMTP id 36-v6mr1025745wrs.99.1532600182651; Thu, 26 Jul 2018 03:16:22 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:35bd:fbdf:74b5:3f51]) by smtp.gmail.com with ESMTPSA id f6-v6sm957303wrp.30.2018.07.26.03.16.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jul 2018 03:16:21 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org, stanley.chu@mediatek.com, baolin.wang@linaro.org, Sudeep.Holla@arm.com, Matthias Brugger , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 4/7] clocksource/drivers/timer-mediatek: Use specific prefix for GPT Date: Thu, 26 Jul 2018 12:15:27 +0200 Message-Id: <1532600131-28168-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> References: <014f94f9-54d4-1ee0-aa89-67ca5d221989@free.fr> <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stanley Chu Use specific prefix to specify the name of supported timer hardware: "General Purpose Timer (GPT)". Signed-off-by: Stanley Chu Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-mediatek.c | 157 ++++++++++++++++++----------------- 1 file changed, 80 insertions(+), 77 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c index f9b724f..e3657d2 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -29,32 +29,35 @@ #include #include -#define GPT_IRQ_EN_REG 0x00 -#define GPT_IRQ_ENABLE(val) BIT((val) - 1) -#define GPT_IRQ_ACK_REG 0x08 -#define GPT_IRQ_ACK(val) BIT((val) - 1) - -#define TIMER_CTRL_REG(val) (0x10 * (val)) -#define TIMER_CTRL_OP(val) (((val) & 0x3) << 4) -#define TIMER_CTRL_OP_ONESHOT (0) -#define TIMER_CTRL_OP_REPEAT (1) -#define TIMER_CTRL_OP_FREERUN (3) -#define TIMER_CTRL_CLEAR (2) -#define TIMER_CTRL_ENABLE (1) -#define TIMER_CTRL_DISABLE (0) - -#define TIMER_CLK_REG(val) (0x04 + (0x10 * (val))) -#define TIMER_CLK_SRC(val) (((val) & 0x1) << 4) -#define TIMER_CLK_SRC_SYS13M (0) -#define TIMER_CLK_SRC_RTC32K (1) -#define TIMER_CLK_DIV1 (0x0) -#define TIMER_CLK_DIV2 (0x1) - -#define TIMER_CNT_REG(val) (0x08 + (0x10 * (val))) -#define TIMER_CMP_REG(val) (0x0C + (0x10 * (val))) - -#define GPT_CLK_EVT 1 -#define GPT_CLK_SRC 2 +#define TIMER_CLK_EVT (1) +#define TIMER_CLK_SRC (2) + +#define TIMER_SYNC_TICKS (3) + +/* gpt */ +#define GPT_IRQ_EN_REG 0x00 +#define GPT_IRQ_ENABLE(val) BIT((val) - 1) +#define GPT_IRQ_ACK_REG 0x08 +#define GPT_IRQ_ACK(val) BIT((val) - 1) + +#define GPT_CTRL_REG(val) (0x10 * (val)) +#define GPT_CTRL_OP(val) (((val) & 0x3) << 4) +#define GPT_CTRL_OP_ONESHOT (0) +#define GPT_CTRL_OP_REPEAT (1) +#define GPT_CTRL_OP_FREERUN (3) +#define GPT_CTRL_CLEAR (2) +#define GPT_CTRL_ENABLE (1) +#define GPT_CTRL_DISABLE (0) + +#define GPT_CLK_REG(val) (0x04 + (0x10 * (val))) +#define GPT_CLK_SRC(val) (((val) & 0x1) << 4) +#define GPT_CLK_SRC_SYS13M (0) +#define GPT_CLK_SRC_RTC32K (1) +#define GPT_CLK_DIV1 (0x0) +#define GPT_CLK_DIV2 (0x1) + +#define GPT_CNT_REG(val) (0x08 + (0x10 * (val))) +#define GPT_CMP_REG(val) (0x0C + (0x10 * (val))) struct mtk_clock_event_device { void __iomem *gpt_base; @@ -64,7 +67,7 @@ struct mtk_clock_event_device { static void __iomem *gpt_sched_reg __read_mostly; -static u64 notrace mtk_read_sched_clock(void) +static u64 notrace mtk_gpt_read_sched_clock(void) { return readl_relaxed(gpt_sched_reg); } @@ -75,22 +78,22 @@ static inline struct mtk_clock_event_device *to_mtk_clk( return container_of(c, struct mtk_clock_event_device, dev); } -static void mtk_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer) +static void mtk_gpt_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer) { u32 val; - val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); - writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base + - TIMER_CTRL_REG(timer)); + val = readl(evt->gpt_base + GPT_CTRL_REG(timer)); + writel(val & ~GPT_CTRL_ENABLE, evt->gpt_base + + GPT_CTRL_REG(timer)); } -static void mtk_clkevt_time_setup(struct mtk_clock_event_device *evt, +static void mtk_gpt_clkevt_time_setup(struct mtk_clock_event_device *evt, unsigned long delay, u8 timer) { - writel(delay, evt->gpt_base + TIMER_CMP_REG(timer)); + writel(delay, evt->gpt_base + GPT_CMP_REG(timer)); } -static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt, +static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt, bool periodic, u8 timer) { u32 val; @@ -98,75 +101,75 @@ static void mtk_clkevt_time_start(struct mtk_clock_event_device *evt, /* Acknowledge interrupt */ writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); - val = readl(evt->gpt_base + TIMER_CTRL_REG(timer)); + val = readl(evt->gpt_base + GPT_CTRL_REG(timer)); /* Clear 2 bit timer operation mode field */ - val &= ~TIMER_CTRL_OP(0x3); + val &= ~GPT_CTRL_OP(0x3); if (periodic) - val |= TIMER_CTRL_OP(TIMER_CTRL_OP_REPEAT); + val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT); else - val |= TIMER_CTRL_OP(TIMER_CTRL_OP_ONESHOT); + val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT); - writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR, - evt->gpt_base + TIMER_CTRL_REG(timer)); + writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR, + evt->gpt_base + GPT_CTRL_REG(timer)); } -static int mtk_clkevt_shutdown(struct clock_event_device *clk) +static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk) { - mtk_clkevt_time_stop(to_mtk_clk(clk), GPT_CLK_EVT); + mtk_gpt_clkevt_time_stop(to_mtk_clk(clk), TIMER_CLK_EVT); return 0; } -static int mtk_clkevt_set_periodic(struct clock_event_device *clk) +static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk) { struct mtk_clock_event_device *evt = to_mtk_clk(clk); - mtk_clkevt_time_stop(evt, GPT_CLK_EVT); - mtk_clkevt_time_setup(evt, evt->ticks_per_jiffy, GPT_CLK_EVT); - mtk_clkevt_time_start(evt, true, GPT_CLK_EVT); + mtk_gpt_clkevt_time_stop(evt, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_setup(evt, evt->ticks_per_jiffy, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_start(evt, true, TIMER_CLK_EVT); return 0; } -static int mtk_clkevt_next_event(unsigned long event, +static int mtk_gpt_clkevt_next_event(unsigned long event, struct clock_event_device *clk) { struct mtk_clock_event_device *evt = to_mtk_clk(clk); - mtk_clkevt_time_stop(evt, GPT_CLK_EVT); - mtk_clkevt_time_setup(evt, event, GPT_CLK_EVT); - mtk_clkevt_time_start(evt, false, GPT_CLK_EVT); + mtk_gpt_clkevt_time_stop(evt, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_setup(evt, event, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_start(evt, false, TIMER_CLK_EVT); return 0; } -static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id) +static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id) { struct mtk_clock_event_device *evt = dev_id; /* Acknowledge timer0 irq */ - writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); + writel(GPT_IRQ_ACK(TIMER_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); evt->dev.event_handler(&evt->dev); return IRQ_HANDLED; } static void -__init mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) +__init mtk_gpt_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) { - writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); + writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE, + evt->gpt_base + GPT_CTRL_REG(timer)); - writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1, - evt->gpt_base + TIMER_CLK_REG(timer)); + writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1, + evt->gpt_base + GPT_CLK_REG(timer)); - writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); + writel(0x0, evt->gpt_base + GPT_CMP_REG(timer)); - writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); + writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE, + evt->gpt_base + GPT_CTRL_REG(timer)); } -static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer) +static void mtk_gpt_enable_irq(struct mtk_clock_event_device *evt, u8 timer) { u32 val; @@ -181,7 +184,7 @@ static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer) evt->gpt_base + GPT_IRQ_EN_REG); } -static int __init mtk_timer_init(struct device_node *node) +static int __init mtk_gpt_init(struct device_node *node) { struct mtk_clock_event_device *evt; struct resource res; @@ -195,14 +198,14 @@ static int __init mtk_timer_init(struct device_node *node) evt->dev.name = "mtk_tick"; evt->dev.rating = 300; evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - evt->dev.set_state_shutdown = mtk_clkevt_shutdown; - evt->dev.set_state_periodic = mtk_clkevt_set_periodic; - evt->dev.set_state_oneshot = mtk_clkevt_shutdown; - evt->dev.tick_resume = mtk_clkevt_shutdown; - evt->dev.set_next_event = mtk_clkevt_next_event; + evt->dev.set_state_shutdown = mtk_gpt_clkevt_shutdown; + evt->dev.set_state_periodic = mtk_gpt_clkevt_set_periodic; + evt->dev.set_state_oneshot = mtk_gpt_clkevt_shutdown; + evt->dev.tick_resume = mtk_gpt_clkevt_shutdown; + evt->dev.set_next_event = mtk_gpt_clkevt_next_event; evt->dev.cpumask = cpu_possible_mask; - evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer"); + evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer-gpt"); if (IS_ERR(evt->gpt_base)) { pr_err("Can't get resource\n"); goto err_kzalloc; @@ -226,7 +229,7 @@ static int __init mtk_timer_init(struct device_node *node) } rate = clk_get_rate(clk); - if (request_irq(evt->dev.irq, mtk_timer_interrupt, + if (request_irq(evt->dev.irq, mtk_gpt_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) { pr_err("failed to setup irq %d\n", evt->dev.irq); goto err_clk_disable; @@ -235,18 +238,18 @@ static int __init mtk_timer_init(struct device_node *node) evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); /* Configure clock source */ - mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); - clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), + mtk_gpt_setup(evt, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN); + clocksource_mmio_init(evt->gpt_base + GPT_CNT_REG(TIMER_CLK_SRC), node->name, rate, 300, 32, clocksource_mmio_readl_up); - gpt_sched_reg = evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC); - sched_clock_register(mtk_read_sched_clock, 32, rate); + gpt_sched_reg = evt->gpt_base + GPT_CNT_REG(TIMER_CLK_SRC); + sched_clock_register(mtk_gpt_read_sched_clock, 32, rate); /* Configure clock event */ - mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); - clockevents_config_and_register(&evt->dev, rate, 0x3, + mtk_gpt_setup(evt, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT); + clockevents_config_and_register(&evt->dev, rate, TIMER_SYNC_TICKS, 0xffffffff); - mtk_timer_enable_irq(evt, GPT_CLK_EVT); + mtk_gpt_enable_irq(evt, TIMER_CLK_EVT); return 0; @@ -265,4 +268,4 @@ static int __init mtk_timer_init(struct device_node *node) return -EINVAL; } -TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init); +TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init); From patchwork Thu Jul 26 10:15:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 142951 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp274028ljj; Thu, 26 Jul 2018 03:16:31 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdiyr1EgfTBwpVtnPCA1uDX///koQ9J9H4gIhvPMHdn4zcTHnRiXgvGhRG14RhV6vN2akka X-Received: by 2002:a17:902:8a8e:: with SMTP id p14-v6mr1352872plo.213.1532600191584; Thu, 26 Jul 2018 03:16:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532600191; cv=none; d=google.com; s=arc-20160816; b=Z9e7IGWwaWs5I0P2spBTAqgyMqS4ElOZPAHEoct1tM4JD4XDXWAoEKmO7c7/hu1m9S vbEIgP07UJo83j3iYMcsBvuwrLYXBOBntdJRvvjdaCR05PKzVxTYOMuw1bB7AMsTnNFb Swg9VuG4GFFAdLs2IWfwF3QwThDvouKxxz1+MBQO6h3hQCEDJ5lAXD1RtqjGZ70SIyWa 9cBvEl62Hie0HkoOC+T11T+CGuUdhkKSn1nw07d3UVpSPVtIqeBXvWSpldPASdeiEkGH o0HmbyinVTlDuLgIKMDBFoL7vUhWqpfdrYefZHRVVIJ3hOeOnlswdWxnSpvEOLUTy0ZD JkiQ== ARC-Message-Signature: i=1; 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This allows to remove custom proprietary structure, factors out and simplifies the code. Signed-off-by: Stanley Chu Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-mediatek.c | 205 ++++++++++++++--------------------- 1 file changed, 80 insertions(+), 125 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c index e3657d2..e57c4d7 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -18,16 +18,13 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#include #include +#include #include -#include #include -#include -#include -#include #include #include +#include "timer-of.h" #define TIMER_CLK_EVT (1) #define TIMER_CLK_SRC (2) @@ -59,12 +56,6 @@ #define GPT_CNT_REG(val) (0x08 + (0x10 * (val))) #define GPT_CMP_REG(val) (0x0C + (0x10 * (val))) -struct mtk_clock_event_device { - void __iomem *gpt_base; - u32 ticks_per_jiffy; - struct clock_event_device dev; -}; - static void __iomem *gpt_sched_reg __read_mostly; static u64 notrace mtk_gpt_read_sched_clock(void) @@ -72,36 +63,30 @@ static u64 notrace mtk_gpt_read_sched_clock(void) return readl_relaxed(gpt_sched_reg); } -static inline struct mtk_clock_event_device *to_mtk_clk( - struct clock_event_device *c) -{ - return container_of(c, struct mtk_clock_event_device, dev); -} - -static void mtk_gpt_clkevt_time_stop(struct mtk_clock_event_device *evt, u8 timer) +static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer) { u32 val; - val = readl(evt->gpt_base + GPT_CTRL_REG(timer)); - writel(val & ~GPT_CTRL_ENABLE, evt->gpt_base + - GPT_CTRL_REG(timer)); + val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); + writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + + GPT_CTRL_REG(timer)); } -static void mtk_gpt_clkevt_time_setup(struct mtk_clock_event_device *evt, - unsigned long delay, u8 timer) +static void mtk_gpt_clkevt_time_setup(struct timer_of *to, + unsigned long delay, u8 timer) { - writel(delay, evt->gpt_base + GPT_CMP_REG(timer)); + writel(delay, timer_of_base(to) + GPT_CMP_REG(timer)); } -static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt, - bool periodic, u8 timer) +static void mtk_gpt_clkevt_time_start(struct timer_of *to, + bool periodic, u8 timer) { u32 val; /* Acknowledge interrupt */ - writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); + writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); - val = readl(evt->gpt_base + GPT_CTRL_REG(timer)); + val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); /* Clear 2 bit timer operation mode field */ val &= ~GPT_CTRL_OP(0x3); @@ -112,160 +97,130 @@ static void mtk_gpt_clkevt_time_start(struct mtk_clock_event_device *evt, val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT); writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR, - evt->gpt_base + GPT_CTRL_REG(timer)); + timer_of_base(to) + GPT_CTRL_REG(timer)); } static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk) { - mtk_gpt_clkevt_time_stop(to_mtk_clk(clk), TIMER_CLK_EVT); + mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT); + return 0; } static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk) { - struct mtk_clock_event_device *evt = to_mtk_clk(clk); + struct timer_of *to = to_timer_of(clk); + + mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT); - mtk_gpt_clkevt_time_stop(evt, TIMER_CLK_EVT); - mtk_gpt_clkevt_time_setup(evt, evt->ticks_per_jiffy, TIMER_CLK_EVT); - mtk_gpt_clkevt_time_start(evt, true, TIMER_CLK_EVT); return 0; } static int mtk_gpt_clkevt_next_event(unsigned long event, - struct clock_event_device *clk) + struct clock_event_device *clk) { - struct mtk_clock_event_device *evt = to_mtk_clk(clk); + struct timer_of *to = to_timer_of(clk); - mtk_gpt_clkevt_time_stop(evt, TIMER_CLK_EVT); - mtk_gpt_clkevt_time_setup(evt, event, TIMER_CLK_EVT); - mtk_gpt_clkevt_time_start(evt, false, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT); + mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT); return 0; } static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id) { - struct mtk_clock_event_device *evt = dev_id; + struct clock_event_device *clkevt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(clkevt); /* Acknowledge timer0 irq */ - writel(GPT_IRQ_ACK(TIMER_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); - evt->dev.event_handler(&evt->dev); + writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG); + clkevt->event_handler(clkevt); return IRQ_HANDLED; } static void -__init mtk_gpt_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) +__init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option) { writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE, - evt->gpt_base + GPT_CTRL_REG(timer)); + timer_of_base(to) + GPT_CTRL_REG(timer)); writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1, - evt->gpt_base + GPT_CLK_REG(timer)); + timer_of_base(to) + GPT_CLK_REG(timer)); - writel(0x0, evt->gpt_base + GPT_CMP_REG(timer)); + writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer)); writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE, - evt->gpt_base + GPT_CTRL_REG(timer)); + timer_of_base(to) + GPT_CTRL_REG(timer)); } -static void mtk_gpt_enable_irq(struct mtk_clock_event_device *evt, u8 timer) +static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer) { u32 val; /* Disable all interrupts */ - writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG); + writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); /* Acknowledge all spurious pending interrupts */ - writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); + writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG); - val = readl(evt->gpt_base + GPT_IRQ_EN_REG); + val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); writel(val | GPT_IRQ_ENABLE(timer), - evt->gpt_base + GPT_IRQ_EN_REG); + timer_of_base(to) + GPT_IRQ_EN_REG); } +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = "mtk-clkevt", + .rating = 300, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + static int __init mtk_gpt_init(struct device_node *node) { - struct mtk_clock_event_device *evt; - struct resource res; - unsigned long rate = 0; - struct clk *clk; - - evt = kzalloc(sizeof(*evt), GFP_KERNEL); - if (!evt) - return -ENOMEM; - - evt->dev.name = "mtk_tick"; - evt->dev.rating = 300; - evt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - evt->dev.set_state_shutdown = mtk_gpt_clkevt_shutdown; - evt->dev.set_state_periodic = mtk_gpt_clkevt_set_periodic; - evt->dev.set_state_oneshot = mtk_gpt_clkevt_shutdown; - evt->dev.tick_resume = mtk_gpt_clkevt_shutdown; - evt->dev.set_next_event = mtk_gpt_clkevt_next_event; - evt->dev.cpumask = cpu_possible_mask; - - evt->gpt_base = of_io_request_and_map(node, 0, "mtk-timer-gpt"); - if (IS_ERR(evt->gpt_base)) { - pr_err("Can't get resource\n"); - goto err_kzalloc; - } - - evt->dev.irq = irq_of_parse_and_map(node, 0); - if (evt->dev.irq <= 0) { - pr_err("Can't parse IRQ\n"); - goto err_mem; - } - - clk = of_clk_get(node, 0); - if (IS_ERR(clk)) { - pr_err("Can't get timer clock\n"); - goto err_irq; - } - - if (clk_prepare_enable(clk)) { - pr_err("Can't prepare clock\n"); - goto err_clk_put; - } - rate = clk_get_rate(clk); - - if (request_irq(evt->dev.irq, mtk_gpt_interrupt, - IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) { - pr_err("failed to setup irq %d\n", evt->dev.irq); - goto err_clk_disable; - } - - evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); + int ret; + + to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown; + to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic; + to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown; + to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown; + to.clkevt.set_next_event = mtk_gpt_clkevt_next_event; + to.of_irq.handler = mtk_gpt_interrupt; + + ret = timer_of_init(node, &to); + if (ret) + goto err; /* Configure clock source */ - mtk_gpt_setup(evt, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN); - clocksource_mmio_init(evt->gpt_base + GPT_CNT_REG(TIMER_CLK_SRC), - node->name, rate, 300, 32, clocksource_mmio_readl_up); - gpt_sched_reg = evt->gpt_base + GPT_CNT_REG(TIMER_CLK_SRC); - sched_clock_register(mtk_gpt_read_sched_clock, 32, rate); + mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN); + clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC), + node->name, timer_of_rate(&to), 300, 32, + clocksource_mmio_readl_up); + gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC); + sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to)); /* Configure clock event */ - mtk_gpt_setup(evt, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT); - clockevents_config_and_register(&evt->dev, rate, TIMER_SYNC_TICKS, - 0xffffffff); + mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + TIMER_SYNC_TICKS, 0xffffffff); - mtk_gpt_enable_irq(evt, TIMER_CLK_EVT); + mtk_gpt_enable_irq(&to, TIMER_CLK_EVT); return 0; -err_clk_disable: - clk_disable_unprepare(clk); -err_clk_put: - clk_put(clk); -err_irq: - irq_dispose_mapping(evt->dev.irq); -err_mem: - iounmap(evt->gpt_base); - of_address_to_resource(node, 0, &res); - release_mem_region(res.start, resource_size(&res)); -err_kzalloc: - kfree(evt); - - return -EINVAL; +err: + timer_of_cleanup(&to); + return ret; } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init); From patchwork Thu Jul 26 10:15:29 2018 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id g4-v6si982794plm.181.2018.07.26.03.16.33; Thu, 26 Jul 2018 03:16:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DzQ4Hh00; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729521AbeGZLcj (ORCPT + 31 others); Thu, 26 Jul 2018 07:32:39 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:36094 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729031AbeGZLci (ORCPT ); Thu, 26 Jul 2018 07:32:38 -0400 Received: by mail-wr1-f67.google.com with SMTP id h9-v6so1150401wro.3 for ; Thu, 26 Jul 2018 03:16:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GkrEodfqJJ8aTUmNgXy4dk77JThB9rdS+3bHfRD7mVo=; b=DzQ4Hh001XPzoeCUk+CQceEsyAYL5j0ou1m/1yNPw9UpF73LRVq7yxbFjtmH67D3g7 vWDP0Y754GJV6ouq5V25e/9cBhCVSD56X9Nf4fIo8KEm/t80SOMEVtbqUHhWAiB6PP/l DqbNQWui2jGizvLiGXVq3f+JehzIF0QFdclY0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GkrEodfqJJ8aTUmNgXy4dk77JThB9rdS+3bHfRD7mVo=; b=lEszjOb10j2FJ0AIxO8AGIhAcpQP9dnHiLRdOZzKsNDD+2LSiLtifKYO4MR+QBp4VA VysDU+2r6cZbe7nYui5WWPTn5Ze1pvrC7+x+ZAkSl9xDlzQxqXPbSelVTi5jL1sJlY+a BLNohC5gTQFRG51BsJ5n1/w/w3m73PRxHzl1ArP1CV9HJmIjKrrMMZ2w4hDfSQF+p1Db jFeVpJ4r69pjcLxJQ5DBQu6rAouKV70H7F20hpu2BTbKpJABIXRc3nlMdnKcRQXzGSX9 95KZybmGQUYpIucv530gkViD0xj0WAv6Vjy2NjhfLhXuNkr9id6d4JIvtDwhz1m3GJoF zxwg== X-Gm-Message-State: AOUpUlG0HvEOLVGMQArABau/YtNuFuoOBGR7C45uwqQRpS2bzZMbC5gd JZKQgk0ZVDu3io8dfpZTuDJRtw== X-Received: by 2002:adf:e584:: with SMTP id l4-v6mr1024964wrm.190.1532600186925; Thu, 26 Jul 2018 03:16:26 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:35bd:fbdf:74b5:3f51]) by smtp.gmail.com with ESMTPSA id f6-v6sm957303wrp.30.2018.07.26.03.16.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jul 2018 03:16:26 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org, stanley.chu@mediatek.com, baolin.wang@linaro.org, Sudeep.Holla@arm.com, Matthias Brugger , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 6/7] clocksource/drivers/timer-mediatek: Add support for system timer Date: Thu, 26 Jul 2018 12:15:29 +0200 Message-Id: <1532600131-28168-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> References: <014f94f9-54d4-1ee0-aa89-67ca5d221989@free.fr> <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stanley Chu This patch adds a new "System Timer" on the Mediatek SoCs. The System Timer is introduced as an always-on timer being clockevent device for tick-broadcasting. For clock, it is driven by 13 MHz system clock. The implementation uses the system clock with no clock source divider. For interrupt, the clock event timer can be used by all cores. Signed-off-by: Stanley Chu Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-mediatek.c | 104 ++++++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c index e57c4d7..eb10321 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -56,8 +56,86 @@ #define GPT_CNT_REG(val) (0x08 + (0x10 * (val))) #define GPT_CMP_REG(val) (0x0C + (0x10 * (val))) +/* system timer */ +#define SYST_BASE (0x40) + +#define SYST_CON (SYST_BASE + 0x0) +#define SYST_VAL (SYST_BASE + 0x4) + +#define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON) +#define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL) + +/* + * SYST_CON_EN: Clock enable. Shall be set to + * - Start timer countdown. + * - Allow timeout ticks being updated. + * - Allow changing interrupt functions. + * + * SYST_CON_IRQ_EN: Set to allow interrupt. + * + * SYST_CON_IRQ_CLR: Set to clear interrupt. + */ +#define SYST_CON_EN BIT(0) +#define SYST_CON_IRQ_EN BIT(1) +#define SYST_CON_IRQ_CLR BIT(4) + static void __iomem *gpt_sched_reg __read_mostly; +static void mtk_syst_ack_irq(struct timer_of *to) +{ + /* Clear and disable interrupt */ + writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to)); +} + +static irqreturn_t mtk_syst_handler(int irq, void *dev_id) +{ + struct clock_event_device *clkevt = dev_id; + struct timer_of *to = to_timer_of(clkevt); + + mtk_syst_ack_irq(to); + clkevt->event_handler(clkevt); + + return IRQ_HANDLED; +} + +static int mtk_syst_clkevt_next_event(unsigned long ticks, + struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + /* Enable clock to allow timeout tick update later */ + writel(SYST_CON_EN, SYST_CON_REG(to)); + + /* + * Write new timeout ticks. Timer shall start countdown + * after timeout ticks are updated. + */ + writel(ticks, SYST_VAL_REG(to)); + + /* Enable interrupt */ + writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to)); + + return 0; +} + +static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt) +{ + /* Disable timer */ + writel(0, SYST_CON_REG(to_timer_of(clkevt))); + + return 0; +} + +static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt) +{ + return mtk_syst_clkevt_shutdown(clkevt); +} + +static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt) +{ + return 0; +} + static u64 notrace mtk_gpt_read_sched_clock(void) { return readl_relaxed(gpt_sched_reg); @@ -186,6 +264,30 @@ static struct timer_of to = { }, }; +static int __init mtk_syst_init(struct device_node *node) +{ + int ret; + + to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT; + to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown; + to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot; + to.clkevt.tick_resume = mtk_syst_clkevt_resume; + to.clkevt.set_next_event = mtk_syst_clkevt_next_event; + to.of_irq.handler = mtk_syst_handler; + + ret = timer_of_init(node, &to); + if (ret) + goto err; + + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + TIMER_SYNC_TICKS, 0xffffffff); + + return 0; +err: + timer_of_cleanup(&to); + return ret; +} + static int __init mtk_gpt_init(struct device_node *node) { int ret; @@ -218,9 +320,9 @@ static int __init mtk_gpt_init(struct device_node *node) mtk_gpt_enable_irq(&to, TIMER_CLK_EVT); return 0; - err: timer_of_cleanup(&to); return ret; } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init); +TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init); From patchwork Thu Jul 26 10:15:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 142953 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp274064ljj; Thu, 26 Jul 2018 03:16:34 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeOreDQGuTVrWjZovtFgp6+HPhyLE1OwLt+Ny259huWx6NeOQz3wf9LhAPf3s0cJBvL9qsC X-Received: by 2002:a63:2c8e:: with SMTP id s136-v6mr1320803pgs.390.1532600194356; Thu, 26 Jul 2018 03:16:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532600194; cv=none; d=google.com; s=arc-20160816; b=J4OxZZftLSNsfj+Tp64ARuIhb1p3zEvuY0pAjcj8OGxykrMPffsPk3EO1gXrTsDHJx kmmjMqFPR02oLl69MBqnj3HcXREY5gnRajZKjdctZ+Q+g4aATefLXFW92yAUj72Wyz+f m+eiTcDelEs4+TaXQXlucI8iufQ4kUslvuoUfioiH78FRFlrjiwCJgO//2NnfgdjVE2r iWspF2LlWrBtyN9dlAvJ2fd5IIkZQRcn0zkfXvNFs9P0tw8ocNU/bFEZ9EZJk7eYqZNG Q6OsCAl2EAfVwm7Txn6VejY4EIGnB4zP2czfJ1WWVZt2tiyKxDLYg4m4awj8jJtVT87J HaQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=nZok4+MHcZ2Rmmvuy9wXzlMzMAeBIWyc64eLlpaY/ps=; b=jegl2KR69sQsdI9eOPUqdz0SUsOWdsKm1z1B+G3OrxApcfQychwmCmeMtfqUyIhgn4 D7H4Ds+aMkqmL3rm7wHMso/NkKR58zx8HihJG7VWaiyvqImLxP6btMnRQDQSWqYhoVfl +iO1lAg9xKlLHx8x74vBuofG3rv2FF7MwRSHNdNO3ii/RsV0xZP+kEAq4YionJERrCQs fuYZff83saIkQolM4w5zHHv7x5llgXG1mPeTYhwwEwlSppz643LgHstJgvURUZeWGSYe n2+3Io4j3VGP3B4UuoENqdXVQ42FfyEUPIkeIpt9YVTV2SduW3dm0gJz5g8izTLW4nTm 5hkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f4aft561; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v71-v6si1065298pfj.354.2018.07.26.03.16.34; Thu, 26 Jul 2018 03:16:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f4aft561; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729812AbeGZLck (ORCPT + 31 others); Thu, 26 Jul 2018 07:32:40 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:52689 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729391AbeGZLcj (ORCPT ); Thu, 26 Jul 2018 07:32:39 -0400 Received: by mail-wm0-f68.google.com with SMTP id o11-v6so1396845wmh.2 for ; Thu, 26 Jul 2018 03:16:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nZok4+MHcZ2Rmmvuy9wXzlMzMAeBIWyc64eLlpaY/ps=; b=f4aft561/IOAdqJnFPamXdJqu9t25NHwcBW8/SopBLaT9zJrBGIGb6Dfzs8S7FNdHC PMjEKVQ3YQnoFdGw4TYpJkGKVbh7XFyMPBI/fyBd4M2AdrFSvK/Wdbl1yVV9ESJL+cRm OLe0s0UsDWvkmNOgy4W8XhchgzeWaheK9IutE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nZok4+MHcZ2Rmmvuy9wXzlMzMAeBIWyc64eLlpaY/ps=; b=UEY3ybafnOkpgzcXBvrRPAJx4kfOeHnneqoBeZwLt4HC9QHSyfuLwxGTOIBsxlNJI/ q0Givkq3lJXL375/jKVFfBWxYd1Guut4VzQwsY44b2nbffJAbVuQhw80GF9AipEcEIVL 8eUPuZzkD2z5zAegOx2hcEF86iftZAcskSHe60HNyxyVUQvOYlYIsBO1+pKjSoE4r8Tq DARvVptraomiKbRbACJbfxxdcU2UkE/pe61aHZmttbQ8WzDDvL6mRvV/tE58wFlH8VC7 xkjKUQnru0xDeeuLslD8jtRSzMQGLuFlEEtQnWCmHjFWF4xngb+uU0UvPQplud7dJnCg G2iw== X-Gm-Message-State: AOUpUlGgEVp7XJN5jI+uS8cm3kfi1gq0MizmAVS4RYJMPZMbgOO9FDYf NasnYs1ojhQD431uxFmk8loScA== X-Received: by 2002:a1c:80b:: with SMTP id 11-v6mr1204834wmi.125.1532600188821; Thu, 26 Jul 2018 03:16:28 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:879a:6cd0:35bd:fbdf:74b5:3f51]) by smtp.gmail.com with ESMTPSA id f6-v6sm957303wrp.30.2018.07.26.03.16.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jul 2018 03:16:27 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, mingo@kernel.org Cc: linux-kernel@vger.kernel.org, stanley.chu@mediatek.com, baolin.wang@linaro.org, Sudeep.Holla@arm.com, Orson Zhai , Chunyan Zhang Subject: [PATCH 7/7] clocksource/drivers/sprd: Register one always-on timer to compensate suspend time Date: Thu, 26 Jul 2018 12:15:30 +0200 Message-Id: <1532600131-28168-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> References: <014f94f9-54d4-1ee0-aa89-67ca5d221989@free.fr> <1532600131-28168-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Baolin Wang Since the clocksource framework has introduced one suspend clocksource to compensate the suspend time, this patch registers one always-on timer as the suspend clocksource. Signed-off-by: Baolin Wang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-sprd.c | 50 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-sprd.c b/drivers/clocksource/timer-sprd.c index ef9ebea..430cb99 100644 --- a/drivers/clocksource/timer-sprd.c +++ b/drivers/clocksource/timer-sprd.c @@ -156,4 +156,54 @@ static int __init sprd_timer_init(struct device_node *np) return 0; } +static struct timer_of suspend_to = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, +}; + +static u64 sprd_suspend_timer_read(struct clocksource *cs) +{ + return ~(u64)readl_relaxed(timer_of_base(&suspend_to) + + TIMER_VALUE_SHDW_LO) & cs->mask; +} + +static int sprd_suspend_timer_enable(struct clocksource *cs) +{ + sprd_timer_update_counter(timer_of_base(&suspend_to), + TIMER_VALUE_LO_MASK); + sprd_timer_enable(timer_of_base(&suspend_to), TIMER_CTL_PERIOD_MODE); + + return 0; +} + +static void sprd_suspend_timer_disable(struct clocksource *cs) +{ + sprd_timer_disable(timer_of_base(&suspend_to)); +} + +static struct clocksource suspend_clocksource = { + .name = "sprd_suspend_timer", + .rating = 200, + .read = sprd_suspend_timer_read, + .enable = sprd_suspend_timer_enable, + .disable = sprd_suspend_timer_disable, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, +}; + +static int __init sprd_suspend_timer_init(struct device_node *np) +{ + int ret; + + ret = timer_of_init(np, &suspend_to); + if (ret) + return ret; + + clocksource_register_hz(&suspend_clocksource, + timer_of_rate(&suspend_to)); + + return 0; +} + TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init); +TIMER_OF_DECLARE(sc9860_persistent_timer, "sprd,sc9860-suspend-timer", + sprd_suspend_timer_init);