From patchwork Sat Jun 12 02:59:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deren Wu X-Patchwork-Id: 459419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16492C48BE6 for ; Sat, 12 Jun 2021 02:59:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E79F960FE5 for ; Sat, 12 Jun 2021 02:59:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229976AbhFLDBf (ORCPT ); Fri, 11 Jun 2021 23:01:35 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:57186 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229584AbhFLDBf (ORCPT ); Fri, 11 Jun 2021 23:01:35 -0400 X-UUID: 854ef98a33a24aa5983fb67f7505aa44-20210612 X-UUID: 854ef98a33a24aa5983fb67f7505aa44-20210612 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 280069896; Sat, 12 Jun 2021 10:59:32 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 12 Jun 2021 10:59:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 12 Jun 2021 10:59:29 +0800 From: Deren Wu To: Felix Fietkau , Lorenzo Bianconi CC: Sean Wang , Soul Huang , YN Chen , Leon Yen , Eric-SY Chang , Deren Wu , KM Lin , Robin Chiu , CH Yeh , Posh Sun , Eric Liang , Stella Chang , , , linux-wireless , linux-mediatek , Deren Wu Subject: [PATCH] mt76: mt7921: introduce PCIe ASPM support (L0s/L1/L1ss) Date: Sat, 12 Jun 2021 10:59:26 +0800 Message-ID: X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Deren Wu for better power consumption, default enable PCIe ASPM Tested-by: Leon Yen Signed-off-by: Deren Wu --- .../net/wireless/mediatek/mt76/mt7921/pci.c | 68 ++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c index 13263f50dc00..5358836bb00e 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7921/pci.c +++ b/drivers/net/wireless/mediatek/mt76/mt7921/pci.c @@ -88,6 +88,72 @@ static void mt7921_irq_tasklet(unsigned long data) napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); } +static void mt7921_pci_config_L1(struct pci_dev *pdev, u8 enable) +{ + u32 reg32; + int pos; + + if (!pdev) + return; + + /* capability check */ + pos = pdev->pcie_cap; + pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); + if (!(reg32 & PCI_EXP_LNKCAP_ASPMS)) { + dev_info(&pdev->dev, "ASPM L1: Invalid cap 0x%X\n", reg32); + return; + } + + /* set config */ + pci_read_config_dword(pdev, pos + PCI_EXP_LNKCTL, ®32); + if (enable) + reg32 |= (PCI_EXP_LNKCTL_ASPMC); + else + reg32 &= ~(PCI_EXP_LNKCTL_ASPMC); + dev_dbg(&pdev->dev, "%s ASPM L1\n", (enable) ? "enable" : "disable"); + + pci_write_config_dword(pdev, pos + PCI_EXP_LNKCTL, reg32); +} + +static void mt7921_pci_config_L1ss(struct pci_dev *pdev, u8 enable) +{ +#define PCIE_L1SS_CAP_CHK \ + (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2) +#define PCIE_L1SS_CTL_CHK \ + (PCI_L1SS_CTL1_ASPM_L1_1 | PCI_L1SS_CTL1_ASPM_L1_2) + + int pos; + u32 reg32; + + if (!pdev) + return; + + /* capability check */ + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); + pci_read_config_dword(pdev, pos + PCI_L1SS_CAP, ®32); + if (!(reg32 & (PCIE_L1SS_CAP_CHK))) { + dev_info(&pdev->dev, "ASPM L1SS: Invalid cap 0x%X\n", reg32); + return; + } + + /* set config */ + pci_read_config_dword(pdev, pos + PCI_L1SS_CTL1, ®32); + if (enable) + reg32 |= (PCIE_L1SS_CTL_CHK); + else + reg32 &= ~(PCIE_L1SS_CTL_CHK); + + dev_dbg(&pdev->dev, "%s ASPM L1SS\n", (enable) ? "enable" : "disable"); + + pci_write_config_dword(pdev, pos + PCI_L1SS_CTL1, reg32); +} + +void mt7921_pci_enable_aspm(struct pci_dev *pdev) +{ + mt7921_pci_config_L1ss(pdev, true); + mt7921_pci_config_L1(pdev, true); +} + static int mt7921_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -131,7 +197,7 @@ static int mt7921_pci_probe(struct pci_dev *pdev, if (ret) goto err_free_pci_vec; - mt76_pci_disable_aspm(pdev); + mt7921_pci_enable_aspm(pdev); mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops, &drv_ops);