From patchwork Sun Jun 13 07:38:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 459730 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C27AAC49360 for ; Sun, 13 Jun 2021 07:41:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A853161075 for ; Sun, 13 Jun 2021 07:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231704AbhFMHnv (ORCPT ); Sun, 13 Jun 2021 03:43:51 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6342 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231136AbhFMHnh (ORCPT ); Sun, 13 Jun 2021 03:43:37 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.56]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4G2mdG415tz6x8m; Sun, 13 Jun 2021 15:37:38 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:34 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:34 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH net-next 01/11] net: z85230: remove redundant blank lines Date: Sun, 13 Jun 2021 15:38:13 +0800 Message-ID: <1623569903-47930-2-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> References: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li This patch removes some redundant blank lines. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 34 +--------------------------------- 1 file changed, 1 insertion(+), 33 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index 002b8c99..f074cb1 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -55,7 +55,6 @@ #include "z85230.h" - /** * z8530_read_port - Architecture specific interface function * @p: port to read @@ -95,7 +94,6 @@ static inline int z8530_read_port(unsigned long p) * dread 5uS sanity delay. */ - static inline void z8530_write_port(unsigned long p, u8 d) { outb(d,Z8530_PORT_OF(p)); @@ -103,12 +101,9 @@ static inline void z8530_write_port(unsigned long p, u8 d) udelay(5); } - - static void z8530_rx_done(struct z8530_channel *c); static void z8530_tx_done(struct z8530_channel *c); - /** * read_zsreg - Read a register from a Z85230 * @c: Z8530 channel to read from (2 per chip) @@ -159,7 +154,6 @@ static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val) if(reg) z8530_write_port(c->ctrlio, reg); z8530_write_port(c->ctrlio, val); - } /** @@ -182,8 +176,6 @@ static inline void write_zsctrl(struct z8530_channel *c, u8 val) * * Write directly to the data register on the Z8530 */ - - static inline void write_zsdata(struct z8530_channel *c, u8 val) { z8530_write_port(c->dataio, val); @@ -204,7 +196,6 @@ EXPORT_SYMBOL(z8530_dead_port); * Register loading parameters for currently supported circuit types */ - /* * Data clocked by telco end. This is the correct data for the UK * "kilostream" service, and most other similar services. @@ -352,7 +343,6 @@ static void z8530_rx(struct z8530_channel *c) if(stat&END_FR) { - /* * Error ? */ @@ -392,7 +382,6 @@ static void z8530_rx(struct z8530_channel *c) write_zsctrl(c, RES_H_IUS); } - /** * z8530_tx - Handle a PIO transmit event * @c: Z8530 channel to process @@ -423,7 +412,6 @@ static void z8530_tx(struct z8530_channel *c) } } - /* * End of frame TX - fire another one */ @@ -474,7 +462,6 @@ static void z8530_status(struct z8530_channel *chan) if (chan->netdevice) netif_carrier_off(chan->netdevice); } - } write_zsctrl(chan, RES_EXT_INT); write_zsctrl(chan, RES_H_IUS); @@ -564,7 +551,6 @@ static void z8530_dma_status(struct z8530_channel *chan) chan->status=status; - if(chan->dma_tx) { if(status&TxEOM) @@ -621,7 +607,6 @@ static struct z8530_irqhandler z8530_txdma_sync = { * (eg the MacII) we must clear the interrupt cause or die. */ - static void z8530_rx_clear(struct z8530_channel *c) { /* @@ -680,7 +665,6 @@ struct z8530_irqhandler z8530_nop = { .status = z8530_status_clear, }; - EXPORT_SYMBOL(z8530_nop); /** @@ -718,7 +702,6 @@ irqreturn_t z8530_interrupt(int irq, void *dev_id) while(++work<5000) { - intr = read_zsreg(&dev->chanA, R3); if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT))) break; @@ -772,7 +755,6 @@ static const u8 reg_init[16]= 0x55,0,0,0 }; - /** * z8530_sync_open - Open a Z8530 channel for PIO * @dev: The network interface we are using @@ -808,7 +790,6 @@ int z8530_sync_open(struct net_device *dev, struct z8530_channel *c) return 0; } - EXPORT_SYMBOL(z8530_sync_open); /** @@ -1070,7 +1051,6 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2; - spin_lock_irqsave(c->lock, cflags); /* @@ -1150,7 +1130,6 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) unsigned long dflags, cflags; u8 chk; - spin_lock_irqsave(c->lock, cflags); c->irqs = &z8530_nop; @@ -1195,10 +1174,8 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) return 0; } - EXPORT_SYMBOL(z8530_sync_txdma_close); - /* * Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny * it exists... @@ -1333,7 +1310,6 @@ int z8530_init(struct z8530_dev *dev) return ret; } - EXPORT_SYMBOL(z8530_init); /** @@ -1408,7 +1384,6 @@ int z8530_channel_load(struct z8530_channel *c, u8 *rtable) EXPORT_SYMBOL(z8530_channel_load); - /** * z8530_tx_begin - Begin packet transmission * @c: The Z8530 channel to kick @@ -1455,8 +1430,7 @@ static void z8530_tx_begin(struct z8530_channel *c) else { c->txcount=c->tx_skb->len; - - + if(c->dma_tx) { /* @@ -1490,7 +1464,6 @@ static void z8530_tx_begin(struct z8530_channel *c) } else { - /* ABUNDER off */ write_zsreg(c, R10, c->regs[10]); write_zsctrl(c, RES_Tx_CRC); @@ -1500,7 +1473,6 @@ static void z8530_tx_begin(struct z8530_channel *c) write_zsreg(c, R8, *c->tx_ptr++); c->txcount--; } - } } /* @@ -1573,14 +1545,12 @@ static void z8530_rx_done(struct z8530_channel *c) /* * Is our receive engine in DMA mode */ - if(c->rxdma_on) { /* * Save the ready state and the buffer currently * being used as the DMA target */ - int ready=c->dma_ready; unsigned char *rxb=c->rx_buf[c->dma_num]; unsigned long flags; @@ -1588,7 +1558,6 @@ static void z8530_rx_done(struct z8530_channel *c) /* * Complete this DMA. Necessary to find the length */ - flags=claim_dma_lock(); disable_dma(c->rxdma); @@ -1731,7 +1700,6 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) if(c->tx_next_skb) return NETDEV_TX_BUSY; - /* PC SPECIFIC - DMA limits */ /* From patchwork Sun Jun 13 07:38:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 459732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A410C48BDF for ; Sun, 13 Jun 2021 07:41:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EFF986023F for ; Sun, 13 Jun 2021 07:41:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231511AbhFMHnl (ORCPT ); Sun, 13 Jun 2021 03:43:41 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4055 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230525AbhFMHnh (ORCPT ); Sun, 13 Jun 2021 03:43:37 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G2mc52frzzWr0x; Sun, 13 Jun 2021 15:36:37 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:34 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:34 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH net-next 02/11] net: z85230: add blank line after declarations Date: Sun, 13 Jun 2021 15:38:14 +0800 Message-ID: <1623569903-47930-3-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> References: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li This patch fixes the checkpatch error about missing a blank line after declarations. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index f074cb1..3036d58 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -74,6 +74,7 @@ static inline int z8530_read_port(unsigned long p) { u8 r=inb(Z8530_PORT_OF(p)); + if(p&Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */ udelay(5); return r; @@ -133,6 +134,7 @@ static inline u8 read_zsreg(struct z8530_channel *c, u8 reg) static inline u8 read_zsdata(struct z8530_channel *c) { u8 r; + r=z8530_read_port(c->dataio); return r; } @@ -653,6 +655,7 @@ static void z8530_tx_clear(struct z8530_channel *c) static void z8530_status_clear(struct z8530_channel *chan) { u8 status=read_zsreg(chan, R0); + if(status&TxEOM) write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_EXT_INT); @@ -1360,6 +1363,7 @@ int z8530_channel_load(struct z8530_channel *c, u8 *rtable) while(*rtable!=255) { int reg=*rtable++; + if(reg>0x0F) write_zsreg(c, R15, c->regs[15]|1); write_zsreg(c, reg&0x0F, *rtable); @@ -1401,6 +1405,7 @@ EXPORT_SYMBOL(z8530_channel_load); static void z8530_tx_begin(struct z8530_channel *c) { unsigned long flags; + if(c->tx_skb) return; @@ -1672,6 +1677,7 @@ static void z8530_rx_done(struct z8530_channel *c) static inline int spans_boundary(struct sk_buff *skb) { unsigned long a=(unsigned long)skb->data; + a^=(a+skb->len); if(a&0x00010000) /* If the 64K bit is different.. */ return 1; From patchwork Sun Jun 13 07:38:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 459733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C85AAC48BCF for ; Sun, 13 Jun 2021 07:41:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE5BA61075 for ; Sun, 13 Jun 2021 07:41:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231294AbhFMHnk (ORCPT ); Sun, 13 Jun 2021 03:43:40 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4056 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229777AbhFMHnh (ORCPT ); Sun, 13 Jun 2021 03:43:37 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G2mc5632tzWr8k; Sun, 13 Jun 2021 15:36:37 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:35 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:34 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH net-next 05/11] net: z85230: replace comparison to NULL with "!skb" Date: Sun, 13 Jun 2021 15:38:17 +0800 Message-ID: <1623569903-47930-6-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> References: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li According to the chackpatch.pl, comparison to NULL could be written "!skb". Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index f815bb5..ced746d 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -851,12 +851,12 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) return -EMSGSIZE; c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); - if(c->rx_buf[0]==NULL) + if (!c->rx_buf[0]) return -ENOBUFS; c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2; c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); - if(c->tx_dma_buf[0]==NULL) + if (!c->tx_dma_buf[0]) { free_page((unsigned long)c->rx_buf[0]); c->rx_buf[0]=NULL; @@ -1039,7 +1039,7 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) return -EMSGSIZE; c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); - if(c->tx_dma_buf[0]==NULL) + if (!c->tx_dma_buf[0]) return -ENOBUFS; c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2; @@ -1397,7 +1397,7 @@ static void z8530_tx_begin(struct z8530_channel *c) c->tx_next_skb=NULL; c->tx_ptr=c->tx_next_ptr; - if(c->tx_skb==NULL) + if (!c->tx_skb) { /* Idle on */ if(c->dma_tx) @@ -1486,7 +1486,7 @@ static void z8530_tx_done(struct z8530_channel *c) struct sk_buff *skb; /* Actually this can happen.*/ - if (c->tx_skb == NULL) + if (!c->tx_skb) return; skb = c->tx_skb; @@ -1589,7 +1589,7 @@ static void z8530_rx_done(struct z8530_channel *c) */ skb = dev_alloc_skb(ct); - if (skb == NULL) { + if (!skb) { c->netdevice->stats.rx_dropped++; netdev_warn(c->netdevice, "Memory squeeze\n"); } else { @@ -1630,7 +1630,7 @@ static void z8530_rx_done(struct z8530_channel *c) RT_UNLOCK; c->skb2 = dev_alloc_skb(c->mtu); - if (c->skb2 == NULL) + if (!c->skb2) netdev_warn(c->netdevice, "memory squeeze\n"); else skb_put(c->skb2, c->mtu); From patchwork Sun Jun 13 07:38:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 459731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4CC5C48BE8 for ; Sun, 13 Jun 2021 07:41:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B217F6109F for ; Sun, 13 Jun 2021 07:41:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231649AbhFMHnq (ORCPT ); Sun, 13 Jun 2021 03:43:46 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:6343 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231173AbhFMHnh (ORCPT ); Sun, 13 Jun 2021 03:43:37 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.57]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4G2mdH5Ysyz6x8r; Sun, 13 Jun 2021 15:37:39 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:35 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:34 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH net-next 07/11] net: z85230: fix the code style issue about "if..else.." Date: Sun, 13 Jun 2021 15:38:19 +0800 Message-ID: <1623569903-47930-8-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> References: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li According to the chackpatch.pl, else should follow close brace '}', braces {} should be used on all arms of this statement. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index a3a2051..556de05 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -354,9 +354,7 @@ static void z8530_rx(struct z8530_channel *c) /* printk("crc error\n"); */ } /* Shove the frame upstream */ - } - else - { + } else { /* Drop the lock for RX processing, or * there are deadlocks */ @@ -489,9 +487,7 @@ static void z8530_dma_rx(struct z8530_channel *chan) } write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_H_IUS); - } - else - { + } else { /* DMA is off right now, drain the slow way */ z8530_rx(chan); } @@ -1379,9 +1375,7 @@ static void z8530_tx_begin(struct z8530_channel *c) release_dma_lock(flags); } c->txcount=0; - } - else - { + } else { c->txcount=c->tx_skb->len; if(c->dma_tx) @@ -1412,9 +1406,7 @@ static void z8530_tx_begin(struct z8530_channel *c) release_dma_lock(flags); write_zsctrl(c, RES_EOM_L); write_zsreg(c, R5, c->regs[R5]|TxENAB); - } - else - { + } else { /* ABUNDER off */ write_zsreg(c, R10, c->regs[10]); write_zsctrl(c, RES_Tx_CRC); @@ -1530,12 +1522,12 @@ static void z8530_rx_done(struct z8530_channel *c) * from passing */ write_zsreg(c, R0, RES_Rx_CRC); - } - else + } else { /* Can't occur as we dont reenable the DMA irq until * after the flip is done */ netdev_warn(c->netdevice, "DMA flip overrun!\n"); + } release_dma_lock(flags); @@ -1661,9 +1653,9 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used]; c->tx_dma_used^=1; /* Flip temp buffer */ skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len); + } else { + c->tx_next_ptr = skb->data; } - else - c->tx_next_ptr=skb->data; RT_LOCK; c->tx_next_skb=skb; RT_UNLOCK; From patchwork Sun Jun 13 07:38:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 459728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A42F6C49360 for ; Sun, 13 Jun 2021 07:41:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8986A611ED for ; Sun, 13 Jun 2021 07:41:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231755AbhFMHn4 (ORCPT ); Sun, 13 Jun 2021 03:43:56 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:9108 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231485AbhFMHnn (ORCPT ); Sun, 13 Jun 2021 03:43:43 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G2mfb2GvJzZcv4; Sun, 13 Jun 2021 15:38:47 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:35 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:35 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH net-next 08/11] net: z85230: remove trailing whitespaces Date: Sun, 13 Jun 2021 15:38:20 +0800 Message-ID: <1623569903-47930-9-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> References: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li This patch removes trailing whitespaces. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 224 ++++++++++++++++++++++------------------------- 1 file changed, 105 insertions(+), 119 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index 556de05..ea4628c 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -10,7 +10,7 @@ * Asynchronous mode dropped for 2.2. For 2.5 we will attempt the * unification of all the Z85x30 asynchronous drivers for real. * - * DMA now uses get_free_page as kmalloc buffers may span a 64K + * DMA now uses get_free_page as kmalloc buffers may span a 64K * boundary. * * Modified for SMP safety and SMP locking by Alan Cox @@ -59,7 +59,7 @@ * * Provided port access methods. The Comtrol SV11 requires no delays * between accesses and uses PC I/O. Some drivers may need a 5uS delay - * + * * In the longer term this should become an architecture specific * section so that this can become a generic driver interface for all * platforms. For now we only handle PC I/O ports with or without the @@ -104,16 +104,16 @@ static void z8530_rx_done(struct z8530_channel *c); static void z8530_tx_done(struct z8530_channel *c); /** - * read_zsreg - Read a register from a Z85230 + * read_zsreg - Read a register from a Z85230 * @c: Z8530 channel to read from (2 per chip) * @reg: Register to read * FIXME: Use a spinlock. - * + * * Most of the Z8530 registers are indexed off the control registers. * A read is done by writing to the control register and reading the * register back. The caller must hold the lock */ - + static inline u8 read_zsreg(struct z8530_channel *c, u8 reg) { if(reg) @@ -183,7 +183,7 @@ static inline void write_zsdata(struct z8530_channel *c, u8 val) /* Register loading parameters for a dead port */ - + u8 z8530_dead_port[]= { 255 @@ -196,7 +196,7 @@ EXPORT_SYMBOL(z8530_dead_port); /* Data clocked by telco end. This is the correct data for the UK * "kilostream" service, and most other similar services. */ - + u8 z8530_hdlc_kilostream[]= { 4, SYNC_ENAB|SDLC|X1CLK, @@ -219,7 +219,7 @@ EXPORT_SYMBOL(z8530_hdlc_kilostream); /* As above but for enhanced chips. */ - + u8 z8530_hdlc_kilostream_85230[]= { 4, SYNC_ENAB|SDLC|X1CLK, @@ -237,7 +237,7 @@ u8 z8530_hdlc_kilostream_85230[]= 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx, 9, NV|MIE|NORESET, 23, 3, /* Extended mode AUTO TX and EOM*/ - + 255 }; EXPORT_SYMBOL(z8530_hdlc_kilostream_85230); @@ -246,14 +246,14 @@ EXPORT_SYMBOL(z8530_hdlc_kilostream_85230); * z8530_flush_fifo - Flush on chip RX FIFO * @c: Channel to flush * - * Flush the receive FIFO. There is no specific option for this, we + * Flush the receive FIFO. There is no specific option for this, we * blindly read bytes and discard them. Reading when there is no data * is harmless. The 8530 has a 4 byte FIFO, the 85230 has 8 bytes. - * + * * All locking is handled for the caller. On return data may still be * present if it arrived during the flush. */ - + static void z8530_flush_fifo(struct z8530_channel *c) { read_zsreg(c, R1); @@ -267,7 +267,7 @@ static void z8530_flush_fifo(struct z8530_channel *c) read_zsreg(c, R1); read_zsreg(c, R1); } -} +} /** * z8530_rtsdtr - Control the outgoing DTS/RTS line @@ -293,7 +293,7 @@ static void z8530_rtsdtr(struct z8530_channel *c, int set) * z8530_rx - Handle a PIO receive event * @c: Z8530 channel to process * - * Receive handler for receiving in PIO mode. This is much like the + * Receive handler for receiving in PIO mode. This is much like the * async one but not quite the same or as complex * * Note: Its intended that this handler can easily be separated from @@ -306,13 +306,13 @@ static void z8530_rtsdtr(struct z8530_channel *c, int set) * other code - this is true in the RT case too. * * We only cover the sync cases for this. If you want 2Mbit async - * do it yourself but consider medical assistance first. This non DMA - * synchronous mode is portable code. The DMA mode assumes PCI like + * do it yourself but consider medical assistance first. This non DMA + * synchronous mode is portable code. The DMA mode assumes PCI like * ISA DMA * * Called with the device lock held */ - + static void z8530_rx(struct z8530_channel *c) { u8 ch,stat; @@ -324,7 +324,7 @@ static void z8530_rx(struct z8530_channel *c) break; ch=read_zsdata(c); stat=read_zsreg(c, R1); - + /* Overrun ? */ if(c->count < c->max) @@ -378,7 +378,7 @@ static void z8530_rx(struct z8530_channel *c) * in as possible, its quite possible that we won't keep up with the * data rate otherwise. */ - + static void z8530_tx(struct z8530_channel *c) { while(c->txcount) { @@ -400,10 +400,10 @@ static void z8530_tx(struct z8530_channel *c) /* End of frame TX - fire another one */ - + write_zsctrl(c, RES_Tx_P); - z8530_tx_done(c); + z8530_tx_done(c); write_zsctrl(c, RES_H_IUS); } @@ -468,29 +468,29 @@ EXPORT_SYMBOL(z8530_sync); * events are handled by the DMA hardware. We get a kick here only if * a frame ended. */ - + static void z8530_dma_rx(struct z8530_channel *chan) { if(chan->rxdma_on) { /* Special condition check only */ u8 status; - + read_zsreg(chan, R7); read_zsreg(chan, R6); - + status=read_zsreg(chan, R1); - + if(status&END_FR) { z8530_rx_done(chan); /* Fire up the next one */ - } + } write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_H_IUS); } else { /* DMA is off right now, drain the slow way */ z8530_rx(chan); - } + } } /** @@ -500,7 +500,6 @@ static void z8530_dma_rx(struct z8530_channel *chan) * We have received an interrupt while doing DMA transmissions. It * shouldn't happen. Scream loudly if it does. */ - static void z8530_dma_tx(struct z8530_channel *chan) { if(!chan->dma_tx) @@ -517,20 +516,19 @@ static void z8530_dma_tx(struct z8530_channel *chan) /** * z8530_dma_status - Handle a DMA status exception * @chan: Z8530 channel to process - * + * * A status event occurred on the Z8530. We receive these for two reasons * when in DMA mode. Firstly if we finished a packet transfer we get one * and kick the next packet out. Secondly we may see a DCD change. * */ - static void z8530_dma_status(struct z8530_channel *chan) { u8 status, altered; status=read_zsreg(chan, R0); altered=chan->status^status; - + chan->status=status; if(chan->dma_tx) @@ -538,10 +536,10 @@ static void z8530_dma_status(struct z8530_channel *chan) if(status&TxEOM) { unsigned long flags; - + flags=claim_dma_lock(); disable_dma(chan->txdma); - clear_dma_ff(chan->txdma); + clear_dma_ff(chan->txdma); chan->txdma_on=0; release_dma_lock(flags); z8530_tx_done(chan); @@ -597,7 +595,7 @@ static void z8530_rx_clear(struct z8530_channel *c) read_zsdata(c); stat=read_zsreg(c, R1); - + if(stat&END_FR) write_zsctrl(c, RES_Rx_CRC); /* Clear irq @@ -670,7 +668,7 @@ irqreturn_t z8530_interrupt(int irq, void *dev_id) static int locker; int work=0; struct z8530_irqhandler *irqs; - + if(locker) { pr_err("IRQ re-enter\n"); @@ -685,15 +683,15 @@ irqreturn_t z8530_interrupt(int irq, void *dev_id) intr = read_zsreg(&dev->chanA, R3); if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT))) break; - + /* This holds the IRQ status. On the 8530 you must read it * from chan A even though it applies to the whole chip */ - + /* Now walk the chip and see what it is wanting - it may be * an IRQ for someone else remember */ - + irqs=dev->chanA.irqs; if(intr & (CHARxIP|CHATxIP|CHAEXT)) @@ -744,7 +742,6 @@ static const u8 reg_init[16]= * Switch a Z8530 into synchronous mode without DMA assist. We * raise the RTS/DTR and commence network operation. */ - int z8530_sync_open(struct net_device *dev, struct z8530_channel *c) { unsigned long flags; @@ -780,17 +777,16 @@ EXPORT_SYMBOL(z8530_sync_open); * Close down a Z8530 interface and switch its interrupt handlers * to discard future events. */ - int z8530_sync_close(struct net_device *dev, struct z8530_channel *c) { u8 chk; unsigned long flags; - + spin_lock_irqsave(c->lock, flags); c->irqs = &z8530_nop; c->max = 0; c->sync = 0; - + chk=read_zsreg(c,R0); write_zsreg(c, R3, c->regs[R3]); z8530_rtsdtr(c,0); @@ -809,11 +805,10 @@ EXPORT_SYMBOL(z8530_sync_close); * ISA DMA channels must be available for this to work. We assume ISA * DMA driven I/O and PC limits on access. */ - int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) { unsigned long cflags, dflags; - + c->sync = 1; c->mtu = dev->mtu+64; c->count = 0; @@ -829,15 +824,15 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) * Everyone runs 1500 mtu or less on wan links so this * should be fine. */ - + if(c->mtu > PAGE_SIZE/2) return -EMSGSIZE; - + c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); if (!c->rx_buf[0]) return -ENOBUFS; c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2; - + c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); if (!c->tx_dma_buf[0]) { @@ -851,7 +846,7 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->dma_tx = 1; c->dma_num=0; c->dma_ready=1; - + /* Enable DMA control mode */ @@ -859,15 +854,15 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) /* TX DMA via DIR/REQ */ - + c->regs[R14]|= DTRREQ; - write_zsreg(c, R14, c->regs[R14]); + write_zsreg(c, R14, c->regs[R14]); c->regs[R1]&= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); /* RX DMA via W/Req - */ + */ c->regs[R1]|= WT_FN_RDYFN; c->regs[R1]|= WT_RDY_RT; @@ -875,16 +870,16 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->regs[R1]&= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); c->regs[R1]|= WT_RDY_ENAB; - write_zsreg(c, R1, c->regs[R1]); + write_zsreg(c, R1, c->regs[R1]); /* DMA interrupts */ /* Set up the DMA configuration - */ - + */ + dflags=claim_dma_lock(); - + disable_dma(c->rxdma); clear_dma_ff(c->rxdma); set_dma_mode(c->rxdma, DMA_MODE_READ|0x10); @@ -896,7 +891,7 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) clear_dma_ff(c->txdma); set_dma_mode(c->txdma, DMA_MODE_WRITE); disable_dma(c->txdma); - + release_dma_lock(dflags); /* Select the DMA interrupt handlers @@ -905,13 +900,13 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->rxdma_on = 1; c->txdma_on = 1; c->tx_dma_used = 1; - + c->irqs = &z8530_dma_sync; z8530_rtsdtr(c,1); write_zsreg(c, R3, c->regs[R3]|RxENABLE); spin_unlock_irqrestore(c->lock, cflags); - + return 0; } EXPORT_SYMBOL(z8530_sync_dma_open); @@ -924,29 +919,28 @@ EXPORT_SYMBOL(z8530_sync_dma_open); * Shut down a DMA mode synchronous interface. Halt the DMA, and * free the buffers. */ - int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c) { u8 chk; unsigned long flags; - + c->irqs = &z8530_nop; c->max = 0; c->sync = 0; /* Disable the PC DMA channels */ - - flags=claim_dma_lock(); + + flags = claim_dma_lock(); disable_dma(c->rxdma); clear_dma_ff(c->rxdma); - + c->rxdma_on = 0; - + disable_dma(c->txdma); clear_dma_ff(c->txdma); release_dma_lock(flags); - + c->txdma_on = 0; c->tx_dma_used = 0; @@ -954,15 +948,15 @@ int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c) /* Disable DMA control mode */ - + c->regs[R1]&= ~WT_RDY_ENAB; - write_zsreg(c, R1, c->regs[R1]); + write_zsreg(c, R1, c->regs[R1]); c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); c->regs[R1]|= INT_ALL_Rx; write_zsreg(c, R1, c->regs[R1]); c->regs[R14]&= ~DTRREQ; - write_zsreg(c, R14, c->regs[R14]); - + write_zsreg(c, R14, c->regs[R14]); + if(c->rx_buf[0]) { free_page((unsigned long)c->rx_buf[0]); @@ -1008,10 +1002,10 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) * Everyone runs 1500 mtu or less on wan links so this * should be fine. */ - + if(c->mtu > PAGE_SIZE/2) return -EMSGSIZE; - + c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); if (!c->tx_dma_buf[0]) return -ENOBUFS; @@ -1031,7 +1025,7 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->rxdma_on = 0; c->txdma_on = 0; - + c->tx_dma_used=0; c->dma_num=0; c->dma_ready=1; @@ -1043,14 +1037,14 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) /* TX DMA via DIR/REQ */ c->regs[R14]|= DTRREQ; - write_zsreg(c, R14, c->regs[R14]); - + write_zsreg(c, R14, c->regs[R14]); + c->regs[R1]&= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); /* Set up the DMA configuration - */ - + */ + dflags = claim_dma_lock(); disable_dma(c->txdma); @@ -1066,12 +1060,12 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->rxdma_on = 0; c->txdma_on = 1; c->tx_dma_used = 1; - + c->irqs = &z8530_txdma_sync; z8530_rtsdtr(c,1); write_zsreg(c, R3, c->regs[R3]|RxENABLE); spin_unlock_irqrestore(c->lock, cflags); - + return 0; } EXPORT_SYMBOL(z8530_sync_txdma_open); @@ -1081,7 +1075,7 @@ EXPORT_SYMBOL(z8530_sync_txdma_open); * @dev: Network device to detach * @c: Z8530 channel to move into discard mode * - * Shut down a DMA/PIO split mode synchronous interface. Halt the DMA, + * Shut down a DMA/PIO split mode synchronous interface. Halt the DMA, * and free the buffers. */ @@ -1091,14 +1085,14 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) u8 chk; spin_lock_irqsave(c->lock, cflags); - + c->irqs = &z8530_nop; c->max = 0; c->sync = 0; /* Disable the PC DMA channels */ - + dflags = claim_dma_lock(); disable_dma(c->txdma); @@ -1110,15 +1104,15 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) /* Disable DMA control mode */ - + c->regs[R1]&= ~WT_RDY_ENAB; - write_zsreg(c, R1, c->regs[R1]); + write_zsreg(c, R1, c->regs[R1]); c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); c->regs[R1]|= INT_ALL_Rx; write_zsreg(c, R1, c->regs[R1]); c->regs[R14]&= ~DTRREQ; - write_zsreg(c, R14, c->regs[R14]); - + write_zsreg(c, R14, c->regs[R14]); + if(c->tx_dma_buf[0]) { free_page((unsigned long)c->tx_dma_buf[0]); @@ -1136,7 +1130,6 @@ EXPORT_SYMBOL(z8530_sync_txdma_close); /* Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny * it exists... */ - static const char *z8530_type_name[]={ "Z8530", "Z85C30", @@ -1157,7 +1150,7 @@ static const char *z8530_type_name[]={ void z8530_describe(struct z8530_dev *dev, char *mapping, unsigned long io) { pr_info("%s: %s found at %s 0x%lX, IRQ %d\n", - dev->name, + dev->name, z8530_type_name[dev->type], mapping, Z8530_PORT_OF(io), @@ -1167,7 +1160,6 @@ EXPORT_SYMBOL(z8530_describe); /* Locked operation part of the z8530 init code */ - static inline int do_z8530_init(struct z8530_dev *dev) { /* NOP the interrupt handlers first - we might get a @@ -1188,18 +1180,18 @@ static inline int do_z8530_init(struct z8530_dev *dev) write_zsreg(&dev->chanA, R12, 0x55); if(read_zsreg(&dev->chanA, R12)!=0x55) return -ENODEV; - + dev->type=Z8530; /* See the application note. */ - + write_zsreg(&dev->chanA, R15, 0x01); /* If we can set the low bit of R15 then * the chip is enhanced. */ - + if(read_zsreg(&dev->chanA, R15)==0x01) { /* This C30 versus 230 detect is from Klaus Kudielka's dmascc */ @@ -1215,15 +1207,15 @@ static inline int do_z8530_init(struct z8530_dev *dev) * off. Use write_zsext() for these and keep * this bit clear. */ - + write_zsreg(&dev->chanA, R15, 0); /* At this point it looks like the chip is behaving */ - + memcpy(dev->chanA.regs, reg_init, 16); memcpy(dev->chanB.regs, reg_init ,16); - + return 0; } @@ -1266,13 +1258,12 @@ EXPORT_SYMBOL(z8530_init); * z8530_shutdown - Shutdown a Z8530 device * @dev: The Z8530 chip to shutdown * - * We set the interrupt handlers to silence any interrupts. We then + * We set the interrupt handlers to silence any interrupts. We then * reset the chip and wait 100uS to be sure the reset completed. Just * in case the caller then tries to do stuff. * * This is called without the lock held */ - int z8530_shutdown(struct z8530_dev *dev) { unsigned long flags; @@ -1295,7 +1286,7 @@ EXPORT_SYMBOL(z8530_shutdown); * @rtable: table of register, value pairs * FIXME: ioctl to allow user uploaded tables * - * Load a Z8530 channel up from the system data. We use +16 to + * Load a Z8530 channel up from the system data. We use +16 to * indicate the "prime" registers. The value 255 terminates the * table. */ @@ -1339,7 +1330,7 @@ EXPORT_SYMBOL(z8530_channel_load); * * This is the speed sensitive side of transmission. If we are called * and no buffer is being transmitted we commence the next buffer. If - * nothing is queued we idle the sync. + * nothing is queued we idle the sync. * * Note: We are handling this code path in the interrupt path, keep it * fast or bad things will happen. @@ -1353,11 +1344,11 @@ static void z8530_tx_begin(struct z8530_channel *c) if(c->tx_skb) return; - + c->tx_skb=c->tx_next_skb; c->tx_next_skb=NULL; c->tx_ptr=c->tx_next_ptr; - + if (!c->tx_skb) { /* Idle on */ @@ -1383,21 +1374,20 @@ static void z8530_tx_begin(struct z8530_channel *c) /* FIXME. DMA is broken for the original 8530, * on the older parts we need to set a flag and * wait for a further TX interrupt to fire this - * stage off + * stage off */ - + flags=claim_dma_lock(); disable_dma(c->txdma); /* These two are needed by the 8530/85C30 * and must be issued when idling. */ - if(c->dev->type!=Z85230) { write_zsctrl(c, RES_Tx_CRC); write_zsctrl(c, RES_EOM_L); - } + } write_zsreg(c, R10, c->regs[10]&~ABUNDER); clear_dma_ff(c->txdma); set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr)); @@ -1410,9 +1400,8 @@ static void z8530_tx_begin(struct z8530_channel *c) /* ABUNDER off */ write_zsreg(c, R10, c->regs[10]); write_zsctrl(c, RES_Tx_CRC); - - while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP)) - { + + while (c->txcount && (read_zsreg(c, R0) & Tx_BUF_EMP)) { write_zsreg(c, R8, *c->tx_ptr++); c->txcount--; } @@ -1458,7 +1447,6 @@ static void z8530_tx_done(struct z8530_channel *c) * We point the receive handler at this function when idle. Instead * of processing the frames we get to throw them away. */ - void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb) { dev_kfree_skb_any(skb); @@ -1477,7 +1465,6 @@ EXPORT_SYMBOL(z8530_null_rx); * * Called with the lock held */ - static void z8530_rx_done(struct z8530_channel *c) { struct sk_buff *skb; @@ -1495,9 +1482,9 @@ static void z8530_rx_done(struct z8530_channel *c) unsigned long flags; /* Complete this DMA. Necessary to find the length - */ + */ flags=claim_dma_lock(); - + disable_dma(c->rxdma); clear_dma_ff(c->rxdma); c->rxdma_on=0; @@ -1509,7 +1496,7 @@ static void z8530_rx_done(struct z8530_channel *c) /* Normal case: the other slot is free, start the next DMA * into it immediately. */ - + if(ready) { c->dma_num^=1; @@ -1621,18 +1608,17 @@ static inline int spans_boundary(struct sk_buff *skb) * @skb: The packet to kick down the channel * * Queue a packet for transmission. Because we have rather - * hard to hit interrupt latencies for the Z85230 per packet + * hard to hit interrupt latencies for the Z85230 per packet * even in DMA mode we do the flip to DMA buffer if needed here * not in the IRQ. * - * Called from the network code. The lock is not held at this + * Called from the network code. The lock is not held at this * point. */ - netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) { unsigned long flags; - + netif_stop_queue(c->netdevice); if(c->tx_next_skb) return NETDEV_TX_BUSY; @@ -1641,7 +1627,7 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) /* If we will DMA the transmit and its gone over the ISA bus * limit, then copy to the flip buffer */ - + if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb))) { /* Send the flip buffer, and flip the flippy bit. @@ -1659,11 +1645,11 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) RT_LOCK; c->tx_next_skb=skb; RT_UNLOCK; - + spin_lock_irqsave(c->lock, flags); z8530_tx_begin(c); spin_unlock_irqrestore(c->lock, flags); - + return NETDEV_TX_OK; } EXPORT_SYMBOL(z8530_queue_xmit); From patchwork Sun Jun 13 07:38:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 459729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACF88C48BCF for ; Sun, 13 Jun 2021 07:41:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7AE79611CE for ; Sun, 13 Jun 2021 07:41:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231722AbhFMHnw (ORCPT ); Sun, 13 Jun 2021 03:43:52 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:4058 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231210AbhFMHnj (ORCPT ); Sun, 13 Jun 2021 03:43:39 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G2mc65V4nzWrJH; Sun, 13 Jun 2021 15:36:38 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:35 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sun, 13 Jun 2021 15:41:35 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH net-next 09/11] net: z85230: add some required spaces Date: Sun, 13 Jun 2021 15:38:21 +0800 Message-ID: <1623569903-47930-10-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> References: <1623569903-47930-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li Add space required before the open parenthesis '(' and '{'. Add space required after that close brace '}' and ',' Add spaces required around that '=' , '&', '*', '|', '+', '/' and '-'. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 418 ++++++++++++++++++++++++----------------------- 1 file changed, 210 insertions(+), 208 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index ea4628c..35aa032 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -71,9 +71,9 @@ static inline int z8530_read_port(unsigned long p) { - u8 r=inb(Z8530_PORT_OF(p)); + u8 r = inb(Z8530_PORT_OF(p)); - if(p&Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */ + if (p & Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */ udelay(5); return r; } @@ -95,8 +95,8 @@ static inline int z8530_read_port(unsigned long p) static inline void z8530_write_port(unsigned long p, u8 d) { - outb(d,Z8530_PORT_OF(p)); - if(p&Z8530_PORT_SLEEP) + outb(d, Z8530_PORT_OF(p)); + if (p & Z8530_PORT_SLEEP) udelay(5); } @@ -116,7 +116,7 @@ static void z8530_tx_done(struct z8530_channel *c); static inline u8 read_zsreg(struct z8530_channel *c, u8 reg) { - if(reg) + if (reg) z8530_write_port(c->ctrlio, reg); return z8530_read_port(c->ctrlio); } @@ -133,7 +133,7 @@ static inline u8 read_zsdata(struct z8530_channel *c) { u8 r; - r=z8530_read_port(c->dataio); + r = z8530_read_port(c->dataio); return r; } @@ -151,7 +151,7 @@ static inline u8 read_zsdata(struct z8530_channel *c) */ static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val) { - if(reg) + if (reg) z8530_write_port(c->ctrlio, reg); z8530_write_port(c->ctrlio, val); } @@ -184,7 +184,7 @@ static inline void write_zsdata(struct z8530_channel *c, u8 val) /* Register loading parameters for a dead port */ -u8 z8530_dead_port[]= +u8 z8530_dead_port[] = { 255 }; @@ -197,22 +197,22 @@ EXPORT_SYMBOL(z8530_dead_port); * "kilostream" service, and most other similar services. */ -u8 z8530_hdlc_kilostream[]= +u8 z8530_hdlc_kilostream[] = { - 4, SYNC_ENAB|SDLC|X1CLK, + 4, SYNC_ENAB | SDLC | X1CLK, 2, 0, /* No vector */ 1, 0, - 3, ENT_HM|RxCRC_ENAB|Rx8, - 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR, + 3, ENT_HM | RxCRC_ENAB | Rx8, + 5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR, 9, 0, /* Disable interrupts */ 6, 0xFF, 7, FLAG, - 10, ABUNDER|NRZ|CRCPS,/*MARKIDLE ??*/ + 10, ABUNDER | NRZ | CRCPS, /*MARKIDLE ??*/ 11, TCTRxCP, 14, DISDPLL, - 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE, - 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx, - 9, NV|MIE|NORESET, + 15, DCDIE | SYNCIE | CTSIE | TxUIE | BRKIE, + 1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx, + 9, NV | MIE | NORESET, 255 }; EXPORT_SYMBOL(z8530_hdlc_kilostream); @@ -220,22 +220,22 @@ EXPORT_SYMBOL(z8530_hdlc_kilostream); /* As above but for enhanced chips. */ -u8 z8530_hdlc_kilostream_85230[]= +u8 z8530_hdlc_kilostream_85230[] = { - 4, SYNC_ENAB|SDLC|X1CLK, + 4, SYNC_ENAB | SDLC | X1CLK, 2, 0, /* No vector */ 1, 0, - 3, ENT_HM|RxCRC_ENAB|Rx8, - 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR, + 3, ENT_HM | RxCRC_ENAB | Rx8, + 5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR, 9, 0, /* Disable interrupts */ 6, 0xFF, 7, FLAG, - 10, ABUNDER|NRZ|CRCPS, /* MARKIDLE?? */ + 10, ABUNDER | NRZ | CRCPS, /* MARKIDLE?? */ 11, TCTRxCP, 14, DISDPLL, - 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE, - 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx, - 9, NV|MIE|NORESET, + 15, DCDIE | SYNCIE | CTSIE | TxUIE | BRKIE, + 1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx, + 9, NV | MIE | NORESET, 23, 3, /* Extended mode AUTO TX and EOM*/ 255 @@ -260,7 +260,7 @@ static void z8530_flush_fifo(struct z8530_channel *c) read_zsreg(c, R1); read_zsreg(c, R1); read_zsreg(c, R1); - if(c->dev->type==Z85230) + if (c->dev->type == Z85230) { read_zsreg(c, R1); read_zsreg(c, R1); @@ -315,40 +315,40 @@ static void z8530_rtsdtr(struct z8530_channel *c, int set) static void z8530_rx(struct z8530_channel *c) { - u8 ch,stat; + u8 ch, stat; - while(1) + while (1) { /* FIFO empty ? */ - if(!(read_zsreg(c, R0)&1)) + if (!(read_zsreg(c, R0) & 1)) break; - ch=read_zsdata(c); - stat=read_zsreg(c, R1); + ch = read_zsdata(c); + stat = read_zsreg(c, R1); /* Overrun ? */ - if(c->count < c->max) + if (c->count < c->max) { - *c->dptr++=ch; + *c->dptr++ = ch; c->count++; } - if(stat&END_FR) + if (stat & END_FR) { /* Error ? */ - if(stat&(Rx_OVR|CRC_ERR)) + if (stat & (Rx_OVR | CRC_ERR)) { /* Rewind the buffer and return */ - if(c->skb) - c->dptr=c->skb->data; - c->count=0; - if(stat&Rx_OVR) + if (c->skb) + c->dptr = c->skb->data; + c->count = 0; + if (stat & Rx_OVR) { pr_warn("%s: overrun\n", c->dev->name); c->rx_overrun++; } - if(stat&CRC_ERR) + if (stat & CRC_ERR) { c->rx_crc_err++; /* printk("crc error\n"); */ @@ -356,8 +356,8 @@ static void z8530_rx(struct z8530_channel *c) /* Shove the frame upstream */ } else { /* Drop the lock for RX processing, or - * there are deadlocks - */ + * there are deadlocks + */ z8530_rx_done(c); write_zsctrl(c, RES_Rx_CRC); } @@ -381,9 +381,9 @@ static void z8530_rx(struct z8530_channel *c) static void z8530_tx(struct z8530_channel *c) { - while(c->txcount) { + while (c->txcount) { /* FIFO full ? */ - if(!(read_zsreg(c, R0)&4)) + if (!(read_zsreg(c, R0) & 4)) return; c->txcount--; /* Shovel out the byte @@ -391,10 +391,10 @@ static void z8530_tx(struct z8530_channel *c) write_zsreg(c, R8, *c->tx_ptr++); write_zsctrl(c, RES_H_IUS); /* We are about to underflow */ - if(c->txcount==0) + if (c->txcount == 0) { write_zsctrl(c, RES_EOM_L); - write_zsreg(c, R10, c->regs[10]&~ABUNDER); + write_zsreg(c, R10, c->regs[10] & ~ABUNDER); } } @@ -471,7 +471,7 @@ EXPORT_SYMBOL(z8530_sync); static void z8530_dma_rx(struct z8530_channel *chan) { - if(chan->rxdma_on) + if (chan->rxdma_on) { /* Special condition check only */ u8 status; @@ -479,12 +479,11 @@ static void z8530_dma_rx(struct z8530_channel *chan) read_zsreg(chan, R7); read_zsreg(chan, R6); - status=read_zsreg(chan, R1); + status = read_zsreg(chan, R1); - if(status&END_FR) - { + if (status & END_FR) z8530_rx_done(chan); /* Fire up the next one */ - } + write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_H_IUS); } else { @@ -502,7 +501,7 @@ static void z8530_dma_rx(struct z8530_channel *chan) */ static void z8530_dma_tx(struct z8530_channel *chan) { - if(!chan->dma_tx) + if (!chan->dma_tx) { pr_warn("Hey who turned the DMA off?\n"); z8530_tx(chan); @@ -526,21 +525,21 @@ static void z8530_dma_status(struct z8530_channel *chan) { u8 status, altered; - status=read_zsreg(chan, R0); - altered=chan->status^status; + status = read_zsreg(chan, R0); + altered = chan->status ^ status; - chan->status=status; + chan->status = status; - if(chan->dma_tx) + if (chan->dma_tx) { - if(status&TxEOM) + if (status & TxEOM) { unsigned long flags; - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(chan->txdma); clear_dma_ff(chan->txdma); - chan->txdma_on=0; + chan->txdma_on = 0; release_dma_lock(flags); z8530_tx_done(chan); } @@ -594,9 +593,9 @@ static void z8530_rx_clear(struct z8530_channel *c) u8 stat; read_zsdata(c); - stat=read_zsreg(c, R1); + stat = read_zsreg(c, R1); - if(stat&END_FR) + if (stat & END_FR) write_zsctrl(c, RES_Rx_CRC); /* Clear irq */ @@ -630,9 +629,9 @@ static void z8530_tx_clear(struct z8530_channel *c) static void z8530_status_clear(struct z8530_channel *chan) { - u8 status=read_zsreg(chan, R0); + u8 status = read_zsreg(chan, R0); - if(status&TxEOM) + if (status & TxEOM) write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_EXT_INT); write_zsctrl(chan, RES_H_IUS); @@ -647,7 +646,7 @@ EXPORT_SYMBOL(z8530_nop); /** * z8530_interrupt - Handle an interrupt from a Z8530 - * @irq: Interrupt number + * @irq: Interrupt number * @dev_id: The Z8530 device that is interrupting. * * A Z85[2]30 device has stuck its hand in the air for attention. @@ -663,25 +662,26 @@ EXPORT_SYMBOL(z8530_nop); irqreturn_t z8530_interrupt(int irq, void *dev_id) { - struct z8530_dev *dev=dev_id; + struct z8530_dev *dev = dev_id; u8 intr; static int locker; - int work=0; + int work = 0; struct z8530_irqhandler *irqs; - if(locker) + if (locker) { pr_err("IRQ re-enter\n"); return IRQ_NONE; } - locker=1; + locker = 1; spin_lock(&dev->lock); - while(++work<5000) + while (++work < 5000) { intr = read_zsreg(&dev->chanA, R3); - if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT))) + if (!(intr & + (CHARxIP | CHATxIP | CHAEXT | CHBRxIP | CHBTxIP | CHBEXT))) break; /* This holds the IRQ status. On the 8530 you must read it @@ -692,46 +692,46 @@ irqreturn_t z8530_interrupt(int irq, void *dev_id) * an IRQ for someone else remember */ - irqs=dev->chanA.irqs; + irqs = dev->chanA.irqs; - if(intr & (CHARxIP|CHATxIP|CHAEXT)) + if (intr & (CHARxIP | CHATxIP | CHAEXT)) { - if(intr&CHARxIP) + if (intr & CHARxIP) irqs->rx(&dev->chanA); - if(intr&CHATxIP) + if (intr & CHATxIP) irqs->tx(&dev->chanA); - if(intr&CHAEXT) + if (intr & CHAEXT) irqs->status(&dev->chanA); } - irqs=dev->chanB.irqs; + irqs = dev->chanB.irqs; - if(intr & (CHBRxIP|CHBTxIP|CHBEXT)) + if (intr & (CHBRxIP | CHBTxIP | CHBEXT)) { - if(intr&CHBRxIP) + if (intr & CHBRxIP) irqs->rx(&dev->chanB); - if(intr&CHBTxIP) + if (intr & CHBTxIP) irqs->tx(&dev->chanB); - if(intr&CHBEXT) + if (intr & CHBEXT) irqs->status(&dev->chanB); } } spin_unlock(&dev->lock); - if(work==5000) + if (work == 5000) pr_err("%s: interrupt jammed - abort(0x%X)!\n", dev->name, intr); /* Ok all done */ - locker=0; + locker = 0; return IRQ_HANDLED; } EXPORT_SYMBOL(z8530_interrupt); -static const u8 reg_init[16]= +static const u8 reg_init[16] = { - 0,0,0,0, - 0,0,0,0, - 0,0,0,0, - 0x55,0,0,0 + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x55, 0, 0, 0 }; /** @@ -749,7 +749,7 @@ int z8530_sync_open(struct net_device *dev, struct z8530_channel *c) spin_lock_irqsave(c->lock, flags); c->sync = 1; - c->mtu = dev->mtu+64; + c->mtu = dev->mtu + 64; c->count = 0; c->skb = NULL; c->skb2 = NULL; @@ -758,11 +758,11 @@ int z8530_sync_open(struct net_device *dev, struct z8530_channel *c) /* This loads the double buffer up */ z8530_rx_done(c); /* Load the frame ring */ z8530_rx_done(c); /* Load the backup frame */ - z8530_rtsdtr(c,1); + z8530_rtsdtr(c, 1); c->dma_tx = 0; - c->regs[R1]|=TxINT_ENAB; + c->regs[R1] |= TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, flags); return 0; @@ -787,9 +787,9 @@ int z8530_sync_close(struct net_device *dev, struct z8530_channel *c) c->max = 0; c->sync = 0; - chk=read_zsreg(c,R0); + chk = read_zsreg(c, R0); write_zsreg(c, R3, c->regs[R3]); - z8530_rtsdtr(c,0); + z8530_rtsdtr(c, 0); spin_unlock_irqrestore(c->lock, flags); return 0; @@ -810,7 +810,7 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) unsigned long cflags, dflags; c->sync = 1; - c->mtu = dev->mtu+64; + c->mtu = dev->mtu + 64; c->count = 0; c->skb = NULL; c->skb2 = NULL; @@ -825,27 +825,27 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) * should be fine. */ - if(c->mtu > PAGE_SIZE/2) + if (c->mtu > PAGE_SIZE / 2) return -EMSGSIZE; - c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); + c->rx_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); if (!c->rx_buf[0]) return -ENOBUFS; - c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2; + c->rx_buf[1] = c->rx_buf[0] + PAGE_SIZE / 2; - c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); + c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); if (!c->tx_dma_buf[0]) { free_page((unsigned long)c->rx_buf[0]); - c->rx_buf[0]=NULL; + c->rx_buf[0] = NULL; return -ENOBUFS; } - c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2; + c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2; - c->tx_dma_used=0; + c->tx_dma_used = 0; c->dma_tx = 1; - c->dma_num=0; - c->dma_ready=1; + c->dma_num = 0; + c->dma_ready = 1; /* Enable DMA control mode */ @@ -855,21 +855,21 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) /* TX DMA via DIR/REQ */ - c->regs[R14]|= DTRREQ; + c->regs[R14] |= DTRREQ; write_zsreg(c, R14, c->regs[R14]); - c->regs[R1]&= ~TxINT_ENAB; + c->regs[R1] &= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); /* RX DMA via W/Req */ - c->regs[R1]|= WT_FN_RDYFN; - c->regs[R1]|= WT_RDY_RT; - c->regs[R1]|= INT_ERR_Rx; - c->regs[R1]&= ~TxINT_ENAB; + c->regs[R1] |= WT_FN_RDYFN; + c->regs[R1] |= WT_RDY_RT; + c->regs[R1] |= INT_ERR_Rx; + c->regs[R1] &= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); - c->regs[R1]|= WT_RDY_ENAB; + c->regs[R1] |= WT_RDY_ENAB; write_zsreg(c, R1, c->regs[R1]); /* DMA interrupts @@ -878,11 +878,11 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) /* Set up the DMA configuration */ - dflags=claim_dma_lock(); + dflags = claim_dma_lock(); disable_dma(c->rxdma); clear_dma_ff(c->rxdma); - set_dma_mode(c->rxdma, DMA_MODE_READ|0x10); + set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10); set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0])); set_dma_count(c->rxdma, c->mtu); enable_dma(c->rxdma); @@ -902,8 +902,8 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->tx_dma_used = 1; c->irqs = &z8530_dma_sync; - z8530_rtsdtr(c,1); - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + z8530_rtsdtr(c, 1); + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, cflags); @@ -949,27 +949,27 @@ int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c) /* Disable DMA control mode */ - c->regs[R1]&= ~WT_RDY_ENAB; + c->regs[R1] &= ~WT_RDY_ENAB; write_zsreg(c, R1, c->regs[R1]); - c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); - c->regs[R1]|= INT_ALL_Rx; + c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx); + c->regs[R1] |= INT_ALL_Rx; write_zsreg(c, R1, c->regs[R1]); - c->regs[R14]&= ~DTRREQ; + c->regs[R14] &= ~DTRREQ; write_zsreg(c, R14, c->regs[R14]); - if(c->rx_buf[0]) + if (c->rx_buf[0]) { free_page((unsigned long)c->rx_buf[0]); - c->rx_buf[0]=NULL; + c->rx_buf[0] = NULL; } - if(c->tx_dma_buf[0]) + if (c->tx_dma_buf[0]) { free_page((unsigned long)c->tx_dma_buf[0]); - c->tx_dma_buf[0]=NULL; + c->tx_dma_buf[0] = NULL; } - chk=read_zsreg(c,R0); + chk = read_zsreg(c, R0); write_zsreg(c, R3, c->regs[R3]); - z8530_rtsdtr(c,0); + z8530_rtsdtr(c, 0); spin_unlock_irqrestore(c->lock, flags); @@ -993,7 +993,7 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) printk("Opening sync interface for TX-DMA\n"); c->sync = 1; - c->mtu = dev->mtu+64; + c->mtu = dev->mtu + 64; c->count = 0; c->skb = NULL; c->skb2 = NULL; @@ -1003,14 +1003,14 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) * should be fine. */ - if(c->mtu > PAGE_SIZE/2) + if (c->mtu > PAGE_SIZE / 2) return -EMSGSIZE; - c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); + c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); if (!c->tx_dma_buf[0]) return -ENOBUFS; - c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2; + c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2; spin_lock_irqsave(c->lock, cflags); @@ -1026,9 +1026,9 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->rxdma_on = 0; c->txdma_on = 0; - c->tx_dma_used=0; - c->dma_num=0; - c->dma_ready=1; + c->tx_dma_used = 0; + c->dma_num = 0; + c->dma_ready = 1; c->dma_tx = 1; /* Enable DMA control mode @@ -1036,10 +1036,10 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) /* TX DMA via DIR/REQ */ - c->regs[R14]|= DTRREQ; + c->regs[R14] |= DTRREQ; write_zsreg(c, R14, c->regs[R14]); - c->regs[R1]&= ~TxINT_ENAB; + c->regs[R1] &= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); /* Set up the DMA configuration @@ -1062,8 +1062,8 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->tx_dma_used = 1; c->irqs = &z8530_txdma_sync; - z8530_rtsdtr(c,1); - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + z8530_rtsdtr(c, 1); + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, cflags); return 0; @@ -1105,22 +1105,22 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) /* Disable DMA control mode */ - c->regs[R1]&= ~WT_RDY_ENAB; + c->regs[R1] &= ~WT_RDY_ENAB; write_zsreg(c, R1, c->regs[R1]); - c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); - c->regs[R1]|= INT_ALL_Rx; + c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx); + c->regs[R1] |= INT_ALL_Rx; write_zsreg(c, R1, c->regs[R1]); - c->regs[R14]&= ~DTRREQ; + c->regs[R14] &= ~DTRREQ; write_zsreg(c, R14, c->regs[R14]); - if(c->tx_dma_buf[0]) + if (c->tx_dma_buf[0]) { free_page((unsigned long)c->tx_dma_buf[0]); - c->tx_dma_buf[0]=NULL; + c->tx_dma_buf[0] = NULL; } - chk=read_zsreg(c,R0); + chk = read_zsreg(c, R0); write_zsreg(c, R3, c->regs[R3]); - z8530_rtsdtr(c,0); + z8530_rtsdtr(c, 0); spin_unlock_irqrestore(c->lock, cflags); return 0; @@ -1130,7 +1130,7 @@ EXPORT_SYMBOL(z8530_sync_txdma_close); /* Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny * it exists... */ -static const char *z8530_type_name[]={ +static const char * const z8530_type_name[] = { "Z8530", "Z85C30", "Z85230" @@ -1165,23 +1165,23 @@ static inline int do_z8530_init(struct z8530_dev *dev) /* NOP the interrupt handlers first - we might get a * floating IRQ transition when we reset the chip */ - dev->chanA.irqs=&z8530_nop; - dev->chanB.irqs=&z8530_nop; - dev->chanA.dcdcheck=DCD; - dev->chanB.dcdcheck=DCD; + dev->chanA.irqs = &z8530_nop; + dev->chanB.irqs = &z8530_nop; + dev->chanA.dcdcheck = DCD; + dev->chanB.dcdcheck = DCD; /* Reset the chip */ write_zsreg(&dev->chanA, R9, 0xC0); udelay(200); /* Now check its valid */ write_zsreg(&dev->chanA, R12, 0xAA); - if(read_zsreg(&dev->chanA, R12)!=0xAA) + if (read_zsreg(&dev->chanA, R12) != 0xAA) return -ENODEV; write_zsreg(&dev->chanA, R12, 0x55); - if(read_zsreg(&dev->chanA, R12)!=0x55) + if (read_zsreg(&dev->chanA, R12) != 0x55) return -ENODEV; - dev->type=Z8530; + dev->type = Z8530; /* See the application note. */ @@ -1192,12 +1192,12 @@ static inline int do_z8530_init(struct z8530_dev *dev) * the chip is enhanced. */ - if(read_zsreg(&dev->chanA, R15)==0x01) + if (read_zsreg(&dev->chanA, R15) == 0x01) { /* This C30 versus 230 detect is from Klaus Kudielka's dmascc */ /* Put a char in the fifo */ write_zsreg(&dev->chanA, R8, 0); - if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP) + if (read_zsreg(&dev->chanA, R0) & Tx_BUF_EMP) dev->type = Z85230; /* Has a FIFO */ else dev->type = Z85C30; /* Z85C30, 1 byte FIFO */ @@ -1214,7 +1214,7 @@ static inline int do_z8530_init(struct z8530_dev *dev) */ memcpy(dev->chanA.regs, reg_init, 16); - memcpy(dev->chanB.regs, reg_init ,16); + memcpy(dev->chanB.regs, reg_init, 16); return 0; } @@ -1270,8 +1270,8 @@ int z8530_shutdown(struct z8530_dev *dev) /* Reset the chip */ spin_lock_irqsave(&dev->lock, flags); - dev->chanA.irqs=&z8530_nop; - dev->chanB.irqs=&z8530_nop; + dev->chanA.irqs = &z8530_nop; + dev->chanB.irqs = &z8530_nop; write_zsreg(&dev->chanA, R9, 0xC0); /* We must lock the udelay, the chip is offlimits here */ udelay(100); @@ -1297,27 +1297,27 @@ int z8530_channel_load(struct z8530_channel *c, u8 *rtable) spin_lock_irqsave(c->lock, flags); - while(*rtable!=255) + while (*rtable != 255) { - int reg=*rtable++; - - if(reg>0x0F) - write_zsreg(c, R15, c->regs[15]|1); - write_zsreg(c, reg&0x0F, *rtable); - if(reg>0x0F) - write_zsreg(c, R15, c->regs[15]&~1); - c->regs[reg]=*rtable++; + int reg = *rtable++; + + if (reg > 0x0F) + write_zsreg(c, R15, c->regs[15] | 1); + write_zsreg(c, reg & 0x0F, *rtable); + if (reg > 0x0F) + write_zsreg(c, R15, c->regs[15] & ~1); + c->regs[reg] = *rtable++; } - c->rx_function=z8530_null_rx; - c->skb=NULL; - c->tx_skb=NULL; - c->tx_next_skb=NULL; - c->mtu=1500; - c->max=0; - c->count=0; - c->status=read_zsreg(c, R0); - c->sync=1; - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + c->rx_function = z8530_null_rx; + c->skb = NULL; + c->tx_skb = NULL; + c->tx_next_skb = NULL; + c->mtu = 1500; + c->max = 0; + c->count = 0; + c->status = read_zsreg(c, R0); + c->sync = 1; + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, flags); return 0; @@ -1342,19 +1342,19 @@ static void z8530_tx_begin(struct z8530_channel *c) { unsigned long flags; - if(c->tx_skb) + if (c->tx_skb) return; - c->tx_skb=c->tx_next_skb; - c->tx_next_skb=NULL; - c->tx_ptr=c->tx_next_ptr; + c->tx_skb = c->tx_next_skb; + c->tx_next_skb = NULL; + c->tx_ptr = c->tx_next_ptr; if (!c->tx_skb) { /* Idle on */ - if(c->dma_tx) + if (c->dma_tx) { - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(c->txdma); /* Check if we crapped out. */ @@ -1365,11 +1365,11 @@ static void z8530_tx_begin(struct z8530_channel *c) } release_dma_lock(flags); } - c->txcount=0; + c->txcount = 0; } else { - c->txcount=c->tx_skb->len; + c->txcount = c->tx_skb->len; - if(c->dma_tx) + if (c->dma_tx) { /* FIXME. DMA is broken for the original 8530, * on the older parts we need to set a flag and @@ -1377,25 +1377,25 @@ static void z8530_tx_begin(struct z8530_channel *c) * stage off */ - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(c->txdma); /* These two are needed by the 8530/85C30 * and must be issued when idling. */ - if(c->dev->type!=Z85230) + if (c->dev->type != Z85230) { write_zsctrl(c, RES_Tx_CRC); write_zsctrl(c, RES_EOM_L); } - write_zsreg(c, R10, c->regs[10]&~ABUNDER); + write_zsreg(c, R10, c->regs[10] & ~ABUNDER); clear_dma_ff(c->txdma); set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr)); set_dma_count(c->txdma, c->txcount); enable_dma(c->txdma); release_dma_lock(flags); write_zsctrl(c, RES_EOM_L); - write_zsreg(c, R5, c->regs[R5]|TxENAB); + write_zsreg(c, R5, c->regs[R5] | TxENAB); } else { /* ABUNDER off */ write_zsreg(c, R10, c->regs[10]); @@ -1472,35 +1472,35 @@ static void z8530_rx_done(struct z8530_channel *c) /* Is our receive engine in DMA mode */ - if(c->rxdma_on) + if (c->rxdma_on) { /* Save the ready state and the buffer currently * being used as the DMA target */ - int ready=c->dma_ready; - unsigned char *rxb=c->rx_buf[c->dma_num]; + int ready = c->dma_ready; + unsigned char *rxb = c->rx_buf[c->dma_num]; unsigned long flags; /* Complete this DMA. Necessary to find the length */ - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(c->rxdma); clear_dma_ff(c->rxdma); - c->rxdma_on=0; - ct=c->mtu-get_dma_residue(c->rxdma); - if(ct<0) - ct=2; /* Shit happens.. */ - c->dma_ready=0; + c->rxdma_on = 0; + ct = c->mtu - get_dma_residue(c->rxdma); + if (ct < 0) + ct = 2; /* Shit happens.. */ + c->dma_ready = 0; /* Normal case: the other slot is free, start the next DMA * into it immediately. */ - if(ready) + if (ready) { - c->dma_num^=1; - set_dma_mode(c->rxdma, DMA_MODE_READ|0x10); + c->dma_num ^= 1; + set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10); set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num])); set_dma_count(c->rxdma, c->mtu); c->rxdma_on = 1; @@ -1551,7 +1551,7 @@ static void z8530_rx_done(struct z8530_channel *c) * sync IRQ for the RT_LOCK area. * */ - ct=c->count; + ct = c->count; c->skb = c->skb2; c->count = 0; @@ -1594,10 +1594,10 @@ static void z8530_rx_done(struct z8530_channel *c) static inline int spans_boundary(struct sk_buff *skb) { - unsigned long a=(unsigned long)skb->data; + unsigned long a = (unsigned long)skb->data; - a^=(a+skb->len); - if(a&0x00010000) /* If the 64K bit is different.. */ + a ^= (a + skb->len); + if (a & 0x00010000) /* If the 64K bit is different.. */ return 1; return 0; } @@ -1620,7 +1620,7 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) unsigned long flags; netif_stop_queue(c->netdevice); - if(c->tx_next_skb) + if (c->tx_next_skb) return NETDEV_TX_BUSY; /* PC SPECIFIC - DMA limits */ @@ -1628,7 +1628,9 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) * limit, then copy to the flip buffer */ - if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb))) + if (c->dma_tx && + ((unsigned long)(virt_to_bus(skb->data + skb->len)) >= + 16 * 1024 * 1024 || spans_boundary(skb))) { /* Send the flip buffer, and flip the flippy bit. * We don't care which is used when just so long as @@ -1636,14 +1638,14 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) * only one buffer can be going out at a time the other * has to be safe. */ - c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used]; - c->tx_dma_used^=1; /* Flip temp buffer */ + c->tx_next_ptr = c->tx_dma_buf[c->tx_dma_used]; + c->tx_dma_used ^= 1; /* Flip temp buffer */ skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len); } else { c->tx_next_ptr = skb->data; } RT_LOCK; - c->tx_next_skb=skb; + c->tx_next_skb = skb; RT_UNLOCK; spin_lock_irqsave(c->lock, flags);