From patchwork Tue Jun 15 17:32:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 315B5C48BDF for ; Tue, 15 Jun 2021 17:33:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1685E61417 for ; Tue, 15 Jun 2021 17:33:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231398AbhFORfE (ORCPT ); Tue, 15 Jun 2021 13:35:04 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35338 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231199AbhFORez (ORCPT ); Tue, 15 Jun 2021 13:34:55 -0400 X-UUID: 8d4b15fd808f4b959c5b70b847e000b1-20210616 X-UUID: 8d4b15fd808f4b959c5b70b847e000b1-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 336697304; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:42 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Crystal Guo Subject: [PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node Date: Wed, 16 Jun 2021 01:32:08 +0800 Message-ID: <20210615173233.26682-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Crystal Guo add infracfg_rst node which is for MT8195 platform Signed-off-by: Crystal Guo --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 629cd883facf..8cda62f736b3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -8,6 +8,7 @@ #include #include +#include / { compatible = "mediatek,mt8195"; @@ -273,6 +274,20 @@ }; }; + infracfg: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x140 26 0x144 26 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x100>; From patchwork Tue Jun 15 17:32:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BD7BC48BE8 for ; Tue, 15 Jun 2021 17:32:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42F8F61417 for ; Tue, 15 Jun 2021 17:32:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231294AbhFORe6 (ORCPT ); Tue, 15 Jun 2021 13:34:58 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34916 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231146AbhFORex (ORCPT ); Tue, 15 Jun 2021 13:34:53 -0400 X-UUID: 903d1f8434e54ddabce44268d6df31bd-20210616 X-UUID: 903d1f8434e54ddabce44268d6df31bd-20210616 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1992062278; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:42 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Zhiqiang Ma Subject: [PATCH 02/27] arm64: dts: mt8195: add pinctrl node Date: Wed, 16 Jun 2021 01:32:09 +0800 Message-ID: <20210615173233.26682-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Zhiqiang Ma add support of pinctrl for mt8195 soc. Signed-off-by: Zhiqiang Ma --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8cda62f736b3..640f09100bb7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include / { @@ -288,6 +289,27 @@ }; }; + pio: pinctrl@10005000 { + compatible = "mediatek,mt8195-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11eb0000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 144>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x100>; From patchwork Tue Jun 15 17:32:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E94CC49361 for ; Tue, 15 Jun 2021 17:33:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C92B61417 for ; Tue, 15 Jun 2021 17:33:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231388AbhFORfP (ORCPT ); Tue, 15 Jun 2021 13:35:15 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34925 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231341AbhFORfA (ORCPT ); Tue, 15 Jun 2021 13:35:00 -0400 X-UUID: 3fcc64b316c44cc6971b1d2739854cb4-20210616 X-UUID: 3fcc64b316c44cc6971b1d2739854cb4-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 202066784; Wed, 16 Jun 2021 01:32:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:42 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Henry Chen Subject: [PATCH 03/27] arm64: dts: mt8195: add pwrap node Date: Wed, 16 Jun 2021 01:32:10 +0800 Message-ID: <20210615173233.26682-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Henry Chen Add pwrap node to SOC MT8195. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 640f09100bb7..bbb1e008e522 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -322,6 +322,18 @@ clocks = <&clk26m>; }; + pwrap: pwrap@10024000 { + compatible = "mediatek,mt8195-pwrap", "syscon"; + reg = <0 0x10024000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>; + }; + uart0: serial@11001100 { compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; reg = <0 0x11001100 0 0x100>; From patchwork Tue Jun 15 17:32:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F0C3C48BE5 for ; Tue, 15 Jun 2021 17:32:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 378AC61417 for ; Tue, 15 Jun 2021 17:32:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231314AbhFORe7 (ORCPT ); Tue, 15 Jun 2021 13:34:59 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34890 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231168AbhFORey (ORCPT ); Tue, 15 Jun 2021 13:34:54 -0400 X-UUID: e1fda26ec8714744a3bc3d71bcd487ef-20210616 X-UUID: e1fda26ec8714744a3bc3d71bcd487ef-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1823724307; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:43 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Henry Chen Subject: [PATCH 05/27] arm64: dts: mt8195: add spmi node Date: Wed, 16 Jun 2021 01:32:11 +0800 Message-ID: <20210615173233.26682-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Henry Chen Add spmi node to SOC MT8195. Signed-off-by: Henry Chen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index bbb1e008e522..965445d07e92 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -334,6 +334,21 @@ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>; }; + spmi: spmi@10027000 { + compatible = "mediatek,mt8195-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_M_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>; + }; + uart0: serial@11001100 { compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; reg = <0 0x11001100 0 0x100>; From patchwork Tue Jun 15 17:32:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDD7AC48BE5 for ; Tue, 15 Jun 2021 17:32:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D770061420 for ; Tue, 15 Jun 2021 17:32:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231366AbhFORfC (ORCPT ); Tue, 15 Jun 2021 13:35:02 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34925 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231174AbhFORey (ORCPT ); Tue, 15 Jun 2021 13:34:54 -0400 X-UUID: 3bb73b996dca47ec92289ec07e4fe47d-20210616 X-UUID: 3bb73b996dca47ec92289ec07e4fe47d-20210616 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1061415854; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:43 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Weiyi Lu Subject: [PATCH 06/27] arm64: dts: mt8195: add clock controllers Date: Wed, 16 Jun 2021 01:32:12 +0800 Message-ID: <20210615173233.26682-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Weiyi Lu Add clock controller nodes for SoC mt8195 Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 215 ++++++++++++++++++++++- 1 file changed, 213 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 965445d07e92..7946a13fcbc3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -6,6 +6,7 @@ /dts-v1/; +#include #include #include #include @@ -275,8 +276,14 @@ }; }; - infracfg: syscon@10001000 { - compatible = "mediatek,mt8195-infracfg", "syscon", "simple-mfd"; + topckgen: syscon@10000000 { + compatible = "mediatek,mt8195-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: infracfg_ao@10001000 { + compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; @@ -315,6 +322,12 @@ reg = <0 0x10007000 0 0x100>; }; + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8195-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; @@ -349,6 +362,30 @@ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>; }; + nnasys: syscon@10211000 { + compatible = "mediatek,mt8195-nnasys", "syscon"; + reg = <0 0x10211000 0 0x1000>; + #clock-cells = <1>; + }; + + scp_adsp: syscon@10720000 { + compatible = "mediatek,mt8195-scp_adsp", "syscon"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + }; + + audsys: syscon@10890000 { + compatible = "mediatek,mt8195-audsys", "syscon"; + reg = <0 0x10890000 0 0x1000>; + #clock-cells = <1>; + }; + + audsys_src: syscon@108a0000 { + compatible = "mediatek,mt8195-audsys_src", "syscon"; + reg = <0 0x108a0000 0 0x2000>; + #clock-cells = <1>; + }; + uart0: serial@11001100 { compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; reg = <0 0x11001100 0 0x100>; @@ -411,6 +448,12 @@ status = "disabled"; }; + pericfg_ao: syscon@11003000 { + compatible = "mediatek,mt8195-pericfg_ao", "syscon"; + reg = <0 0x11003000 0 0x1000>; + #clock-cells = <1>; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; reg = <0 0x11230000 0 0x10000>, @@ -472,6 +515,18 @@ }; }; + imp_iic_wrap_s: syscon@11d03000 { + compatible = "mediatek,mt8195-imp_iic_wrap_s", "syscon"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + + imp_iic_wrap_w: syscon@11e05000 { + compatible = "mediatek,mt8195-imp_iic_wrap_w", "syscon"; + reg = <0 0x11e05000 0 0x1000>; + #clock-cells = <1>; + }; + u3phy1: t-phy@11e30000 { compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -524,5 +579,161 @@ #phy-cells = <0>; status = "disabled"; }; + + mfgcfg: syscon@13fbf000 { + compatible = "mediatek,mt8195-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + vppsys0: syscon@14000000 { + compatible = "mediatek,mt8195-vppsys0", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys: syscon@14e00000 { + compatible = "mediatek,mt8195-wpesys", "syscon"; + reg = <0 0x14e00000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp0: syscon@14e02000 { + compatible = "mediatek,mt8195-wpesys_vpp0", "syscon"; + reg = <0 0x14e02000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp1: syscon@14e03000 { + compatible = "mediatek,mt8195-wpesys_vpp1", "syscon"; + reg = <0 0x14e03000 0 0x1000>; + #clock-cells = <1>; + }; + + vppsys1: syscon@14f00000 { + compatible = "mediatek,mt8195-vppsys1", "syscon"; + reg = <0 0x14f00000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt8195-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_dip_top: syscon@15110000 { + compatible = "mediatek,mt8195-imgsys1_dip_top", "syscon"; + reg = <0 0x15110000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_dip_nr: syscon@15130000 { + compatible = "mediatek,mt8195-imgsys1_dip_nr", "syscon"; + reg = <0 0x15130000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_wpe: syscon@15220000 { + compatible = "mediatek,mt8195-imgsys1_wpe", "syscon"; + reg = <0 0x15220000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: syscon@15330000 { + compatible = "mediatek,mt8195-ipesys", "syscon"; + reg = <0 0x15330000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: syscon@16000000 { + compatible = "mediatek,mt8195-camsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: syscon@1604f000 { + compatible = "mediatek,mt8195-camsys_rawa", "syscon"; + reg = <0 0x1604f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuva: syscon@1606f000 { + compatible = "mediatek,mt8195-camsys_yuva", "syscon"; + reg = <0 0x1606f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: syscon@1608f000 { + compatible = "mediatek,mt8195-camsys_rawb", "syscon"; + reg = <0 0x1608f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuvb: syscon@160af000 { + compatible = "mediatek,mt8195-camsys_yuvb", "syscon"; + reg = <0 0x160af000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_mraw: syscon@16140000 { + compatible = "mediatek,mt8195-camsys_mraw", "syscon"; + reg = <0 0x16140000 0 0x1000>; + #clock-cells = <1>; + }; + + ccusys: syscon@17200000 { + compatible = "mediatek,mt8195-ccusys", "syscon"; + reg = <0 0x17200000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_soc: syscon@1800f000 { + compatible = "mediatek,mt8195-vdecsys_soc", "syscon"; + reg = <0 0x1800f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@1802f000 { + compatible = "mediatek,mt8195-vdecsys", "syscon"; + reg = <0 0x1802f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_core1: syscon@1803f000 { + compatible = "mediatek,mt8195-vdecsys_core1", "syscon"; + reg = <0 0x1803f000 0 0x1000>; + #clock-cells = <1>; + }; + + apusys_pll: syscon@190f3000 { + compatible = "mediatek,mt8195-apusys_pll", "syscon"; + reg = <0 0x190f3000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: syscon@1a000000 { + compatible = "mediatek,mt8195-vencsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys_core1: syscon@1b000000 { + compatible = "mediatek,mt8195-vencsys_core1", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-vdosys0", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + #clock-cells = <1>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8195-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + }; }; }; From patchwork Tue Jun 15 17:32:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89CEEC49EA2 for ; Tue, 15 Jun 2021 17:33:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D00661417 for ; Tue, 15 Jun 2021 17:33:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231461AbhFORfJ (ORCPT ); Tue, 15 Jun 2021 13:35:09 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35346 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229919AbhFORe5 (ORCPT ); Tue, 15 Jun 2021 13:34:57 -0400 X-UUID: c49ea505637b40bdad6bb8395c2bc47c-20210616 X-UUID: c49ea505637b40bdad6bb8395c2bc47c-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1167870845; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:43 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Weiyi Lu Subject: [PATCH 07/27] arm64: dts: mt8195: add power domains controller Date: Wed, 16 Jun 2021 01:32:13 +0800 Message-ID: <20210615173233.26682-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Weiyi Lu Add power domains controller node for SoC mt8195 Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 364 +++++++++++++++++++++++ 1 file changed, 364 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 7946a13fcbc3..5463e7ba1061 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include / { @@ -317,6 +318,369 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8195-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_SENINF_SEL>, + <&topckgen CLK_TOP_SENINF2_SEL>; + clock-names = "csi_rx_top", "csi_rx_top1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ETHER { + reg = ; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names = "ether"; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_ADSP { + reg = ; + clocks = <&topckgen CLK_TOP_ADSP_SEL>; + clock-names = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; + clock-names = "audio", "audio1", "audio2", + "audio3"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_AUDIO_ASRC { + reg = ; + clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>, + <&topckgen CLK_TOP_ASM_L_SEL>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; + clock-names = "audio_asrc", "audio_asrc1", "audio_asrc2"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_NNA { + reg = ; + clocks = <&topckgen CLK_TOP_NNA0_SEL>; + clock-names = "nna"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_NNA0 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_NNA1 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG0 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG1 { + reg = ; + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; + clock-names = "mfg"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG5 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_MFG6 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_VPP_SEL>, + <&topckgen CLK_TOP_CAM_SEL>, + <&topckgen CLK_TOP_CCU_SEL>, + <&topckgen CLK_TOP_IMG_SEL>, + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_WPE_VPP_SEL>, + <&topckgen CLK_TOP_CFG_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_INFRA>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, + <&vppsys0 CLK_VPP0_SMI_REORDER>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", + "vppsys4", "vppsys5", "vppsys6", "vppsys7", + "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", + "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", + "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", + "vppsys0-12", "vppsys0-13", "vppsys0-14", + "vppsys0-15", "vppsys0-16", "vppsys0-17", + "vppsys0-18"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_VDEC1 { + reg = ; + clocks = <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec1-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_CFG_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>; + clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", + "vdosys0-2", "vdosys0-3", + "vdosys0-4", "vdosys0-5"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFG_VPP1>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; + clock-names = "vppsys1", "vppsys1-0", + "vppsys1-1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_WPESYS { + reg = ; + clocks = <&wpesys CLK_WPE_SMI_LARB7>, + <&wpesys CLK_WPE_SMI_LARB8>, + <&wpesys CLK_WPE_SMI_LARB7_P>, + <&wpesys CLK_WPE_SMI_LARB8_P>; + clock-names = "wepsys-0", "wepsys-1", "wepsys-2", + "wepsys-3"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC0 { + reg = ; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec0-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDEC2 { + reg = ; + clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; + clock-names = "vdec2-0"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VENC { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFG_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "vdosys1", "vdosys1-0", + "vdosys1-1", "vdosys1-2"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_DP_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_EPD_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_HDMI_TX { + reg = ; + clocks = <&topckgen CLK_TOP_HDMI_APB_SEL>; + clock-names = "hdmi_tx"; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_HDMI_RX { + reg = ; + clocks = <&topckgen CLK_TOP_HDMI_APB_SEL>; + clock-names = "hdmi_rx"; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_IMG { + reg = ; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "img-0", "img-1"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_DIP { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE_SEL>, + <&imgsys CLK_IMG_IPE>, + <&ipesys CLK_IPE_SMI_LARB12>; + clock-names = "ipe", "ipe-0", "ipe-1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM { + reg = ; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CAM2MM0_GALS>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&camsys CLK_CAM_CAM2SYS_GALS>; + clock-names = "cam-0", "cam-1", "cam-2", "cam-3", + "cam-4"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x100>; From patchwork Tue Jun 15 17:32:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A536C48BDF for ; Tue, 15 Jun 2021 17:32:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09B816141E for ; Tue, 15 Jun 2021 17:32:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231328AbhFORe7 (ORCPT ); Tue, 15 Jun 2021 13:34:59 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34885 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231166AbhFORey (ORCPT ); Tue, 15 Jun 2021 13:34:54 -0400 X-UUID: b24082219a414d1da813fcba98545cfd-20210616 X-UUID: b24082219a414d1da813fcba98545cfd-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 20401373; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:43 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Kewei Xu Subject: [PATCH 08/27] arm64: dts: mt8195: add i2c dts Date: Wed, 16 Jun 2021 01:32:14 +0800 Message-ID: <20210615173233.26682-8-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kewei Xu add i2c dts config for mt8195 soc. Signed-off-by: Kewei Xu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 105 +++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5463e7ba1061..9b002bb6d344 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -879,12 +879,117 @@ }; }; + i2c5: i2c@11d00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x10220580 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11d02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d02000 0 0x1000>, + <0 0x10220680 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + imp_iic_wrap_s: syscon@11d03000 { compatible = "mediatek,mt8195-imp_iic_wrap_s", "syscon"; reg = <0 0x11d03000 0 0x1000>; #clock-cells = <1>; }; + i2c0: i2c@11e00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e00000 0 0x1000>, + <0 0x10220080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + i2c1: i2c@11e01000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e01000 0 0x1000>, + <0 0x10220200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11e02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e02000 0 0x1000>, + <0 0x10220380 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11e03000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e03000 0 0x1000>, + <0 0x10220480 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11e04000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e04000 0 0x1000>, + <0 0x10220500 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + imp_iic_wrap_w: syscon@11e05000 { compatible = "mediatek,mt8195-imp_iic_wrap_w", "syscon"; reg = <0 0x11e05000 0 0x1000>; From patchwork Tue Jun 15 17:32:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F891C48BDF for ; Tue, 15 Jun 2021 17:32:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6DB6161414 for ; Tue, 15 Jun 2021 17:32:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231176AbhFORey (ORCPT ); Tue, 15 Jun 2021 13:34:54 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34885 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229728AbhFORex (ORCPT ); Tue, 15 Jun 2021 13:34:53 -0400 X-UUID: 0187e62bc676475d959a10ce8ba042a7-20210616 X-UUID: 0187e62bc676475d959a10ce8ba042a7-20210616 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2133741345; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:43 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Leilk Liu Subject: [PATCH 09/27] arm64: dts: mt8195: add spi controller Date: Wed, 16 Jun 2021 01:32:15 +0800 Message-ID: <20210615173233.26682-9-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Leilk Liu add spi controller node into mt8195 SoC Signed-off-by: Leilk Liu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 106 +++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 9b002bb6d344..80a272703879 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -818,6 +818,112 @@ #clock-cells = <1>; }; + spi0: spi@1100a000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spis0: spi@1101d000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101d000 0 0x100>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + + spis1: spi@1101e000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101e000 0 0x100>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; reg = <0 0x11230000 0 0x10000>, From patchwork Tue Jun 15 17:32:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A6E8C48BDF for ; Tue, 15 Jun 2021 17:33:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72DB461417 for ; Tue, 15 Jun 2021 17:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231480AbhFORfM (ORCPT ); Tue, 15 Jun 2021 13:35:12 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34916 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231308AbhFORe7 (ORCPT ); Tue, 15 Jun 2021 13:34:59 -0400 X-UUID: 00ff0ee9a06641ecac3fc873d0fa480a-20210616 X-UUID: 00ff0ee9a06641ecac3fc873d0fa480a-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 985036743; Wed, 16 Jun 2021 01:32:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:44 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jianjun Wang Subject: [PATCH 10/27] arm64: dts: mt8195: add PCIe phy device node Date: Wed, 16 Jun 2021 01:32:16 +0800 Message-ID: <20210615173233.26682-10-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jianjun Wang Add PCIe phy device node for mt8195 SoC. Signed-off-by: Jianjun Wang --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 80a272703879..dd5644410fea 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1107,6 +1107,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x11e30000 0xe00>; + power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; status = "disabled"; u2port1: usb-phy@0 { @@ -1146,6 +1147,19 @@ }; }; + pciephy: phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + #address-cells = <2>; + #size-cells = <2>; + #phy-cells = <0>; + reg = <0 0x11e80000 0 0x10000>, + <0 0x11e90000 0 0x10000>; + reg-names = "phy-sif", "phy-ckm"; + + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + status = "disabled"; + }; + ufsphy: phy@11fa0000 { compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg = <0 0x11fa0000 0 0xc000>; From patchwork Tue Jun 15 17:32:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96D7FC49361 for ; Tue, 15 Jun 2021 17:32:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 719B161414 for ; Tue, 15 Jun 2021 17:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231255AbhFORe5 (ORCPT ); Tue, 15 Jun 2021 13:34:57 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35307 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230506AbhFORex (ORCPT ); Tue, 15 Jun 2021 13:34:53 -0400 X-UUID: 347347ff149d4800b730ae0427770430-20210616 X-UUID: 347347ff149d4800b730ae0427770430-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 687593839; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:44 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jianjun Wang Subject: [PATCH 11/27] arm64: dts: mt8195: add PCIe device node Date: Wed, 16 Jun 2021 01:32:17 +0800 Message-ID: <20210615173233.26682-11-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jianjun Wang Add PCIe device node for mt8195. Signed-off-by: Jianjun Wang --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 74 ++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index dd5644410fea..539f405a4f3d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -944,6 +945,79 @@ status = "disabled"; }; + pcie0: pcie@112f0000 { + device_type = "pci"; + compatible = "mediatek,mt8195-pcie"; + reg = <0 0x112f0000 0 0x2000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 + 0x0 0x20000000 0 0x4000000>; + + status = "disabled"; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@112f8000 { + device_type = "pci"; + compatible = "mediatek,mt8195-pcie"; + reg = <0 0x112f8000 0 0x2000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x24000000 + 0x0 0x24000000 0 0x4000000>; + + status = "disabled"; + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: nor@1132c000 { compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; reg = <0 0x1132c000 0 0x1000>; From patchwork Tue Jun 15 17:32:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBB6CC48BE5 for ; Tue, 15 Jun 2021 17:32:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ADD3661420 for ; Tue, 15 Jun 2021 17:32:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231229AbhFORez (ORCPT ); Tue, 15 Jun 2021 13:34:55 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34890 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230500AbhFORex (ORCPT ); Tue, 15 Jun 2021 13:34:53 -0400 X-UUID: a70f86e2f3ad466e8e22238fe7ee09cb-20210616 X-UUID: a70f86e2f3ad466e8e22238fe7ee09cb-20210616 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 655523478; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:44 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Wenbin Mei Subject: [PATCH 12/27] arm64: dts: mt8195: fix mmc driver Date: Wed, 16 Jun 2021 01:32:18 +0800 Message-ID: <20210615173233.26682-12-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Wenbin Mei fix mmc driver with proper clock for mt8195 SoC. Signed-off-by: Wenbin Mei --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 539f405a4f3d..327ff1b856d2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -926,22 +926,32 @@ }; mmc0: mmc@11230000 { - compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8192-mmc", + "mediatek,mt8183-mmc"; reg = <0 0x11230000 0 0x10000>, <0 0x11f50000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>, <&clk26m>; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; mmc1: mmc@11240000 { - compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8192-mmc", + "mediatek,mt8183-mmc"; reg = <0 0x11240000 0 0x1000>, <0 0x11c70000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>, <&clk26m>; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; status = "disabled"; }; From patchwork Tue Jun 15 17:32:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 172F3C48BDF for ; Tue, 15 Jun 2021 17:32:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E80AF61414 for ; Tue, 15 Jun 2021 17:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231270AbhFORe6 (ORCPT ); Tue, 15 Jun 2021 13:34:58 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35324 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231161AbhFORex (ORCPT ); Tue, 15 Jun 2021 13:34:53 -0400 X-UUID: 710e977156df40f696cf861e13030b66-20210616 X-UUID: 710e977156df40f696cf861e13030b66-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1060949818; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:44 +0800 From: Tinghan Shen To: , CC: , , , , , , , , James Zheng Subject: [PATCH 13/27] arm64: dts: mt8195: add hdmi nodes Date: Wed, 16 Jun 2021 01:32:19 +0800 Message-ID: <20210615173233.26682-13-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: James Zheng Add HDMI support for mt8195 SoC. Signed-off-by: James Zheng --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 327ff1b856d2..1a281551d011 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -20,6 +20,10 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + dpi1 = &disp_dpi1; + }; + clocks { clk26m: oscillator0 { compatible = "fixed-clock"; @@ -317,6 +321,28 @@ interrupt-controller; interrupts = ; #interrupt-cells = <2>; + + hdmi_pin: hdmipinctrl { + hdmi_hotplug { + pinmux = ; + bias-pull-down; + }; + hdmi_ddc { + pinmux = , + ; + mediatek,drive-strength-adv = <0>; + drive-strength = ; + }; + hdmi_cec { + pinmux = ; + bias-disable; + }; + hdmi_5vctrl { + pinmux = ; + slew-rate = <1>; + output-high; + }; + }; }; scpsys: syscon@10006000 { @@ -693,6 +719,12 @@ #clock-cells = <1>; }; + cec: cec@10014000 { + compatible = "mediatek,mt8195-cec"; + reg = <0 0x10014000 0 0x100>; + interrupts = ; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; @@ -1105,6 +1137,22 @@ #clock-cells = <1>; }; + hdmi_phy: hdmi-phy@11d5f000 { + compatible = "mediatek,mt8195-hdmi-phy"; + reg = <0 0x11d5f000 0 0x100>; + clocks = <&topckgen CLK_TOP_HDMI_XTAL_SEL>, + <&infracfg_ao CLK_INFRA_AO_HDMI_26M>, + <&apmixedsys CLK_APMIXED_HDMIPLL1>, + <&apmixedsys CLK_APMIXED_HDMIPLL2>; + clock-names = "hdmi_xtal_sel", + "hdmi_26m", + "hdmi_pll1", + "hdmi_pll2"; + clock-output-names = "hdmi_txpll"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + i2c0: i2c@11e00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -1408,5 +1456,41 @@ reg = <0 0x1c100000 0 0x1000>; #clock-cells = <1>; }; + + disp_dpi1: disp_dpi1@1c112000 { + compatible = "mediatek,mt8195-dpi"; + reg = <0 0x1c112000 0 0x1000>; + interrupts = ; + clock-names = "pixel", "engine"; + status = "disabled"; + }; + + hdmi0: hdmi@1c300000 { + compatible = "mediatek,mt8195-hdmi"; + reg = <0 0x1c300000 0 0x1000>; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_HDCP_SEL>, + <&topckgen CLK_TOP_HDCP_24M_SEL>, + <&topckgen CLK_TOP_HD20_HDCP_C_SEL>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "hdcp_sel", + "hdcp24_sel", + "hd20_hdcp_sel", + "split_hdmi"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pin>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + cec = <&cec>; + ddc-i2c-bus = <&hdmiddc0>; + status = "disabled"; + }; + }; + + hdmiddc0: ddc_i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + clock-names = "ddc-i2c"; }; }; From patchwork Tue Jun 15 17:32:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BAA3C48BE8 for ; Tue, 15 Jun 2021 17:33:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 14F00613E4 for ; Tue, 15 Jun 2021 17:33:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231380AbhFORfD (ORCPT ); Tue, 15 Jun 2021 13:35:03 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35307 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231186AbhFORez (ORCPT ); Tue, 15 Jun 2021 13:34:55 -0400 X-UUID: 2ba9a969a76c4ec594749d2d43112c68-20210616 X-UUID: 2ba9a969a76c4ec594749d2d43112c68-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 918936174; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:44 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Tianping Fang Subject: [PATCH 14/27] arm64: dts: mt8195: add usb support Date: Wed, 16 Jun 2021 01:32:20 +0800 Message-ID: <20210615173233.26682-14-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tianping Fang Add usb support for mt8195 SoC. Signed-off-by: Tianping Fang --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 110 ++++++++++++++++++++--- 1 file changed, 100 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 1a281551d011..41d9f167701f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -957,6 +957,28 @@ status = "disabled"; }; + xhci: xhci@11200000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>, + <&topckgen CLK_TOP_SSUSB_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc", @@ -987,6 +1009,70 @@ status = "disabled"; }; + xhci1: xhci1@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P1_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + + xhci2: xhci2@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P2_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + + xhci3: xhci3@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port3 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>, + <&topckgen CLK_TOP_SSUSB_P3_REF>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + usb2-lpm-disable; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + pcie0: pcie@112f0000 { device_type = "pci"; compatible = "mediatek,mt8195-pcie"; @@ -1080,7 +1166,7 @@ u2port2: usb-phy@0 { reg = <0x0 0x700>; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; clock-names = "ref"; #phy-cells = <1>; }; @@ -1095,7 +1181,7 @@ u2port3: usb-phy@0 { reg = <0x0 0x700>; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; clock-names = "ref"; #phy-cells = <1>; }; @@ -1244,15 +1330,17 @@ u2port1: usb-phy@0 { reg = <0x0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>; + clock-names = "ref", "da_ref"; #phy-cells = <1>; }; u3port1: usb-phy@700 { reg = <0x700 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names = "ref", "da_ref"; #phy-cells = <1>; }; }; @@ -1266,15 +1354,17 @@ u2port0: usb-phy@0 { reg = <0x0 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>; + clock-names = "ref", "da_ref"; #phy-cells = <1>; }; u3port0: usb-phy@700 { reg = <0x700 0x700>; - clocks = <&clk26m>; - clock-names = "ref"; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names = "ref", "da_ref"; #phy-cells = <1>; }; }; From patchwork Tue Jun 15 17:32:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C983C49361 for ; Tue, 15 Jun 2021 17:33:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A66761425 for ; Tue, 15 Jun 2021 17:33:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231439AbhFORfH (ORCPT ); Tue, 15 Jun 2021 13:35:07 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34965 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231213AbhFORe4 (ORCPT ); Tue, 15 Jun 2021 13:34:56 -0400 X-UUID: d1cbf97e3e8d42d4b0523043857ad32e-20210616 X-UUID: d1cbf97e3e8d42d4b0523043857ad32e-20210616 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1865074562; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:44 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Yong Wu Subject: [PATCH 15/27] arm64: dts: mt8195: add IOMMU and smi nodes Date: Wed, 16 Jun 2021 01:32:21 +0800 Message-ID: <20210615173233.26682-15-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yong Wu add smi support for mt8195 SoC. Signed-off-by: Yong Wu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 445 +++++++++++++++++++++++ 1 file changed, 445 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 41d9f167701f..856b0e938009 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -765,6 +766,17 @@ #clock-cells = <1>; }; + iommu_infra: infra-iommu@10315000 { + compatible = "mediatek,mt8195-iommu-infra"; + reg = <0 0x10315000 0 0x1000>, + <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + clock-names = "bclk"; + #iommu-cells = <1>; + status = "disabled"; + }; + scp_adsp: syscon@10720000 { compatible = "mediatek,mt8195-scp_adsp", "syscon"; reg = <0 0x10720000 0 0x1000>; @@ -1403,6 +1415,55 @@ #clock-cells = <1>; }; + smi_common2: smi@1400e000 { + compatible = "mediatek,mt8195-smi-common"; + mediatek,common-id = <2>; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_SMI_COMMON>, + <&vppsys0 CLK_VPP0_SMI_COMMON>, + <&vppsys0 CLK_VPP0_GALS_INFRA>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + smi_common1: smi@14012000 { + compatible = "mediatek,mt8195-smi-common"; + mediatek,common-id = <1>; + reg = <0 0x14012000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + larb4: larb@14013000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14013000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + iommu_vpp: iommu@14018000 { + compatible = "mediatek,mt8195-iommu-vpp"; + reg = <0 0x14018000 0 0x1000>; + mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 + &larb12 &larb14 &larb16 &larb18 + &larb20 &larb22 &larb23 &larb26 + &larb27>; + interrupts = ; + clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; + clock-names = "bclk"; + #iommu-cells = <1>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + wpesys: syscon@14e00000 { compatible = "mediatek,mt8195-wpesys", "syscon"; reg = <0 0x14e00000 0 0x1000>; @@ -1421,24 +1482,97 @@ #clock-cells = <1>; }; + larb7: larb@14e04000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14e04000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common0>; + clocks = <&wpesys CLK_WPE_SMI_LARB7>, + <&wpesys CLK_WPE_SMI_LARB7>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; + }; + + larb8: larb@14e05000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14e05000 0 0x1000>; + mediatek,larb-id = <8>; + mediatek,smi = <&smi_common1>; + clocks = <&wpesys CLK_WPE_SMI_LARB8>, + <&wpesys CLK_WPE_SMI_LARB8>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; + }; + vppsys1: syscon@14f00000 { compatible = "mediatek,mt8195-vppsys1", "syscon"; reg = <0 0x14f00000 0 0x1000>; #clock-cells = <1>; }; + larb5: larb@14f02000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14f02000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common0>; + clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + larb6: larb@14f03000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x14f03000 0 0x1000>; + mediatek,larb-id = <6>; + mediatek,smi = <&smi_common1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, + <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, + <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; + clock-names = "apb", "smi", "gals", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8195-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; }; + larb9: larb@15001000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common0>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; + }; + imgsys1_dip_top: syscon@15110000 { compatible = "mediatek,mt8195-imgsys1_dip_top", "syscon"; reg = <0 0x15110000 0 0x1000>; #clock-cells = <1>; }; + larb10: larb@15120000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15120000 0 0x1000>; + mediatek,larb-id = <10>; + mediatek,smi = <&smi_common0>; + clocks = <&imgsys CLK_IMG_DIP0>, + <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "apb", "smi", "gals", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; + }; + imgsys1_dip_nr: syscon@15130000 { compatible = "mediatek,mt8195-imgsys1_dip_nr", "syscon"; reg = <0 0x15130000 0 0x1000>; @@ -1451,18 +1585,122 @@ #clock-cells = <1>; }; + larb11: larb@15230000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15230000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common0>; + clocks = <&imgsys CLK_IMG_WPE0>, + <&imgsys1_wpe CLK_IMG1_WPE_LARB11>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "apb", "smi", "gals", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; + }; + ipesys: syscon@15330000 { compatible = "mediatek,mt8195-ipesys", "syscon"; reg = <0 0x15330000 0 0x1000>; #clock-cells = <1>; }; + larb12: larb@15340000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x15340000 0 0x1000>; + mediatek,larb-id = <12>; + mediatek,smi = <&smi_common1>; + clocks = <&imgsys CLK_IMG_IPE>, + <&ipesys CLK_IPE_SMI_LARB12>, + <&imgsys CLK_IMG_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; + }; + camsys: syscon@16000000 { compatible = "mediatek,mt8195-camsys", "syscon"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb13: larb@16001000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common0>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb14: larb@16002000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common1>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&camsys CLK_CAM_CAM2SYS_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals", "gals1", "gals2"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb16: larb@16012000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16012000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common1>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&camsys CLK_CAM_CAM2SYS_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals", "gals1", "gals2"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@16013000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16013000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common0>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys_yuva CLK_CAM_YUVA_LARBX>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; + }; + + larb27: larb@16014000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16014000 0 0x1000>; + mediatek,larb-id = <27>; + mediatek,smi = <&smi_common1>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&camsys CLK_CAM_CAM2SYS_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals", "gals1", "gals2"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; + }; + + larb28: larb@16015000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16015000 0 0x1000>; + mediatek,larb-id = <28>; + mediatek,smi = <&smi_common0>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys_yuvb CLK_CAM_YUVB_LARBX>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; + }; + camsys_rawa: syscon@1604f000 { compatible = "mediatek,mt8195-camsys_rawa", "syscon"; reg = <0 0x1604f000 0 0x1000>; @@ -1493,30 +1731,135 @@ #clock-cells = <1>; }; + larb25: larb@16141000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16141000 0 0x1000>; + mediatek,larb-id = <25>; + mediatek,smi = <&smi_common0>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys_mraw CLK_CAM_MRAW_LARBX>, + <&camsys CLK_CAM_CAM2MM0_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; + }; + + larb26: larb@16142000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x16142000 0 0x1000>; + mediatek,larb-id = <26>; + mediatek,smi = <&smi_common1>; + clocks = <&camsys CLK_CAM_LARB14>, + <&camsys_mraw CLK_CAM_MRAW_LARBX>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; + + }; + ccusys: syscon@17200000 { compatible = "mediatek,mt8195-ccusys", "syscon"; reg = <0 0x17200000 0 0x1000>; #clock-cells = <1>; }; + larb18: larb@17201000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x17201000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_common1>; + clocks = <&camsys CLK_CAM_LARB14>, + <&ccusys CLK_CCU_LARB18>, + <&camsys CLK_CAM_CAM2MM1_GALS>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; + clock-names = "apb", "smi", "gals", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; + }; + + larb24: larb@1800d000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1800d000 0 0x1000>; + mediatek,larb-id = <24>; + mediatek,smi = <&smi_common0>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + larb23: larb@1800e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1800e000 0 0x1000>; + mediatek,larb-id = <23>; + mediatek,smi = <&smi_common1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + vdecsys_soc: syscon@1800f000 { compatible = "mediatek,mt8195-vdecsys_soc", "syscon"; reg = <0 0x1800f000 0 0x1000>; #clock-cells = <1>; }; + larb21: larb@1802e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1802e000 0 0x1000>; + mediatek,larb-id = <21>; + mediatek,smi = <&smi_common0>; + clocks = <&vdecsys CLK_VDEC_LARB1>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + vdecsys: syscon@1802f000 { compatible = "mediatek,mt8195-vdecsys", "syscon"; reg = <0 0x1802f000 0 0x1000>; #clock-cells = <1>; }; + larb22: larb@1803e000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1803e000 0 0x1000>; + mediatek,larb-id = <22>; + mediatek,smi = <&smi_common1>; + clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; + }; + vdecsys_core1: syscon@1803f000 { compatible = "mediatek,mt8195-vdecsys_core1", "syscon"; reg = <0 0x1803f000 0 0x1000>; #clock-cells = <1>; }; + iommu_apu0: iommu@19010000 { + compatible = "mediatek,mt8195-iommu-apu"; + reg = <0 0x19010000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + clock-names = "bclk"; + #iommu-cells = <1>; + /* power-domains = <&apuspm MT8195_POWER_DOMAIN_APUSYS_TOP>; */ + status = "disabled"; + }; + + iommu_apu1: iommu@19015000 { + compatible = "mediatek,mt8195-iommu-apu"; + reg = <0 0x19015000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + clock-names = "bclk"; + #iommu-cells = <1>; + /* power-domains = <&apuspm MT8195_POWER_DOMAIN_APUSYS_TOP>; */ + status = "disabled"; + }; + apusys_pll: syscon@190f3000 { compatible = "mediatek,mt8195-apusys_pll", "syscon"; reg = <0 0x190f3000 0 0x1000>; @@ -1529,24 +1872,126 @@ #clock-cells = <1>; }; + larb19: larb@1a010000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common0>; + clocks = <&vencsys CLK_VENC_VENC>, + <&vencsys CLK_VENC_LARB>, + <&vencsys CLK_VENC_GALS>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS>; + clock-names = "apb", "smi", "gals", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + }; + vencsys_core1: syscon@1b000000 { compatible = "mediatek,mt8195-vencsys_core1", "syscon"; reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; + larb20: larb@1b010000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1b010000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common1>; + clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, + <&vencsys_core1 CLK_VENC_CORE1_LARB>, + <&vencsys_core1 CLK_VENC_CORE1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>; + clock-names = "apb", "smi", "gals", "gals1", "gals2"; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; + }; + vdosys0: syscon@1c01a000 { compatible = "mediatek,mt8195-vdosys0", "syscon"; reg = <0 0x1c01a000 0 0x1000>; #clock-cells = <1>; }; + smi_common0: smi@1c01b000 { + compatible = "mediatek,mt8195-smi-common"; + mediatek,common-id = <0>; + reg = <0 0x1c01b000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + + }; + + iommu_vdo: iommu@1c01f000 { + compatible = "mediatek,mt8195-iommu-vdo"; + reg = <0 0x1c01f000 0 0x1000>; + mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 + &larb10 &larb11 &larb13 &larb17 + &larb19 &larb21 &larb24 &larb25 + &larb28>; + interrupts = ; + #iommu-cells = <1>; + clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + larb0: larb@1c018000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c018000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common0>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + larb1: larb@1c019000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c019000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common1>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + vdosys1: syscon@1c100000 { compatible = "mediatek,mt8195-vdosys1", "syscon"; reg = <0 0x1c100000 0 0x1000>; #clock-cells = <1>; }; + larb2: larb@1c102000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c102000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common0>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + }; + + larb3: larb@1c103000 { + compatible = "mediatek,mt8195-smi-larb"; + reg = <0 0x1c103000 0 0x1000>; + mediatek,larb-id = <3>; + mediatek,smi = <&smi_common1>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + }; + disp_dpi1: disp_dpi1@1c112000 { compatible = "mediatek,mt8195-dpi"; reg = <0 0x1c112000 0 0x1000>; From patchwork Tue Jun 15 17:32:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2771C48BDF for ; Tue, 15 Jun 2021 17:33:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C2D7F6144E for ; Tue, 15 Jun 2021 17:33:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231468AbhFORfK (ORCPT ); Tue, 15 Jun 2021 13:35:10 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35329 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231262AbhFORe6 (ORCPT ); Tue, 15 Jun 2021 13:34:58 -0400 X-UUID: 38ef2d217b464496a555ce6007250263-20210616 X-UUID: 38ef2d217b464496a555ce6007250263-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 907989659; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:45 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jason-JH Lin Subject: [PATCH 16/27] arm64: dts: mt8195: add display node Date: Wed, 16 Jun 2021 01:32:22 +0800 Message-ID: <20210615173233.26682-16-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jason-JH Lin add display node. Signed-off-by: Jason-JH Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 856b0e938009..f362288ad828 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1911,6 +1911,82 @@ #clock-cells = <1>; }; + vdosys_config@1c01a000 { + compatible = "mediatek,mt8195-vdosys"; + reg = <0 0x1c01a000 0 0x1000>; + reg-names = "vdosys0_config"; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + mutex: disp_mutex0@1c016000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + reg-names = "vdo0_mutex"; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clock-names = "vdo0_mutex"; + interrupts = ; + }; + + ovl0: disp_ovl@1c000000 { + compatible = "mediatek,mt8195-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + }; + + rdma0: disp_rdma@1c002000 { + compatible = "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + }; + + color0: disp_color@1c003000 { + compatible = "mediatek,mt8195-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + ccorr0: disp_ccorr@1c004000 { + compatible = "mediatek,mt8195-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + aal0: disp_aal@1c005000 { + compatible = "mediatek,mt8195-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + gamma0: disp_gamma@1c006000 { + compatible = "mediatek,mt8195-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + + dither0: disp_dither@1c007000 { + compatible = "mediatek,mt8195-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + smi_common0: smi@1c01b000 { compatible = "mediatek,mt8195-smi-common"; mediatek,common-id = <0>; From patchwork Tue Jun 15 17:32:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E163C48BE8 for ; Tue, 15 Jun 2021 17:32:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42F3F613F5 for ; Tue, 15 Jun 2021 17:32:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231352AbhFORfA (ORCPT ); Tue, 15 Jun 2021 13:35:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35329 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231172AbhFORey (ORCPT ); Tue, 15 Jun 2021 13:34:54 -0400 X-UUID: 5efe464edf514003a25262ce4d53c41a-20210616 X-UUID: 5efe464edf514003a25262ce4d53c41a-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 170522514; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:45 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jason-JH Lin Subject: [PATCH 17/27] arm64: dts: mt8195: add merge node Date: Wed, 16 Jun 2021 01:32:23 +0800 Message-ID: <20210615173233.26682-17-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jason-JH Lin add merge node Signed-off-by: Jason-JH Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index f362288ad828..34f7e99d1fd2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1987,6 +1987,14 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; }; + merge0: disp_vpp_merge0@1c014000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + smi_common0: smi@1c01b000 { compatible = "mediatek,mt8195-smi-common"; mediatek,common-id = <0>; From patchwork Tue Jun 15 17:32:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41E15C49EA3 for ; Tue, 15 Jun 2021 17:33:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3325361403 for ; Tue, 15 Jun 2021 17:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231493AbhFORfO (ORCPT ); Tue, 15 Jun 2021 13:35:14 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34890 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231315AbhFORe7 (ORCPT ); Tue, 15 Jun 2021 13:34:59 -0400 X-UUID: 383a314539574a10a6e448c1e3816297-20210616 X-UUID: 383a314539574a10a6e448c1e3816297-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 590020444; Wed, 16 Jun 2021 01:32:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:45 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jason-JH Lin Subject: [PATCH 18/27] arm64: dts: mt8195: add dsc node Date: Wed, 16 Jun 2021 01:32:24 +0800 Message-ID: <20210615173233.26682-18-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jason-JH Lin add dsc node Signed-off-by: Jason-JH Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 34f7e99d1fd2..0399aa8cf994 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1995,6 +1995,14 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; }; + dsc0: disp_dsc_wrap@1c009000 { + compatible = "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + }; + smi_common0: smi@1c01b000 { compatible = "mediatek,mt8195-smi-common"; mediatek,common-id = <0>; From patchwork Tue Jun 15 17:32:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED71AC49EA3 for ; Tue, 15 Jun 2021 17:33:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB9AA6147D for ; Tue, 15 Jun 2021 17:33:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231324AbhFORfF (ORCPT ); Tue, 15 Jun 2021 13:35:05 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35324 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231238AbhFORe4 (ORCPT ); Tue, 15 Jun 2021 13:34:56 -0400 X-UUID: fe010a276f864cdf8738f7f02467bf6e-20210616 X-UUID: fe010a276f864cdf8738f7f02467bf6e-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1654132548; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:45 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jason-JH Lin Subject: [PATCH 19/27] arm64: dts: mt8195: add dp_intf node Date: Wed, 16 Jun 2021 01:32:25 +0800 Message-ID: <20210615173233.26682-19-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jason-JH Lin add dp_intf cnode Signed-off-by: Jason-JH Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 0399aa8cf994..560a0583ca0b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2003,6 +2003,29 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; }; + dp_intf0: dp_intf0@1c015000 { + status = "disabled"; + compatible = "mediatek,mt8195-dpintf"; + reg = <0 0x1c015000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&topckgen CLK_TOP_EDP_SEL>, + <&topckgen CLK_TOP_TVDPLL1_D2>, + <&topckgen CLK_TOP_TVDPLL1_D4>, + <&topckgen CLK_TOP_TVDPLL1_D8>, + <&topckgen CLK_TOP_TVDPLL1_D16>, + <&topckgen CLK_TOP_TVDPLL1>; + clock-names = "hf_fmm_ck", + "hf_fdp_ck", + "MUX_DP", + "TVDPLL_D2", + "TVDPLL_D4", + "TVDPLL_D8", + "TVDPLL_D16", + "DPI_CK"; + }; + smi_common0: smi@1c01b000 { compatible = "mediatek,mt8195-smi-common"; mediatek,common-id = <0>; @@ -2113,6 +2136,14 @@ ddc-i2c-bus = <&hdmiddc0>; status = "disabled"; }; + + edp_tx: edp_tx@1c500000 { + status = "disabled"; + compatible = "mediatek,mt8195-dp_tx"; + reg = <0 0x1c500000 0 0x8000>; + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts = ; + }; }; hdmiddc0: ddc_i2c { From patchwork Tue Jun 15 17:32:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7E2CC49EA4 for ; Tue, 15 Jun 2021 17:33:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE0EB61424 for ; Tue, 15 Jun 2021 17:33:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231396AbhFORfO (ORCPT ); Tue, 15 Jun 2021 13:35:14 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34885 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231320AbhFORfA (ORCPT ); Tue, 15 Jun 2021 13:35:00 -0400 X-UUID: f9c254ca4329491b8106fffdfce3f0ac-20210616 X-UUID: f9c254ca4329491b8106fffdfce3f0ac-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 636951409; Wed, 16 Jun 2021 01:32:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:45 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Dong Huang , Yidi Lin Subject: [PATCH 20/27] arm64: dts: mt8195: fix nor_flash node Date: Wed, 16 Jun 2021 01:32:26 +0800 Message-ID: <20210615173233.26682-20-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dong Huang Fix nor_flash with proper clock for mt8195 Signed-off-by: Dong Huang Signed-off-by: Yidi Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 560a0583ca0b..d78cd4d4201b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1162,8 +1162,12 @@ compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; reg = <0 0x1132c000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; - clock-names = "spi", "sf"; + clocks = <&topckgen CLK_TOP_SPINOR_SEL>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; + clock-names = "spi", "sf", "axi"; + assigned-clocks = <&topckgen CLK_TOP_SPINOR_SEL>; + assigned-clock-parents = <&clk26m>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From patchwork Tue Jun 15 17:32:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6633CC49361 for ; Tue, 15 Jun 2021 17:33:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50835613F8 for ; Tue, 15 Jun 2021 17:33:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231477AbhFORfK (ORCPT ); Tue, 15 Jun 2021 13:35:10 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34925 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231274AbhFORe6 (ORCPT ); Tue, 15 Jun 2021 13:34:58 -0400 X-UUID: 4f017c1fe921478db264e921e3471eb5-20210616 X-UUID: 4f017c1fe921478db264e921e3471eb5-20210616 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1875419988; Wed, 16 Jun 2021 01:32:47 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:45 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Trevor Wu Subject: [PATCH 21/27] arm64: dts: mt8195: add audio related nodes Date: Wed, 16 Jun 2021 01:32:27 +0800 Message-ID: <20210615173233.26682-21-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Trevor Wu add audio related nodes on dts and dtsi Signed-off-by: Trevor Wu --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 286 ++++++++++++++++++++++- 1 file changed, 285 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d78cd4d4201b..256818c4c0bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -230,6 +230,12 @@ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <50>; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; @@ -785,8 +791,280 @@ audsys: syscon@10890000 { compatible = "mediatek,mt8195-audsys", "syscon"; - reg = <0 0x10890000 0 0x1000>; + reg = <0 0x10890000 0 0x10000>; #clock-cells = <1>; + + afe: mt8195-afe-pcm { + compatible = "mediatek,mt8195-audio"; + topckgen = <&topckgen>; + power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; + interrupts = ; + clocks = <&clk26m>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&apmixedsys CLK_APMIXED_APLL3>, + <&apmixedsys CLK_APMIXED_APLL4>, + <&apmixedsys CLK_APMIXED_APLL5>, + <&apmixedsys CLK_APMIXED_HDMIRX_APLL>, + <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_APLL1_D4>, + <&topckgen CLK_TOP_APLL2>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_APLL3>, + <&topckgen CLK_TOP_APLL3_D4>, + <&topckgen CLK_TOP_APLL4>, + <&topckgen CLK_TOP_APLL4_D4>, + <&topckgen CLK_TOP_APLL5>, + <&topckgen CLK_TOP_APLL5_D4>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_HDMIRX_APLL>, + <&topckgen CLK_TOP_MAINPLL_D4_D4>, + <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_MAINPLL_D7_D2>, + <&topckgen CLK_TOP_UNIVPLL_D4>, + <&topckgen CLK_TOP_APLL1_SEL>, + <&topckgen CLK_TOP_APLL2_SEL>, + <&topckgen CLK_TOP_APLL3_SEL>, + <&topckgen CLK_TOP_APLL4_SEL>, + <&topckgen CLK_TOP_APLL5_SEL>, + <&topckgen CLK_TOP_A1SYS_HP_SEL>, + <&topckgen CLK_TOP_A2SYS_SEL>, + <&topckgen CLK_TOP_A3SYS_SEL>, + <&topckgen CLK_TOP_A4SYS_SEL>, + <&topckgen CLK_TOP_ASM_H_SEL>, + <&topckgen CLK_TOP_ASM_M_SEL>, + <&topckgen CLK_TOP_ASM_L_SEL>, + <&topckgen CLK_TOP_AUD_IEC_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_AUDIO_H_SEL>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>, + <&topckgen CLK_TOP_DPTX_M_SEL>, + <&topckgen CLK_TOP_INTDIR_SEL>, + <&topckgen CLK_TOP_I2SO1_M_SEL>, + <&topckgen CLK_TOP_I2SO2_M_SEL>, + <&topckgen CLK_TOP_I2SI1_M_SEL>, + <&topckgen CLK_TOP_I2SI2_M_SEL>, + <&topckgen CLK_TOP_MPHONE_SLAVE_B>, + <&topckgen CLK_TOP_CFG_26M_AUD>, + <&infracfg_ao CLK_INFRA_AO_AUDIO>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, + <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, + <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_LRCK_CNT>, + <&audsys CLK_AUD_SPDIFIN_TUNER_APLL>, + <&audsys CLK_AUD_SPDIFIN_TUNER_DBG>, + <&audsys CLK_AUD_UL_TML>, + <&audsys CLK_AUD_APLL1_TUNER>, + <&audsys CLK_AUD_APLL2_TUNER>, + <&audsys CLK_AUD_TOP0_SPDF>, + <&audsys CLK_AUD_APLL>, + <&audsys CLK_AUD_APLL2>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&audsys CLK_AUD_TML>, + <&audsys CLK_AUD_ADC>, + <&audsys CLK_AUD_DAC_HIRES>, + <&audsys CLK_AUD_A1SYS_HP>, + <&audsys CLK_AUD_AFE_DMIC1>, + <&audsys CLK_AUD_AFE_DMIC2>, + <&audsys CLK_AUD_AFE_DMIC3>, + <&audsys CLK_AUD_AFE_DMIC4>, + <&audsys CLK_AUD_AFE_26M_DMIC_TM>, + <&audsys CLK_AUD_UL_TML_HIRES>, + <&audsys CLK_AUD_ADC_HIRES>, + <&audsys CLK_AUD_ADDA6_ADC>, + <&audsys CLK_AUD_ADDA6_ADC_HIRES>, + <&audsys CLK_AUD_LINEIN_TUNER>, + <&audsys CLK_AUD_EARC_TUNER>, + <&audsys CLK_AUD_I2SIN>, + <&audsys CLK_AUD_TDM_IN>, + <&audsys CLK_AUD_I2S_OUT>, + <&audsys CLK_AUD_TDM_OUT>, + <&audsys CLK_AUD_HDMI_OUT>, + <&audsys CLK_AUD_ASRC11>, + <&audsys CLK_AUD_ASRC12>, + <&audsys CLK_AUD_MULTI_IN>, + <&audsys CLK_AUD_INTDIR>, + <&audsys CLK_AUD_A1SYS>, + <&audsys CLK_AUD_A2SYS>, + <&audsys CLK_AUD_PCMIF>, + <&audsys CLK_AUD_A3SYS>, + <&audsys CLK_AUD_A4SYS>, + <&audsys CLK_AUD_MEMIF_UL1>, + <&audsys CLK_AUD_MEMIF_UL2>, + <&audsys CLK_AUD_MEMIF_UL3>, + <&audsys CLK_AUD_MEMIF_UL4>, + <&audsys CLK_AUD_MEMIF_UL5>, + <&audsys CLK_AUD_MEMIF_UL6>, + <&audsys CLK_AUD_MEMIF_UL8>, + <&audsys CLK_AUD_MEMIF_UL9>, + <&audsys CLK_AUD_MEMIF_UL10>, + <&audsys CLK_AUD_MEMIF_DL2>, + <&audsys CLK_AUD_MEMIF_DL3>, + <&audsys CLK_AUD_MEMIF_DL6>, + <&audsys CLK_AUD_MEMIF_DL7>, + <&audsys CLK_AUD_MEMIF_DL8>, + <&audsys CLK_AUD_MEMIF_DL10>, + <&audsys CLK_AUD_MEMIF_DL11>, + <&audsys CLK_AUD_GASRC0>, + <&audsys CLK_AUD_GASRC1>, + <&audsys CLK_AUD_GASRC2>, + <&audsys CLK_AUD_GASRC3>, + <&audsys CLK_AUD_GASRC4>, + <&audsys CLK_AUD_GASRC5>, + <&audsys CLK_AUD_GASRC6>, + <&audsys CLK_AUD_GASRC7>, + <&audsys CLK_AUD_GASRC8>, + <&audsys CLK_AUD_GASRC9>, + <&audsys CLK_AUD_GASRC10>, + <&audsys CLK_AUD_GASRC11>, + <&audsys CLK_AUD_GASRC12>, + <&audsys CLK_AUD_GASRC13>, + <&audsys CLK_AUD_GASRC14>, + <&audsys CLK_AUD_GASRC15>, + <&audsys CLK_AUD_GASRC16>, + <&audsys CLK_AUD_GASRC17>, + <&audsys CLK_AUD_GASRC18>, + <&audsys CLK_AUD_GASRC19>; + clock-names = "clk26m", + "apll1", + "apll2", + "apll3", + "apll4", + "apll5", + "hdmirx_apll", + "apll1_ck", + "apll1_d4", + "apll2_ck", + "apll2_d4", + "apll3_ck", + "apll3_d4", + "apll4_ck", + "apll4_d4", + "apll5_ck", + "apll5_d4", + "apll12_div0", + "apll12_div1", + "apll12_div2", + "apll12_div3", + "apll12_div4", + "apll12_div9", + "hdmirx_apll_ck", + "mainpll_d4_d4", + "mainpll_d5_d2", + "mainpll_d7_d2", + "univpll_d4", + "apll1_sel", + "apll2_sel", + "apll3_sel", + "apll4_sel", + "apll5_sel", + "a1sys_hp_sel", + "a2sys_sel", + "a3sys_sel", + "a4sys_sel", + "asm_h_sel", + "asm_m_sel", + "asm_l_sel", + "aud_iec_sel", + "aud_intbus_sel", + "audio_h_sel", + "audio_local_bus_sel", + "dptx_m_sel", + "intdir_sel", + "i2so1_m_sel", + "i2so2_m_sel", + "i2si1_m_sel", + "i2si2_m_sel", + "mphone_slave_b", + "cfg_26m_aud", + "infra_ao_audio", + "infra_ao_audio_26m_b", + "scp_adsp_audiodsp", + "aud_afe", + "aud_lrck_cnt", + "aud_spdifin_tuner_apll", + "aud_spdifin_tuner_dbg", + "aud_ul_tml", + "aud_apll1_tuner", + "aud_apll2_tuner", + "aud_top0_spdf", + "aud_apll", + "aud_apll2", + "aud_dac", + "aud_dac_predis", + "aud_tml", + "aud_adc", + "aud_dac_hires", + "aud_a1sys_hp", + "aud_afe_dmic1", + "aud_afe_dmic2", + "aud_afe_dmic3", + "aud_afe_dmic4", + "aud_afe_26m_dmic_tm", + "aud_ul_tml_hires", + "aud_adc_hires", + "aud_adda6_adc", + "aud_adda6_adc_hires", + "aud_linein_tuner", + "aud_earc_tuner", + "aud_i2sin", + "aud_tdm_in", + "aud_i2s_out", + "aud_tdm_out", + "aud_hdmi_out", + "aud_asrc11", + "aud_asrc12", + "aud_multi_in", + "aud_intdir", + "aud_a1sys", + "aud_a2sys", + "aud_pcmif", + "aud_a3sys", + "aud_a4sys", + "aud_memif_ul1", + "aud_memif_ul2", + "aud_memif_ul3", + "aud_memif_ul4", + "aud_memif_ul5", + "aud_memif_ul6", + "aud_memif_ul8", + "aud_memif_ul9", + "aud_memif_ul10", + "aud_memif_dl2", + "aud_memif_dl3", + "aud_memif_dl6", + "aud_memif_dl7", + "aud_memif_dl8", + "aud_memif_dl10", + "aud_memif_dl11", + "aud_gasrc0", + "aud_gasrc1", + "aud_gasrc2", + "aud_gasrc3", + "aud_gasrc4", + "aud_gasrc5", + "aud_gasrc6", + "aud_gasrc7", + "aud_gasrc8", + "aud_gasrc9", + "aud_gasrc10", + "aud_gasrc11", + "aud_gasrc12", + "aud_gasrc13", + "aud_gasrc14", + "aud_gasrc15", + "aud_gasrc16", + "aud_gasrc17", + "aud_gasrc18", + "aud_gasrc19"; + status = "disabled"; + }; }; audsys_src: syscon@108a0000 { @@ -2155,4 +2433,10 @@ clocks = <&clk26m>; clock-names = "ddc-i2c"; }; + + sound: mt8195-sound { + compatible = "mediatek,mt8195_mt6359_rt1019_rt5682"; + mediatek,platform = <&afe>; + status = "disabled"; + }; }; From patchwork Tue Jun 15 17:32:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC96AC49EA2 for ; Tue, 15 Jun 2021 17:33:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D6BD161403 for ; Tue, 15 Jun 2021 17:33:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231479AbhFORfM (ORCPT ); Tue, 15 Jun 2021 13:35:12 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:35307 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231289AbhFORe7 (ORCPT ); Tue, 15 Jun 2021 13:34:59 -0400 X-UUID: 558b68876c8e450e9b7d3a41ff547240-20210616 X-UUID: 558b68876c8e450e9b7d3a41ff547240-20210616 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 789805714; Wed, 16 Jun 2021 01:32:47 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:46 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jitao Shi Subject: [PATCH 22/27] arm64: dts: mt8195: add edp nodes Date: Wed, 16 Jun 2021 01:32:28 +0800 Message-ID: <20210615173233.26682-22-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jitao Shi add edp nodes for mt8195 Signed-off-by: Jitao Shi --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 59 +++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 256818c4c0bf..d7d2c2a8f461 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -23,6 +23,8 @@ aliases { dpi1 = &disp_dpi1; + dp-intf0 = &dp_intf0; + dp-intf1 = &dp_intf1; }; clocks { @@ -1155,6 +1157,29 @@ status = "disabled"; }; + disp_pwm0: disp_pwm0@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM0_SEL>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + disp_pwm1: disp_pwm1@1100f000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM1_SEL>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; + clock-names = "main", "mm"; + status = "disabled"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -2397,6 +2422,30 @@ status = "disabled"; }; + dp_intf1: dp_intf1@1c113000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&topckgen CLK_TOP_DP_SEL>, + <&topckgen CLK_TOP_TVDPLL2_D2>, + <&topckgen CLK_TOP_TVDPLL2_D4>, + <&topckgen CLK_TOP_TVDPLL2_D8>, + <&topckgen CLK_TOP_TVDPLL2_D16>, + <&topckgen CLK_TOP_TVDPLL2>; + clock-names = "hf_fmm_ck", + "hf_fdp_ck", + "MUX_DP", + "TVDPLL_D2", + "TVDPLL_D4", + "TVDPLL_D8", + "TVDPLL_D16", + "DPI_CK"; + status = "disabled"; + }; + hdmi0: hdmi@1c300000 { compatible = "mediatek,mt8195-hdmi"; reg = <0 0x1c300000 0 0x1000>; @@ -2421,11 +2470,19 @@ edp_tx: edp_tx@1c500000 { status = "disabled"; - compatible = "mediatek,mt8195-dp_tx"; + compatible = "mediatek,mt8195-edp_tx"; reg = <0 0x1c500000 0 0x8000>; power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; interrupts = ; }; + + dp_tx: dp_tx@1c600000 { + compatible = "mediatek,mt8195-dp_tx"; + reg = <0 0x1c600000 0 0x8000>; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = ; + status = "disabled"; + }; }; hdmiddc0: ddc_i2c { From patchwork Tue Jun 15 17:32:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9380C48BE5 for ; Tue, 15 Jun 2021 17:33:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A709D61424 for ; Tue, 15 Jun 2021 17:33:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231446AbhFORfI (ORCPT ); Tue, 15 Jun 2021 13:35:08 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34885 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231258AbhFORe5 (ORCPT ); Tue, 15 Jun 2021 13:34:57 -0400 X-UUID: 7c456b5ac98944e9bc53e1851dd43532-20210616 X-UUID: 7c456b5ac98944e9bc53e1851dd43532-20210616 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1396806676; Wed, 16 Jun 2021 01:32:47 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:46 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jason-JH Lin Subject: [PATCH 23/27] arm64: dts: mt8195: add gce node Date: Wed, 16 Jun 2021 01:32:29 +0800 Message-ID: <20210615173233.26682-23-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jason-JH Lin add gce node on dts file. Signed-off-by: Jason-JH Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d7d2c2a8f461..51edb8ee35a8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include #include @@ -1075,6 +1076,26 @@ #clock-cells = <1>; }; + gce0: mdp_mailbox@10320000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = ; + #mbox-cells = <3>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>, + <&infracfg_ao CLK_INFRA_AO_GCE2>; + clock-names = "gce0", "gce1"; + }; + + gce1: disp_mailbox@10330000 { + compatible = "mediatek,mt8195-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = ; + #mbox-cells = <3>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>, + <&infracfg_ao CLK_INFRA_AO_GCE2>; + clock-names = "gce0", "gce1"; + }; + uart0: serial@11001100 { compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; reg = <0 0x11001100 0 0x100>; From patchwork Tue Jun 15 17:32:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F6E3C48BDF for ; Tue, 15 Jun 2021 17:33:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B8FE613E4 for ; Tue, 15 Jun 2021 17:33:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231354AbhFORfH (ORCPT ); Tue, 15 Jun 2021 13:35:07 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34890 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230507AbhFORe5 (ORCPT ); Tue, 15 Jun 2021 13:34:57 -0400 X-UUID: 5ff78f30d68143489c675450805a90a8-20210616 X-UUID: 5ff78f30d68143489c675450805a90a8-20210616 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 892757725; Wed, 16 Jun 2021 01:32:48 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:46 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Jason-JH Lin Subject: [PATCH 24/27] arm64: dts: mt8195: add gce setting for disply node Date: Wed, 16 Jun 2021 01:32:30 +0800 Message-ID: <20210615173233.26682-24-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jason-JH Lin add gce setting for disply node Signed-off-by: Jason-JH Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 51edb8ee35a8..e273833a49f8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2245,6 +2245,7 @@ reg-names = "vdosys0_config"; iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>; }; mutex: disp_mutex0@1c016000 { @@ -2255,6 +2256,7 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clock-names = "vdo0_mutex"; interrupts = ; + mediatek,gce-events = ; }; ovl0: disp_ovl@1c000000 { @@ -2264,6 +2266,7 @@ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>; }; rdma0: disp_rdma@1c002000 { @@ -2273,6 +2276,7 @@ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>; }; color0: disp_color@1c003000 { @@ -2281,6 +2285,7 @@ interrupts = ; clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>; }; ccorr0: disp_ccorr@1c004000 { @@ -2289,6 +2294,7 @@ interrupts = ; clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>; }; aal0: disp_aal@1c005000 { @@ -2297,6 +2303,7 @@ interrupts = ; clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>; }; gamma0: disp_gamma@1c006000 { @@ -2305,6 +2312,7 @@ interrupts = ; clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>; }; dither0: disp_dither@1c007000 { @@ -2313,6 +2321,7 @@ interrupts = ; clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>; }; merge0: disp_vpp_merge0@1c014000 { @@ -2321,6 +2330,7 @@ interrupts = ; clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>; }; dsc0: disp_dsc_wrap@1c009000 { @@ -2329,6 +2339,7 @@ interrupts = ; clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>; }; dp_intf0: dp_intf0@1c015000 { From patchwork Tue Jun 15 17:32:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF5FC48BDF for ; Tue, 15 Jun 2021 17:33:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D75E861417 for ; Tue, 15 Jun 2021 17:33:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231520AbhFORfS (ORCPT ); Tue, 15 Jun 2021 13:35:18 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34965 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231382AbhFORfE (ORCPT ); Tue, 15 Jun 2021 13:35:04 -0400 X-UUID: a4788473769c439a8a93dcebc126d821-20210616 X-UUID: a4788473769c439a8a93dcebc126d821-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1811227526; Wed, 16 Jun 2021 01:32:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:46 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Nancy Lin Subject: [PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195 Date: Wed, 16 Jun 2021 01:32:31 +0800 Message-ID: <20210615173233.26682-25-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Nancy Lin add vdosys1 support for MT8195 Signed-off-by: Nancy Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 178 +++++++++++++++++++++-- 1 file changed, 169 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index e273833a49f8..a98609989905 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,6 +26,7 @@ dpi1 = &disp_dpi1; dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + merge5 = &merge5; }; clocks { @@ -2241,22 +2242,27 @@ vdosys_config@1c01a000 { compatible = "mediatek,mt8195-vdosys"; - reg = <0 0x1c01a000 0 0x1000>; - reg-names = "vdosys0_config"; + reg = <0 0x1c01a000 0 0x1000>,<0 0x1c100000 0 0x1000>; + reg-names = "vdosys0_config","vdosys1_config"; iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; - mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>; + mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>, + <&gce1 1 0 CMDQ_THR_PRIO_4>; }; mutex: disp_mutex0@1c016000 { compatible = "mediatek,mt8195-disp-mutex"; - reg = <0 0x1c016000 0 0x1000>; - reg-names = "vdo0_mutex"; - clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + reg = <0 0x1c016000 0 0x1000>, + <0 0x1c101000 0 0x1000>; + reg-names = "vdo0_mutex","vdo1_mutex"; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>, + <&vdosys1 CLK_VDO1_DISP_MUTEX>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; - clock-names = "vdo0_mutex"; - interrupts = ; - mediatek,gce-events = ; + clock-names = "vdo0_mutex","sub_mutex"; + interrupts = , + ; + mediatek,gce-events = , + ; }; ovl0: disp_ovl@1c000000 { @@ -2446,6 +2452,92 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + disp_pseudo_ovl0@1c104000 { + compatible = "mediatek,mt8195-disp-pseudo-ovl"; + reg = <0 0x1c104000 0 0x1000>, + <0 0x1c105000 0 0x1000>, + <0 0x1c106000 0 0x1000>, + <0 0x1c107000 0 0x1000>, + <0 0x1c108000 0 0x1000>, + <0 0x1c109000 0 0x1000>, + <0 0x1c10A000 0 0x1000>, + <0 0x1c10B000 0 0x1000>, + <0 0x1c10C000 0 0x1000>, + <0 0x1c10D000 0 0x1000>, + <0 0x1c10E000 0 0x1000>, + <0 0x1c10F000 0 0x1000>, + <0 0x1c100000 0 0x1000>; + reg-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1","vdo1_mdp_rdma2", + "vdo1_mdp_rdma3","vdo1_mdp_rdma4", + "vdo1_mdp_rdma5","vdo1_mdp_rdma6", + "vdo1_mdp_rdma7","vdo1_merge0", + "vdo1_merge1","vdo1_merge2","vdo1_merge3","top"; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0xA000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0xB000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0xC000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0xD000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0xE000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0xF000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>, + <&vdosys1 CLK_VDO1_MDP_RDMA1>, + <&vdosys1 CLK_VDO1_MDP_RDMA2>, + <&vdosys1 CLK_VDO1_MDP_RDMA3>, + <&vdosys1 CLK_VDO1_MDP_RDMA4>, + <&vdosys1 CLK_VDO1_MDP_RDMA5>, + <&vdosys1 CLK_VDO1_MDP_RDMA6>, + <&vdosys1 CLK_VDO1_MDP_RDMA7>, + <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1", + "vdo1_mdp_rdma2","vdo1_mdp_rdma3", + "vdo1_mdp_rdma4","vdo1_mdp_rdma5", + "vdo1_mdp_rdma6","vdo1_mdp_rdma7", + "vdo1_merge0","vdo1_merge1", + "vdo1_merge2","vdo1_merge3", + "vdo1_merge0_async","vdo1_merge1_async", + "vdo1_merge2_async","vdo1_merge3_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,larb = <&larb2>; + mediatek,smi-id = <0>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + interrupts = , /*rdma0*/ + , /*rdma1*/ + , /*rdma2*/ + , /*rdma3*/ + , /*rdma4*/ + , /*rdma5*/ + , /*rdma6*/ + , /*rdma7*/ + , /*merge0*/ + , /*merge1*/ + , /*merge2*/ + ; /*merge3*/ + }; + + merge5: disp_vpp_merge5@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge5","merge5_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>; + }; + disp_dpi1: disp_dpi1@1c112000 { compatible = "mediatek,mt8195-dpi"; reg = <0 0x1c112000 0 0x1000>; @@ -2478,6 +2570,54 @@ status = "disabled"; }; + disp_ethdr@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11A000 0 0x1000>, + <0 0x1c11B000 0 0x1000>, + <0 0x1c11C000 0 0x1000>, + <0 0x1c100000 0 0x1000>; + reg-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1", + "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be", + "hdr_adl_ds","top"; + mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>, + <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>, + <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR_SEL>; + clock-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1", + "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be", + "hdr_adl_ds","hdr_vdo_fe0_async", + "hdr_vdo_fe1_async","hdr_gfx_fe0_async", + "hdr_gfx_fe1_async","hdr_vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,larb = <&larb3>; + mediatek,smi-id = <1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = ; /*disp mixer*/ + }; + hdmi0: hdmi@1c300000 { compatible = "mediatek,mt8195-hdmi"; reg = <0 0x1c300000 0 0x1000>; @@ -2517,6 +2657,26 @@ }; }; + disp_pseudo_ovl_l2 { + compatible = "mediatek,mt8195-pseudo-ovl-larb"; + mediatek,larb-id = <2>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>, + <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>, + <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>, + <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; + }; + + disp_pseudo_ovl_l3 { + compatible = "mediatek,mt8195-pseudo-ovl-larb"; + mediatek,larb-id = <3>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>, + <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>, + <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>, + <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; + }; + hdmiddc0: ddc_i2c { compatible = "mediatek,mt8195-hdmi-ddc"; clocks = <&clk26m>; From patchwork Tue Jun 15 17:32:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 460668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D495C48BE8 for ; Tue, 15 Jun 2021 17:33:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E0286143E for ; Tue, 15 Jun 2021 17:33:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231423AbhFORfG (ORCPT ); Tue, 15 Jun 2021 13:35:06 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34916 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231233AbhFORe4 (ORCPT ); Tue, 15 Jun 2021 13:34:56 -0400 X-UUID: 1acad08ecc874235a51cc75833a71ce4-20210616 X-UUID: 1acad08ecc874235a51cc75833a71ce4-20210616 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1410474194; Wed, 16 Jun 2021 01:32:48 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:46 +0800 From: Tinghan Shen To: , CC: , , , , , , , , Tinghan Shen Subject: [PATCH 26/27] arm64: dts: mt8195: add scp device node Date: Wed, 16 Jun 2021 01:32:32 +0800 Message-ID: <20210615173233.26682-26-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add scp node for mt8195 Signed-off-by: Tinghan Shen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a98609989905..25a6ee7c6659 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -787,6 +787,16 @@ status = "disabled"; }; + scp: scp@10500000 { + compatible = "mediatek,mt8195-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10700000 0 0x8000>, + <0 0x10720000 0 0xe0000>; + reg-names = "sram", "l1tcm", "cfg"; + interrupts = ; + status = "okay"; + }; + scp_adsp: syscon@10720000 { compatible = "mediatek,mt8195-scp_adsp", "syscon"; reg = <0 0x10720000 0 0x1000>; From patchwork Tue Jun 15 17:32:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 461617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A137C49EA6 for ; Tue, 15 Jun 2021 17:33:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8610E61424 for ; Tue, 15 Jun 2021 17:33:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231202AbhFORfQ (ORCPT ); Tue, 15 Jun 2021 13:35:16 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:34916 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231371AbhFORfD (ORCPT ); Tue, 15 Jun 2021 13:35:03 -0400 X-UUID: 1caaa7783bf846d3b6503ba572f258cc-20210616 X-UUID: 1caaa7783bf846d3b6503ba572f258cc-20210616 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1925669352; Wed, 16 Jun 2021 01:32:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 01:32:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 16 Jun 2021 01:32:46 +0800 From: Tinghan Shen To: , CC: , , , , , , , , YT Lee Subject: [PATCH 27/27] arm64: dts: mt8195: add cpufreq device nodes Date: Wed, 16 Jun 2021 01:32:33 +0800 Message-ID: <20210615173233.26682-27-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.15.GIT In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com> References: <20210615173233.26682-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: YT Lee this 8195 cpufreq device nodes is based on below dt-bindings document https://patchwork.kernel.org/project/linux-mediatek/patch/1615549235-27700-3-git-send-email-hector.yuan@mediatek.com/ and it also rely on below patches to work [1]https://patchwork.kernel.org/project/linux-mediatek/patch/1615549235-27700-2-git-send-email-hector.yuan@mediatek.com/ [2]https://patchwork.kernel.org/project/linux-pm/patch/20201105125001.32473-1-lukasz.luba@arm.com/ [3]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-3-lukasz.luba@arm.com/ [4]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-4-lukasz.luba@arm.com/ [5]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-5-lukasz.luba@arm.com/ Signed-off-by: YT Lee --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 25a6ee7c6659..e5ebf8d663df 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -54,6 +54,7 @@ compatible = "arm,cortex-a55", "arm,armv8"; reg = <0x000>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpuoff_l &clusteroff_l>; @@ -66,6 +67,7 @@ compatible = "arm,cortex-a55", "arm,armv8"; reg = <0x100>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpuoff_l &clusteroff_l>; @@ -78,6 +80,7 @@ compatible = "arm,cortex-a55", "arm,armv8"; reg = <0x200>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpuoff_l &clusteroff_l>; @@ -90,6 +93,7 @@ compatible = "arm,cortex-a55", "arm,armv8"; reg = <0x300>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpuoff_l &clusteroff_l>; @@ -102,6 +106,7 @@ compatible = "arm,cortex-a78", "arm,armv8"; reg = <0x400>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b>; @@ -114,6 +119,7 @@ compatible = "arm,cortex-a78", "arm,armv8"; reg = <0x500>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b>; @@ -126,6 +132,7 @@ compatible = "arm,cortex-a78", "arm,armv8"; reg = <0x600>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b>; @@ -138,6 +145,7 @@ compatible = "arm,cortex-a78", "arm,armv8"; reg = <0x700>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b>; @@ -257,6 +265,12 @@ method = "smc"; }; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>;