From patchwork Tue Jun 15 02:43:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 460953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1140DC48BE8 for ; Tue, 15 Jun 2021 02:47:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F3BAA613C2 for ; Tue, 15 Jun 2021 02:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230364AbhFOCtO (ORCPT ); Mon, 14 Jun 2021 22:49:14 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:10061 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230331AbhFOCtC (ORCPT ); Mon, 14 Jun 2021 22:49:02 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.56]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G3t1b1GGKzZf0c; Tue, 15 Jun 2021 10:44:03 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:57 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:57 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH V2 net-next 02/10] net: z85230: add blank line after declarations Date: Tue, 15 Jun 2021 10:43:37 +0800 Message-ID: <1623725025-50976-3-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> References: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li This patch fixes the checkpatch error about missing a blank line after declarations. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index f074cb1..3036d58 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -74,6 +74,7 @@ static inline int z8530_read_port(unsigned long p) { u8 r=inb(Z8530_PORT_OF(p)); + if(p&Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */ udelay(5); return r; @@ -133,6 +134,7 @@ static inline u8 read_zsreg(struct z8530_channel *c, u8 reg) static inline u8 read_zsdata(struct z8530_channel *c) { u8 r; + r=z8530_read_port(c->dataio); return r; } @@ -653,6 +655,7 @@ static void z8530_tx_clear(struct z8530_channel *c) static void z8530_status_clear(struct z8530_channel *chan) { u8 status=read_zsreg(chan, R0); + if(status&TxEOM) write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_EXT_INT); @@ -1360,6 +1363,7 @@ int z8530_channel_load(struct z8530_channel *c, u8 *rtable) while(*rtable!=255) { int reg=*rtable++; + if(reg>0x0F) write_zsreg(c, R15, c->regs[15]|1); write_zsreg(c, reg&0x0F, *rtable); @@ -1401,6 +1405,7 @@ EXPORT_SYMBOL(z8530_channel_load); static void z8530_tx_begin(struct z8530_channel *c) { unsigned long flags; + if(c->tx_skb) return; @@ -1672,6 +1677,7 @@ static void z8530_rx_done(struct z8530_channel *c) static inline int spans_boundary(struct sk_buff *skb) { unsigned long a=(unsigned long)skb->data; + a^=(a+skb->len); if(a&0x00010000) /* If the 64K bit is different.. */ return 1; From patchwork Tue Jun 15 02:43:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 460950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6D69C2B9F4 for ; Tue, 15 Jun 2021 02:47:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB7FB613B6 for ; Tue, 15 Jun 2021 02:47:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231286AbhFOCta (ORCPT ); Mon, 14 Jun 2021 22:49:30 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:10063 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230411AbhFOCtH (ORCPT ); Mon, 14 Jun 2021 22:49:07 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G3t1h43HxzZf14; Tue, 15 Jun 2021 10:44:08 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:57 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:57 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH V2 net-next 04/10] net: z85230: replace comparison to NULL with "!skb" Date: Tue, 15 Jun 2021 10:43:39 +0800 Message-ID: <1623725025-50976-5-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> References: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li According to the chackpatch.pl, comparison to NULL could be written "!skb". Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index 94ed9a2..0162239 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -851,12 +851,12 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) return -EMSGSIZE; c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); - if(c->rx_buf[0]==NULL) + if (!c->rx_buf[0]) return -ENOBUFS; c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2; c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); - if(c->tx_dma_buf[0]==NULL) + if (!c->tx_dma_buf[0]) { free_page((unsigned long)c->rx_buf[0]); c->rx_buf[0]=NULL; @@ -1039,7 +1039,7 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) return -EMSGSIZE; c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); - if(c->tx_dma_buf[0]==NULL) + if (!c->tx_dma_buf[0]) return -ENOBUFS; c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2; @@ -1397,7 +1397,7 @@ static void z8530_tx_begin(struct z8530_channel *c) c->tx_next_skb=NULL; c->tx_ptr=c->tx_next_ptr; - if(c->tx_skb==NULL) + if (!c->tx_skb) { /* Idle on */ if(c->dma_tx) @@ -1486,7 +1486,7 @@ static void z8530_tx_done(struct z8530_channel *c) struct sk_buff *skb; /* Actually this can happen.*/ - if (c->tx_skb == NULL) + if (!c->tx_skb) return; skb = c->tx_skb; @@ -1589,7 +1589,7 @@ static void z8530_rx_done(struct z8530_channel *c) */ skb = dev_alloc_skb(ct); - if (skb == NULL) { + if (!skb) { c->netdevice->stats.rx_dropped++; netdev_warn(c->netdevice, "Memory squeeze\n"); } else { @@ -1630,7 +1630,7 @@ static void z8530_rx_done(struct z8530_channel *c) RT_UNLOCK; c->skb2 = dev_alloc_skb(c->mtu); - if (c->skb2 == NULL) + if (!c->skb2) netdev_warn(c->netdevice, "memory squeeze\n"); else skb_put(c->skb2, c->mtu); From patchwork Tue Jun 15 02:43:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 460952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 275ADC48BE8 for ; Tue, 15 Jun 2021 02:47:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1296761166 for ; Tue, 15 Jun 2021 02:47:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230447AbhFOCtT (ORCPT ); Mon, 14 Jun 2021 22:49:19 -0400 Received: from szxga08-in.huawei.com ([45.249.212.255]:7259 "EHLO szxga08-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230346AbhFOCtD (ORCPT ); Mon, 14 Jun 2021 22:49:03 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4G3szB4hpQz1BMYB; Tue, 15 Jun 2021 10:41:58 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:58 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:57 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH V2 net-next 05/10] net: z85230: fix the comments style issue Date: Tue, 15 Jun 2021 10:43:40 +0800 Message-ID: <1623725025-50976-6-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> References: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li Networking block comments don't use an empty /* line, use /* Comment... Block comments use * on subsequent lines. Block comments use a trailing */ on a separate line. This patch fixes the comments style issues. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 214 ++++++++++++++++++----------------------------- 1 file changed, 83 insertions(+), 131 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index 0162239..e130c8c 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-or-later -/* - * - * (c) Copyright 1998 Alan Cox +/* (c) Copyright 1998 Alan Cox * (c) Copyright 2000, 2001 Red Hat Inc * * Development of this driver was funded by Equiinet Ltd @@ -183,8 +181,7 @@ static inline void write_zsdata(struct z8530_channel *c, u8 val) z8530_write_port(c->dataio, val); } -/* - * Register loading parameters for a dead port +/* Register loading parameters for a dead port */ u8 z8530_dead_port[]= @@ -193,12 +190,10 @@ u8 z8530_dead_port[]= }; EXPORT_SYMBOL(z8530_dead_port); -/* - * Register loading parameters for currently supported circuit types +/* Register loading parameters for currently supported circuit types */ -/* - * Data clocked by telco end. This is the correct data for the UK +/* Data clocked by telco end. This is the correct data for the UK * "kilostream" service, and most other similar services. */ @@ -222,8 +217,7 @@ u8 z8530_hdlc_kilostream[]= }; EXPORT_SYMBOL(z8530_hdlc_kilostream); -/* - * As above but for enhanced chips. +/* As above but for enhanced chips. */ u8 z8530_hdlc_kilostream_85230[]= @@ -331,8 +325,7 @@ static void z8530_rx(struct z8530_channel *c) ch=read_zsdata(c); stat=read_zsreg(c, R1); - /* - * Overrun ? + /* Overrun ? */ if(c->count < c->max) { @@ -342,8 +335,7 @@ static void z8530_rx(struct z8530_channel *c) if(stat&END_FR) { - /* - * Error ? + /* Error ? */ if(stat&(Rx_OVR|CRC_ERR)) { @@ -365,8 +357,7 @@ static void z8530_rx(struct z8530_channel *c) } else { - /* - * Drop the lock for RX processing, or + /* Drop the lock for RX processing, or * there are deadlocks */ z8530_rx_done(c); @@ -374,8 +365,7 @@ static void z8530_rx(struct z8530_channel *c) } } } - /* - * Clear irq + /* Clear irq */ write_zsctrl(c, ERR_RES); write_zsctrl(c, RES_H_IUS); @@ -398,8 +388,7 @@ static void z8530_tx(struct z8530_channel *c) if(!(read_zsreg(c, R0)&4)) return; c->txcount--; - /* - * Shovel out the byte + /* Shovel out the byte */ write_zsreg(c, R8, *c->tx_ptr++); write_zsctrl(c, RES_H_IUS); @@ -411,8 +400,7 @@ static void z8530_tx(struct z8530_channel *c) } } - /* - * End of frame TX - fire another one + /* End of frame TX - fire another one */ write_zsctrl(c, RES_Tx_P); @@ -607,8 +595,7 @@ static struct z8530_irqhandler z8530_txdma_sync = { static void z8530_rx_clear(struct z8530_channel *c) { - /* - * Data and status bytes + /* Data and status bytes */ u8 stat; @@ -617,8 +604,7 @@ static void z8530_rx_clear(struct z8530_channel *c) if(stat&END_FR) write_zsctrl(c, RES_Rx_CRC); - /* - * Clear irq + /* Clear irq */ write_zsctrl(c, ERR_RES); write_zsctrl(c, RES_H_IUS); @@ -704,11 +690,13 @@ irqreturn_t z8530_interrupt(int irq, void *dev_id) if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT))) break; - /* This holds the IRQ status. On the 8530 you must read it from chan - A even though it applies to the whole chip */ + /* This holds the IRQ status. On the 8530 you must read it + * from chan A even though it applies to the whole chip + */ /* Now walk the chip and see what it is wanting - it may be - an IRQ for someone else remember */ + * an IRQ for someone else remember + */ irqs=dev->chanA.irqs; @@ -835,14 +823,13 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->count = 0; c->skb = NULL; c->skb2 = NULL; - /* - * Load the DMA interfaces up + + /* Load the DMA interfaces up */ c->rxdma_on = 0; c->txdma_on = 0; - - /* - * Allocate the DMA flip buffers. Limit by page size. + + /* Allocate the DMA flip buffers. Limit by page size. * Everyone runs 1500 mtu or less on wan links so this * should be fine. */ @@ -869,14 +856,12 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->dma_num=0; c->dma_ready=1; - /* - * Enable DMA control mode + /* Enable DMA control mode */ spin_lock_irqsave(c->lock, cflags); - - /* - * TX DMA via DIR/REQ + + /* TX DMA via DIR/REQ */ c->regs[R14]|= DTRREQ; @@ -884,9 +869,8 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->regs[R1]&= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); - - /* - * RX DMA via W/Req + + /* RX DMA via W/Req */ c->regs[R1]|= WT_FN_RDYFN; @@ -896,13 +880,11 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) write_zsreg(c, R1, c->regs[R1]); c->regs[R1]|= WT_RDY_ENAB; write_zsreg(c, R1, c->regs[R1]); - - /* - * DMA interrupts + + /* DMA interrupts */ - - /* - * Set up the DMA configuration + + /* Set up the DMA configuration */ dflags=claim_dma_lock(); @@ -920,9 +902,8 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) disable_dma(c->txdma); release_dma_lock(dflags); - - /* - * Select the DMA interrupt handlers + + /* Select the DMA interrupt handlers */ c->rxdma_on = 1; @@ -956,9 +937,8 @@ int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c) c->irqs = &z8530_nop; c->max = 0; c->sync = 0; - - /* - * Disable the PC DMA channels + + /* Disable the PC DMA channels */ flags=claim_dma_lock(); @@ -976,8 +956,7 @@ int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c) spin_lock_irqsave(c->lock, flags); - /* - * Disable DMA control mode + /* Disable DMA control mode */ c->regs[R1]&= ~WT_RDY_ENAB; @@ -1028,9 +1007,8 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->count = 0; c->skb = NULL; c->skb2 = NULL; - - /* - * Allocate the DMA flip buffers. Limit by page size. + + /* Allocate the DMA flip buffers. Limit by page size. * Everyone runs 1500 mtu or less on wan links so this * should be fine. */ @@ -1046,15 +1024,13 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) spin_lock_irqsave(c->lock, cflags); - /* - * Load the PIO receive ring + /* Load the PIO receive ring */ z8530_rx_done(c); z8530_rx_done(c); - /* - * Load the DMA interfaces up + /* Load the DMA interfaces up */ c->rxdma_on = 0; @@ -1065,21 +1041,18 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->dma_ready=1; c->dma_tx = 1; - /* - * Enable DMA control mode + /* Enable DMA control mode */ - /* - * TX DMA via DIR/REQ + /* TX DMA via DIR/REQ */ c->regs[R14]|= DTRREQ; write_zsreg(c, R14, c->regs[R14]); c->regs[R1]&= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); - - /* - * Set up the DMA configuration + + /* Set up the DMA configuration */ dflags = claim_dma_lock(); @@ -1090,9 +1063,8 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) disable_dma(c->txdma); release_dma_lock(dflags); - - /* - * Select the DMA interrupt handlers + + /* Select the DMA interrupt handlers */ c->rxdma_on = 0; @@ -1127,9 +1099,8 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) c->irqs = &z8530_nop; c->max = 0; c->sync = 0; - - /* - * Disable the PC DMA channels + + /* Disable the PC DMA channels */ dflags = claim_dma_lock(); @@ -1141,8 +1112,7 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) release_dma_lock(dflags); - /* - * Disable DMA control mode + /* Disable DMA control mode */ c->regs[R1]&= ~WT_RDY_ENAB; @@ -1167,8 +1137,7 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) } EXPORT_SYMBOL(z8530_sync_txdma_close); -/* - * Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny +/* Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny * it exists... */ @@ -1200,14 +1169,14 @@ void z8530_describe(struct z8530_dev *dev, char *mapping, unsigned long io) } EXPORT_SYMBOL(z8530_describe); -/* - * Locked operation part of the z8530 init code +/* Locked operation part of the z8530 init code */ static inline int do_z8530_init(struct z8530_dev *dev) { /* NOP the interrupt handlers first - we might get a - floating IRQ transition when we reset the chip */ + * floating IRQ transition when we reset the chip + */ dev->chanA.irqs=&z8530_nop; dev->chanB.irqs=&z8530_nop; dev->chanA.dcdcheck=DCD; @@ -1225,15 +1194,13 @@ static inline int do_z8530_init(struct z8530_dev *dev) return -ENODEV; dev->type=Z8530; - - /* - * See the application note. + + /* See the application note. */ write_zsreg(&dev->chanA, R15, 0x01); - - /* - * If we can set the low bit of R15 then + + /* If we can set the low bit of R15 then * the chip is enhanced. */ @@ -1247,17 +1214,15 @@ static inline int do_z8530_init(struct z8530_dev *dev) else dev->type = Z85C30; /* Z85C30, 1 byte FIFO */ } - - /* - * The code assumes R7' and friends are + + /* The code assumes R7' and friends are * off. Use write_zsext() for these and keep * this bit clear. */ write_zsreg(&dev->chanA, R15, 0); - - /* - * At this point it looks like the chip is behaving + + /* At this point it looks like the chip is behaving */ memcpy(dev->chanA.regs, reg_init, 16); @@ -1404,8 +1369,7 @@ static void z8530_tx_begin(struct z8530_channel *c) { flags=claim_dma_lock(); disable_dma(c->txdma); - /* - * Check if we crapped out. + /* Check if we crapped out. */ if (get_dma_residue(c->txdma)) { @@ -1422,8 +1386,7 @@ static void z8530_tx_begin(struct z8530_channel *c) if(c->dma_tx) { - /* - * FIXME. DMA is broken for the original 8530, + /* FIXME. DMA is broken for the original 8530, * on the older parts we need to set a flag and * wait for a further TX interrupt to fire this * stage off @@ -1432,8 +1395,7 @@ static void z8530_tx_begin(struct z8530_channel *c) flags=claim_dma_lock(); disable_dma(c->txdma); - /* - * These two are needed by the 8530/85C30 + /* These two are needed by the 8530/85C30 * and must be issued when idling. */ @@ -1464,8 +1426,7 @@ static void z8530_tx_begin(struct z8530_channel *c) } } } - /* - * Since we emptied tx_skb we can ask for more + /* Since we emptied tx_skb we can ask for more */ netif_wake_queue(c->netdevice); } @@ -1529,22 +1490,19 @@ static void z8530_rx_done(struct z8530_channel *c) { struct sk_buff *skb; int ct; - - /* - * Is our receive engine in DMA mode + + /* Is our receive engine in DMA mode */ if(c->rxdma_on) { - /* - * Save the ready state and the buffer currently + /* Save the ready state and the buffer currently * being used as the DMA target */ int ready=c->dma_ready; unsigned char *rxb=c->rx_buf[c->dma_num]; unsigned long flags; - - /* - * Complete this DMA. Necessary to find the length + + /* Complete this DMA. Necessary to find the length */ flags=claim_dma_lock(); @@ -1555,9 +1513,8 @@ static void z8530_rx_done(struct z8530_channel *c) if(ct<0) ct=2; /* Shit happens.. */ c->dma_ready=0; - - /* - * Normal case: the other slot is free, start the next DMA + + /* Normal case: the other slot is free, start the next DMA * into it immediately. */ @@ -1569,19 +1526,20 @@ static void z8530_rx_done(struct z8530_channel *c) set_dma_count(c->rxdma, c->mtu); c->rxdma_on = 1; enable_dma(c->rxdma); - /* Stop any frames that we missed the head of - from passing */ + /* Stop any frames that we missed the head of + * from passing + */ write_zsreg(c, R0, RES_Rx_CRC); } else /* Can't occur as we dont reenable the DMA irq until - after the flip is done */ + * after the flip is done + */ netdev_warn(c->netdevice, "DMA flip overrun!\n"); release_dma_lock(flags); - /* - * Shove the old buffer into an sk_buff. We can't DMA + /* Shove the old buffer into an sk_buff. We can't DMA * directly into one on a PC - it might be above the 16Mb * boundary. Optimisation - we could check to see if we * can avoid the copy. Optimisation 2 - make the memcpy @@ -1603,8 +1561,7 @@ static void z8530_rx_done(struct z8530_channel *c) RT_LOCK; skb = c->skb; - /* - * The game we play for non DMA is similar. We want to + /* The game we play for non DMA is similar. We want to * get the controller set up for the next packet as fast * as possible. We potentially only have one byte + the * fifo length for this. Thus we want to flip to the new @@ -1637,8 +1594,7 @@ static void z8530_rx_done(struct z8530_channel *c) c->netdevice->stats.rx_packets++; c->netdevice->stats.rx_bytes += ct; } - /* - * If we received a frame we must now process it. + /* If we received a frame we must now process it. */ if (skb) { skb_trim(skb, ct); @@ -1690,16 +1646,13 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) return NETDEV_TX_BUSY; /* PC SPECIFIC - DMA limits */ - - /* - * If we will DMA the transmit and its gone over the ISA bus + /* If we will DMA the transmit and its gone over the ISA bus * limit, then copy to the flip buffer */ if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb))) { - /* - * Send the flip buffer, and flip the flippy bit. + /* Send the flip buffer, and flip the flippy bit. * We don't care which is used when just so long as * we never use the same buffer twice in a row. Since * only one buffer can be going out at a time the other @@ -1723,8 +1676,7 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) } EXPORT_SYMBOL(z8530_queue_xmit); -/* - * Module support +/* Module support */ static const char banner[] __initconst = KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n"; From patchwork Tue Jun 15 02:43:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 460954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB4BEC2B9F4 for ; Tue, 15 Jun 2021 02:47:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8511613FA for ; Tue, 15 Jun 2021 02:47:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230400AbhFOCtG (ORCPT ); Mon, 14 Jun 2021 22:49:06 -0400 Received: from szxga08-in.huawei.com ([45.249.212.255]:7258 "EHLO szxga08-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230344AbhFOCtD (ORCPT ); Mon, 14 Jun 2021 22:49:03 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.54]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4G3szB5RJyz1BMb1; Tue, 15 Jun 2021 10:41:58 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:58 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:57 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH V2 net-next 06/10] net: z85230: fix the code style issue about "if..else.." Date: Tue, 15 Jun 2021 10:43:41 +0800 Message-ID: <1623725025-50976-7-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> References: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li According to the chackpatch.pl, else should follow close brace '}', braces {} should be used on all arms of this statement. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index e130c8c..34004e4 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -354,9 +354,7 @@ static void z8530_rx(struct z8530_channel *c) /* printk("crc error\n"); */ } /* Shove the frame upstream */ - } - else - { + } else { /* Drop the lock for RX processing, or * there are deadlocks */ @@ -489,9 +487,7 @@ static void z8530_dma_rx(struct z8530_channel *chan) } write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_H_IUS); - } - else - { + } else { /* DMA is off right now, drain the slow way */ z8530_rx(chan); } @@ -1379,9 +1375,7 @@ static void z8530_tx_begin(struct z8530_channel *c) release_dma_lock(flags); } c->txcount=0; - } - else - { + } else { c->txcount=c->tx_skb->len; if(c->dma_tx) @@ -1412,9 +1406,7 @@ static void z8530_tx_begin(struct z8530_channel *c) release_dma_lock(flags); write_zsctrl(c, RES_EOM_L); write_zsreg(c, R5, c->regs[R5]|TxENAB); - } - else - { + } else { /* ABUNDER off */ write_zsreg(c, R10, c->regs[10]); write_zsctrl(c, RES_Tx_CRC); @@ -1530,12 +1522,12 @@ static void z8530_rx_done(struct z8530_channel *c) * from passing */ write_zsreg(c, R0, RES_Rx_CRC); - } - else + } else { /* Can't occur as we dont reenable the DMA irq until * after the flip is done */ netdev_warn(c->netdevice, "DMA flip overrun!\n"); + } release_dma_lock(flags); @@ -1661,9 +1653,9 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used]; c->tx_dma_used^=1; /* Flip temp buffer */ skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len); + } else { + c->tx_next_ptr = skb->data; } - else - c->tx_next_ptr=skb->data; RT_LOCK; c->tx_next_skb=skb; RT_UNLOCK; From patchwork Tue Jun 15 02:43:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 460949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EE56C2B9F4 for ; Tue, 15 Jun 2021 02:47:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 274A5611CE for ; Tue, 15 Jun 2021 02:47:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230451AbhFOCto (ORCPT ); Mon, 14 Jun 2021 22:49:44 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6494 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230462AbhFOCtN (ORCPT ); Mon, 14 Jun 2021 22:49:13 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4G3t1n23QlzZhKb; Tue, 15 Jun 2021 10:44:13 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:58 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 15 Jun 2021 10:46:58 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH V2 net-next 08/10] net: z85230: add some required spaces Date: Tue, 15 Jun 2021 10:43:43 +0800 Message-ID: <1623725025-50976-9-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> References: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li Add space required before the open parenthesis '(' and '{'. Add space required after that close brace '}' and ',' Add spaces required around that '=' , '&', '*', '|', '+', '/' and '-'. Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 418 ++++++++++++++++++++++++----------------------- 1 file changed, 210 insertions(+), 208 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index 5db452d..cab963f 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -71,9 +71,9 @@ static inline int z8530_read_port(unsigned long p) { - u8 r=inb(Z8530_PORT_OF(p)); + u8 r = inb(Z8530_PORT_OF(p)); - if(p&Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */ + if (p & Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */ udelay(5); return r; } @@ -95,8 +95,8 @@ static inline int z8530_read_port(unsigned long p) static inline void z8530_write_port(unsigned long p, u8 d) { - outb(d,Z8530_PORT_OF(p)); - if(p&Z8530_PORT_SLEEP) + outb(d, Z8530_PORT_OF(p)); + if (p & Z8530_PORT_SLEEP) udelay(5); } @@ -116,7 +116,7 @@ static void z8530_tx_done(struct z8530_channel *c); static inline u8 read_zsreg(struct z8530_channel *c, u8 reg) { - if(reg) + if (reg) z8530_write_port(c->ctrlio, reg); return z8530_read_port(c->ctrlio); } @@ -133,7 +133,7 @@ static inline u8 read_zsdata(struct z8530_channel *c) { u8 r; - r=z8530_read_port(c->dataio); + r = z8530_read_port(c->dataio); return r; } @@ -151,7 +151,7 @@ static inline u8 read_zsdata(struct z8530_channel *c) */ static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val) { - if(reg) + if (reg) z8530_write_port(c->ctrlio, reg); z8530_write_port(c->ctrlio, val); } @@ -184,7 +184,7 @@ static inline void write_zsdata(struct z8530_channel *c, u8 val) /* Register loading parameters for a dead port */ -u8 z8530_dead_port[]= +u8 z8530_dead_port[] = { 255 }; @@ -197,22 +197,22 @@ EXPORT_SYMBOL(z8530_dead_port); * "kilostream" service, and most other similar services. */ -u8 z8530_hdlc_kilostream[]= +u8 z8530_hdlc_kilostream[] = { - 4, SYNC_ENAB|SDLC|X1CLK, + 4, SYNC_ENAB | SDLC | X1CLK, 2, 0, /* No vector */ 1, 0, - 3, ENT_HM|RxCRC_ENAB|Rx8, - 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR, + 3, ENT_HM | RxCRC_ENAB | Rx8, + 5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR, 9, 0, /* Disable interrupts */ 6, 0xFF, 7, FLAG, - 10, ABUNDER|NRZ|CRCPS,/*MARKIDLE ??*/ + 10, ABUNDER | NRZ | CRCPS,/*MARKIDLE ??*/ 11, TCTRxCP, 14, DISDPLL, - 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE, - 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx, - 9, NV|MIE|NORESET, + 15, DCDIE | SYNCIE | CTSIE | TxUIE | BRKIE, + 1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx, + 9, NV | MIE | NORESET, 255 }; EXPORT_SYMBOL(z8530_hdlc_kilostream); @@ -220,22 +220,22 @@ EXPORT_SYMBOL(z8530_hdlc_kilostream); /* As above but for enhanced chips. */ -u8 z8530_hdlc_kilostream_85230[]= +u8 z8530_hdlc_kilostream_85230[] = { - 4, SYNC_ENAB|SDLC|X1CLK, + 4, SYNC_ENAB | SDLC | X1CLK, 2, 0, /* No vector */ 1, 0, - 3, ENT_HM|RxCRC_ENAB|Rx8, - 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR, + 3, ENT_HM | RxCRC_ENAB | Rx8, + 5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR, 9, 0, /* Disable interrupts */ 6, 0xFF, 7, FLAG, - 10, ABUNDER|NRZ|CRCPS, /* MARKIDLE?? */ + 10, ABUNDER | NRZ | CRCPS, /* MARKIDLE?? */ 11, TCTRxCP, 14, DISDPLL, - 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE, - 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx, - 9, NV|MIE|NORESET, + 15, DCDIE | SYNCIE | CTSIE | TxUIE | BRKIE, + 1, EXT_INT_ENAB | TxINT_ENAB | INT_ALL_Rx, + 9, NV | MIE | NORESET, 23, 3, /* Extended mode AUTO TX and EOM*/ 255 @@ -260,7 +260,7 @@ static void z8530_flush_fifo(struct z8530_channel *c) read_zsreg(c, R1); read_zsreg(c, R1); read_zsreg(c, R1); - if(c->dev->type==Z85230) + if (c->dev->type == Z85230) { read_zsreg(c, R1); read_zsreg(c, R1); @@ -315,40 +315,40 @@ static void z8530_rtsdtr(struct z8530_channel *c, int set) static void z8530_rx(struct z8530_channel *c) { - u8 ch,stat; + u8 ch, stat; - while(1) + while (1) { /* FIFO empty ? */ - if(!(read_zsreg(c, R0)&1)) + if (!(read_zsreg(c, R0) & 1)) break; - ch=read_zsdata(c); - stat=read_zsreg(c, R1); + ch = read_zsdata(c); + stat = read_zsreg(c, R1); /* Overrun ? */ - if(c->count < c->max) + if (c->count < c->max) { - *c->dptr++=ch; + *c->dptr++ = ch; c->count++; } - if(stat&END_FR) + if (stat & END_FR) { /* Error ? */ - if(stat&(Rx_OVR|CRC_ERR)) + if (stat & (Rx_OVR | CRC_ERR)) { /* Rewind the buffer and return */ - if(c->skb) - c->dptr=c->skb->data; - c->count=0; - if(stat&Rx_OVR) + if (c->skb) + c->dptr = c->skb->data; + c->count = 0; + if (stat & Rx_OVR) { pr_warn("%s: overrun\n", c->dev->name); c->rx_overrun++; } - if(stat&CRC_ERR) + if (stat & CRC_ERR) { c->rx_crc_err++; /* printk("crc error\n"); */ @@ -356,8 +356,8 @@ static void z8530_rx(struct z8530_channel *c) /* Shove the frame upstream */ } else { /* Drop the lock for RX processing, or - * there are deadlocks - */ + * there are deadlocks + */ z8530_rx_done(c); write_zsctrl(c, RES_Rx_CRC); } @@ -381,9 +381,9 @@ static void z8530_rx(struct z8530_channel *c) static void z8530_tx(struct z8530_channel *c) { - while(c->txcount) { + while (c->txcount) { /* FIFO full ? */ - if(!(read_zsreg(c, R0)&4)) + if (!(read_zsreg(c, R0) & 4)) return; c->txcount--; /* Shovel out the byte @@ -391,10 +391,10 @@ static void z8530_tx(struct z8530_channel *c) write_zsreg(c, R8, *c->tx_ptr++); write_zsctrl(c, RES_H_IUS); /* We are about to underflow */ - if(c->txcount==0) + if (c->txcount == 0) { write_zsctrl(c, RES_EOM_L); - write_zsreg(c, R10, c->regs[10]&~ABUNDER); + write_zsreg(c, R10, c->regs[10] & ~ABUNDER); } } @@ -471,7 +471,7 @@ EXPORT_SYMBOL(z8530_sync); static void z8530_dma_rx(struct z8530_channel *chan) { - if(chan->rxdma_on) + if (chan->rxdma_on) { /* Special condition check only */ u8 status; @@ -479,12 +479,11 @@ static void z8530_dma_rx(struct z8530_channel *chan) read_zsreg(chan, R7); read_zsreg(chan, R6); - status=read_zsreg(chan, R1); + status = read_zsreg(chan, R1); - if(status&END_FR) - { + if (status & END_FR) z8530_rx_done(chan); /* Fire up the next one */ - } + write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_H_IUS); } else { @@ -502,7 +501,7 @@ static void z8530_dma_rx(struct z8530_channel *chan) */ static void z8530_dma_tx(struct z8530_channel *chan) { - if(!chan->dma_tx) + if (!chan->dma_tx) { pr_warn("Hey who turned the DMA off?\n"); z8530_tx(chan); @@ -526,21 +525,21 @@ static void z8530_dma_status(struct z8530_channel *chan) { u8 status, altered; - status=read_zsreg(chan, R0); - altered=chan->status^status; + status = read_zsreg(chan, R0); + altered = chan->status ^ status; - chan->status=status; + chan->status = status; - if(chan->dma_tx) + if (chan->dma_tx) { - if(status&TxEOM) + if (status & TxEOM) { unsigned long flags; - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(chan->txdma); clear_dma_ff(chan->txdma); - chan->txdma_on=0; + chan->txdma_on = 0; release_dma_lock(flags); z8530_tx_done(chan); } @@ -594,9 +593,9 @@ static void z8530_rx_clear(struct z8530_channel *c) u8 stat; read_zsdata(c); - stat=read_zsreg(c, R1); + stat = read_zsreg(c, R1); - if(stat&END_FR) + if (stat & END_FR) write_zsctrl(c, RES_Rx_CRC); /* Clear irq */ @@ -630,9 +629,9 @@ static void z8530_tx_clear(struct z8530_channel *c) static void z8530_status_clear(struct z8530_channel *chan) { - u8 status=read_zsreg(chan, R0); + u8 status = read_zsreg(chan, R0); - if(status&TxEOM) + if (status & TxEOM) write_zsctrl(chan, ERR_RES); write_zsctrl(chan, RES_EXT_INT); write_zsctrl(chan, RES_H_IUS); @@ -647,7 +646,7 @@ EXPORT_SYMBOL(z8530_nop); /** * z8530_interrupt - Handle an interrupt from a Z8530 - * @irq: Interrupt number + * @irq: Interrupt number * @dev_id: The Z8530 device that is interrupting. * * A Z85[2]30 device has stuck its hand in the air for attention. @@ -663,25 +662,26 @@ EXPORT_SYMBOL(z8530_nop); irqreturn_t z8530_interrupt(int irq, void *dev_id) { - struct z8530_dev *dev=dev_id; + struct z8530_dev *dev = dev_id; u8 intr; static volatile int locker=0; - int work=0; + int work = 0; struct z8530_irqhandler *irqs; - if(locker) + if (locker) { pr_err("IRQ re-enter\n"); return IRQ_NONE; } - locker=1; + locker = 1; spin_lock(&dev->lock); - while(++work<5000) + while (++work < 5000) { intr = read_zsreg(&dev->chanA, R3); - if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT))) + if (!(intr & + (CHARxIP | CHATxIP | CHAEXT | CHBRxIP | CHBTxIP | CHBEXT))) break; /* This holds the IRQ status. On the 8530 you must read it @@ -692,46 +692,46 @@ irqreturn_t z8530_interrupt(int irq, void *dev_id) * an IRQ for someone else remember */ - irqs=dev->chanA.irqs; + irqs = dev->chanA.irqs; - if(intr & (CHARxIP|CHATxIP|CHAEXT)) + if (intr & (CHARxIP | CHATxIP | CHAEXT)) { - if(intr&CHARxIP) + if (intr & CHARxIP) irqs->rx(&dev->chanA); - if(intr&CHATxIP) + if (intr & CHATxIP) irqs->tx(&dev->chanA); - if(intr&CHAEXT) + if (intr & CHAEXT) irqs->status(&dev->chanA); } - irqs=dev->chanB.irqs; + irqs = dev->chanB.irqs; - if(intr & (CHBRxIP|CHBTxIP|CHBEXT)) + if (intr & (CHBRxIP | CHBTxIP | CHBEXT)) { - if(intr&CHBRxIP) + if (intr & CHBRxIP) irqs->rx(&dev->chanB); - if(intr&CHBTxIP) + if (intr & CHBTxIP) irqs->tx(&dev->chanB); - if(intr&CHBEXT) + if (intr & CHBEXT) irqs->status(&dev->chanB); } } spin_unlock(&dev->lock); - if(work==5000) + if (work == 5000) pr_err("%s: interrupt jammed - abort(0x%X)!\n", dev->name, intr); /* Ok all done */ - locker=0; + locker = 0; return IRQ_HANDLED; } EXPORT_SYMBOL(z8530_interrupt); -static const u8 reg_init[16]= +static const u8 reg_init[16] = { - 0,0,0,0, - 0,0,0,0, - 0,0,0,0, - 0x55,0,0,0 + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x55, 0, 0, 0 }; /** @@ -749,7 +749,7 @@ int z8530_sync_open(struct net_device *dev, struct z8530_channel *c) spin_lock_irqsave(c->lock, flags); c->sync = 1; - c->mtu = dev->mtu+64; + c->mtu = dev->mtu + 64; c->count = 0; c->skb = NULL; c->skb2 = NULL; @@ -758,11 +758,11 @@ int z8530_sync_open(struct net_device *dev, struct z8530_channel *c) /* This loads the double buffer up */ z8530_rx_done(c); /* Load the frame ring */ z8530_rx_done(c); /* Load the backup frame */ - z8530_rtsdtr(c,1); + z8530_rtsdtr(c, 1); c->dma_tx = 0; - c->regs[R1]|=TxINT_ENAB; + c->regs[R1] |= TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, flags); return 0; @@ -787,9 +787,9 @@ int z8530_sync_close(struct net_device *dev, struct z8530_channel *c) c->max = 0; c->sync = 0; - chk=read_zsreg(c,R0); + chk = read_zsreg(c, R0); write_zsreg(c, R3, c->regs[R3]); - z8530_rtsdtr(c,0); + z8530_rtsdtr(c, 0); spin_unlock_irqrestore(c->lock, flags); return 0; @@ -810,7 +810,7 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) unsigned long cflags, dflags; c->sync = 1; - c->mtu = dev->mtu+64; + c->mtu = dev->mtu + 64; c->count = 0; c->skb = NULL; c->skb2 = NULL; @@ -825,27 +825,27 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) * should be fine. */ - if(c->mtu > PAGE_SIZE/2) + if (c->mtu > PAGE_SIZE / 2) return -EMSGSIZE; - c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); + c->rx_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); if (!c->rx_buf[0]) return -ENOBUFS; - c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2; + c->rx_buf[1] = c->rx_buf[0] + PAGE_SIZE / 2; - c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); + c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); if (!c->tx_dma_buf[0]) { free_page((unsigned long)c->rx_buf[0]); - c->rx_buf[0]=NULL; + c->rx_buf[0] = NULL; return -ENOBUFS; } - c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2; + c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2; - c->tx_dma_used=0; + c->tx_dma_used = 0; c->dma_tx = 1; - c->dma_num=0; - c->dma_ready=1; + c->dma_num = 0; + c->dma_ready = 1; /* Enable DMA control mode */ @@ -855,21 +855,21 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) /* TX DMA via DIR/REQ */ - c->regs[R14]|= DTRREQ; + c->regs[R14] |= DTRREQ; write_zsreg(c, R14, c->regs[R14]); - c->regs[R1]&= ~TxINT_ENAB; + c->regs[R1] &= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); /* RX DMA via W/Req */ - c->regs[R1]|= WT_FN_RDYFN; - c->regs[R1]|= WT_RDY_RT; - c->regs[R1]|= INT_ERR_Rx; - c->regs[R1]&= ~TxINT_ENAB; + c->regs[R1] |= WT_FN_RDYFN; + c->regs[R1] |= WT_RDY_RT; + c->regs[R1] |= INT_ERR_Rx; + c->regs[R1] &= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); - c->regs[R1]|= WT_RDY_ENAB; + c->regs[R1] |= WT_RDY_ENAB; write_zsreg(c, R1, c->regs[R1]); /* DMA interrupts @@ -878,11 +878,11 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) /* Set up the DMA configuration */ - dflags=claim_dma_lock(); + dflags = claim_dma_lock(); disable_dma(c->rxdma); clear_dma_ff(c->rxdma); - set_dma_mode(c->rxdma, DMA_MODE_READ|0x10); + set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10); set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0])); set_dma_count(c->rxdma, c->mtu); enable_dma(c->rxdma); @@ -902,8 +902,8 @@ int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c) c->tx_dma_used = 1; c->irqs = &z8530_dma_sync; - z8530_rtsdtr(c,1); - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + z8530_rtsdtr(c, 1); + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, cflags); @@ -949,27 +949,27 @@ int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c) /* Disable DMA control mode */ - c->regs[R1]&= ~WT_RDY_ENAB; + c->regs[R1] &= ~WT_RDY_ENAB; write_zsreg(c, R1, c->regs[R1]); - c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); - c->regs[R1]|= INT_ALL_Rx; + c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx); + c->regs[R1] |= INT_ALL_Rx; write_zsreg(c, R1, c->regs[R1]); - c->regs[R14]&= ~DTRREQ; + c->regs[R14] &= ~DTRREQ; write_zsreg(c, R14, c->regs[R14]); - if(c->rx_buf[0]) + if (c->rx_buf[0]) { free_page((unsigned long)c->rx_buf[0]); - c->rx_buf[0]=NULL; + c->rx_buf[0] = NULL; } - if(c->tx_dma_buf[0]) + if (c->tx_dma_buf[0]) { free_page((unsigned long)c->tx_dma_buf[0]); - c->tx_dma_buf[0]=NULL; + c->tx_dma_buf[0] = NULL; } - chk=read_zsreg(c,R0); + chk = read_zsreg(c, R0); write_zsreg(c, R3, c->regs[R3]); - z8530_rtsdtr(c,0); + z8530_rtsdtr(c, 0); spin_unlock_irqrestore(c->lock, flags); @@ -993,7 +993,7 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) printk("Opening sync interface for TX-DMA\n"); c->sync = 1; - c->mtu = dev->mtu+64; + c->mtu = dev->mtu + 64; c->count = 0; c->skb = NULL; c->skb2 = NULL; @@ -1003,14 +1003,14 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) * should be fine. */ - if(c->mtu > PAGE_SIZE/2) + if (c->mtu > PAGE_SIZE / 2) return -EMSGSIZE; - c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA); + c->tx_dma_buf[0] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); if (!c->tx_dma_buf[0]) return -ENOBUFS; - c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2; + c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE / 2; spin_lock_irqsave(c->lock, cflags); @@ -1026,9 +1026,9 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->rxdma_on = 0; c->txdma_on = 0; - c->tx_dma_used=0; - c->dma_num=0; - c->dma_ready=1; + c->tx_dma_used = 0; + c->dma_num = 0; + c->dma_ready = 1; c->dma_tx = 1; /* Enable DMA control mode @@ -1036,10 +1036,10 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) /* TX DMA via DIR/REQ */ - c->regs[R14]|= DTRREQ; + c->regs[R14] |= DTRREQ; write_zsreg(c, R14, c->regs[R14]); - c->regs[R1]&= ~TxINT_ENAB; + c->regs[R1] &= ~TxINT_ENAB; write_zsreg(c, R1, c->regs[R1]); /* Set up the DMA configuration @@ -1062,8 +1062,8 @@ int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c) c->tx_dma_used = 1; c->irqs = &z8530_txdma_sync; - z8530_rtsdtr(c,1); - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + z8530_rtsdtr(c, 1); + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, cflags); return 0; @@ -1105,22 +1105,22 @@ int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c) /* Disable DMA control mode */ - c->regs[R1]&= ~WT_RDY_ENAB; + c->regs[R1] &= ~WT_RDY_ENAB; write_zsreg(c, R1, c->regs[R1]); - c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx); - c->regs[R1]|= INT_ALL_Rx; + c->regs[R1] &= ~(WT_RDY_RT | WT_FN_RDYFN | INT_ERR_Rx); + c->regs[R1] |= INT_ALL_Rx; write_zsreg(c, R1, c->regs[R1]); - c->regs[R14]&= ~DTRREQ; + c->regs[R14] &= ~DTRREQ; write_zsreg(c, R14, c->regs[R14]); - if(c->tx_dma_buf[0]) + if (c->tx_dma_buf[0]) { free_page((unsigned long)c->tx_dma_buf[0]); - c->tx_dma_buf[0]=NULL; + c->tx_dma_buf[0] = NULL; } - chk=read_zsreg(c,R0); + chk = read_zsreg(c, R0); write_zsreg(c, R3, c->regs[R3]); - z8530_rtsdtr(c,0); + z8530_rtsdtr(c, 0); spin_unlock_irqrestore(c->lock, cflags); return 0; @@ -1130,7 +1130,7 @@ EXPORT_SYMBOL(z8530_sync_txdma_close); /* Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny * it exists... */ -static const char *z8530_type_name[]={ +static const char * const z8530_type_name[] = { "Z8530", "Z85C30", "Z85230" @@ -1165,23 +1165,23 @@ static inline int do_z8530_init(struct z8530_dev *dev) /* NOP the interrupt handlers first - we might get a * floating IRQ transition when we reset the chip */ - dev->chanA.irqs=&z8530_nop; - dev->chanB.irqs=&z8530_nop; - dev->chanA.dcdcheck=DCD; - dev->chanB.dcdcheck=DCD; + dev->chanA.irqs = &z8530_nop; + dev->chanB.irqs = &z8530_nop; + dev->chanA.dcdcheck = DCD; + dev->chanB.dcdcheck = DCD; /* Reset the chip */ write_zsreg(&dev->chanA, R9, 0xC0); udelay(200); /* Now check its valid */ write_zsreg(&dev->chanA, R12, 0xAA); - if(read_zsreg(&dev->chanA, R12)!=0xAA) + if (read_zsreg(&dev->chanA, R12) != 0xAA) return -ENODEV; write_zsreg(&dev->chanA, R12, 0x55); - if(read_zsreg(&dev->chanA, R12)!=0x55) + if (read_zsreg(&dev->chanA, R12) != 0x55) return -ENODEV; - dev->type=Z8530; + dev->type = Z8530; /* See the application note. */ @@ -1192,12 +1192,12 @@ static inline int do_z8530_init(struct z8530_dev *dev) * the chip is enhanced. */ - if(read_zsreg(&dev->chanA, R15)==0x01) + if (read_zsreg(&dev->chanA, R15) == 0x01) { /* This C30 versus 230 detect is from Klaus Kudielka's dmascc */ /* Put a char in the fifo */ write_zsreg(&dev->chanA, R8, 0); - if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP) + if (read_zsreg(&dev->chanA, R0) & Tx_BUF_EMP) dev->type = Z85230; /* Has a FIFO */ else dev->type = Z85C30; /* Z85C30, 1 byte FIFO */ @@ -1214,7 +1214,7 @@ static inline int do_z8530_init(struct z8530_dev *dev) */ memcpy(dev->chanA.regs, reg_init, 16); - memcpy(dev->chanB.regs, reg_init ,16); + memcpy(dev->chanB.regs, reg_init, 16); return 0; } @@ -1270,8 +1270,8 @@ int z8530_shutdown(struct z8530_dev *dev) /* Reset the chip */ spin_lock_irqsave(&dev->lock, flags); - dev->chanA.irqs=&z8530_nop; - dev->chanB.irqs=&z8530_nop; + dev->chanA.irqs = &z8530_nop; + dev->chanB.irqs = &z8530_nop; write_zsreg(&dev->chanA, R9, 0xC0); /* We must lock the udelay, the chip is offlimits here */ udelay(100); @@ -1297,27 +1297,27 @@ int z8530_channel_load(struct z8530_channel *c, u8 *rtable) spin_lock_irqsave(c->lock, flags); - while(*rtable!=255) + while (*rtable != 255) { - int reg=*rtable++; - - if(reg>0x0F) - write_zsreg(c, R15, c->regs[15]|1); - write_zsreg(c, reg&0x0F, *rtable); - if(reg>0x0F) - write_zsreg(c, R15, c->regs[15]&~1); - c->regs[reg]=*rtable++; + int reg = *rtable++; + + if (reg > 0x0F) + write_zsreg(c, R15, c->regs[15] | 1); + write_zsreg(c, reg & 0x0F, *rtable); + if (reg > 0x0F) + write_zsreg(c, R15, c->regs[15] & ~1); + c->regs[reg] = *rtable++; } - c->rx_function=z8530_null_rx; - c->skb=NULL; - c->tx_skb=NULL; - c->tx_next_skb=NULL; - c->mtu=1500; - c->max=0; - c->count=0; - c->status=read_zsreg(c, R0); - c->sync=1; - write_zsreg(c, R3, c->regs[R3]|RxENABLE); + c->rx_function = z8530_null_rx; + c->skb = NULL; + c->tx_skb = NULL; + c->tx_next_skb = NULL; + c->mtu = 1500; + c->max = 0; + c->count = 0; + c->status = read_zsreg(c, R0); + c->sync = 1; + write_zsreg(c, R3, c->regs[R3] | RxENABLE); spin_unlock_irqrestore(c->lock, flags); return 0; @@ -1342,19 +1342,19 @@ static void z8530_tx_begin(struct z8530_channel *c) { unsigned long flags; - if(c->tx_skb) + if (c->tx_skb) return; - c->tx_skb=c->tx_next_skb; - c->tx_next_skb=NULL; - c->tx_ptr=c->tx_next_ptr; + c->tx_skb = c->tx_next_skb; + c->tx_next_skb = NULL; + c->tx_ptr = c->tx_next_ptr; if (!c->tx_skb) { /* Idle on */ - if(c->dma_tx) + if (c->dma_tx) { - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(c->txdma); /* Check if we crapped out. */ @@ -1365,11 +1365,11 @@ static void z8530_tx_begin(struct z8530_channel *c) } release_dma_lock(flags); } - c->txcount=0; + c->txcount = 0; } else { - c->txcount=c->tx_skb->len; + c->txcount = c->tx_skb->len; - if(c->dma_tx) + if (c->dma_tx) { /* FIXME. DMA is broken for the original 8530, * on the older parts we need to set a flag and @@ -1377,25 +1377,25 @@ static void z8530_tx_begin(struct z8530_channel *c) * stage off */ - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(c->txdma); /* These two are needed by the 8530/85C30 * and must be issued when idling. */ - if(c->dev->type!=Z85230) + if (c->dev->type != Z85230) { write_zsctrl(c, RES_Tx_CRC); write_zsctrl(c, RES_EOM_L); } - write_zsreg(c, R10, c->regs[10]&~ABUNDER); + write_zsreg(c, R10, c->regs[10] & ~ABUNDER); clear_dma_ff(c->txdma); set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr)); set_dma_count(c->txdma, c->txcount); enable_dma(c->txdma); release_dma_lock(flags); write_zsctrl(c, RES_EOM_L); - write_zsreg(c, R5, c->regs[R5]|TxENAB); + write_zsreg(c, R5, c->regs[R5] | TxENAB); } else { /* ABUNDER off */ write_zsreg(c, R10, c->regs[10]); @@ -1472,35 +1472,35 @@ static void z8530_rx_done(struct z8530_channel *c) /* Is our receive engine in DMA mode */ - if(c->rxdma_on) + if (c->rxdma_on) { /* Save the ready state and the buffer currently * being used as the DMA target */ - int ready=c->dma_ready; - unsigned char *rxb=c->rx_buf[c->dma_num]; + int ready = c->dma_ready; + unsigned char *rxb = c->rx_buf[c->dma_num]; unsigned long flags; /* Complete this DMA. Necessary to find the length */ - flags=claim_dma_lock(); + flags = claim_dma_lock(); disable_dma(c->rxdma); clear_dma_ff(c->rxdma); - c->rxdma_on=0; - ct=c->mtu-get_dma_residue(c->rxdma); - if(ct<0) - ct=2; /* Shit happens.. */ - c->dma_ready=0; + c->rxdma_on = 0; + ct = c->mtu - get_dma_residue(c->rxdma); + if (ct < 0) + ct = 2; /* Shit happens.. */ + c->dma_ready = 0; /* Normal case: the other slot is free, start the next DMA * into it immediately. */ - if(ready) + if (ready) { - c->dma_num^=1; - set_dma_mode(c->rxdma, DMA_MODE_READ|0x10); + c->dma_num ^= 1; + set_dma_mode(c->rxdma, DMA_MODE_READ | 0x10); set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num])); set_dma_count(c->rxdma, c->mtu); c->rxdma_on = 1; @@ -1551,7 +1551,7 @@ static void z8530_rx_done(struct z8530_channel *c) * sync IRQ for the RT_LOCK area. * */ - ct=c->count; + ct = c->count; c->skb = c->skb2; c->count = 0; @@ -1594,10 +1594,10 @@ static void z8530_rx_done(struct z8530_channel *c) static inline int spans_boundary(struct sk_buff *skb) { - unsigned long a=(unsigned long)skb->data; + unsigned long a = (unsigned long)skb->data; - a^=(a+skb->len); - if(a&0x00010000) /* If the 64K bit is different.. */ + a ^= (a + skb->len); + if (a & 0x00010000) /* If the 64K bit is different.. */ return 1; return 0; } @@ -1620,7 +1620,7 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) unsigned long flags; netif_stop_queue(c->netdevice); - if(c->tx_next_skb) + if (c->tx_next_skb) return NETDEV_TX_BUSY; /* PC SPECIFIC - DMA limits */ @@ -1628,7 +1628,9 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) * limit, then copy to the flip buffer */ - if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb))) + if (c->dma_tx && + ((unsigned long)(virt_to_bus(skb->data + skb->len)) >= + 16 * 1024 * 1024 || spans_boundary(skb))) { /* Send the flip buffer, and flip the flippy bit. * We don't care which is used when just so long as @@ -1636,14 +1638,14 @@ netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb) * only one buffer can be going out at a time the other * has to be safe. */ - c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used]; - c->tx_dma_used^=1; /* Flip temp buffer */ + c->tx_next_ptr = c->tx_dma_buf[c->tx_dma_used]; + c->tx_dma_used ^= 1; /* Flip temp buffer */ skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len); } else { c->tx_next_ptr = skb->data; } RT_LOCK; - c->tx_next_skb=skb; + c->tx_next_skb = skb; RT_UNLOCK; spin_lock_irqsave(c->lock, flags); From patchwork Tue Jun 15 02:43:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 460951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DECCC2B9F4 for ; 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Tue, 15 Jun 2021 10:46:58 +0800 From: Guangbin Huang To: , , , , CC: , , , Subject: [PATCH V2 net-next 10/10] net: z85230: remove unnecessary out of memory message Date: Tue, 15 Jun 2021 10:43:45 +0800 Message-ID: <1623725025-50976-11-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> References: <1623725025-50976-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Li This patch removes unnecessary out of memory message, to fix the following checkpatch.pl warning: "WARNING: Possible unnecessary 'out of memory' message" Signed-off-by: Peng Li Signed-off-by: Guangbin Huang --- drivers/net/wan/z85230.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index 621f730..982a034 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -1531,10 +1531,9 @@ static void z8530_rx_done(struct z8530_channel *c) RT_UNLOCK; c->skb2 = dev_alloc_skb(c->mtu); - if (!c->skb2) - netdev_warn(c->netdevice, "memory squeeze\n"); - else + if (c->skb2) skb_put(c->skb2, c->mtu); + c->netdevice->stats.rx_packets++; c->netdevice->stats.rx_bytes += ct; }