From patchwork Thu Aug 2 10:52:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 143342 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1993313ljj; Thu, 2 Aug 2018 03:53:06 -0700 (PDT) X-Received: by 2002:a62:4b48:: with SMTP id y69-v6mr2391752pfa.93.1533207186581; Thu, 02 Aug 2018 03:53:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533207186; cv=none; d=google.com; s=arc-20160816; b=EqdznP6rAh3VFSeIV8LsEBrxj+1kJamzqHRiX5riaj5ntMKqJh4+b/f4nMFb0jVJ6I 8frWVJvgHpIGNvEHn4Lmcs9In/jBjtvI+iQoQWCk+uVplDc/NZRz0xESaLe7xLnlPWsy lY8gIlBzvQVISbuD+ezRhT+oN2bhR5cvrma7ENWJMxOJN8fIbYZFm6VxZvWmYeKUChZC CSTpsvVDS0wrd19Xj9mkWu55cjqwo/VJaCS8hVbQJNwNwWS2Ksr5vDs0DFhlsWiRfSvD 7eGrpac+Vzcfp8xof38Gug/lIgFnCFDPfTjK96vZfVd1DYvYpTWXLwR8HiqhUhW6XYjK 4z7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=jlyenogbp0Uru3jwaqO4ny8iOCXibNLk9AuycVt0/WU=; b=CVAWQ+cgI1mY4I5KBCFbfQgHDwEAzT1zS3vR4cT01tevrIrGz1dRkn5KrXbuLbi27L DLFNekrAPm1Uj6tiHX8u9XEO8Z4316BamePPTaClVXEb80w7qg6LCWUTJxdmRfFYyP8t cTBhcpv8QDOJga9elwE7uenJv5VQ3qrRftQNr5oFs9QOxH2PjmVw8cZGxD5sZG3/X9BD eMGDclhnvkPX9w8zTVRvy1oljj5jAFH20EH2yKlsmn7Ub8ehglJLbzHn0bk+1rXHCutu jvGHaXu8ambtZXoBcy6pG5/T9B1iGc9bR+0ql/WI04WHAe92j2mBx989X0B1WSYC7y/S oSkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EEbFpsOh; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w21-v6sor405509pgk.76.2018.08.02.03.53.06 for (Google Transport Security); Thu, 02 Aug 2018 03:53:06 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EEbFpsOh; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=jlyenogbp0Uru3jwaqO4ny8iOCXibNLk9AuycVt0/WU=; b=EEbFpsOh23iN7MckPjXt3jC92ZAaciXcWWYzSIBnNirCiahG12+YzI6SRf7DL52cYA GRVqy5hswWcz967EeGvOb1xEgsj4t1+ETmA+n0WPcPYac8YlT1gHF7VU2HlpKK4A8k72 8XvBfd5oIib8+8tiCC8Ln12iBGwsVQr6A6v0A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=jlyenogbp0Uru3jwaqO4ny8iOCXibNLk9AuycVt0/WU=; b=BGPq4QB0RldWjLM0tGyB3WT2uX02rOKF3DglA+XOAvg9/9i4J+oitTdmbrU/rGQKyV NYw2bD3k2LufMeC+g1Hy6mGY41t+FNbLX4LUahibil1XclcCHQzDCqoyVPFfBxjCGPPE t6Q79tfnYNMZg7EjFXsPb4ghAQzru0V0ePmbx8BqMhiTogqX5pcbCu8Xr/io8psRZ76J rvLOGGy/joOnt/JibrqiL9nG8Ar4Y6cXTCQmkW+JN9jl2X0RgdtefZq2qu1HeHS5A0vC uI6xWXqMj2NvTC/FC1YuNiJQXL5J5qNl8GpQ/bpeuNKSCX2mfk6A18/ErLyFNBbF3y/n o2KQ== X-Gm-Message-State: AOUpUlFaE8BRzJvOH8lpcB6YsRzD7OjX/7R1xjuIRFb3QxUz6foP2UVn ha/dvFC82ZFpYtywRJDmIlQxm5YSwPGd5w== X-Google-Smtp-Source: AAOMgpeXoYpDP9vl74ft+xCqWulVhyz/JaQDEbtfkX4grjw84MMYaqDE4VfN73pJlklUXoTn1tOCXw== X-Received: by 2002:a63:e056:: with SMTP id n22-v6mr2248465pgj.205.1533207186170; Thu, 02 Aug 2018 03:53:06 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.197.43.141]) by smtp.gmail.com with ESMTPSA id b67-v6sm3426580pfd.74.2018.08.02.03.53.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Aug 2018 03:53:05 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org, ard.biesheuvel@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [edk2][PATCH edk2-platforms 1/2] Silicon/SynQuacer: add optional OP-TEE DT node Date: Thu, 2 Aug 2018 16:22:37 +0530 Message-Id: <1533207158-18652-1-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 OP-TEE is optional on Developerbox controlled via SCP firmware. To check if we need to enable OP-TEE DT node, we use "IsOpteePresent" OpteeLib api. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 + .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 8 +++++++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 28 ++++++++++++++++++++++ .../SynQuacerDtbLoaderLib.inf | 2 ++ 4 files changed, 39 insertions(+) -- 2.7.4 Reviewed-by: Ard Biesheuvel diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index fc498eb65217..4ff5df978e8e 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -76,6 +76,7 @@ [LibraryClasses.common] ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + OpteeLib|ArmPkg/Library/OpteeLib/OpteeLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 37d642e4b237..d6a5f013e58c 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -574,6 +574,14 @@ #address-cells = <1>; #size-cells = <0>; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; }; #include "SynQuacerCaches.dtsi" diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c index 897d06743708..77db30c204fe 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -19,6 +19,7 @@ #include #include #include +#include #include // add enough space for three instances of 'status = "disabled"' @@ -47,6 +48,29 @@ DisableDtNode ( } } +STATIC +VOID +EnableDtNode ( + IN VOID *Dtb, + IN CONST CHAR8 *NodePath + ) +{ + INT32 Node; + INT32 Rc; + + Node = fdt_path_offset (Dtb, NodePath); + if (Node < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Node))); + return; + } + Rc = fdt_setprop_string (Dtb, Node, "status", "okay"); + if (Rc < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Rc))); + } +} + /** Return a pool allocated copy of the DTB image that is appropriate for booting the current platform via DT. @@ -107,6 +131,10 @@ DtPlatformLoadDtb ( DisableDtNode (CopyDtb, "/sdhci@52300000"); } + if (IsOpteePresent()) { + EnableDtNode (CopyDtb, "/firmware/optee"); + } + *Dtb = CopyDtb; *DtbSize = CopyDtbSize; diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf index 548d62fd5c0a..fd21f7c376ce 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf @@ -24,6 +24,7 @@ [Sources] SynQuacerDtbLoaderLib.c [Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -34,6 +35,7 @@ [LibraryClasses] DxeServicesLib FdtLib MemoryAllocationLib + OpteeLib [Pcd] gSynQuacerTokenSpaceGuid.PcdPcieEnableMask From patchwork Thu Aug 2 10:52:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 143343 Delivered-To: patches@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1993439ljj; Thu, 2 Aug 2018 03:53:16 -0700 (PDT) X-Received: by 2002:a63:161a:: with SMTP id w26-v6mr2278053pgl.257.1533207196041; Thu, 02 Aug 2018 03:53:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533207196; cv=none; d=google.com; s=arc-20160816; b=J010eJhz2Jz8Mcq/nGIERMzVCubBr55POfeTxj8IR3AF7S4LUJ+7gz2DLm59hU69Is 6I0Px1GV47Im5hxom4D6N2h43uZGTke6BzSebXA5SUu9+A383TIU/aIi2e6tT+em9df2 DMkDD1FXVhHB+86PO5LZcnGc2V0ddYiVo4U8955drd7/IwcBr8X4mwlxGHnK0aKqlu2r gHxAN56jxMX7Wjao/3YFAj8iG1d5FQEstHJSVYBPBBO9rvAWoP4NBMatojcgs0pyfFOw tWygXOcK+/PaZQteW4WyL4rIxwjcWFqpl3Zefyl0Ld1VMSlKdUt78gd1xWhUkiz7u9kX /ILA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=LuNE06Zl9W3RH+jQszrGU96pHh5yl5iSeaF7SVYmiRU=; b=xzNBRNDpIUExbZMrOEzbTawjKHPn54pOyJaldVIEgPAltzJuP92+pFv4xlyJt1R0hy IjvVJ6uG4pbUNZzSHGCR6yb81DryS55rWhwPhe47amUZpfRW+Dekb7gTlYc9FttX8kg/ cZIi17+zsbSyLUuIk6X3tUmgHe8oHCHkBK3v0OXM46QWIj6Q+881f3kxhKLpYP0w+3z9 AoArUmsEu+he1DRMHhc85ybpqcbgQVSxxFgCtKPZ1g6EZeRMAiFbBTii3U1xk6Rn4ZC4 K5ckHQLjn2X+x1phbb6u7Nxa9oL0qlg7m/yV9ZKM+z36+ryXx8Qyz3MvWrjxWZmLnG8V cu6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JHMYoDV7; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id w28-v6sor415215pgm.32.2018.08.02.03.53.15 for (Google Transport Security); Thu, 02 Aug 2018 03:53:16 -0700 (PDT) Received-SPF: pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JHMYoDV7; spf=pass (google.com: domain of sumit.garg@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=sumit.garg@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LuNE06Zl9W3RH+jQszrGU96pHh5yl5iSeaF7SVYmiRU=; b=JHMYoDV7NlAAIBcOuHDoxfI/XZq2g29CAOU7x/VxN75KUsjOqATo/bqWlcenK/lQxJ WepgIIqI2tYRPIP6B1g0/LH9dAw+YAFRHj5KM4YjNd8OuVKUmIxjTmTp1uvF4n8N/03v o0LnHkgISVhB5/cJXaJUmsDb3EFU0aM5h9vNY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LuNE06Zl9W3RH+jQszrGU96pHh5yl5iSeaF7SVYmiRU=; b=Dk9LTiWW9kHy+gUUm1Sru8SkAYnPKRS7q0RlMlRVfiDtEqwrShSgj9IM5nUI9LpXB2 mqqCy6hmO3xwTalKcQcGhRlG38v1BfoNJmMTzURyjEkQL9/E9DDyd9TYsbf4oF8xG2rZ xj1618tz9OppnmGwVBlb7d0tNIiRSrvW9n2DyJxqos5CoHB3eUoUdtx4+nD8SPKeTkW8 OBhaeRUMlq3Y7pkd3GcL7S878Ej7wha+x1/nDDr2QboxIgdXrYIxtfMLoDYR3igKkMCL YLXj02Tzqx0Qefja9pzAYgXvWCRqyKUUkltgK+euROTuksLlfQ1eSKe0xbAxEc9TgNC/ yL7Q== X-Gm-Message-State: AOUpUlGQh6pEnj2UVvDZpj/p9HPmXJRnG4KeObf6TQHOA1TSTYSKN0mS BWA5xiOWhFKMTC4OJ9TB1PkqCVtO X-Google-Smtp-Source: AAOMgpcmCg9V6a9FwEirL18PwuX9brcmh+bbeP+ZKSFjBZNPsd07EQSCBVFAsApYKW2ri2ZKa0MRDg== X-Received: by 2002:a63:de4c:: with SMTP id y12-v6mr1088270pgi.435.1533207195660; Thu, 02 Aug 2018 03:53:15 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([117.197.43.141]) by smtp.gmail.com with ESMTPSA id b67-v6sm3426580pfd.74.2018.08.02.03.53.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Aug 2018 03:53:15 -0700 (PDT) From: Sumit Garg To: daniel.thompson@linaro.org, ard.biesheuvel@linaro.org Cc: patches@linaro.org, Sumit Garg Subject: [edk2][PATCH edk2-platforms 2/2] Silicon/SynQuacer: Add status property in PCIe & SDHC DT nodes Date: Thu, 2 Aug 2018 16:22:38 +0530 Message-Id: <1533207158-18652-2-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533207158-18652-1-git-send-email-sumit.garg@linaro.org> References: <1533207158-18652-1-git-send-email-sumit.garg@linaro.org> Add status = "disabled" property by default for PCIe and SDHC DT nodes. If required, update them at runtime with status = "okay". Using this method we don't need extra DTB_PADDING. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg --- .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 3 ++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 40 ++++------------------ 2 files changed, 10 insertions(+), 33 deletions(-) -- 2.7.4 diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index d6a5f013e58c..003e21bd6f85 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -473,6 +473,7 @@ msi-map = <0x000 &its 0x0 0x7f00>; dma-coherent; + status = "disabled"; }; pcie1: pcie@70000000 { @@ -492,6 +493,7 @@ msi-map = <0x0 &its 0x10000 0x7f00>; dma-coherent; + status = "disabled"; }; gpio: gpio@51000000 { @@ -537,6 +539,7 @@ clocks = <&clk_alw_c_0 &clk_alw_b_0>; clock-names = "core", "iface"; dma-coherent; + status = "disabled"; }; clk_alw_1_8: spi_ihclk { diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c index 77db30c204fe..96090c20502c 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -22,32 +22,6 @@ #include #include -// add enough space for three instances of 'status = "disabled"' -#define DTB_PADDING 64 - -STATIC -VOID -DisableDtNode ( - IN VOID *Dtb, - IN CONST CHAR8 *NodePath - ) -{ - INT32 Node; - INT32 Rc; - - Node = fdt_path_offset (Dtb, NodePath); - if (Node < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Node))); - return; - } - Rc = fdt_setprop_string (Dtb, Node, "status", "disabled"); - if (Rc < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Rc))); - } -} - STATIC VOID EnableDtNode ( @@ -105,7 +79,7 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - CopyDtbSize = OrigDtbSize + DTB_PADDING; + CopyDtbSize = OrigDtbSize; CopyDtb = AllocatePool (CopyDtbSize); if (CopyDtb == NULL) { return EFI_OUT_OF_RESOURCES; @@ -118,17 +92,17 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT0)) { - DisableDtNode (CopyDtb, "/pcie@60000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT0) { + EnableDtNode (CopyDtb, "/pcie@60000000"); } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT1)) { - DisableDtNode (CopyDtb, "/pcie@70000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT1) { + EnableDtNode (CopyDtb, "/pcie@70000000"); } SettingsVal = PcdGet64 (PcdPlatformSettings); Settings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; - if (Settings->EnableEmmc == EMMC_DISABLED) { - DisableDtNode (CopyDtb, "/sdhci@52300000"); + if (Settings->EnableEmmc == EMMC_ENABLED) { + EnableDtNode (CopyDtb, "/sdhci@52300000"); } if (IsOpteePresent()) {