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[23.128.96.18]) by mx.google.com with ESMTP id d23si2744800jaq.63.2021.06.16.07.11.26; Wed, 16 Jun 2021 07:11:26 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ivOr+KRe; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233845AbhFPONa (ORCPT + 7 others); Wed, 16 Jun 2021 10:13:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233831AbhFPONa (ORCPT ); Wed, 16 Jun 2021 10:13:30 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDC58C0617A6 for ; Wed, 16 Jun 2021 07:11:23 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id v9so2868010wrx.6 for ; Wed, 16 Jun 2021 07:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HWrm484FRw+CXBsUVTC9kLTPetzFLV6N+ldivPXQSA0=; b=ivOr+KReobJtkhuIa7uOD3UErbtxb02cL0h/pdDUfPd2qxzaK7FzKkCpHpjnh4ukwG o1r/pj8GTabRMnFi6VXJW2E7ILfmHvZJQuD2MYwYbaJzrpl5iwksBJNc2NPnZU9xaPe5 zw7wK4KKkEl/563ebuvmF+4iNE3ThvFxMsGfAlK14v59xaNf4afPc0kiud3mZn9yreLZ nJmvDR9Rx5OGjkKA9OtgHD01jt5VmEvEUNsP6iwJNTbyZXG959qJ3EloczxuOECB8UPc MfBoAWyV14dclN1F8gwKDXgrbnOJZm9hn15En+SUGdGSFeDyLT0NFjrrss6xG1qAlizq f/lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HWrm484FRw+CXBsUVTC9kLTPetzFLV6N+ldivPXQSA0=; b=pUXH1H0715CZY7x9Gw6xXIdk30C2wHYCS2lh9XOA6tx2TBgGmyADKR3gi+GQcyvxIX 6f3rH6kE2oe4EiLgV0XC9IvHCNnSUr7gAnuUdD/7ZYhVsyW42Zlgj28JIv9qAaRATfFg MmYd4iNNu7sYVtt6F9e9Dq00Y5o1ktog7dSr6e1bFun0MeSSW1XLofUBl/w4rgUdHT/Y V2bBlfQmuARNMbvLkQEmoII8ApLDmCN9mDQYw2XpWfVvduN6OGYmmsPFWBoFUyFbLymO /LZEgTTXDhWmrd0FsdC/xPzWgSrwZ4887ZZ5j6NdCi0T4GECrj8hp7CrOmOM/jo1FOUg PYRQ== X-Gm-Message-State: AOAM533qOMH3b3dn3JwQ/v9KPPglUVIginFZ6E9njCMK0OokiFt1hQ+X tsMCe7pm6SWTwkwQdLL5s6d/fQ== X-Received: by 2002:a5d:6b0e:: with SMTP id v14mr5661024wrw.297.1623852682379; Wed, 16 Jun 2021 07:11:22 -0700 (PDT) Received: from xps7590.fritz.box ([2a02:2454:3e5:b700:9df7:76e5:7e94:bf1e]) by smtp.gmail.com with ESMTPSA id g83sm1968375wma.10.2021.06.16.07.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jun 2021 07:11:22 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Cc: Robert Foss Subject: [RFC v1 01/11] clk: qcom: common: Add runtime init/suspend/resume Date: Wed, 16 Jun 2021 16:10:57 +0200 Message-Id: <20210616141107.291430-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210616141107.291430-1-robert.foss@linaro.org> References: <20210616141107.291430-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Ported over from the downstream driver. Is used by SM8350 DISPCC & VIDEOCC. This patch includes support for initializing interconnect bandwidth voting. Signed-off-by: Robert Foss --- drivers/clk/qcom/common.c | 92 +++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/common.h | 6 +++ 2 files changed, 98 insertions(+) -- 2.30.2 diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 60d2a78d1395..1375c5de1bd1 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -3,13 +3,17 @@ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. */ +#include #include +#include #include #include #include #include #include #include +#include +#include #include "common.h" #include "clk-rcg.h" @@ -329,4 +333,92 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index, } EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index); +int qcom_cc_runtime_init(struct platform_device *pdev, + struct qcom_cc_desc *desc) +{ + struct device *dev = &pdev->dev; + struct clk *clk; + int ret; + + clk = clk_get_optional(dev, "iface"); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(dev, "unable to get iface clock\n"); + return PTR_ERR(clk); + } + clk_put(clk); + + desc->path = of_icc_get(dev, NULL); + if (IS_ERR(desc->path)) { + if (PTR_ERR(desc->path) != -EPROBE_DEFER) + dev_err(dev, "error getting path\n"); + return PTR_ERR(desc->path); + } + + platform_set_drvdata(pdev, desc); + pm_runtime_enable(dev); + + ret = pm_clk_create(dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(dev, "iface"); + if (ret < 0) { + dev_err(dev, "failed to acquire iface clock\n"); + goto destroy_pm_clk; + } + + return 0; + +destroy_pm_clk: + pm_clk_destroy(dev); + +disable_pm_runtime: + pm_runtime_disable(dev); + icc_put(desc->path); + + return ret; +} +EXPORT_SYMBOL(qcom_cc_runtime_init); + +int qcom_cc_runtime_resume(struct device *dev) +{ + struct qcom_cc_desc *desc = dev_get_drvdata(dev); + int ret; + + if (desc->path) { + ret = icc_set_bw(desc->path, 0, 1); + if (ret) { + dev_warn(dev, "%s: failed to vote bw\n", __func__); + return ret; + } + } + + ret = pm_clk_resume(dev); + if (ret) + dev_warn(dev, "%s: failed to enable clocks\n", __func__); + + return ret; +} +EXPORT_SYMBOL(qcom_cc_runtime_resume); + +int qcom_cc_runtime_suspend(struct device *dev) +{ + struct qcom_cc_desc *desc = dev_get_drvdata(dev); + int ret; + + ret = pm_clk_suspend(dev); + if (ret) + dev_warn(dev, "%s: failed to disable clocks\n", __func__); + + if (desc->path) { + ret = icc_set_bw(desc->path, 0, 0); + if (ret) + dev_warn(dev, "%s: failed to unvote bw\n", __func__); + } + + return 0; +} +EXPORT_SYMBOL(qcom_cc_runtime_suspend); + MODULE_LICENSE("GPL v2"); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index bb39a7e106d8..e2a9dbd1529d 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -29,6 +29,7 @@ struct qcom_cc_desc { size_t num_gdscs; struct clk_hw **clk_hws; size_t num_clk_hws; + struct icc_path *path; }; /** @@ -64,4 +65,9 @@ extern int qcom_cc_probe(struct platform_device *pdev, extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index, const struct qcom_cc_desc *desc); +int qcom_cc_runtime_init(struct platform_device *pdev, + struct qcom_cc_desc *desc); +int qcom_cc_runtime_suspend(struct device *dev); +int qcom_cc_runtime_resume(struct device *dev); + #endif From patchwork Wed Jun 16 14:10:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 461401 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp680054jae; Wed, 16 Jun 2021 07:11:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOE1fuskoZiflKuXFNIsdK+WhyqQwDpZjNuWhyBGtBabocpW3OzL8/NGPg7p+PR3E2Hqz/ X-Received: by 2002:a02:a41a:: with SMTP id c26mr4383425jal.87.1623852688204; Wed, 16 Jun 2021 07:11:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623852688; cv=none; d=google.com; s=arc-20160816; b=IOnog99T6OniffTRIiI0bNtT0mkZoRqAbWP32nlaxkMQ+SiZJdpExDaNy0oVZP1mOS AtwV+tBL5KSyQnQ6LN202a5ZkrNxampeNX7Xyai1WUoLIdK69FHkHENako/LHzPZWPN3 Zre/WhF37E1vt0lDlVRUiSlTSdoYe/AKdQWjfQOsS9bRQi+hjsS1mseOzeozcMPIPhpB no4ctKtonoHSF1DThq1t2sgSM66udosFtFEv6uSzK+YVBOp/azVVkjc9Pb48qRtSlamj 4QmR8hZVpFSEIsXLakFfLD21cVoeeI83766Q+yv3ifsnJaEEsun/aa407C38KupuM6j0 yNBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ExFCaLr+DmH1KCjQVYY2iL4Mk5cBbz4oYRRMXRoKR7Q=; b=K3slZih355nQywGvm2OWxVuPPLczvVzkl3INgf5ngv9+SkyUy4MtLQN8f3g6E9o5Mo 7mB1gq/o5kRu2f4qKqQKU4wGtNg0ASMnT5DLacycyFAH0Amj/mkoAPhBM5itUeFJ7Vlt y60bziyy2UdKCz8Q0U/bezlvA9EBRrkZSQpEuyyS1oygkHP+71757fqxUXuCLlexiRd3 6WHQD3UnUdDH/0tKA8HF3r7n2fVddbJ2YQ8hmYKj8OU4LRjeIvqNwQeaW1YTek9ry0y8 y56ga9691g+FUvZ1p80xhFUeboMhJTBSfxpvj+hRuLRg1V/v4gQmO9K9v/l7EGwmrw9O /Kjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DcbrMPdH; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Robert Foss --- drivers/clk/qcom/clk-rcg.h | 4 ++++ drivers/clk/qcom/clk-rcg2.c | 3 +++ 2 files changed, 7 insertions(+) -- 2.30.2 diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 99efcc7f8d88..a1f05281d950 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -149,6 +149,10 @@ struct clk_rcg2 { const struct freq_tbl *freq_tbl; struct clk_regmap clkr; u8 cfg_off; + u8 flags; +#define FORCE_ENABLE_RCG BIT(0) +#define HW_CLK_CTRL_MODE BIT(1) +#define DFS_SUPPORT BIT(2) }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 42f13a2d1cc1..ed2c9b6659cc 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -295,6 +295,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; + if (rcg->flags & HW_CLK_CTRL_MODE) + cfg |= CFG_HW_CLK_CTRL_MASK; + return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), mask, cfg); } From patchwork Wed Jun 16 14:10:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 461402 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp680183jae; Wed, 16 Jun 2021 07:11:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpamx/cFOndPOhpyoYsVFdKvlIRK7UXHWrbaZlJjLLv7T66mpWGnfhVwMryoeebGzycOa/ X-Received: by 2002:a05:6602:2be3:: with SMTP id d3mr177774ioy.54.1623852694533; Wed, 16 Jun 2021 07:11:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623852694; cv=none; d=google.com; s=arc-20160816; b=J6hjUvjC2/PzcUy7+2G4pxAFJ88wtY01hNthJIKoi3dxtRR/OtOTDR8U7M2PfqOpvi qx+Z/abtzBlljyln9Lugw5r2kcNjM016jz+3MW7kkXxBVOYgT3i0eNi2QJp9sPeJgmrb /+7GGaNuGF7N5d9f9Q/AvyCGTUQ/EYoUrx49XRnJmp3bPTKKC2kNevxRYkNDy1fCTHXv 2wPWjsqY7zzV8J1dRuuTHaPswaXNt6zkOM+s+qZF3qowuaV0wOa4iQvv+iJprh52cTNL 7pWcXCW6ZCLRJSl3YKZ23NbzLMjLsh3p6mfAHqb7kTDTqoqWRspOlp5DO0qy+FHLz6yu XLfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=u+LrLr5ScKl10ELD0o4ZHSHRjCSJkFhG5a8CEjAWpf0=; b=x743eLyeJyQMahVjJTUI2wXypVCFSMHxg5U1EAVtdKrg9902Dx0QOILQCNb3KkdGby 2Ux7vVIn3WawKSxqgUnK1qBX6qjEl9M2MN6WeJ/BAjeMMjjAEs6HpULo05VZuCbu4iv3 pS4hD/vYeRvSB7fCpFIK01ydHbTduKCxD2mCb+ouOhFFttgMmM3UBSkUGNeYcDrSf81w 6B0tre1LVae5dez+PzgopJGh7SjcOtFqIzIlR4tTY6kg/bBFQJ+VvYdE4LvVNZuyLpzl FCu/Gtpa5PVF2IQ+/jRnwIPuT3prYJB7SIkCBEzZy30NnyTgHZH+pC5rkLzmM3THiOHX Id4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dYpK2lVM; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Robert Foss --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.30.2 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index c6eb99169ddc..01090852ea76 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1399,7 +1399,7 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); /** - * clk_lucid_pll_configure - configure the lucid pll + * clk_trion_pll_configure - configure the trion pll * * @pll: clk alpha pll * @regmap: register map From patchwork Wed Jun 16 14:11:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 461554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3270C49361 for ; Wed, 16 Jun 2021 14:11:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9DA29613C1 for ; Wed, 16 Jun 2021 14:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233871AbhFPONk (ORCPT ); Wed, 16 Jun 2021 10:13:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233877AbhFPONe (ORCPT ); Wed, 16 Jun 2021 10:13:34 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A152C0617AE for ; Wed, 16 Jun 2021 07:11:27 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id r9so2849373wrz.10 for ; Wed, 16 Jun 2021 07:11:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xsn7+Lsp9NGdCiqtkjavVEDgvQSXhZBR2aAMSk2h6M4=; b=AnHj7RoSOlzMjAE3O1GUyGBfuS688F5iiC4eV01XSE1Gy+uC5pLxY8uv3b7JlDvLSZ ugznEp0TSBKX3aL0tZ71/34ec/JcffIxcCQxJlvvKrwvt5+Ufq++uTbyfGah9gNUlSlL WT4YNvtfnwLpUlVyLVlPiLgiW/fAhjHcN4P6v3NqQUa3ymWa0h+j1H0l4dFoGl4vkiwF /pIIbUR0H7c3OHOjdBRLNgD4JAnL/QlTNC3d+s3azQNrRY8TDsvBJMoj21oNwsheu/RG l6tw3OiFHk1bIrhWohwSEiCTELJRSOyqOF31MshLuE04PNlqf2gI7MdCa+Qw/WfWFphz VC8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xsn7+Lsp9NGdCiqtkjavVEDgvQSXhZBR2aAMSk2h6M4=; b=AghJ8RcHAJ1k6hbUoePzwy2fAAqjQFhaR4DEH/tWkRJRFpfDhoEvkX1IaQN9UCRAqf bywHva5/s7a3u3dgL6TB//MRjEqq7BSoHwJ7o3s5VdErW3xHTloyTJvExQc+eJyIzYtI qGStSZvIGeu10++zd4M7YdA2uKRpMSMJJz3tsSS0X15uLQSbtW5gnOW5i+zsfDjIHoyr hy0Kn/qSWfK7Y4adD2VnQ8PBy5juu+/wslQjAIMFCHsQbFE5yIP3qLb2qbApRniGN1C/ 55XFkM000LfprtIHBqLX+drZIlPc8tL0XDr7xgYjZx9zxBU0exSTrymw5J6kxKNoEIU1 DUqQ== X-Gm-Message-State: AOAM530YiQDXtdq9KwT4WQ99o8dkEsvqaiOxe+I+kJLIL+I3YbE8APqj DrXdvUeIWWSx50n3Pa01GTBaNw== X-Google-Smtp-Source: ABdhPJzeKOr/2wJKsYjkuqvXZQfV/09Ppyl5Kn6BkkkCEh+gpB2lRge69iJyjFP1rzu8mBE/Wz+UwA== X-Received: by 2002:a5d:4f8f:: with SMTP id d15mr5576503wru.85.1623852686174; Wed, 16 Jun 2021 07:11:26 -0700 (PDT) Received: from xps7590.fritz.box ([2a02:2454:3e5:b700:9df7:76e5:7e94:bf1e]) by smtp.gmail.com with ESMTPSA id g83sm1968375wma.10.2021.06.16.07.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jun 2021 07:11:25 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Cc: Robert Foss Subject: [RFC v1 04/11] clk: qcom: clk-alpha-pll: Add configuration support for LUCID 5LPE Date: Wed, 16 Jun 2021 16:11:00 +0200 Message-Id: <20210616141107.291430-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210616141107.291430-1-robert.foss@linaro.org> References: <20210616141107.291430-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Ported from the downstream driver. Used on SM8350 for DISPCC & VIDEOCC. Signed-off-by: Robert Foss --- drivers/clk/qcom/clk-alpha-pll.c | 3 +++ drivers/clk/qcom/clk-alpha-pll.h | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 01090852ea76..71040d53d7d8 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -115,6 +115,9 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_STATUS] = 0x30, [PLL_OFF_OPMODE] = 0x38, [PLL_OFF_ALPHA_VAL] = 0x40, + [PLL_OFF_SSC_DELTA_ALPHA] = 0x48, + [PLL_OFF_SSC_NUM_STEPS] = 0x4c, + [PLL_OFF_SSC_UPDATE_RATE] = 0x50, }, [CLK_ALPHA_PLL_TYPE_AGERA] = { [PLL_OFF_L_VAL] = 0x04, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6943e933be0f..9eb4589b6a02 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -37,6 +37,9 @@ enum { PLL_OFF_OPMODE, PLL_OFF_FRAC, PLL_OFF_CAL_VAL, + PLL_OFF_SSC_DELTA_ALPHA, + PLL_OFF_SSC_NUM_STEPS, + PLL_OFF_SSC_UPDATE_RATE, PLL_OFF_MAX_REGS }; @@ -158,6 +161,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config); #define clk_lucid_pll_configure(pll, regmap, config) \ clk_trion_pll_configure(pll, regmap, config) +#define clk_lucid_5lpe_pll_configure(pll, regmap, config) \ + clk_trion_pll_configure(pll, regmap, config) From patchwork Wed Jun 16 14:11:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 461404 Delivered-To: patch@linaro.org Received: by 2002:a02:735a:0:0:0:0:0 with SMTP id a26csp680277jae; Wed, 16 Jun 2021 07:11:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUHt7k7zEEROcM8KiPi0zRGp94Tw0VuPbNVN+PkKsD9X/g59TvBRM7sYfWbOhHPPCZE0vl X-Received: by 2002:a02:6944:: with SMTP id e65mr4401633jac.31.1623852698816; Wed, 16 Jun 2021 07:11:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1623852698; cv=none; d=google.com; s=arc-20160816; b=K3EyD4DowRYVpFmPPLMQLtSSyWEKvh0D+nQoOIUSw53ISpoQ+f63FKTEB/SrPiBIuv NaHdkcb9LgJVUMQYZp3VUAAQMsLV26/7XUZwTZcmvw42cGCrKbEleDks5U9xRGFivOJO +AaTvRAZEsv6lL5WSZxV7uJje+zgItEOyniZumCtd9InpHkMC1n6vtB+hpIjF35mVopv R6ZdssRcyuwC1b1FjHhjbkRzCtBCwAr9QmFkU27ckBz0LjgiP+gqmvJIYc9WSTRx73L9 TC2ge77XzwdjLqf8qpdXwmbYvXG7BazmD0XXwAfkzxBP9Lndq6AAVTrXbUsZSmMGSlDi ttiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cxk0+wVQB5HblxQhN+0OZpVOyii+2f7oNmTqsu1uOb8=; b=wQH8TyL8RafhhvKF0qzLWOiOvT1El5TsACDyd7+E+i4VNiBhizs3ipzOrHlb+ZwRHq 0KE69XcA7ix/txHwor5ztwNvNy8rOCie2M/Dw8F8zFiu+JWgPJkMwRG3DKeeqS/EATsE p7L8YpfTQIKyqq5NVwQvYqy4AbHwKMNFOaaCBhQk45qNwdoVpQ4i1U3NO4aV256Ytael st2+qsW69Pl6F4jIS7EBwvd3Z/AWiiWHe5NL/MpkBGFnHeCPEeubdK/h62m74GQMna0p 4megjfGb6tx/zR61XFZgFnPT+mL/Nz8v+ssxHbrkGq/MKfE1YbZl+UTaomPm8RBUAz1E IKQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cVLiTKlu; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Robert Foss --- .../bindings/clock/qcom,dispcc-sm8x50.yaml | 6 +- .../dt-bindings/clock/qcom,dispcc-sm8350.h | 77 +++++++++++++++++++ 2 files changed, 81 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8350.h -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..c10eefd024f6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,24 +4,26 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150, SM8250 and SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: enum: - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 100644 index 000000000000..361ef27de585 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8350_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AHB_CLK_SRC 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +#define DISP_CC_MDSS_BYTE1_CLK 6 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 9 +#define DISP_CC_MDSS_DP_AUX1_CLK 10 +#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 +#define DISP_CC_MDSS_DP_AUX_CLK 12 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13 +#define DISP_CC_MDSS_DP_LINK1_CLK 14 +#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15 +#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17 +#define DISP_CC_MDSS_DP_LINK_CLK 18 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 22 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23 +#define DISP_CC_MDSS_DP_PIXEL2_CLK 24 +#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25 +#define DISP_CC_MDSS_DP_PIXEL_CLK 26 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27 +#define DISP_CC_MDSS_EDP_AUX_CLK 28 +#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 29 +#define DISP_CC_MDSS_EDP_LINK_CLK 30 +#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 31 +#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 32 +#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 33 +#define DISP_CC_MDSS_EDP_PIXEL_CLK 34 +#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 35 +#define DISP_CC_MDSS_ESC0_CLK 36 +#define DISP_CC_MDSS_ESC0_CLK_SRC 37 +#define DISP_CC_MDSS_ESC1_CLK 38 +#define DISP_CC_MDSS_ESC1_CLK_SRC 39 +#define DISP_CC_MDSS_MDP_CLK 40 +#define DISP_CC_MDSS_MDP_CLK_SRC 41 +#define DISP_CC_MDSS_MDP_LUT_CLK 42 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 43 +#define DISP_CC_MDSS_PCLK0_CLK 44 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 45 +#define DISP_CC_MDSS_PCLK1_CLK 46 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 47 +#define DISP_CC_MDSS_ROT_CLK 48 +#define DISP_CC_MDSS_ROT_CLK_SRC 49 +#define DISP_CC_MDSS_RSCC_AHB_CLK 50 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 51 +#define DISP_CC_MDSS_VSYNC_CLK 52 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 53 +#define DISP_CC_PLL0 54 +#define DISP_CC_PLL1 55 +#define DISP_CC_SLEEP_CLK 56 +#define DISP_CC_SLEEP_CLK_SRC 57 +#define DISP_CC_XO_CLK_SRC 58 + +/* DISP_CC Reset */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif From patchwork Wed Jun 16 14:11:03 2021 Content-Type: text/plain; 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Wed, 16 Jun 2021 07:11:29 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Cc: Robert Foss Subject: [RFC v1 07/11] dt-bindings: clock: Add SM8350 QCOM video clock bindings Date: Wed, 16 Jun 2021 16:11:03 +0200 Message-Id: <20210616141107.291430-8-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210616141107.291430-1-robert.foss@linaro.org> References: <20210616141107.291430-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for video clock controller for SM8350 SoCs. Signed-off-by: Robert Foss --- .../bindings/clock/qcom,videocc.yaml | 2 + .../dt-bindings/clock/qcom,videocc-sm8350.h | 44 +++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..a1dfecbad5c9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -18,6 +18,7 @@ description: | dt-bindings/clock/qcom,videocc-sdm845.h dt-bindings/clock/qcom,videocc-sm8150.h dt-bindings/clock/qcom,videocc-sm8250.h + dt-bindings/clock/qcom,videocc-sm8350.h properties: compatible: @@ -26,6 +27,7 @@ properties: - qcom,sdm845-videocc - qcom,sm8150-videocc - qcom,sm8250-videocc + - qcom,sm8350-videocc clocks: items: diff --git a/include/dt-bindings/clock/qcom,videocc-sm8350.h b/include/dt-bindings/clock/qcom,videocc-sm8350.h new file mode 100644 index 000000000000..531cad2b0ab5 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sm8350.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS0C_CLK 5 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS1_CLK 7 +#define VIDEO_CC_MVS1_CLK_SRC 8 +#define VIDEO_CC_MVS1_DIV2_CLK 9 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 10 +#define VIDEO_CC_MVS1C_CLK 11 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 12 +#define VIDEO_CC_SLEEP_CLK 13 +#define VIDEO_CC_SLEEP_CLK_SRC 14 +#define VIDEO_CC_XO_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 +#define VIDEO_PLL0 17 +#define VIDEO_PLL1 18 + +/* VIDEO_CC resets */ +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES 5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#define MVS0C_GDSC 0 +#define MVS1C_GDSC 1 +#define MVS0_GDSC 2 +#define MVS1_GDSC 3 + +#endif From patchwork Wed Jun 16 14:11:04 2021 Content-Type: text/plain; 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Wed, 16 Jun 2021 07:11:31 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Cc: Robert Foss Subject: [RFC v1 08/11] clk: qcom: Add video clock controller driver for SM8350 Date: Wed, 16 Jun 2021 16:11:04 +0200 Message-Id: <20210616141107.291430-9-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210616141107.291430-1-robert.foss@linaro.org> References: <20210616141107.291430-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the video clock controller found on SM8350 based devices. Derived from the downstream driver. Signed-off-by: Robert Foss --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm8350.c | 593 ++++++++++++++++++++++++++++++ 3 files changed, 603 insertions(+) create mode 100644 drivers/clk/qcom/videocc-sm8350.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index f7c99f97fa57..181967e90a8a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -558,6 +558,15 @@ config SM_VIDEOCC_8250 Say Y if you want to support video devices and functionality such as video encode and decode. +config SM_VIDEOCC_8350 + tristate "SM8350 Video Clock Controller" + select SDM_GCC_8350 + select QCOM_GDSC + help + Support for the video clock controller on SM8350 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config SPMI_PMIC_CLKDIV tristate "SPMI PMIC clkdiv Support" depends on SPMI || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 69dc2a9f43d7..adf644b5c1ba 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o +obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c new file mode 100644 index 000000000000..37e1248454c2 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +enum { + P_BI_TCXO, + P_CORE_BI_PLL_TEST_SE, + P_SLEEP_CLK, + P_VIDEO_PLL0_OUT_MAIN, + P_VIDEO_PLL1_OUT_MAIN, +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 1750000000, 0 }, +}; + +static const struct alpha_pll_config video_pll0_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2A9A699C, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll video_pll0 = { + .offset = 0x42c, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "video_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + .name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct alpha_pll_config video_pll1_config = { + .l = 0x2B, + .alpha = 0xC000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x2A9A699C, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000000, + .test_ctl_hi1_val = 0x01800000, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll video_pll1 = { + .offset = 0x7d0, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "video_pll1", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + .name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_5lpe_ops, + }, + }, +}; + +static const struct parent_map videocc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data videocc_parent_data_0_ao[] = { + { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map videocc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_MAIN, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data videocc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &video_pll0.clkr.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map videocc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL1_OUT_MAIN, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data videocc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &video_pll1.clkr.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map videocc_parent_map_3[] = { + { P_SLEEP_CLK, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data videocc_parent_data_3[] = { + { .fw_name = "sleep_clk", .name = "sleep_clk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct freq_tbl ftbl_videocc_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 videocc_ahb_clk_src = { + .cmd_rcgr = 0xbd4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = videocc_parent_map_0, + .freq_tbl = ftbl_videocc_ahb_clk_src, + .flags = HW_CLK_CTRL_MODE, + .clkr.hw.init = &(struct clk_init_data){ + .name = "videocc_ahb_clk_src", + .parent_data = videocc_parent_data_0_ao, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_videocc_mvs0_clk_src[] = { + F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 videocc_mvs0_clk_src = { + .cmd_rcgr = 0xb94, + .mnd_width = 0, + .hid_width = 5, + .parent_map = videocc_parent_map_1, + .freq_tbl = ftbl_videocc_mvs0_clk_src, + .flags = HW_CLK_CTRL_MODE, + .clkr.hw.init = &(struct clk_init_data){ + .name = "videocc_mvs0_clk_src", + .parent_data = videocc_parent_data_1, + .num_parents = ARRAY_SIZE(videocc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_videocc_mvs1_clk_src[] = { + F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 videocc_mvs1_clk_src = { + .cmd_rcgr = 0xbb4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = videocc_parent_map_2, + .freq_tbl = ftbl_videocc_mvs1_clk_src, + .flags = HW_CLK_CTRL_MODE, + .clkr.hw.init = &(struct clk_init_data){ + .name = "videocc_mvs1_clk_src", + .parent_data = videocc_parent_data_2, + .num_parents = ARRAY_SIZE(videocc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_videocc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 videocc_sleep_clk_src = { + .cmd_rcgr = 0xef0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = videocc_parent_map_3, + .freq_tbl = ftbl_videocc_sleep_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "videocc_sleep_clk_src", + .parent_data = videocc_parent_data_3, + .num_parents = ARRAY_SIZE(videocc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 videocc_xo_clk_src = { + .cmd_rcgr = 0xecc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = videocc_parent_map_0, + .freq_tbl = ftbl_videocc_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "videocc_xo_clk_src", + .parent_data = videocc_parent_data_0_ao, + .num_parents = ARRAY_SIZE(videocc_parent_data_0_ao), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div videocc_mvs0_div_clk_src = { + .reg = 0xd54, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "videocc_mvs0_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div videocc_mvs0c_div2_div_clk_src = { + .reg = 0xc54, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "videocc_mvs0c_div2_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div videocc_mvs1_div_clk_src = { + .reg = 0xdd4, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "videocc_mvs1_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div videocc_mvs1c_div2_div_clk_src = { + .reg = 0xcf4, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "videocc_mvs1c_div2_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch videocc_mvs0_clk = { + .halt_reg = 0xd34, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xd34, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xd34, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "videocc_mvs0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs0c_clk = { + .halt_reg = 0xc34, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xc34, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "videocc_mvs0c_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs0c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs1_clk = { + .halt_reg = 0xdb4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xdb4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xdb4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "videocc_mvs1_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs1_div2_clk = { + .halt_reg = 0xdf4, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0xdf4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xdf4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "videocc_mvs1_div2_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_mvs1c_clk = { + .halt_reg = 0xcd4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xcd4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "videocc_mvs1c_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch videocc_sleep_clk = { + .halt_reg = 0xf10, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf10, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "videocc_sleep_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &videocc_sleep_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mvs0c_gdsc = { + .gdscr = 0xbf8, + .pd = { + .name = "mvs0c_gdsc", + }, + .flags = 0, + .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", +}; + +static struct gdsc mvs1c_gdsc = { + .gdscr = 0xc98, + .pd = { + .name = "mvs1c_gdsc", + }, + .flags = 0, + .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", +}; + +static struct gdsc mvs0_gdsc = { + .gdscr = 0xd18, + .pd = { + .name = "mvs0_gdsc", + }, + .flags = HW_CTRL, + .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", +}; + +static struct gdsc mvs1_gdsc = { + .gdscr = 0xd98, + .pd = { + .name = "mvs1_gdsc", + }, + .flags = HW_CTRL, + .pwrsts = PWRSTS_OFF_ON, + .supply = "mmcx", +}; + +static struct clk_regmap *videocc_sm8350_clocks[] = { + [VIDEO_CC_AHB_CLK_SRC] = &videocc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] = &videocc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] = &videocc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_DIV_CLK_SRC] = &videocc_mvs0_div_clk_src.clkr, + [VIDEO_CC_MVS0C_CLK] = &videocc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &videocc_mvs0c_div2_div_clk_src.clkr, + [VIDEO_CC_MVS1_CLK] = &videocc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] = &videocc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV2_CLK] = &videocc_mvs1_div2_clk.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] = &videocc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1C_CLK] = &videocc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &videocc_mvs1c_div2_div_clk_src.clkr, + [VIDEO_CC_SLEEP_CLK] = &videocc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] = &videocc_sleep_clk_src.clkr, + [VIDEO_CC_XO_CLK_SRC] = &videocc_xo_clk_src.clkr, + [VIDEO_PLL0] = &video_pll0.clkr, + [VIDEO_PLL1] = &video_pll1.clkr, +}; + +static const struct qcom_reset_map videocc_sm8350_resets[] = { + [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 }, + [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 }, + [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 }, + [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 }, + [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 }, + [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 }, +}; + +static struct gdsc *videocc_sm8350_gdscs[] = { + [MVS0C_GDSC] = &mvs0c_gdsc, + [MVS1C_GDSC] = &mvs1c_gdsc, + [MVS0_GDSC] = &mvs0_gdsc, + [MVS1_GDSC] = &mvs1_gdsc, +}; + +static const struct regmap_config videocc_sm8350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xf4c, + .fast_io = true, +}; + +static struct qcom_cc_desc videocc_sm8350_desc = { + .config = &videocc_sm8350_regmap_config, + .clks = videocc_sm8350_clocks, + .num_clks = ARRAY_SIZE(videocc_sm8350_clocks), + .resets = videocc_sm8350_resets, + .num_resets = ARRAY_SIZE(videocc_sm8350_resets), + .gdscs = videocc_sm8350_gdscs, + .num_gdscs = ARRAY_SIZE(videocc_sm8350_gdscs), +}; + +static const struct of_device_id videocc_sm8350_match_table[] = { + { .compatible = "qcom,sm8350-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, videocc_sm8350_match_table); + +static int videocc_sm8350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &videocc_sm8350_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = qcom_cc_runtime_init(pdev, &videocc_sm8350_desc); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + goto err_pm; + + clk_lucid_5lpe_pll_configure(&video_pll0, regmap, &video_pll0_config); + clk_lucid_5lpe_pll_configure(&video_pll1, regmap, &video_pll1_config); + + /* + * Keep clocks always enabled: + * videocc_ahb_clk + * videocc_xo_clk + */ + regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + + ret = qcom_cc_really_probe(pdev, &videocc_sm8350_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register VIDEOCC clocks\n"); + goto err_pm; + } + + pm_runtime_put_sync(&pdev->dev); + dev_info(&pdev->dev, "Registered VIDEOCC clocks\n"); + + return ret; + +err_pm: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static const struct dev_pm_ops videocc_sm8350_pm_ops = { + SET_RUNTIME_PM_OPS(qcom_cc_runtime_suspend, qcom_cc_runtime_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + +static struct platform_driver videocc_sm8350_driver = { + .probe = videocc_sm8350_probe, + .driver = { + .name = "sm8350-videocc", + .of_match_table = videocc_sm8350_match_table, + .pm = &videocc_sm8350_pm_ops, + }, +}; + +static int __init videocc_sm8350_init(void) +{ + return platform_driver_register(&videocc_sm8350_driver); +} +subsys_initcall(videocc_sm8350_init); + +static void __exit videocc_sm8350_exit(void) +{ + platform_driver_unregister(&videocc_sm8350_driver); +} +module_exit(videocc_sm8350_exit); + +MODULE_DESCRIPTION("QTI VIDEOCC SM8350 Driver"); +MODULE_LICENSE("GPL v2"); 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Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.30.2 diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ed0b51bc03ea..5dd32d4b1936 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -169,6 +169,14 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + mmcx_reg: mmcx-reg { + compatible = "regulator-fixed-domain"; + power-domains = <&rpmhpd SM8350_MMCX>; + required-opps = <&rpmhpd_opp_nom>; + regulator-name = "MMCX"; + regulator-always-on; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; From patchwork Wed Jun 16 14:11:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 461551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A62AC48BE8 for ; Wed, 16 Jun 2021 14:12:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C01161107 for ; Wed, 16 Jun 2021 14:12:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233879AbhFPOOc (ORCPT ); Wed, 16 Jun 2021 10:14:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233908AbhFPOOY (ORCPT ); Wed, 16 Jun 2021 10:14:24 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F5F4C061198 for ; Wed, 16 Jun 2021 07:11:35 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id h22-20020a05600c3516b02901a826f84095so1782686wmq.5 for ; Wed, 16 Jun 2021 07:11:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4OGHMR1jQwoAH96uaUuvrSUUPBxq6apuQySMYgFNC+8=; b=kGxNcqKYzteoQLEjouWsoqpog/GQkUccBVFhhkiTeIe5/t0daMxG4P9ctOdRj3FKDf f35XXENwD5eF2YD7AjGscAhOjdXmhVmsIqwBaV8nUrkfLfNjRdJ1TceSncUp/dqzSVFO y7CGsb6y983KbkQhubGPOJLMVWByM18yY1WnFoX+MEdZVuCArKj29cePpb0qCzxHtWOr 6cWoIpWRhKVV7hlukN9Mxe0H8o8iJbqX2BI/nJdtRnoZq82eojNPNWbaywvvs6dsIoQI wllAK/dVD+rQdfsSuqN644UdRirYg6dBPvpqYnoLEfixwVDQJ1vHltM2J+nWu7blpEK3 ytbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4OGHMR1jQwoAH96uaUuvrSUUPBxq6apuQySMYgFNC+8=; b=qzG2tAkUFEZY6MTWuyPtEkkPJTJBYNyZIh0O50CfdnRVnmvSB8PCJcOyj8zxuNFJl6 zzTXW4rgNmJMjahXUupOitj3AeeJQZUFnWn1YK+9NSQO2SSsPF+xb12zXKFgACfquIDw nqyStiT15y84m3p7k5C8TRhqh3+MdBHeBqgy5XT2hvegnsg3+gjZCCmcq/3Xm0H1QK02 Y8ZrbUpwHvb0C9PSA3JKzqrDnWIMoyvHjB62cfoS3GphSPU+e5CXQutrrpBllp8ozWSC 46DyN1h/E6R5mmmNoZg0vtwuVh7/X+cqYZ7TuCEXci2CL8iAsQeQdvBBLpyuc7o33XU8 fHVw== X-Gm-Message-State: AOAM533fCBeeUUlWDEHcjusn8b7jKUPocnmijYO7tvY3MzUTox47Fr3p I9Id86O+2XLcDiEin4klc/Xhew== X-Google-Smtp-Source: ABdhPJzwqIxK1guQTFvJIrbdSCMaJU7rjFZiwV51dUJROYEEm75zQ/JOgZVb4ePh2R7keeQGOxoJ0g== X-Received: by 2002:a1c:f60f:: with SMTP id w15mr11591494wmc.5.1623852694046; Wed, 16 Jun 2021 07:11:34 -0700 (PDT) Received: from xps7590.fritz.box ([2a02:2454:3e5:b700:9df7:76e5:7e94:bf1e]) by smtp.gmail.com with ESMTPSA id g83sm1968375wma.10.2021.06.16.07.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Jun 2021 07:11:33 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vinod Koul Cc: Robert Foss Subject: [RFC v1 10/11] arm64: dts: qcom: sm8350: Add videocc DT node Date: Wed, 16 Jun 2021 16:11:06 +0200 Message-Id: <20210616141107.291430-11-robert.foss@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210616141107.291430-1-robert.foss@linaro.org> References: <20210616141107.291430-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds the videocc DTS node for sm8350. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 5dd32d4b1936..b270fb94da8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -1285,6 +1286,18 @@ usb_2_dwc3: dwc3@a800000 { }; }; + videocc: qcom,videocc@abf0000 { + compatible = "qcom,sm8350-videocc"; + reg = <0 0x0abf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>; + mmcx-supply = <&mmcx_reg>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>;