From patchwork Wed Jun 16 12:27:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 461485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41022C49EA2 for ; Wed, 16 Jun 2021 12:27:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2AE7561356 for ; Wed, 16 Jun 2021 12:27:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232856AbhFPM3W (ORCPT ); Wed, 16 Jun 2021 08:29:22 -0400 Received: from relay02.th.seeweb.it ([5.144.164.163]:37117 "EHLO relay02.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232847AbhFPM3V (ORCPT ); Wed, 16 Jun 2021 08:29:21 -0400 Received: from localhost.localdomain (83.6.168.10.neoplus.adsl.tpnet.pl [83.6.168.10]) by m-r1.th.seeweb.it (Postfix) with ESMTPA id 64B6A1FEF7; Wed, 16 Jun 2021 14:27:13 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] arm64: dts: qcom: sm8250: Commonize PCIe pins Date: Wed, 16 Jun 2021 14:27:04 +0200 Message-Id: <20210616122708.144770-2-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210616122708.144770-1-konrad.dybcio@somainline.org> References: <20210616122708.144770-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Commonize PCIe pins, as the configuration is SoC-common and doesn't change (or at least doesn't change much) between boards. While at it, remove "output-low" from the RB5 board, as it's not necessary - we already explicitly pull the perst pin low. Signed-off-by: Konrad Dybcio --- Changes since v1: - Remove SDX55-specific pins arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 87 ------------------------ arch/arm64/boot/dts/qcom/sm8250.dtsi | 87 ++++++++++++++++++++++++ 2 files changed, 87 insertions(+), 87 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d5a4f5a27da6..8ac96f8e79d4 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -669,10 +669,6 @@ wifi-therm@1 { &pcie0 { status = "okay"; - perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; }; &pcie0_phy { @@ -683,10 +679,6 @@ &pcie0_phy { &pcie1 { status = "okay"; - perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; }; &pcie1_phy { @@ -697,10 +689,6 @@ &pcie1_phy { &pcie2 { status = "okay"; - perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_default_state>; }; &pcie2_phy { @@ -1178,81 +1166,6 @@ lt9611_irq_pin: lt9611-irq { bias-disable; }; - pcie0_default_state: pcie0-default { - clkreq { - pins = "gpio80"; - function = "pci_e0"; - bias-pull-up; - }; - - reset-n { - pins = "gpio79"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio81"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default { - clkreq { - pins = "gpio83"; - function = "pci_e1"; - bias-pull-up; - }; - - reset-n { - pins = "gpio82"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio84"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie2_default_state: pcie2-default { - clkreq { - pins = "gpio86"; - function = "pci_e2"; - bias-pull-up; - }; - - reset-n { - pins = "gpio85"; - function = "gpio"; - - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - wake-n { - pins = "gpio87"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; - }; - sdc2_default_state: sdc2-default { clk { pins = "sdc2_clk"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 1665eac49f3b..92dd7e66aaa0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1314,6 +1314,12 @@ pcie0: pci@1c00000 { phys = <&pcie0_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + status = "disabled"; }; @@ -1412,6 +1418,12 @@ pcie1: pci@1c08000 { phys = <&pcie1_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + status = "disabled"; }; @@ -1512,6 +1524,12 @@ pcie2: pci@1c10000 { phys = <&pcie2_lane>; phy-names = "pciephy"; + perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_default_state>; + status = "disabled"; }; @@ -3490,6 +3508,75 @@ data { bias-pull-up; }; }; + + pcie0_default_state: pcie0-default { + pcie0_perst_default: perst { + pins = "gpio79"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio80"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio81"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + pcie1_perst_default: perst { + pins = "gpio82"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio83"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio84"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_default_state: pcie2-default { + pcie2_perst_default: perst { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio86"; + function = "pci_e2"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { From patchwork Wed Jun 16 12:27:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 461484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40A45C48BE8 for ; Wed, 16 Jun 2021 12:27:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2C34D61356 for ; Wed, 16 Jun 2021 12:27:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232870AbhFPM3Y (ORCPT ); Wed, 16 Jun 2021 08:29:24 -0400 Received: from m-r1.th.seeweb.it ([5.144.164.170]:55653 "EHLO m-r1.th.seeweb.it" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232851AbhFPM3X (ORCPT ); Wed, 16 Jun 2021 08:29:23 -0400 Received: from localhost.localdomain (83.6.168.10.neoplus.adsl.tpnet.pl [83.6.168.10]) by m-r1.th.seeweb.it (Postfix) with ESMTPA id 8DE881FFD6; Wed, 16 Jun 2021 14:27:15 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] arm64: dts: qcom: sm8250-edo: Enable ADSP/CDSP/SLPI Date: Wed, 16 Jun 2021 14:27:06 +0200 Message-Id: <20210616122708.144770-4-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210616122708.144770-1-konrad.dybcio@somainline.org> References: <20210616122708.144770-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enabling the hardware thankfully comes down to a simple status = "okay". We assume that the firmware is provided by the Linux distribution, as it's signed and needs to come from the stock Android. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index cb2ff95606b2..a1028dec244f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -118,6 +118,10 @@ ramoops@ffc00000 { }; }; +&adsp { + status = "okay"; +}; + &apps_rsc { pm8150-rpmh-regulators { compatible = "qcom,pm8150-rpmh-regulators"; @@ -410,6 +414,10 @@ vreg_l7f_1p8: ldo7 { }; }; +&cdsp { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -516,6 +524,10 @@ &sdhc_2 { no-emmc; }; +&slpi { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <40 4>, <52 4>; From patchwork Wed Jun 16 12:27:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 461483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA8D4C48BE6 for ; Wed, 16 Jun 2021 12:27:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B568A61245 for ; Wed, 16 Jun 2021 12:27:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232933AbhFPM3e (ORCPT ); Wed, 16 Jun 2021 08:29:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232893AbhFPM32 (ORCPT ); Wed, 16 Jun 2021 08:29:28 -0400 Received: from m-r1.th.seeweb.it (m-r1.th.seeweb.it [IPv6:2001:4b7a:2000:18::170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59D6CC0617AE; Wed, 16 Jun 2021 05:27:20 -0700 (PDT) Received: from localhost.localdomain (83.6.168.10.neoplus.adsl.tpnet.pl [83.6.168.10]) by m-r1.th.seeweb.it (Postfix) with ESMTPA id C8B4D1FC51; Wed, 16 Jun 2021 14:27:17 +0200 (CEST) From: Konrad Dybcio To: ~postmarketos/upstreaming@lists.sr.ht Cc: martin.botka@somainline.org, angelogioacchino.delregno@somainline.org, marijn.suijten@somainline.org, jamipkettunen@somainline.org, Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] arm64: dts: qcom: sm8250-edo: Add Samsung touchscreen Date: Wed, 16 Jun 2021 14:27:08 +0200 Message-Id: <20210616122708.144770-6-konrad.dybcio@somainline.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210616122708.144770-1-konrad.dybcio@somainline.org> References: <20210616122708.144770-1-konrad.dybcio@somainline.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Samsung touchscreen node and relevant pin configuration to make the phones actually interactable with. Signed-off-by: Konrad Dybcio --- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 3f08802100ca..8f2417db4a99 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -462,7 +462,18 @@ &i2c13 { status = "okay"; clock-frequency = <400000>; - /* Samsung touchscreen @ 48 */ + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <39 0x2008>; + /* It's "vddio" downstream but it works anyway! */ + vdd-supply = <&vreg_l1c_1p8>; + avdd-supply = <&vreg_l10c_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + }; }; &i2c15 { @@ -570,6 +581,14 @@ mdm2ap_default: mdm2ap-default { bias-disable; }; + ts_int_default: ts-int-default { + pins = "gpio39"; + function = "gpio"; + drive-strength = <2>; + bias-disabled; + input-enable; + }; + ap2mdm_default: ap2mdm-default { pins = "gpio56", "gpio57"; function = "gpio";