From patchwork Fri Aug 3 06:41:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Garg X-Patchwork-Id: 143384 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp111145ljj; Thu, 2 Aug 2018 23:42:12 -0700 (PDT) X-Google-Smtp-Source: AAOMgpet2ntv8acX7ySGtlybI1+NM/odPTaH+jFiqaIMW1nVLyPxILnthmQXuxTHZNsZE/PGXDO7 X-Received: by 2002:a63:e056:: with SMTP id n22-v6mr2427312pgj.205.1533278532099; Thu, 02 Aug 2018 23:42:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533278532; cv=none; d=google.com; s=arc-20160816; b=KH2iDIpgMngtoWFm+vlkwsL1JifwEFwuCTuP3KgsjByVgs2ATI2wlOkqY6fGSSKkmO sXb1muOGpMbL3RGN+hWTqUaQgDnDdnj4QWkoDNj30W5aL7UtrjpKZHiORxavpa8eqlCO i9vi8CXPbIKZr3b20q1U/a/gHxRk0L9Q366yCcDSas7WOoqhr0ioUCzIj51hh9P0EAYI p9zYTXoun31JJARpi4Btbvz+r6pWCx3O4Rimezzo49l1MJyGfigFqRXmxw+awjdSGAmg Oc6fworNYBRWMpOnpwzFUSAcAu20fiqX+HH3xlyJR2s44KpES09cqre415yzscE2egVU GCnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=sLfbDmRpzmBd8sUz5WkMrJ4qWGunUlmbYpRmNdy9Hhs=; b=Nmak6jHRkIbLPXSS6cbmsBwSn/j541kAgVxRNNEPYza0gXYlwC2l3ci9nLw8cuLl0Y 6YW5t4bZ6mqVpyknhfnbY/jpWxdlK+FytIej+teo7UhgNKLEecK1MygovCmWIsuRWM3c oKx9tge3+oEwf9YtVOlUzzIiy4rD2tqSvETpCrkIIfSy30GmRsIu1y2X2K+a7SQ59ikI 5ZNC0pULowPpOLHRwpQ9OKNKL8d3z95BJSAY9pAhyisBD0nrN/Tgo/ueCg6hnhQlregQ lAFENPLPwEQT8X5tLP/Gqya1Su8Db1ZOKoOuAICweAbphKDc0aW8ewBJxa6F8OAmLOpQ K0hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ENJwD+AV; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id z12-v6si3208000pgu.692.2018.08.02.23.42.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 23:42:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ENJwD+AV; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B22A8210C4DD1; Thu, 2 Aug 2018 23:42:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=sumit.garg@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C0F102097FA8F for ; Thu, 2 Aug 2018 23:42:10 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id z7-v6so2131989plo.9 for ; Thu, 02 Aug 2018 23:42:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sYNdrocr3d2RIZqKYvvA+BDzw7sOhd06MQNo+Ea5E6s=; b=ENJwD+AVSdqQpbtIJUb9xGhI+TBJ26Ura73INtyY34/tipBnK7G9ooAIGLg8X5zs3u C9Jut1mgF4ARbLPijitW5Bpn6Cp2yjOqTWNw5JH17C7tHl310q6bmQHt8JVGfAONAd/D 6ePlbcDMrR/T4/S4RioqooVF+rYUfOypHt6g0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sYNdrocr3d2RIZqKYvvA+BDzw7sOhd06MQNo+Ea5E6s=; b=fC4Bqo1OjzYG55ECAqtcDVz6ZoOR/+UposckoJ9i0NJjisMj3HnwzYACMeEH3Hrfj0 l2XzNe8tKq2fP0/sBdjYVV1C/Q4DsPb1QIGaKTR3wr0oWg8X28WI3tRWsoA0lCt7DXv6 L5xuvQSZCIbL7Yi1ItB3VA2gAaX7My7PPeF+fMoN430ct2GDnvr6MUsR+s0cXAQLtvsd s7SLRA+aRWUN0UlJ8e+gJNwGmuc4GSYOMTqkIdJxDjHc2z2eiQjeX8BInFvV2f/Pzsni JX4S70I2jHo7QqCR7zaEsallpTj3b5HUFvreexb53MZEF7dCvVBgszlxFsPNexggORKJ Y+aw== X-Gm-Message-State: AOUpUlH6CEXGB2+a5PXmKtRYDgkKhKvX07pwb2zm7FGz4dYpqdpjEiyq SzoAiif8pcoI1g0lceNCy7GLlaWD3bs= X-Received: by 2002:a17:902:4906:: with SMTP id u6-v6mr2344410pld.44.1533278530161; Thu, 02 Aug 2018 23:42:10 -0700 (PDT) Received: from localhost.localdomain ([117.197.43.141]) by smtp.gmail.com with ESMTPSA id t88-v6sm10505465pfg.10.2018.08.02.23.42.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Aug 2018 23:42:09 -0700 (PDT) From: Sumit Garg To: edk2-devel@lists.01.org Date: Fri, 3 Aug 2018 12:11:34 +0530 Message-Id: <1533278495-25323-2-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> References: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/2] Silicon/SynQuacer: add optional OP-TEE DT node X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" OP-TEE is optional on Developerbox controlled via SCP firmware. To check if we need to enable OP-TEE DT node, we use "IsOpteePresent" OpteeLib api. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg Cc: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 + .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 8 +++++++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 28 ++++++++++++++++++++++ .../SynQuacerDtbLoaderLib.inf | 2 ++ 4 files changed, 39 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index fc498eb65217..4ff5df978e8e 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -76,6 +76,7 @@ [LibraryClasses.common] ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + OpteeLib|ArmPkg/Library/OpteeLib/OpteeLib.inf BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 37d642e4b237..d6a5f013e58c 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -574,6 +574,14 @@ #address-cells = <1>; #size-cells = <0>; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; }; #include "SynQuacerCaches.dtsi" diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c index 897d06743708..77db30c204fe 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -19,6 +19,7 @@ #include #include #include +#include #include // add enough space for three instances of 'status = "disabled"' @@ -47,6 +48,29 @@ DisableDtNode ( } } +STATIC +VOID +EnableDtNode ( + IN VOID *Dtb, + IN CONST CHAR8 *NodePath + ) +{ + INT32 Node; + INT32 Rc; + + Node = fdt_path_offset (Dtb, NodePath); + if (Node < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Node))); + return; + } + Rc = fdt_setprop_string (Dtb, Node, "status", "okay"); + if (Rc < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Rc))); + } +} + /** Return a pool allocated copy of the DTB image that is appropriate for booting the current platform via DT. @@ -107,6 +131,10 @@ DtPlatformLoadDtb ( DisableDtNode (CopyDtb, "/sdhci@52300000"); } + if (IsOpteePresent()) { + EnableDtNode (CopyDtb, "/firmware/optee"); + } + *Dtb = CopyDtb; *DtbSize = CopyDtbSize; diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf index 548d62fd5c0a..fd21f7c376ce 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf @@ -24,6 +24,7 @@ [Sources] SynQuacerDtbLoaderLib.c [Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -34,6 +35,7 @@ [LibraryClasses] DxeServicesLib FdtLib MemoryAllocationLib + OpteeLib [Pcd] gSynQuacerTokenSpaceGuid.PcdPcieEnableMask From patchwork Fri Aug 3 06:41:35 2018 Content-Type: text/plain; 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[198.145.21.10]) by mx.google.com with ESMTPS id v12-v6si2903463plz.105.2018.08.02.23.42.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 23:42:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JftK4RYg; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E3EAA210C515D; Thu, 2 Aug 2018 23:42:19 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=sumit.garg@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1722E210C4DB5 for ; Thu, 2 Aug 2018 23:42:19 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id f6-v6so2142789plo.1 for ; Thu, 02 Aug 2018 23:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dMI5JYo7UNUCX7qhQtXmYq5671fFvNLWtuZcCv+dwBc=; b=JftK4RYg9IImG2cuhBPpV7nrr7grUeOsHlaT5RTsI4fTDzKDMJr2UfqLcN9oaULfZV BiCPMO6sefcgxgePUgGrBhybmteJKX6RJTOYwuVIhr9Y8KPYSJuL7O5ydWaSJq4uFfvB Dc5oA/B4FWA2oLokacL1KFN0mfuOiXG9H96eo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dMI5JYo7UNUCX7qhQtXmYq5671fFvNLWtuZcCv+dwBc=; b=Px2eYSSxUabzfpWlz1E8NYJVEHxzHG/q5GcCeSunupCiyh20kJFwhOMl/EipBPBJvt sVoogLJ+/PWPgcXcP5uzIFv30TXPUJfRngjBTyaECxWRb04LR3hKCFSs/Bs1EPXiIeYl LlYuT2V+vJOB7pkJCIA4280CiV/1+RhwjdQ+S+k3t0NVq75MbPtQBUJzi91NYeIc8RPE JQPbZpEJT/JZvzJsIvwqRUqGL9GwB7pZgzTczCI8tK1ZjPg4txRZMrWOOo0ff5Fmxm30 FKlG4FAiWyUZ1q4v22P+NipoENvGBj1xevTTndip4mLmOp6MZvGTJ7ArY8bRar1Jj2tx +Tpg== X-Gm-Message-State: AOUpUlEZ1dpijz7KaY5GiYol6TAMGc4WdTVBya9Z7bq48mLQQooKgfEb +AOHBIIRG101SM+zcWLSCpNU303Dbwc= X-Received: by 2002:a17:902:7683:: with SMTP id m3-v6mr2275777pll.255.1533278538399; Thu, 02 Aug 2018 23:42:18 -0700 (PDT) Received: from localhost.localdomain ([117.197.43.141]) by smtp.gmail.com with ESMTPSA id t88-v6sm10505465pfg.10.2018.08.02.23.42.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Aug 2018 23:42:17 -0700 (PDT) From: Sumit Garg To: edk2-devel@lists.01.org Date: Fri, 3 Aug 2018 12:11:35 +0530 Message-Id: <1533278495-25323-3-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> References: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/2] Silicon/SynQuacer: Add status property in PCIe & SDHC DT nodes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add status = "disabled" property by default for PCIe and SDHC DT nodes. If required, update them at runtime with status = "okay". Using this method we don't need extra DTB_PADDING. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg Cc: Leif Lindholm Reviewed-by: Ard Biesheuvel --- .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 3 ++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 40 ++++------------------ 2 files changed, 10 insertions(+), 33 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index d6a5f013e58c..003e21bd6f85 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -473,6 +473,7 @@ msi-map = <0x000 &its 0x0 0x7f00>; dma-coherent; + status = "disabled"; }; pcie1: pcie@70000000 { @@ -492,6 +493,7 @@ msi-map = <0x0 &its 0x10000 0x7f00>; dma-coherent; + status = "disabled"; }; gpio: gpio@51000000 { @@ -537,6 +539,7 @@ clocks = <&clk_alw_c_0 &clk_alw_b_0>; clock-names = "core", "iface"; dma-coherent; + status = "disabled"; }; clk_alw_1_8: spi_ihclk { diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c index 77db30c204fe..96090c20502c 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c @@ -22,32 +22,6 @@ #include #include -// add enough space for three instances of 'status = "disabled"' -#define DTB_PADDING 64 - -STATIC -VOID -DisableDtNode ( - IN VOID *Dtb, - IN CONST CHAR8 *NodePath - ) -{ - INT32 Node; - INT32 Rc; - - Node = fdt_path_offset (Dtb, NodePath); - if (Node < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Node))); - return; - } - Rc = fdt_setprop_string (Dtb, Node, "status", "disabled"); - if (Rc < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Rc))); - } -} - STATIC VOID EnableDtNode ( @@ -105,7 +79,7 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - CopyDtbSize = OrigDtbSize + DTB_PADDING; + CopyDtbSize = OrigDtbSize; CopyDtb = AllocatePool (CopyDtbSize); if (CopyDtb == NULL) { return EFI_OUT_OF_RESOURCES; @@ -118,17 +92,17 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT0)) { - DisableDtNode (CopyDtb, "/pcie@60000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT0) { + EnableDtNode (CopyDtb, "/pcie@60000000"); } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT1)) { - DisableDtNode (CopyDtb, "/pcie@70000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT1) { + EnableDtNode (CopyDtb, "/pcie@70000000"); } SettingsVal = PcdGet64 (PcdPlatformSettings); Settings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; - if (Settings->EnableEmmc == EMMC_DISABLED) { - DisableDtNode (CopyDtb, "/sdhci@52300000"); + if (Settings->EnableEmmc == EMMC_ENABLED) { + EnableDtNode (CopyDtb, "/sdhci@52300000"); } if (IsOpteePresent()) {