From patchwork Mon Aug 6 11:04:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 143479 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp3148634ljj; Mon, 6 Aug 2018 04:05:01 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfPgkpSrY0gMpfpcqD0bNiWdRrZd3wcpVEUi7Q9iEtgYu38TL9iu3zMEQsHDGKIjhflgaB/ X-Received: by 2002:a65:52cc:: with SMTP id z12-v6mr14088543pgp.69.1533553501107; Mon, 06 Aug 2018 04:05:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533553501; cv=none; d=google.com; s=arc-20160816; b=uL/aQT2AanKV2qby5AiOj5zTLsLJBuvQ1MdlZzgzzhhwJkTOV4sMcAL2ds1oCV8u3L joK5zB32bOO7NcO+dcB0oPJWR5Pu8R9Sl203yHw3xKT7fzvog/yFVaLwWc7YJ/bYObFC tdpKdrUPrRKO7+luCvOg2Jl9RH3JiHsJK3sly5rOfPLpYhluxl3YcKWzcPoZ36eRvrfv DolXNFp6joHPYXRPu1rkxGVuj93HCUePOIVPLdRv94MJtBsRfNTvLYirte8kGjiBF7ip 18b+mLhRizDIVflyDjjYg12kzvGY2Jypplm5+NVcshkmN6dGHam96kbTlXar90lSlLs1 VlhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=hQ6n6gkTP39WeVWUZW741VGt7tXjXtY7A2WCNJFH9SM=; b=HN2abvmvF81k/KlzH//VecgLYm7yOYKFjI7blN/Je5ZirhsGqhiePueNy8dEoUcso/ x4a1LYMG+XMCm41JtWSS5f3oV4qCokNfj0s9XV3AZdIDyur6TCXngqKhst7Tt0O2FKpt mwwhS66E2NFWsnZpsgnnoY7dUgDbxXCzldAJLpUxCOreyIDYA260Ep4MxsqqVzZaEGtU jTQMcBUDM0+PMQXnAyMjdBP1R22RAJSHfFcvMCNH+uaQPtOvlIKwS1/4tl6vP57iEbIv IMBv2Y+/Ow+3MufKrTnVYGmK0jilZr0F/MVAX7ra4edFzkxBdwIjzbp4+ZeSZU9W28bw wfCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@kernel.org header.s=default header.b=hdQGjYfX; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d11-v6si12871093pgh.564.2018.08.06.04.05.00; Mon, 06 Aug 2018 04:05:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@kernel.org header.s=default header.b=hdQGjYfX; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728723AbeHFNNc (ORCPT + 5 others); Mon, 6 Aug 2018 09:13:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:40422 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727004AbeHFNNc (ORCPT ); Mon, 6 Aug 2018 09:13:32 -0400 Received: from localhost.localdomain (unknown [122.167.122.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A167521A07; Mon, 6 Aug 2018 11:04:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1533553499; bh=GYB7zRyBPsv+p/ysl6DEePRFs3osNYTSEacuAbrFDwg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hdQGjYfXP6vUzbmxcaDXE8qcQwYRY7AUUfpSQVwtIa3Y9e7FxIpdM1VJyeR3tMrzo lMnyEq7axzmmaEap9RKlV76fdbxSmEy3p/b/eNd/hsKuMKXVPII6XSP9/yRWLF/4kh AXUu2YCwvYI0bq9qpvDsZbPICZsM45b138Xewi/U= From: Vinod Koul To: Wolfram Sang , linux-i2c@vger.kernel.org Cc: Bjorn Andersson , linux-arm-msm@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, Todor Tomov , Vinod Koul Subject: [PATCH v3 1/2] dt-bindings: i2c: Add binding for Qualcomm CCI I2C controller Date: Mon, 6 Aug 2018 16:34:15 +0530 Message-Id: <20180806110416.4288-2-vkoul@kernel.org> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180806110416.4288-1-vkoul@kernel.org> References: <20180806110416.4288-1-vkoul@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Todor Tomov Add DT binding document for Qualcomm Camera Control Interface (CCI) I2C controller. Signed-off-by: Todor Tomov Signed-off-by: Vinod Koul --- .../devicetree/bindings/i2c/i2c-qcom-cci.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt -- 2.14.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt new file mode 100644 index 000000000000..977978dd4444 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt @@ -0,0 +1,55 @@ +Qualcomm Camera Control Interface (CCI) I2C controller + +Required properties: + - compatible: Should be one of: + - "qcom,cci-v1.0.8" for 8916; + - "qcom,cci-v1.4.0" for 8996. + - #address-cells: Should be <1>. + - #size-cells: Should be <0>. + - reg: Base address of the I2C controller and length of memory mapped region. + - interrupts: Specifier for CCI I2C interrupt. + - clocks: List of clock specifiers, one for each entry in clock-names. + - clock-names: Should contain: + - "mmss_mmagic_ahb" - on qcom,cci-v1.4.0 only; + - "camss_top_ahb"; + - "cci_ahb"; + - "cci"; + - "camss_ahb". + +Required subnodes: + - i2c-bus instances: + Mandatory i2c-bus0 subnode + Mandatory i2c-bus1 for qcom,cci-v1.4.0 + - Optional properties: + - clock-frequency: Desired I2C bus clock frequency + in Hz, defaults to 100 kHz if omitted. + +Required properties on qcom,cci-v1.4.0: + - power-domains: Power domain specifier. + +Example: + + cci@a0c000 { + compatible = "qcom,cci-v1.4.0"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa0c000 0x1000>; + interrupts = ; + power-domains = <&mmcc CAMSS_GDSC>; + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, + <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "mmss_mmagic_ahb", + "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + i2c-bus0 { + clock-frequency = <400000>; + }; + i2c-bus1 { + clock-frequency = <400000>; + }; + };