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X-Received-From: 2a00:1450:4864:20::42e Subject: [Qemu-devel] [RFC PATCH 1/4] scripts/decodetree.py: add a disassembly generator (HACK!) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Eduardo Habkost , Cleber Rosa Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Given our issues with failing disassembly we could try and re-use the decode tree data to output what instruction is being decoded. This will be used if registered as a fall-back for when the "proper" disassembler fails to decode an instruction. Signed-off-by: Alex Bennée --- scripts/decodetree.py | 52 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 46 insertions(+), 6 deletions(-) -- 2.17.1 Acked-by: Eduardo Habkost diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 277f9a9bba..f4b4318c96 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -169,6 +169,7 @@ input_file = '' output_file = None output_fd = None insntype = 'uint32_t' +disassemble = False re_ident = '[a-zA-Z][a-zA-Z0-9_]*' @@ -467,6 +468,7 @@ class Pattern(General): def output_code(self, i, extracted, outerbits, outermask): global translate_prefix + global disassemble ind = str_indent(i) arg = self.base.base.name output(ind, '/* line ', str(self.lineno), ' */\n') @@ -474,8 +476,34 @@ class Pattern(General): output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);\n') for n, f in self.fields.items(): output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n') - output(ind, 'return ', translate_prefix, '_', self.name, - '(ctx, &u.f_', arg, ', insn);\n') + output(ind, 'return ', translate_prefix, '_', self.name) + if disassemble: + output("(dstr, maxd, ") + else: + output("(ctx, ") + + output('&u.f_', arg) + + if disassemble: + output(");\n") + else: + output(', insn);\n') + + def output_formatter(self): + global translate_prefix + arg = self.base.base.name + output('/* line ', str(self.lineno), ' */\n') + output('typedef ', self.base.base.struct_name(), + ' arg_', self.name, ';\n') + output(translate_scope, 'bool ', translate_prefix, '_', self.name, + '(char *ptr, size_t n, arg_', self.name, ' *a)\n') + output("{\n") + output(str_indent(4), 'snprintf(ptr, n, "', self.name) + # fill in arguments here + output('"); \n') + output(str_indent(4), "return true;\n") + output("}\n") + # end Pattern @@ -973,11 +1001,12 @@ def main(): global insnwidth global insntype global insnmask + global disassemble decode_function = 'decode' decode_scope = 'static ' - long_opts = ['decode=', 'translate=', 'output=', 'insnwidth='] + long_opts = ['decode=', 'translate=', 'output=', 'insnwidth=', 'disassemble'] try: (opts, args) = getopt.getopt(sys.argv[1:], 'o:w:', long_opts) except getopt.GetoptError as err: @@ -998,6 +1027,8 @@ def main(): insnmask = 0xffff elif insnwidth != 32: error(0, 'cannot handle insns of width', insnwidth) + elif o == '--disassemble': + disassemble = True else: assert False, 'unhandled option' @@ -1031,7 +1062,10 @@ def main(): if i.base.base != p.base.base: error(0, i.name, ' has conflicting argument sets') else: - i.output_decl() + if disassemble: + i.output_formatter() + else: + i.output_decl() out_pats[i.name] = i output('\n') @@ -1039,8 +1073,14 @@ def main(): f = formats[n] f.output_extract() - output(decode_scope, 'bool ', decode_function, - '(DisasContext *ctx, ', insntype, ' insn)\n{\n') + output(decode_scope, 'bool ', decode_function) + + if disassemble: + output("(char *dstr, size_t maxd, ") + else: + output('(DisasContext *ctx, ') + + output(insntype, ' insn)\n{\n') i4 = str_indent(4) output(i4, 'union {\n') From patchwork Wed Aug 8 12:39:32 2018 Content-Type: text/plain; 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [RFC PATCH 2/4] target/arm: move decoder helpers into header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to re-use these helpers. Signed-off-by: Alex Bennée --- target/arm/decoder.h | 50 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 50 +------------------------------------- 2 files changed, 51 insertions(+), 49 deletions(-) create mode 100644 target/arm/decoder.h -- 2.17.1 diff --git a/target/arm/decoder.h b/target/arm/decoder.h new file mode 100644 index 0000000000..09a043fb2b --- /dev/null +++ b/target/arm/decoder.h @@ -0,0 +1,50 @@ +/* + * Helpers for extracting complex instruction fields. + * + * These are referenced in the .decode file and emitted by decodetree.py + */ + +/* See e.g. ASR (immediate, predicated). + * Returns -1 for unallocated encoding; diagnose later. + */ +static inline int tszimm_esz(int x) +{ + x >>= 3; /* discard imm3 */ + return 31 - clz32(x); +} + +static inline int tszimm_shr(int x) +{ + return (16 << tszimm_esz(x)) - x; +} + +/* See e.g. LSL (immediate, predicated). */ +static inline int tszimm_shl(int x) +{ + return x - (8 << tszimm_esz(x)); +} + +static inline int plus1(int x) +{ + return x + 1; +} + +/* The SH bit is in bit 8. Extract the low 8 and shift. */ +static inline int expand_imm_sh8s(int x) +{ + return (int8_t)x << (x & 0x100 ? 8 : 0); +} + +static inline int expand_imm_sh8u(int x) +{ + return (uint8_t)x << (x & 0x100 ? 8 : 0); +} + +/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) + * with unsigned data. C.f. SVE Memory Contiguous Load Group. + */ +static inline int msz_dtype(int msz) +{ + static const uint8_t dtype[4] = { 0, 5, 10, 15 }; + return dtype[msz]; +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 374051cd20..e3ec5c8ec2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -33,7 +33,7 @@ #include "trace-tcg.h" #include "translate-a64.h" #include "fpu/softfloat.h" - +#include "decoder.h" typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, uint32_t, uint32_t); @@ -47,54 +47,6 @@ typedef void gen_helper_gvec_mem(TCGv_env, TCGv_ptr, TCGv_i64, TCGv_i32); typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); -/* - * Helpers for extracting complex instruction fields. - */ - -/* See e.g. ASR (immediate, predicated). - * Returns -1 for unallocated encoding; diagnose later. - */ -static int tszimm_esz(int x) -{ - x >>= 3; /* discard imm3 */ - return 31 - clz32(x); -} - -static int tszimm_shr(int x) -{ - return (16 << tszimm_esz(x)) - x; -} - -/* See e.g. LSL (immediate, predicated). */ -static int tszimm_shl(int x) -{ - return x - (8 << tszimm_esz(x)); -} - -static inline int plus1(int x) -{ - return x + 1; -} - -/* The SH bit is in bit 8. Extract the low 8 and shift. */ -static inline int expand_imm_sh8s(int x) -{ - return (int8_t)x << (x & 0x100 ? 8 : 0); -} - -static inline int expand_imm_sh8u(int x) -{ - return (uint8_t)x << (x & 0x100 ? 8 : 0); -} - -/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) - * with unsigned data. C.f. SVE Memory Contiguous Load Group. - */ -static inline int msz_dtype(int msz) -{ - static const uint8_t dtype[4] = { 0, 5, 10, 15 }; - return dtype[msz]; -} /* * Include the generated decoder. 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X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [RFC PATCH 3/4] target/arm: add a fallback disassemble function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now we can generate a disassembler we need a function to hook into it. As we only deal with SVE instructions at the moment we don't need to differentiate the various decoders. I special case 0x5af0 as it is used by RISU for checkpoints. Signed-off-by: Alex Bennée --- target/arm/Makefile.objs | 8 ++++++++ target/arm/disassemble.c | 22 ++++++++++++++++++++++ target/arm/internals.h | 2 ++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/disassemble.c -- 2.17.1 diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 11c7baf8a3..4339353df8 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -20,3 +20,11 @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) target/arm/translate-sve.o: target/arm/decode-sve.inc.c obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o + +target/arm/disas-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --disassemble -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/disassemble.o: target/arm/disas-sve.inc.c +obj-$(TARGET_AARCH64) += disassemble.o diff --git a/target/arm/disassemble.c b/target/arm/disassemble.c new file mode 100644 index 0000000000..801f9680cb --- /dev/null +++ b/target/arm/disassemble.c @@ -0,0 +1,22 @@ +/* + * Fallback dissasembly + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "decoder.h" + +#include "disas-sve.inc.c" + +size_t do_aarch64_fallback_disassembly(const uint8_t *insnp, char *ptr, size_t n) +{ + uint32_t insn = ldl_p(insnp); + + if (insn == 0x5af0) { + snprintf(ptr, n, "illegal insn (risu checkpoint?)"); + } else if (!decode(ptr, n, insn)) { + snprintf(ptr, n, "failed decode"); + } + + return 4; +} diff --git a/target/arm/internals.h b/target/arm/internals.h index dc9357766c..80796632a2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -796,4 +796,6 @@ static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) } } +size_t do_aarch64_fallback_disassembly(const uint8_t *insn, char *ptr, size_t n); + #endif From patchwork Wed Aug 8 12:39:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 143622 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp796804ljj; Wed, 8 Aug 2018 06:01:42 -0700 (PDT) X-Google-Smtp-Source: AA+uWPwYWdyQ9znqxogOv2MvrQnEGh2HVmFOKNO3CP+doUyW7uJFTQburvO7plU7k5SAsPFCmigu X-Received: by 2002:a0c:8993:: with SMTP id 19-v6mr2379235qvr.56.1533733301914; Wed, 08 Aug 2018 06:01:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533733301; cv=none; d=google.com; s=arc-20160816; b=X+8zifGhaHzp9r//m9pHlw3Yv96Djr2DNVKW8vnNRuLpwmdgiiVJ0R7HvHaSBF6c8p g7B3fQ8Y4tzoMoPe5kHCpQnBHeI57ByZgYXPYpRjzVn1gXZM5DsfAfQupui8M7D0VCCm zukEXHCQh8ANWE9eO8gbFEqWJsfSz/C7DfS5z51Qk7LbVKYb08FJqSVFGWIN9Lxqpom7 EkP6Db7zc86GW49rePSHw/GIMCy/SBYF6vB7hvRZfhnho7SXlyUrxnzQLezhnF8auTCZ YHwthzowD93SE9jj9FLNMrMilZkgeYb2eSvrHm0beMJJ6ea9ViTd84qC6++uJvtfOOnp hGYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=wFgRh7TrCYNNSQSqotvwC6XFsN3uzWP5JoyFlB3dohg=; b=sPpu24gga0DocKJthmjG6e0Tc658qeToBUtuO9Q/RHY2PeSqfj9VhBLhNW5LtPX8eH Bve3elolWrtd23xCHLP8kMKkscMAKwPVCxn6yjJKDqNuDhqtxueBwP45F2oocxVNsIq/ msU+ikFk817dSRhyTbYsyCDaHmmd+OyMZjY8YlN9Ei4Ntl8DfT9XgeZzuwb0RjxedEqM UkEJXUeMxwOKiLTxxX+JmQ1Sw4Brjb9aPdxiPr4DGjTkAG6SRBknd1yfyzBgxDxKzDEX kUY28+W1HKY1GLhqL4hgP0m/Lr+/nCgrzyN1dL2tivuGyy1Umi886Kkh64NEXOW/g8uD W6eQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=idKG4YKO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 4/4] disas: allow capstone to defer to a fallback function on failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can abuse the CS_OPT_SKIPDATA by providing a call back when capstone can't disassemble something. The passing of the string to the dump function is a little clunky but works. Signed-off-by: Alex Bennée --- disas.c | 30 +++++++++++++++++++++++++++++- include/disas/bfd.h | 11 ++++++++++- target/arm/cpu.c | 4 ++++ 3 files changed, 43 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/disas.c b/disas.c index 5325b7e6be..dfd2c251c5 100644 --- a/disas.c +++ b/disas.c @@ -178,6 +178,20 @@ static int print_insn_od_target(bfd_vma pc, disassemble_info *info) to share this across calls and across host vs target disassembly. */ static __thread cs_insn *cap_insn; + +/* Handle fall-back dissasembly. We don't print here but we do set + * cap_fallback_str for cap_dump_insn to used*/ +static size_t cap_disas_fallback(const uint8_t *code, size_t code_size, + size_t offset, void *user_data) +{ + disassemble_info *info = (disassemble_info *) user_data; + info->cap_fallback_str = g_malloc0(256); + size_t skip = info->capstone_fallback_func(code + offset, + info->cap_fallback_str, 256); + return skip; +} + + /* Initialize the Capstone library. */ /* ??? It would be nice to cache this. We would need one handle for the host and one for the target. For most targets we can reset specific @@ -206,6 +220,14 @@ static cs_err cap_disas_start(disassemble_info *info, csh *handle) cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); } + if (info->capstone_fallback_func) { + cs_opt_skipdata skipdata = { + .callback = cap_disas_fallback, + .user_data = info, + }; + cs_option(*handle, CS_OPT_SKIPDATA_SETUP, (size_t) &skipdata); + } + /* "Disassemble" unknown insns as ".byte W,X,Y,Z". */ cs_option(*handle, CS_OPT_SKIPDATA, CS_OPT_ON); @@ -281,7 +303,13 @@ static void cap_dump_insn(disassemble_info *info, cs_insn *insn) } /* Print the actual instruction. */ - print(info->stream, " %-8s %s\n", insn->mnemonic, insn->op_str); + if (info->cap_fallback_str) { + print(info->stream, " %s\n", info->cap_fallback_str); + g_free(info->cap_fallback_str); + info->cap_fallback_str = NULL; + } else { + print(info->stream, " %-8s %s\n", insn->mnemonic, insn->op_str); + } /* Dump any remaining part of the insn on subsequent lines. */ for (i = split; i < n; i += split) { diff --git a/include/disas/bfd.h b/include/disas/bfd.h index 1f69a6e9d3..9d99bfef48 100644 --- a/include/disas/bfd.h +++ b/include/disas/bfd.h @@ -377,6 +377,12 @@ typedef struct disassemble_info { int cap_insn_unit; int cap_insn_split; + /* Fallback function to disassemble things capstone can't. */ + size_t (*capstone_fallback_func) + (const uint8_t *insn, char *ptr, size_t n); + + char *cap_fallback_str; + } disassemble_info; @@ -491,7 +497,10 @@ int generic_symbol_at_address(bfd_vma, struct disassemble_info *); (INFO).bytes_per_chunk = 0, \ (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \ (INFO).disassembler_options = NULL, \ - (INFO).insn_info_valid = 0 + (INFO).insn_info_valid = 0, \ + (INFO).capstone_fallback_func = NULL, \ + (INFO).cap_fallback_str = NULL + #ifndef ATTRIBUTE_UNUSED #define ATTRIBUTE_UNUSED __attribute__((unused)) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 64a8005a4b..cfefbfb0b9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -519,6 +519,10 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) info->cap_arch = CS_ARCH_ARM64; info->cap_insn_unit = 4; info->cap_insn_split = 4; + +#if defined(TARGET_AARCH64) + info->capstone_fallback_func = do_aarch64_fallback_disassembly; +#endif } else { int cap_mode; if (env->thumb) {