From patchwork Mon Jun 21 17:56:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 465612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E6F7C48BC2 for ; Mon, 21 Jun 2021 18:14:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BC356100B for ; Mon, 21 Jun 2021 18:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231132AbhFUSRL (ORCPT ); Mon, 21 Jun 2021 14:17:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232131AbhFUSQm (ORCPT ); Mon, 21 Jun 2021 14:16:42 -0400 Received: from mail-il1-x131.google.com (mail-il1-x131.google.com [IPv6:2607:f8b0:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FB5BC08ED6C for ; Mon, 21 Jun 2021 10:56:32 -0700 (PDT) Received: by mail-il1-x131.google.com with SMTP id b5so4129001ilc.12 for ; Mon, 21 Jun 2021 10:56:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=akzgFtmgF+CdBGifyk1rw0w+qVh3UK440Vu2WfXCaUc=; b=TlL31i+5DGSa2KSeDSKE9m3tLYAnA3RhVCnTFVGlGTdMzRLkIgzrHlfU+SXbfvyOAi I85SKzF7Tb38Qw2DaQ0I1sWUMN5VPxEjHZPWpN/ahCUE0uLa37TwMaCV9t5BeRJLcysQ gqu6/hH8SuyDlKrp7sbpABGnzjAetIB3gotBsMdpbHGViEQv08ZR1wjFq7nghVg5Lzum lgG3R4W95dE1rFT0G9c1/gLmo3XmPCcF9j2j3Tee8NWhJr0iFoMVU3mLoUFfLQfQFQOY yuLuEn1C7eICNG+OftUWXe5K62xGDUkMozXF1v8qN+BEt1+h+riK21MjSExGbouVwcF7 MRcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=akzgFtmgF+CdBGifyk1rw0w+qVh3UK440Vu2WfXCaUc=; b=TpNwOFYe0WmpwOjySvR23762Q2QcUOdu9FktbLeQGQgaTW4egbsotaIH6xo4AzoE1N /kyCh7bwUuGXK/Zj6zGxCPHAEYobT7JjghuE+kEnq+56tGFcUOMJFFnZiKwIxGet5rJH XGX7N5m8XuRqvhQyAnwHKwIpdGGuDLBXTSYyjB/ntUy03Y2pFG6yz1pP72IHBeSzj2mr kZEcD17osya2LhHK1rUw5VYwOz2vwn7PlbfIQQZF+zdqwrgRnfYt/ccTIuMFc6Y0wjza 9T++VNUAcpsDK6KggM4M+1ZOXedfDpaSkpUFd0VKoUJ86es43HpHcs/+wLGlTNmaE+fm nYeg== X-Gm-Message-State: AOAM530s6yLnaAELHxh5d451crr26MBxzFGrKjGKevG47SrsW8PApPS1 frnAWcs3urYuebV0mPfTow07LA== X-Google-Smtp-Source: ABdhPJymfUiaLImoqo/ZgRpFizkf3lHZ3nBsWiL0ig19escJ6nfeuMQRVdWv8xlA7GJtFLkiKnjKRA== X-Received: by 2002:a92:2a0a:: with SMTP id r10mr19224965ile.274.1624298192234; Mon, 21 Jun 2021 10:56:32 -0700 (PDT) Received: from presto.localdomain (c-73-185-129-58.hsd1.mn.comcast.net. [73.185.129.58]) by smtp.gmail.com with ESMTPSA id m13sm6259264iob.35.2021.06.21.10.56.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 10:56:31 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org Cc: angelogioacchino.delregno@somainline.org, jamipkettunen@gmail.com, bjorn.andersson@linaro.org, agross@kernel.org, elder@kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 1/6] dt-bindings: net: qcom, ipa: add support for MSM8998 Date: Mon, 21 Jun 2021 12:56:22 -0500 Message-Id: <20210621175627.238474-2-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210621175627.238474-1-elder@linaro.org> References: <20210621175627.238474-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for "qcom,msm8998-ipa", which uses IPA v3.1. Originally proposed by AngeloGioacchino Del Regno. Link: https://lore.kernel.org/linux-arm-msm/20210211175015.200772-8-angelogioacchino.delregno@somainline.org Signed-off-by: Alex Elder --- Documentation/devicetree/bindings/net/qcom,ipa.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index 5fe6d3dceb082..ed88ba4b94df5 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -44,6 +44,7 @@ description: properties: compatible: enum: + - qcom,msm8998-ipa - qcom,sc7180-ipa - qcom,sc7280-ipa - qcom,sdm845-ipa From patchwork Mon Jun 21 17:56:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 464598 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp2833449jao; Mon, 21 Jun 2021 11:15:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7YyJmOZLkcvXMfOQ7uPgjfTHxNplJ6b2hBM8fnAQdY+U2QsjjXt2SJQ6spnANBXJ2JNJG X-Received: by 2002:a5d:9f07:: with SMTP id q7mr20133594iot.169.1624299311053; Mon, 21 Jun 2021 11:15:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624299311; cv=none; d=google.com; s=arc-20160816; b=wmDAU3Av0trwt9cSdEvr8OC61hK8pZn3vAgVtBp9TMjI5HYkh6cR+qQyISn9X38lRw 9CIdu//1fiCkpw7IXnYupa+Ud4R2DxfZ71pX1CixEgC8Za4HW95dB4qYCiQy0W7aADKh iVE+Q3rvW/9XPZuPV4PA746xSjtiYArcwjjMAT/8es0NRFwWwegL6ApiVoRc78Bog0BJ SMntvFmE3/g/DKfGqNhnlLN28SOaX9cQ5CrL3YVR6o6SAg4sTi7vAWXOpTCt7mI5XbGu LRHsPEh8poqZBmIpradUmFLIMbGTPHmUsAOD1P97QH2RJkud5MAjw8OSq7/SZwdwOXUh NY7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=e7K1tI1lYYipcc5AxyBMccBKPqQyHUZh+yTOba27WkI=; b=SqCnfasuAAXDV9noH4pRJlTpcUk45nVo5UqQrDpTvAmsV+ZFTs7Q3Jmj9pLu1+SpxX /MzacLknJ/4ZJe1hTOcy5KsrkBZ79ezuE6MvVKyObJVXu3u9HVZTQrv34E3hmsu5VkeI L50ZL0Q9GZfh6BrbPJ2VMzfmy6E2H/KZkyj8v2/5rDCaa+BjXHMSiAUFP4MEt8ARu06M Fd8QFSsM+o2P5dADGuFnGXQfdug0RFryEqNamfO2vL+g8qWkxiKn68yzrRTB52K95TGo sYAIAOE4qAoroEIN9i33CJeIqWHxhdr52XuoozPfGUfP8XMlXxMdi4IkVXRg4ohGvYLG v0+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r+aFpl3F; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m12si3729637ili.36.2021.06.21.11.15.10; Mon, 21 Jun 2021 11:15:11 -0700 (PDT) Received-SPF: pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r+aFpl3F; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231464AbhFUSRR (ORCPT + 8 others); Mon, 21 Jun 2021 14:17:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232006AbhFUSQu (ORCPT ); Mon, 21 Jun 2021 14:16:50 -0400 Received: from mail-il1-x12b.google.com (mail-il1-x12b.google.com [IPv6:2607:f8b0:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB84DC08ED71 for ; Mon, 21 Jun 2021 10:56:33 -0700 (PDT) Received: by mail-il1-x12b.google.com with SMTP id s19so9372235ilj.1 for ; Mon, 21 Jun 2021 10:56:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e7K1tI1lYYipcc5AxyBMccBKPqQyHUZh+yTOba27WkI=; b=r+aFpl3Foyz72/gjSSAg+lldx+pun+eZ88u2hTBG+NLXfsOqggy8dK71eC8MfgMf6G hBynC3uTNpuXAQEcI6RVrZaLgRltLGcQcsXYcdAmWoOtjoQ/5th3+vI8CZNZnAl1EqTU j1dzgv9w64q99bRnBL0FxXXxgkZxjp4CjAANZYEoSipntJIZnZngXTFRet0MEX1+UGBY HEmMqRHc6j2DsVVne108UYkYySEeGn9tMjM46ytcPcFBq+Oy+jUnRMpXZamH/e5MvJRW pf+ntvwEzt4b5YuTeiEnyQksNTYCfWjuHWlU/JhF66f8RMBR3a6aunzaoKmMUVtjj32f 9jEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e7K1tI1lYYipcc5AxyBMccBKPqQyHUZh+yTOba27WkI=; b=IUWknjZSXIbeR+Buw+OVYj366AiOio3+MzjwCKaBtZglLeN9+VtvCvJWY3cBYUS/MR HN2eKNED/r0KH3FdXDaq8DRbxKkc3tAH5jOjUiCPu7sV8T5OBqA41oblKsF9B4hb/yJT gjNpUK00a6k9Zm4EuDY9JCM/Q4cZ5baqcqRyrolEnfnQLxDcReybkhUPgEzPjhbRqBjt j10sPpuuCA6PE4qb69g6Be319q3D0ZwYvqYPg0UwRUJoa261aWpkNgbIDMao9J46nBmz jthjDfbjXrn5i65bjdmosRkaY/aAungJkUqgOBuCR8eP9MgYNhpbwabf9u3Rdp+TDrSo f2TQ== X-Gm-Message-State: AOAM531CvJThvXYPXbGXPIu0L8mL/oM89sKoyobB+SnfZmHghMt7vP7k bTHf+FpCQICJSNK5UgenBIeZ8Q== X-Received: by 2002:a05:6e02:2183:: with SMTP id j3mr6219006ila.244.1624298193140; Mon, 21 Jun 2021 10:56:33 -0700 (PDT) Received: from presto.localdomain (c-73-185-129-58.hsd1.mn.comcast.net. [73.185.129.58]) by smtp.gmail.com with ESMTPSA id m13sm6259264iob.35.2021.06.21.10.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 10:56:32 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, jamipkettunen@gmail.com, bjorn.andersson@linaro.org, agross@kernel.org, elder@kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/6] net: ipa: inter-EE interrupts aren't always available Date: Mon, 21 Jun 2021 12:56:23 -0500 Message-Id: <20210621175627.238474-3-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210621175627.238474-1-elder@linaro.org> References: <20210621175627.238474-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The GSI inter-EE interrupts are not supported prior to IPA v3.5. Don't attempt to initialize them in gsi_irq_setup() for hardware that does not support them. Originally proposed by AngeloGioacchino Del Regno. Link: https://lore.kernel.org/netdev/20210211175015.200772-4-angelogioacchino.delregno@somainline.org Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 13 ++++++++++--- drivers/net/ipa/gsi_reg.h | 3 ++- 2 files changed, 12 insertions(+), 4 deletions(-) -- 2.27.0 Acked-by: AngeloGioacchino Del Regno diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index e374079603cf7..efd826e508bce 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -210,9 +210,16 @@ static void gsi_irq_setup(struct gsi *gsi) iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); - /* The inter-EE registers are in the non-adjusted address range */ - iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET); - iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET); + /* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */ + if (gsi->version > IPA_VERSION_3_1) { + u32 offset; + + /* These registers are in the non-adjusted address range */ + offset = GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET; + iowrite32(0, gsi->virt_raw + offset); + offset = GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET; + iowrite32(0, gsi->virt_raw + offset); + } iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); } diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index cb42c5ae86fa2..bf9593d9eaead 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -52,7 +52,8 @@ */ #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ -/* The two inter-EE IRQ register offsets are relative to gsi->virt_raw */ +/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */ + #define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \ GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) #define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \ From patchwork Mon Jun 21 17:56:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 465611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A947C4743C for ; Mon, 21 Jun 2021 18:15:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 10F5B6100B for ; Mon, 21 Jun 2021 18:15:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233180AbhFUSRa (ORCPT ); Mon, 21 Jun 2021 14:17:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232755AbhFUSQz (ORCPT ); Mon, 21 Jun 2021 14:16:55 -0400 Received: from mail-il1-x12e.google.com (mail-il1-x12e.google.com [IPv6:2607:f8b0:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A829BC08ED7E for ; Mon, 21 Jun 2021 10:56:34 -0700 (PDT) Received: by mail-il1-x12e.google.com with SMTP id s19so9372275ilj.1 for ; Mon, 21 Jun 2021 10:56:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d/cuSVPf2C9JoDJEerp4ashep36Ed4c3PDe794UkqTE=; b=QXBOq+qDq/k6P+u1/Wa9tu3UyvJ16dlS685s534u+p6G2XXrpywLgruYhQ9aKMS32M BmyCZXGwKno+l0V04csxLdMkwGUbqARpcesvrL1jfwpQsneLisD/Pmj2EvaJsksW0xBC qNJSq4mHnFa063RyTp8RhBxQNu6OkYP+Tnja8LaqWsc/s6yjc8BmXhU0ht51BYBVy0t+ 7sZ9rA/gUGCPclPYVLDPmBq81XU9wReGS+9eUdkl8202P6WJN5Gzm7Mj6kTqQ+maCm5o pxOXXR5tKfunt8pSWpPpM8b4AMXIVum9XRXREywdLth2NjSIHRPWEuJCBEnFQwonkyD2 T1jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d/cuSVPf2C9JoDJEerp4ashep36Ed4c3PDe794UkqTE=; b=d6bGrBgGPLVtj5fux/OXXWqed1TCWw1OtC/jZ4EeH54L07h2uNyy5d015z7lKhSETl VO4/bWiTSESRDucIflPUiXDiKdzFaHRzPjTfMAd36v+rw9dpCoyGM20oDbO4EDHZlml1 USAAI1iJpi0qYTlTHlqlSlKd8MrlXUH410Y/62TwQB1t1neH/a/NL5rX9QVhDdvxL8O/ yazi1NyFKVlUvgv7EtLJYNTRwFYyJNMu7b8cEAZirDLVoK/LlQKXog68zbpUsj88iUcQ W6ms8Ustbk7Tx/mpp5GrOfOJesPYdXKbKL686Ce/2PD/NxC9mg1fmh5z8d4qvQzA8hRc UuXA== X-Gm-Message-State: AOAM532f5e4E3YLFUT0Y7EOJxWvHCUMuF+4eh53ieGpkUvX6F2z+FfkH ODXJzpro+Tj9qZCOKo5zffXEdA== X-Google-Smtp-Source: ABdhPJzNmw1xwymLiMqFyT/7Hd7Ddo69DcqidsbPNUL4gsGaYjY/Jk3R0CeF4cSq5h6qge68As+QhA== X-Received: by 2002:a05:6e02:20c2:: with SMTP id 2mr18928806ilq.222.1624298194066; Mon, 21 Jun 2021 10:56:34 -0700 (PDT) Received: from presto.localdomain (c-73-185-129-58.hsd1.mn.comcast.net. [73.185.129.58]) by smtp.gmail.com with ESMTPSA id m13sm6259264iob.35.2021.06.21.10.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 10:56:33 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, jamipkettunen@gmail.com, bjorn.andersson@linaro.org, agross@kernel.org, elder@kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 3/6] net: ipa: disable misc clock gating for IPA v3.1 Date: Mon, 21 Jun 2021 12:56:24 -0500 Message-Id: <20210621175627.238474-4-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210621175627.238474-1-elder@linaro.org> References: <20210621175627.238474-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org For IPA v3.1, a workaround is needed to disable gating on a MISC clock. I have no further explanation, but this is what the downstream code (msm-4.4) does. This was suggested in a patch from AngeloGioacchino Del Regno. Link: https://lore.kernel.org/netdev/20210211175015.200772-2-angelogioacchino.delregno@somainline.org Signed-off-by: Alex Elder --- drivers/net/ipa/ipa_main.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index f82130db32f6d..20a83c7f671f3 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -400,16 +400,20 @@ static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) /* Implement some hardware workarounds */ if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) { - /* Enable open global clocks (not needed for IPA v4.5) */ - val = GLOBAL_FMASK; - val |= GLOBAL_2X_CLK_FMASK; - iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); - /* Disable PA mask to allow HOLB drop */ val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); val &= ~PA_MASK_EN_FMASK; iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); + + /* Enable open global clocks in the CLKON configuration */ + val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK; + } else if (version == IPA_VERSION_3_1) { + val = MISC_FMASK; /* Disable MISC clock gating */ + } else { + val = 0; /* No CLKON configuration needed */ } + if (val) + iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); ipa_hardware_config_comp(ipa); From patchwork Mon Jun 21 17:56:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 464874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 314B6C48BE5 for ; Mon, 21 Jun 2021 18:15:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 199F26115B for ; Mon, 21 Jun 2021 18:15:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233271AbhFUSRn (ORCPT ); Mon, 21 Jun 2021 14:17:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231833AbhFUSQ5 (ORCPT ); Mon, 21 Jun 2021 14:16:57 -0400 Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88AF2C08ED83 for ; Mon, 21 Jun 2021 10:56:35 -0700 (PDT) Received: by mail-io1-xd2a.google.com with SMTP id p66so16839000iod.8 for ; Mon, 21 Jun 2021 10:56:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PTTHSOVXexKSxKQpfvVOtl3Ci56/avUWgDl+NfjQ6/4=; b=AnONkDWeZBMGQEzfvUxpc1lVInHZ3+vSW5gveECtFKuFlcdfqt0jbk9SQeaJoz9v0o 0cuIGhSLtNOHYRhBVf3mCzcbC1xHUnp7LYVeBfqYRkrbH4QJBGqs6E1DlNDOOGzM/j8H 2Ijo4eMZaD3UAc8+xvtXhOgtFOOTU54txVbZIcLCK/nTcU5fpCd25Mo8RIpMWha8PRFj gfWBHS+g+th+kLQB2aydqEJuL8oy72JueINRpEZmb2it9S1AynWDDc+2XgRALtzuvpk3 H0Z0TU9OqHIMVcvm/b/TlBbbSsbx42+mrLqgEy7JFsIXvZ4KJ0Kte7zt9ENn3VIK3pwO jkyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PTTHSOVXexKSxKQpfvVOtl3Ci56/avUWgDl+NfjQ6/4=; b=nu+4h3I5UPanaWE/iE1vUPK1cRIcWF5icP/JeO0OhVcQhweuOaaQa8h0yFCZuYXhpY f6+zO6qzywf3YJFM9NMCcJkr/ztjzx/rt4ecQalJg+1q260ew9sE/TmxJiCP7Ss+4tkR egLJgrziBKB88OHdbGU/wgwjz8z2uLD/VPnkxsrZfDMosXYy4hSekp/fg06hOv2GdQpk gLVToiLGrIQX1Mr1FDWXyJTGSnlYcJgxbN20jwqf98jI37P8Qx36VLkDZw012MRc4y3y peoqP7XRlLamOyX8dXIXU2eOt/8TX9fuPsghwlhgyWfncW6ZJlGqyL4+TyIhvNCNFH6b 88/A== X-Gm-Message-State: AOAM531HzaL8omZudLmedD2PVLj9/snCVHq4QOPFTA6bkaf8oXwpoAY1 VcnlKRA6BsMhPSBgmVuhnUNbSw== X-Google-Smtp-Source: ABdhPJzVdzySf0yUti4z5+eyQfFqOIv2XKrWLB+V9dFx4ynrpVHUwct/lRroaz5SKnI9V659KmWhbw== X-Received: by 2002:a6b:6813:: with SMTP id d19mr7034410ioc.35.1624298195034; Mon, 21 Jun 2021 10:56:35 -0700 (PDT) Received: from presto.localdomain (c-73-185-129-58.hsd1.mn.comcast.net. [73.185.129.58]) by smtp.gmail.com with ESMTPSA id m13sm6259264iob.35.2021.06.21.10.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 10:56:34 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, jamipkettunen@gmail.com, bjorn.andersson@linaro.org, agross@kernel.org, elder@kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/6] net: ipa: FLAVOR_0 register doesn't exist until IPA v3.5 Date: Mon, 21 Jun 2021 12:56:25 -0500 Message-Id: <20210621175627.238474-5-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210621175627.238474-1-elder@linaro.org> References: <20210621175627.238474-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The FLAVOR_0 version first appears in IPA v3.5, so avoid attempting to read it for versions prior to that. This register contains a concise definition of the number and direction of endpoints supported by the hardware, and without it we can't verify endpoint configuration in ipa_endpoint_config(). In this case, just indicate that any endpoint number is available for use. Originally proposed by AngeloGioacchino Del Regno. Link: https://lore.kernel.org/netdev/20210211175015.200772-3-angelogioacchino.delregno@somainline.org Signed-off-by: Alex Elder Acked-by: AngeloGioacchino Del Regno --- drivers/net/ipa/ipa_endpoint.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 3520852936ed1..ab02669bae4e6 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -1731,6 +1731,21 @@ int ipa_endpoint_config(struct ipa *ipa) u32 max; u32 val; + /* Prior to IPAv3.5, the FLAVOR_0 register was not supported. + * Furthermore, the endpoints were not grouped such that TX + * endpoint numbers started with 0 and RX endpoints had numbers + * higher than all TX endpoints, so we can't do the simple + * direction check used for newer hardware below. + * + * For hardware that doesn't support the FLAVOR_0 register, + * just set the available mask to support any endpoint, and + * assume the configuration is valid. + */ + if (ipa->version < IPA_VERSION_3_5) { + ipa->available = ~0; + return 0; + } + /* Find out about the endpoints supplied by the hardware, and ensure * the highest one doesn't exceed the number we support. */ From patchwork Mon Jun 21 17:56:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 465610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10AE7C4743C for ; Mon, 21 Jun 2021 18:15:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF1326115B for ; Mon, 21 Jun 2021 18:15:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232635AbhFUSR7 (ORCPT ); Mon, 21 Jun 2021 14:17:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232441AbhFUSRH (ORCPT ); Mon, 21 Jun 2021 14:17:07 -0400 Received: from mail-il1-x12b.google.com (mail-il1-x12b.google.com [IPv6:2607:f8b0:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B85A8C08ED8B for ; Mon, 21 Jun 2021 10:56:36 -0700 (PDT) Received: by mail-il1-x12b.google.com with SMTP id u2so5810067ilk.7 for ; Mon, 21 Jun 2021 10:56:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=US5bOn0Zhlz2K4BSfH9yYaNsj8Mc3bOQWak9F9GKcgw=; b=WrDJqP5lgdxNpkzDUnPUfstO+IkZYtIgLW7BE8ULRmECf4egUcKe+QpKaaaGTrqIYa bRI6C4h0ryOEcdDstpfLMhFT3KH7zx/RzSSmvmMBnpWcw1wUAchILYsrjmIr1PR9VfAa pd1LoQRt4N2t/8vlhPGZEK8DiRP8mlwyjZ7zV9fN2RyBSEJM1PNe5VAPY8IvdoU25s2h ofqSo1O2fxWXcNa4AYLPl2Ca1vIwLkHSG88TRF1lzxV0yrG++xY6xi9zxJR+Mq/19tgc Eo9TBfPK5a5tPlrkeNnx33f/7DITSX7fzhxGpPAd93u44A0q5qJgT2lLPcd/Dkz700hS Eomw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=US5bOn0Zhlz2K4BSfH9yYaNsj8Mc3bOQWak9F9GKcgw=; b=AQMfD8YtNo9rOdFBxwyBODXBp8IoSW1F2XRBAwclVv6ScQhXaNElF2wnGK7WoW9mYP CF17SKNkG6uDbLbBbaajYkrH3tbll/qrSxIZNWydjTXnOPsfTCxDxoEJOdZt8xF9PO06 bN5VFCNLReNLRW8ABGE64fFfgjp0aUe2HcK4yxJ0wLMWTTmf9ZOTdRDyuHzNQht9oQnL SfMury65/StnsLQChsmlQpHtZocAWeyOjuWJcRV69kLEqOw4PyOemOTBBWpBxrQ3ELha Ie2s2FEAuk9qVQX2aHYSEVrFFwk8MbaUsdO1ez7Tr/DnDiL5AgwFegaC7I0VPVhYK1Ey 5SwA== X-Gm-Message-State: AOAM530mIhNKnf4AEcwdsxY7PA7nPsqKaT2YAMiKtHcgWjNqK8hVzIJg LKrDjyH3jkwz0mnTgE4jNr3cSA== X-Google-Smtp-Source: ABdhPJzdv3BH3fL4HdAOQyQHjdPgtxJ+7ZhvCHkAzg68RkQ1VMQtujxM0RYLG73tbZlALQEdJBcgBg== X-Received: by 2002:a92:3302:: with SMTP id a2mr18866126ilf.62.1624298195944; Mon, 21 Jun 2021 10:56:35 -0700 (PDT) Received: from presto.localdomain (c-73-185-129-58.hsd1.mn.comcast.net. [73.185.129.58]) by smtp.gmail.com with ESMTPSA id m13sm6259264iob.35.2021.06.21.10.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 10:56:35 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, jamipkettunen@gmail.com, bjorn.andersson@linaro.org, agross@kernel.org, elder@kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 5/6] net: ipa: introduce gsi_ring_setup() Date: Mon, 21 Jun 2021 12:56:26 -0500 Message-Id: <20210621175627.238474-6-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210621175627.238474-1-elder@linaro.org> References: <20210621175627.238474-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Prior to IPA v3.5.1, there is no HW_PARAM_2 GSI register, which we use to determine the number of channels and endpoints per execution environment. In that case, we will just assume the number supported is the maximum supported by the driver. Introduce gsi_ring_setup() to encapsulate the code that determines the number of channels and endpoints. Update GSI_EVT_RING_COUNT_MAX so it is big enough to handle any available channel for all supported hardware (IPA v4.9 can have 23 channels and 24 event rings). Signed-off-by: Alex Elder --- drivers/net/ipa/gsi.c | 77 ++++++++++++++++++++++++++++--------------- drivers/net/ipa/gsi.h | 2 +- 2 files changed, 51 insertions(+), 28 deletions(-) diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index efd826e508bce..427c68b2ad8f3 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -224,6 +224,51 @@ static void gsi_irq_setup(struct gsi *gsi) iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); } +/* Get # supported channel and event rings; there is no gsi_ring_teardown() */ +static int gsi_ring_setup(struct gsi *gsi) +{ + struct device *dev = gsi->dev; + u32 count; + u32 val; + + if (gsi->version < IPA_VERSION_3_5_1) { + /* No HW_PARAM_2 register prior to IPA v3.5.1, assume the max */ + gsi->channel_count = GSI_CHANNEL_COUNT_MAX; + gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX; + + return 0; + } + + val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET); + + count = u32_get_bits(val, NUM_CH_PER_EE_FMASK); + if (!count) { + dev_err(dev, "GSI reports zero channels supported\n"); + return -EINVAL; + } + if (count > GSI_CHANNEL_COUNT_MAX) { + dev_warn(dev, "limiting to %u channels; hardware supports %u\n", + GSI_CHANNEL_COUNT_MAX, count); + count = GSI_CHANNEL_COUNT_MAX; + } + gsi->channel_count = count; + + count = u32_get_bits(val, NUM_EV_PER_EE_FMASK); + if (!count) { + dev_err(dev, "GSI reports zero event rings supported\n"); + return -EINVAL; + } + if (count > GSI_EVT_RING_COUNT_MAX) { + dev_warn(dev, + "limiting to %u event rings; hardware supports %u\n", + GSI_EVT_RING_COUNT_MAX, count); + count = GSI_EVT_RING_COUNT_MAX; + } + gsi->evt_ring_count = count; + + return 0; +} + /* Event ring commands are performed one at a time. Their completion * is signaled by the event ring control GSI interrupt type, which is * only enabled when we issue an event ring command. Only the event @@ -1834,43 +1879,21 @@ static void gsi_channel_teardown(struct gsi *gsi) /* Setup function for GSI. GSI firmware must be loaded and initialized */ int gsi_setup(struct gsi *gsi) { - struct device *dev = gsi->dev; u32 val; + int ret; /* Here is where we first touch the GSI hardware */ val = ioread32(gsi->virt + GSI_GSI_STATUS_OFFSET); if (!(val & ENABLED_FMASK)) { - dev_err(dev, "GSI has not been enabled\n"); + dev_err(gsi->dev, "GSI has not been enabled\n"); return -EIO; } gsi_irq_setup(gsi); /* No matching teardown required */ - val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET); - - gsi->channel_count = u32_get_bits(val, NUM_CH_PER_EE_FMASK); - if (!gsi->channel_count) { - dev_err(dev, "GSI reports zero channels supported\n"); - return -EINVAL; - } - if (gsi->channel_count > GSI_CHANNEL_COUNT_MAX) { - dev_warn(dev, - "limiting to %u channels; hardware supports %u\n", - GSI_CHANNEL_COUNT_MAX, gsi->channel_count); - gsi->channel_count = GSI_CHANNEL_COUNT_MAX; - } - - gsi->evt_ring_count = u32_get_bits(val, NUM_EV_PER_EE_FMASK); - if (!gsi->evt_ring_count) { - dev_err(dev, "GSI reports zero event rings supported\n"); - return -EINVAL; - } - if (gsi->evt_ring_count > GSI_EVT_RING_COUNT_MAX) { - dev_warn(dev, - "limiting to %u event rings; hardware supports %u\n", - GSI_EVT_RING_COUNT_MAX, gsi->evt_ring_count); - gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX; - } + ret = gsi_ring_setup(gsi); /* No matching teardown required */ + if (ret) + return ret; /* Initialize the error log */ iowrite32(0, gsi->virt + GSI_ERROR_LOG_OFFSET); diff --git a/drivers/net/ipa/gsi.h b/drivers/net/ipa/gsi.h index d5996bdb20ef5..81cd7b07f6e14 100644 --- a/drivers/net/ipa/gsi.h +++ b/drivers/net/ipa/gsi.h @@ -17,7 +17,7 @@ /* Maximum number of channels and event rings supported by the driver */ #define GSI_CHANNEL_COUNT_MAX 23 -#define GSI_EVT_RING_COUNT_MAX 20 +#define GSI_EVT_RING_COUNT_MAX 24 /* Maximum TLV FIFO size for a channel; 64 here is arbitrary (and high) */ #define GSI_TLV_MAX 64 From patchwork Mon Jun 21 17:56:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 464602 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:102:0:0:0:0 with SMTP id x2csp2833956jao; Mon, 21 Jun 2021 11:15:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpZhiBh2FUGM7p7MPbTQobNaQr/U80vETpdIMv1trRoBYxCFb8QflH5tVM3/cb0DXeRXeD X-Received: by 2002:a02:8521:: with SMTP id g30mr19019227jai.113.1624299351826; Mon, 21 Jun 2021 11:15:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624299351; cv=none; d=google.com; s=arc-20160816; b=zmvHKTP3kAg9kNju0gU9MJwew2ddviUbnT1nLq2keUHl2RLBF9JrH9PDWKvUlUG6Ke SCZejbEeMV05DpxQKBKv7h/Fks2KMNPH1jWCYuVHYELoAZN99XKhB64tulyBOfDqdkPQ O/jp7JCJsKOXHGNE8VOwanRr8SYnMU5E4lrLTPDjKiH78zjnbcQB0c99uLRiEBCF1zpd 9KTkfqXPepkexdf0Vkn+lW8f+DoamfizzAMSyNA8kMrU9JHbcLIaB9megyh58Yr9mjcr Q1lFewjK0cBtOcnLmC+ICHgiOUpY/9w5cL/FK+2KveaSqmX9nyI5vBDLtB2O8u0Q/d8K gvTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FsAurCoNFFJayoeiLx6rofwwsjk1qR9gtCLQMlN5NdA=; b=hzq36p5hD8NEeEP6g/IMidqAPMFbNZxj8Kkc8E/2yHJiPRVIyNfMXJoYeWlig7dnGm +BQ7J4hVNOCMxc2WL8bhdJgzLL/a2pQcDk8T1eCEpW/qS87M7VRlWwMF8DtXNj6GdlWQ +tOG6DsvpoGtKj9D9cGrNBn2tAjJZyYQyY+fWlFpl9YJ8qqnhtfhllP10Cp4dcggox1W 19HhxlYgg5EbT5M7kBvxTUIg/MPhOiX7Qxmf5hqPBI+3GBwVf/BxlQElR8aRyfFlx5y9 603JYDNwovmu/OZEvLR5FmYovKrJ8nJiVzzFMTfvz7KrWCcVIuc97kK1i2M8nQBiWBW0 ywVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zduiZR3a; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id l16si3906126ilo.155.2021.06.21.11.15.51; Mon, 21 Jun 2021 11:15:51 -0700 (PDT) Received-SPF: pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zduiZR3a; spf=pass (google.com: domain of netdev-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231977AbhFUSSE (ORCPT + 8 others); Mon, 21 Jun 2021 14:18:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231740AbhFUSRM (ORCPT ); Mon, 21 Jun 2021 14:17:12 -0400 Received: from mail-il1-x132.google.com (mail-il1-x132.google.com [IPv6:2607:f8b0:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EF9FC061226 for ; Mon, 21 Jun 2021 10:56:37 -0700 (PDT) Received: by mail-il1-x132.google.com with SMTP id b5so4129297ilc.12 for ; Mon, 21 Jun 2021 10:56:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FsAurCoNFFJayoeiLx6rofwwsjk1qR9gtCLQMlN5NdA=; b=zduiZR3a2hwthG/uvXbBl1BwtfLILzjgki15moIehapr9EevwYAR1UjWWK1MZVWUtq sETdu4l0qi05VoaeOMoyf9USVSjgUu+WzLfqxDNlnCsBF8fsC0EFEIXAJT3CJifhvlsE zNDJFuR7MyPBjiFivnHg7JgE+boLglIzoQ8WIxe1sKMAsP4ei66zOObXqM2XYENB8gQi JRTSkIBd+E8dmFKORIQA3MN1qMhlDIgDEjKxTM24E5hsPjMYDuqtTTlt0e658ncIK5Cy +1VKeomToQNCj35KnWbQyTtTPptIqi72U7hkSN4b6SIH8X1A8Uu2m8BabRHfB40OeNYI OnOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FsAurCoNFFJayoeiLx6rofwwsjk1qR9gtCLQMlN5NdA=; b=LTFjxg9PWuhEz8fG2ajKONdj+rdOWcXAvLTtJg+v5qYFwj5+z/lA/+4LLtmx+NeRI0 FmQWd940HA3Y4QL0kT1pDlpCz7ydMYALdjjwCOB3rXofUUchEGMNC9n+m5gIotJU2wL5 VzdpOtEIBo5Ej6nnbxjp/LQz3i6E3UbcTGljwPWuVdmIML4ZNkyCAplw7+JdwT/wqE1r 4aM30oNatqdn2UFSAjNtGBZ9gp5BWCDjChApeYhQdI8J5sli1tU8M2lXD8UqDDl/nykq MT57ePa5hV3/GsA0jxcC09tXtnIQgAapCHtv3FvY/KQpetBqspBM89naL2VariaZ7AYv JZ2A== X-Gm-Message-State: AOAM530W794miBIL/PDbubOB8PnvPdQC2gkbjrhauPnUXFWC6+77omrG WKnZg6ED4WrxpX5UqahcGa72rYZNNplMUg== X-Received: by 2002:a05:6e02:1be1:: with SMTP id y1mr19727287ilv.204.1624298196914; Mon, 21 Jun 2021 10:56:36 -0700 (PDT) Received: from presto.localdomain (c-73-185-129-58.hsd1.mn.comcast.net. [73.185.129.58]) by smtp.gmail.com with ESMTPSA id m13sm6259264iob.35.2021.06.21.10.56.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 10:56:36 -0700 (PDT) From: Alex Elder To: davem@davemloft.net, kuba@kernel.org Cc: robh+dt@kernel.org, angelogioacchino.delregno@somainline.org, jamipkettunen@gmail.com, bjorn.andersson@linaro.org, agross@kernel.org, elder@kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 6/6] net: ipa: add IPA v3.1 configuration data Date: Mon, 21 Jun 2021 12:56:27 -0500 Message-Id: <20210621175627.238474-7-elder@linaro.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210621175627.238474-1-elder@linaro.org> References: <20210621175627.238474-1-elder@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for the MSM8998 SoC, which includes IPA version 3.1. Originally proposed by AngeloGioacchino Del Regno. Link: https://lore.kernel.org/netdev/20210211175015.200772-6-angelogioacchino.delregno@somainline.org Signed-off-by: Alex Elder --- drivers/net/ipa/Makefile | 6 +- drivers/net/ipa/ipa_data-v3.1.c | 533 ++++++++++++++++++++++++++++++++ drivers/net/ipa/ipa_data.h | 1 + drivers/net/ipa/ipa_main.c | 4 + 4 files changed, 541 insertions(+), 3 deletions(-) create mode 100644 drivers/net/ipa/ipa_data-v3.1.c -- 2.27.0 Acked-by: AngeloGioacchino Del Regno diff --git a/drivers/net/ipa/Makefile b/drivers/net/ipa/Makefile index bd34fce8f6e63..506f8d5cd4eeb 100644 --- a/drivers/net/ipa/Makefile +++ b/drivers/net/ipa/Makefile @@ -10,6 +10,6 @@ ipa-y := ipa_main.o ipa_clock.o ipa_reg.o ipa_mem.o \ ipa_resource.o ipa_qmi.o ipa_qmi_msg.o \ ipa_sysfs.o -ipa-y += ipa_data-v3.5.1.o ipa_data-v4.2.o \ - ipa_data-v4.5.o ipa_data-v4.9.o \ - ipa_data-v4.11.o +ipa-y += ipa_data-v3.1.o ipa_data-v3.5.1.o \ + ipa_data-v4.2.o ipa_data-v4.5.o \ + ipa_data-v4.9.o ipa_data-v4.11.o diff --git a/drivers/net/ipa/ipa_data-v3.1.c b/drivers/net/ipa/ipa_data-v3.1.c new file mode 100644 index 0000000000000..4c28189462a70 --- /dev/null +++ b/drivers/net/ipa/ipa_data-v3.1.c @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019-2021 Linaro Ltd. + */ + +#include + +#include "gsi.h" +#include "ipa_data.h" +#include "ipa_endpoint.h" +#include "ipa_mem.h" + +/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.1 */ +enum ipa_resource_type { + /* Source resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, + IPA_RESOURCE_TYPE_SRC_HDR_SECTORS, + IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, + IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, + IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS, + IPA_RESOURCE_TYPE_SRC_HPS_DMARS, + IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, + + /* Destination resource types; first must have value 0 */ + IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, + IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS, + IPA_RESOURCE_TYPE_DST_DPS_DMARS, +}; + +/* Resource groups used for an SoC having IPA v3.1 */ +enum ipa_rsrc_group_id { + /* Source resource group identifiers */ + IPA_RSRC_GROUP_SRC_UL = 0, + IPA_RSRC_GROUP_SRC_DL, + IPA_RSRC_GROUP_SRC_DIAG, + IPA_RSRC_GROUP_SRC_DMA, + IPA_RSRC_GROUP_SRC_UNUSED, + IPA_RSRC_GROUP_SRC_UC_RX_Q, + IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ + + /* Destination resource group identifiers */ + IPA_RSRC_GROUP_DST_UL = 0, + IPA_RSRC_GROUP_DST_DL, + IPA_RSRC_GROUP_DST_DIAG_DPL, + IPA_RSRC_GROUP_DST_DMA, + IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL, + IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE, + IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ +}; + +/* QSB configuration data for an SoC having IPA v3.1 */ +static const struct ipa_qsb_data ipa_qsb_data[] = { + [IPA_QSB_MASTER_DDR] = { + .max_writes = 8, + .max_reads = 8, + }, + [IPA_QSB_MASTER_PCIE] = { + .max_writes = 2, + .max_reads = 8, + }, +}; + +/* Endpoint data for an SoC having IPA v3.1 */ +static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { + [IPA_ENDPOINT_AP_COMMAND_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 6, + .endpoint_id = 22, + .toward_ipa = true, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 18, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL, + .dma_mode = true, + .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, + .tx = { + .seq_type = IPA_SEQ_DMA, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_LAN_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 7, + .endpoint_id = 15, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 8, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL, + .aggregation = true, + .status_enable = true, + .rx = { + .pad_align = ilog2(sizeof(u32)), + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_TX] = { + .ee_id = GSI_EE_AP, + .channel_id = 5, + .endpoint_id = 3, + .toward_ipa = true, + .channel = { + .tre_count = 512, + .event_count = 512, + .tlv_count = 16, + }, + .endpoint = { + .filter_support = true, + .config = { + .resource_group = IPA_RSRC_GROUP_SRC_UL, + .checksum = true, + .qmap = true, + .status_enable = true, + .tx = { + .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, + .status_endpoint = + IPA_ENDPOINT_MODEM_AP_RX, + }, + }, + }, + }, + [IPA_ENDPOINT_AP_MODEM_RX] = { + .ee_id = GSI_EE_AP, + .channel_id = 8, + .endpoint_id = 16, + .toward_ipa = false, + .channel = { + .tre_count = 256, + .event_count = 256, + .tlv_count = 8, + }, + .endpoint = { + .config = { + .resource_group = IPA_RSRC_GROUP_DST_DL, + .checksum = true, + .qmap = true, + .aggregation = true, + .rx = { + .aggr_close_eof = true, + }, + }, + }, + }, + [IPA_ENDPOINT_MODEM_LAN_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 4, + .endpoint_id = 9, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_TX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 0, + .endpoint_id = 5, + .toward_ipa = true, + .endpoint = { + .filter_support = true, + }, + }, + [IPA_ENDPOINT_MODEM_AP_RX] = { + .ee_id = GSI_EE_MODEM, + .channel_id = 5, + .endpoint_id = 18, + .toward_ipa = false, + }, +}; + +/* Source resource configuration data for an SoC having IPA v3.1 */ +static const struct ipa_resource ipa_resource_src[] = { + [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 3, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 3, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 1, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 1, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 2, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HDR_SECTORS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HDRI1_BUFFER] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 14, .max = 14, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 16, .max = 16, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 19, .max = 19, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 26, .max = 26, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 5, .max = 5, /* 3 downstream */ + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 5, .max = 5, /* 7 downstream */ + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HDRI2_BUFFERS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { + .limits[IPA_RSRC_GROUP_SRC_UL] = { + .min = 19, .max = 19, + }, + .limits[IPA_RSRC_GROUP_SRC_DL] = { + .min = 26, .max = 26, + }, + .limits[IPA_RSRC_GROUP_SRC_DIAG] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_DMA] = { + .min = 5, .max = 5, + }, + .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = { + .min = 8, .max = 8, + }, + }, +}; + +/* Destination resource configuration data for an SoC having IPA v3.1 */ +static const struct ipa_resource ipa_resource_dst[] = { + [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { + .limits[IPA_RSRC_GROUP_DST_UL] = { + .min = 3, .max = 3, /* 2 downstream */ + }, + .limits[IPA_RSRC_GROUP_DST_DL] = { + .min = 3, .max = 3, + }, + .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { + .min = 1, .max = 1, /* 0 downstream */ + }, + /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */ + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { + .min = 3, .max = 3, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { + .min = 3, .max = 3, + }, + }, + [IPA_RESOURCE_TYPE_DST_DATA_SECTOR_LISTS] = { + .limits[IPA_RSRC_GROUP_DST_UL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_DL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_DMA] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { + .min = 0, .max = 255, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_ENGINE] = { + .min = 0, .max = 255, + }, + }, + [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { + .limits[IPA_RSRC_GROUP_DST_UL] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_DL] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_DIAG_DPL] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_DMA] = { + .min = 1, .max = 1, + }, + .limits[IPA_RSRC_GROUP_DST_Q6ZIP_GENERAL] = { + .min = 1, .max = 1, + }, + }, +}; + +/* Resource configuration data for an SoC having IPA v3.1 */ +static const struct ipa_resource_data ipa_resource_data = { + .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, + .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, + .resource_src_count = ARRAY_SIZE(ipa_resource_src), + .resource_src = ipa_resource_src, + .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), + .resource_dst = ipa_resource_dst, +}; + +/* IPA-resident memory region data for an SoC having IPA v3.1 */ +static const struct ipa_mem ipa_mem_local_data[] = { + { + .id = IPA_MEM_UC_SHARED, + .offset = 0x0000, + .size = 0x0080, + .canary_count = 0, + }, + { + .id = IPA_MEM_UC_INFO, + .offset = 0x0080, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_V4_FILTER_HASHED, + .offset = 0x0288, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_FILTER, + .offset = 0x0308, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER_HASHED, + .offset = 0x0388, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_FILTER, + .offset = 0x0408, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE_HASHED, + .offset = 0x0488, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V4_ROUTE, + .offset = 0x0508, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE_HASHED, + .offset = 0x0588, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_V6_ROUTE, + .offset = 0x0608, + .size = 0x0078, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_HEADER, + .offset = 0x0688, + .size = 0x0140, + .canary_count = 2, + }, + { + .id = IPA_MEM_MODEM_PROC_CTX, + .offset = 0x07d0, + .size = 0x0200, + .canary_count = 2, + }, + { + .id = IPA_MEM_AP_PROC_CTX, + .offset = 0x09d0, + .size = 0x0200, + .canary_count = 0, + }, + { + .id = IPA_MEM_MODEM, + .offset = 0x0bd8, + .size = 0x1424, + .canary_count = 0, + }, + { + .id = IPA_MEM_END_MARKER, + .offset = 0x2000, + .size = 0, + .canary_count = 1, + }, +}; + +/* Memory configuration data for an SoC having IPA v3.1 */ +static const struct ipa_mem_data ipa_mem_data = { + .local_count = ARRAY_SIZE(ipa_mem_local_data), + .local = ipa_mem_local_data, + .imem_addr = 0x146bd000, + .imem_size = 0x00002000, + .smem_id = 497, + .smem_size = 0x00002000, +}; + +/* Interconnect bandwidths are in 1000 byte/second units */ +static const struct ipa_interconnect_data ipa_interconnect_data[] = { + { + .name = "memory", + .peak_bandwidth = 640000, /* 640 MBps */ + .average_bandwidth = 80000, /* 80 MBps */ + }, + { + .name = "imem", + .peak_bandwidth = 640000, /* 640 MBps */ + .average_bandwidth = 80000, /* 80 MBps */ + }, + /* Average bandwidth is unused for the next interconnect */ + { + .name = "config", + .peak_bandwidth = 80000, /* 80 MBps */ + .average_bandwidth = 0, /* unused */ + }, +}; + +/* Clock and interconnect configuration data for an SoC having IPA v3.1 */ +static const struct ipa_clock_data ipa_clock_data = { + .core_clock_rate = 16 * 1000 * 1000, /* Hz */ + .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), + .interconnect_data = ipa_interconnect_data, +}; + +/* Configuration data for an SoC having IPA v3.1 */ +const struct ipa_data ipa_data_v3_1 = { + .version = IPA_VERSION_3_1, + .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK, + .qsb_count = ARRAY_SIZE(ipa_qsb_data), + .qsb_data = ipa_qsb_data, + .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), + .endpoint_data = ipa_gsi_endpoint_data, + .resource_data = &ipa_resource_data, + .mem_data = &ipa_mem_data, + .clock_data = &ipa_clock_data, +}; diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h index 5c4c8d72d7d87..5bc244c8f94e7 100644 --- a/drivers/net/ipa/ipa_data.h +++ b/drivers/net/ipa/ipa_data.h @@ -300,6 +300,7 @@ struct ipa_data { const struct ipa_clock_data *clock_data; }; +extern const struct ipa_data ipa_data_v3_1; extern const struct ipa_data ipa_data_v3_5_1; extern const struct ipa_data ipa_data_v4_2; extern const struct ipa_data ipa_data_v4_5; diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 20a83c7f671f3..9810c61a03202 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -578,6 +578,10 @@ static int ipa_firmware_load(struct device *dev) } static const struct of_device_id ipa_match[] = { + { + .compatible = "qcom,msm8998-ipa", + .data = &ipa_data_v3_1, + }, { .compatible = "qcom,sdm845-ipa", .data = &ipa_data_v3_5_1,