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[209.132.180.67]) by mx.google.com with ESMTP id n68-v6si10606803pga.662.2018.08.10.10.54.05; Fri, 10 Aug 2018 10:54:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AOUTMHrT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729179AbeHJUYz (ORCPT + 31 others); Fri, 10 Aug 2018 16:24:55 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:39697 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728438AbeHJUYz (ORCPT ); Fri, 10 Aug 2018 16:24:55 -0400 Received: by mail-pl0-f67.google.com with SMTP id w14-v6so4341053plp.6 for ; Fri, 10 Aug 2018 10:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AqR/PqYzzBuT/vbk6GCgvnwim/3ASCroxnBmM/gm6rY=; b=AOUTMHrTasJZzVbuTgY9eg1zHstYwmxsU8aQ8ty4UDHLUtHGNvlvKELKFt7SCk6+Or 0ETnZdlh+E0Nc1B7TxWzUEkS1SwT5tQ8JYgbGUeBtKn5LImLSosJ6BFc5rh+OLAaK7ZU 6bKiBto9VP1HKU1O/G3rVvQPll1dPMHJ4ZEak= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AqR/PqYzzBuT/vbk6GCgvnwim/3ASCroxnBmM/gm6rY=; b=Tbv8rP6zukW9u5aNwwfn7l6EczcGZsZjfiNeOE7yZdM4X5cQziC+/Yt6yK9iQEO0st aze2tzWc5GxTTHj0VaYMkpqWoV21gOZNjUfFw98gPZQky8y9Em/NTy+CQcieN3B3y6qg FvxNB/dN3UxdyJd6PMQpo1tIAy7NH/b1rkwWmLRK5h8/SUDK0miPESCccm15rFdxNOZP 5jvdLU1RpMUPnOT+mX+aR719XG6guw6Cmg0FdvbOFjbxCovk9kzMMrfjhTl/1XE/jbsT coha50tqSWT7fU/O+/wHk9PwPZwf8PSOpvRd3S5qZuqI0P07SUDr09F07tkxlZSXIE4p qOZQ== X-Gm-Message-State: AOUpUlGJbYGVX9K6qG1eCmbgZlK8RG4YgPENsGVtvet3FmC8JpJSh6Au mUT77CpCArhD4ykMINBbqFJ+ X-Received: by 2002:a17:902:4381:: with SMTP id j1-v6mr7059782pld.104.1533923643153; Fri, 10 Aug 2018 10:54:03 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:6391:e983:9562:f5f7:1a60:4363]) by smtp.gmail.com with ESMTPSA id l127-v6sm16981262pfc.55.2018.08.10.10.53.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Aug 2018 10:54:02 -0700 (PDT) From: Manivannan Sadhasivam To: xuwei5@hisilicon.com, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kucheria@linaro.org, guodong.xu@linaro.org, Manivannan Sadhasivam Subject: [PATCH 1/4] dt-bindings: arm: hisilicon: Add binding for Hi3670 SoC Date: Fri, 10 Aug 2018 23:23:36 +0530 Message-Id: <20180810175339.25421-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180810175339.25421-1-manivannan.sadhasivam@linaro.org> References: <20180810175339.25421-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree binding for Hi3670 SoC. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 199cd36fe1ba..14f54f569c63 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -8,6 +8,10 @@ HiKey960 Board Required root node properties: - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; +Hi3670 SoC +Required root node properties: + - compatible = "hisilicon,hi3670"; + Hi3798cv200 SoC Required root node properties: - compatible = "hisilicon,hi3798cv200"; From patchwork Fri Aug 10 17:53:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143957 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp237775ljj; Fri, 10 Aug 2018 10:54:10 -0700 (PDT) X-Google-Smtp-Source: AA+uWPw3xXRc6oUFVDJHRBCrHOzEGaqfDLvCeNzqmW3enMqVlgAh9IHZmzSbuGEfWcslysnGVBT0 X-Received: by 2002:a17:902:1101:: with SMTP id d1-v6mr6927925pla.131.1533923650588; Fri, 10 Aug 2018 10:54:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533923650; cv=none; d=google.com; s=arc-20160816; b=GqhbRAoEloU42qBvRig69/81ON4meQBiY1wraLK0GYOB/iPL2g/qbsYxmMLghOmeaF aJ4fXLVBGItJeggR/Jvyaay/DsQfHYNv3oq2iB8U9fJzQQD31Eb71Bq1VMLH6EKLDRV8 Fa7jnppYMJwa4XMdugNK8Tq2UDeDjk8UKPYnDrH34RgnoJJbZzmijqfYlXvxfUdxYYRc Lvn6I1tJXGsMFBEVFUkqEq7jtlLEw34fljhB2t4UrEOGP0ppcU4CNGlh3fT+FPD+adje Ho4DRIIJ5M0knXWu0paQtXV3pOT1tNM1H2lNgs0Rblwvwmi0743efO/RyGpxgDFpyM4c ERLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=8L70xoQazhZ+vmqb3tr43erEpnJ9J2hYHapvvy6sfeA=; b=DmMvZgKaiyZ0gbsHzqh6gshRs2jfAvbJFFFs+nfqotKPb2PCiDinA7bPs6k8PJEwjC QZNVI+dE1xbRjnBwlmM24oddRDB1P3UtYC9R4JsH79MBfdXOJok2WB9dwi4ovItsdUYd /fH3o97FRsnXvOPIyQ/H31JsDP7sYo6SWo7BOCgLXyYkxoI0a+qAlnTQQ0SHnH7Gh9N8 FPjcPK3yZAgKzkZOKTqs6eGuLfm37caw4vdHuUTc7T2m3ahIvWGAnTLAMsCNtuROjs3o tbiMwDCnVBw0/OBaE5aF3ce5I3TVp4uYQVo8z/9XNKODEyJW9rcoYsFw+YARD4KdkRrc gRQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EHQ4kXdq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This SoC has Octal core BigLittle CPUs in two clusters(4 * A53 & 4 * A73). Only UART6 has been added for console support which is pre configured by the bootloader. A fixed clock is sourcing the UART6 which will get replaced by the clock driver when available. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 162 ++++++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hi3670.dtsi -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi new file mode 100644 index 000000000000..c90e6f6a34ec --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hisilicon Hi3670 SoC + * + * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2018, Linaro Ltd. + */ + +#include + +/ { + compatible = "hisilicon,hi3670"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a73", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@e82b0000 { + compatible = "arm,gic-400"; + reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ + <0x0 0xe82b2000 0 0x2000>, /* GICC */ + <0x0 0xe82b4000 0 0x2000>, /* GICH */ + <0x0 0xe82b6000 0 0x2000>; /* GICV */ + #interrupt-cells = <3>; + #address-cells = <0>; + interrupts = ; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <1920000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart6_clk: clk_19_2M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + uart6: serial@fff32000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfff32000 0x0 0x1000>; + interrupts = ; + clocks = <&uart6_clk &uart6_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; From patchwork Fri Aug 10 17:53:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143958 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp237848ljj; Fri, 10 Aug 2018 10:54:14 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxyJ+CblwUjN/F5MigOL0mD1qwAvlqO/0pWJoGZ3LQ1yxDEucJr6ABh8EaZXWJ89/uS/qg1 X-Received: by 2002:a17:902:2e83:: with SMTP id r3-v6mr7077132plb.80.1533923654798; Fri, 10 Aug 2018 10:54:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533923654; cv=none; d=google.com; s=arc-20160816; b=Rt21Mbf37sBTMXmlrTtn8GOrpEPBD4PwiadfF/D5ldOo2tlgVa/9wKaq5r1tkMF9iw W0jQpHgdYn4ELNGju6i8CSO6dB/8WuOmBGbwA67KZldEXz7wG2HwSTsxg3oyA1+WVYfD V8Yl/xrQKc3kQTk+0ET3L+NLc8cP/Xgw0CjD5Jr5zpiELcpH4g/QDIQiF/gjhtOI89aj YoxorjN+DGRSSLMZeN8JfxrNbzBIK+5jIu7wSxaLMZ3pc5pqhBFV/qoauR0J06E/jtjM M9/1ZvDfyxF3SzVh+RuQataW1myAiAlqMyD8I/9HHsIdtL3cAEK1KKUEewmfTM2hILn+ FzJg== ARC-Message-Signature: i=1; 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Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 14f54f569c63..a97f643e7d1c 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -12,6 +12,10 @@ Hi3670 SoC Required root node properties: - compatible = "hisilicon,hi3670"; +HiKey970 Board +Required root node properties: + - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; + Hi3798cv200 SoC Required root node properties: - compatible = "hisilicon,hi3798cv200"; From patchwork Fri Aug 10 17:53:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143959 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp237945ljj; Fri, 10 Aug 2018 10:54:20 -0700 (PDT) X-Google-Smtp-Source: AA+uWPwwBR/05wHyNsYCBkAYiRKQf8Uivb1ZN3WgkyV/5/E05UMwSzD2Hez3/fXOrgIMfFSz9VCV X-Received: by 2002:a17:902:7147:: with SMTP id u7-v6mr6943359plm.154.1533923660325; Fri, 10 Aug 2018 10:54:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1533923660; cv=none; d=google.com; s=arc-20160816; b=YPDdz9QQCmUyL+QOCb2Eqd1MnvhpkXkXngNo7A81lFVXoKseLA74IftdYK2UtMj4Dc noktwfhATwid5Bw00vkv6Gv2jdmQ60vmQkoNBCUB5qkLEUz1ksVgapU+F/C7oMwELPMP +Ro0bH3EJzy3ZwBIY8M6UqWDhhx+wT1vSC6zOLgU/e0jPM0BT2tpz9+3scs7diEbYi88 AU4k93gDLx4E3VWRClCeGMBCfLmHWd7C3cdPRTHrk2nRP/TFJHhDAFcANgAbq27uUmX/ s/Yo9El4f8Jot2BGi6V9lyttHfhmjCFSjTPZj26+RWQKN/PWGUbQ1MC/BdxvV66Zf6q3 55Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=itUr3AAkHAduxXXhlrEFU6xz8Tobq25hv6Z136WoREo=; b=DzWh18DfTMTk5zMjUFPCOPgaosUQE5Bvmk32opRRhA/BWsI4h0dSpdAZPbn09j13s7 WtSP5aYfLgeyi4SyHm9AvcgJDTnyVNgj9F2tdwW1csM2Ml++C+KOKMIRc4DgLJF+ZQ6J QvsVzOPdx7glvfGI8oI4QI+bcyuR77dutaxDoh5y/FPHX/HGIKk2Iq5KHINCQ7sTusOD U83pkbmfOmiRdRnO2WmsJ7OOqEkaondrD+6UNLrp+LAaoFGIMZSIANUf/5jsPhFMKPwh L34mXYdMWuNWpUThyXkchWCXklgrUOt9D+UKoR9FG4Dq1AulY5Pv/iW2CKw9zCfg1U3v aRdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GJQ2v4gO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Only UART6 is enabled which is the default console required by the 96Boards Consumer Edition Specification. This patch has been tested on HiKey970 Board. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/hisilicon/Makefile | 1 + .../boot/dts/hisilicon/hi3670-hikey970.dts | 35 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts -- 2.17.1 diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile index 03d93f8ef8a9..f4d68caeba83 100644 --- a/arch/arm64/boot/dts/hisilicon/Makefile +++ b/arch/arm64/boot/dts/hisilicon/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb +dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts new file mode 100644 index 000000000000..4f5118642024 --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Hisilicon HiKey970 Development Board + * + * Copyright (C) 2016, Hisilicon Ltd. + * Copyright (C) 2018, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "hi3670.dtsi" + +/ { + model = "HiKey970"; + compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; + + aliases { + serial6 = &uart6; /* console UART */ + }; + + chosen { + stdout-path = "serial6:115200n8"; + }; + + memory@0 { + device_type = "memory"; + /* expect bootloader to fill in this region */ + reg = <0x0 0x0 0x0 0x0>; + }; +}; + +&uart6 { + status = "okay"; +};