From patchwork Sat Jun 26 05:02:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467413 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2135648jao; Fri, 25 Jun 2021 22:03:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+e55EkjYRpjYLHMQmqgbvKWIGi4qOexNJxYutM+1abO5VU4N7R5ydn145jItu3CAzakbc X-Received: by 2002:ac8:1008:: with SMTP id z8mr12250973qti.232.1624683806738; Fri, 25 Jun 2021 22:03:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624683806; cv=none; d=google.com; s=arc-20160816; b=NwzAI5gZdwHCDQbN0YY8cG3BOOpqJou4bD73QuHkiD/8k6QXal3HnE304bL+IH8vKg n0aDlcPMhq7mBPU3qKw3Kj3Slbglc14szHjsK/afxLdKL06bjmRywlXeJ/bFCA2yfGag LZGQ0RYFbHzuYTEL/MjJ532KGLtC744ktJ90gX60VQFY/rjruhVCaRcwCUJw/401qeG5 6Ab/wZy3NzP7Nc08m2paIO2JZm8Iao4uXWtZ75N2adhLq32LgRJ5UcztKmStOWkuCVgv Vm7yGUuUQlyW6QMheOC3ia+pJXo+cK8FjKziS3nzroaMTI+b38qr7TlhoUIdapya/ERE fbtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bbklp3w91AZnxV0DVY+ehnYj/Fm0IUkDRzdevgcjq84=; b=foAuiuGJhtOlOTvOgjRmsZWzzyTz0BqZ2frhu1JXyKW/414cPYRzvTzWFwRLWTMJMM Mh4NISj3hEDWzKP5dIA5FPC5y0IIGvuUGj+fbhFTnixezOUUtafTiOEEz6ucgM7NO9+I 16xnfP8jbYhCcw4cJVMAgWIigMQHqaOsgIoUWKOdCrEBT8qXCP4AWpIg81bWS3S1xjYe DA5ZngFXV8RUD9RFNvDNfVGr1MtVh81iNUHaMitd8bOU/N9Eg9UN9A4PTILqksUXpOn8 lkdpUEIZr697MTP2dL0b6aD3QtuWvlidREbSrf0SWvu5JBZm2VNKZxyqMIuFDL6ftjqP QVag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OohdtbFM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h22si5585431qtr.395.2021.06.25.22.03.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:03:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OohdtbFM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0TW-0006lV-8w for patch@linaro.org; Sat, 26 Jun 2021 01:03:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TH-0006kq-HL for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:11 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:45759) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TF-0008CU-TL for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:11 -0400 Received: by mail-pf1-x42a.google.com with SMTP id k6so9101200pfk.12 for ; Fri, 25 Jun 2021 22:03:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bbklp3w91AZnxV0DVY+ehnYj/Fm0IUkDRzdevgcjq84=; b=OohdtbFMvTiNxf2kloSKhqZFLh7gyP9T++6HSX+QMPHqdV+EyaAig7iYcFWn/47sFZ gymwhZM5k/1Mw0xLQOr6GpUq1HTzzWqlEy2vDuP/CSGQ+TmQGqqkKLLO7diu/VaoIXV3 eRXzwkVI6TmJxgU/v0ZuxVCGc+u/qt6lMXeDnzOAx/5855nCX6EURMXMyswU44MNXRmq /jdsa080N9RPDL2fwvdgbDqc4pepirMJyXvNX9Ytb6/VxOLP1qqKx3Lm3gLRZ6JZy7Hw 4oTf1YLyZoicYGdRn4Ci4xego4PUon0pLOtkAe9pz/wDH8j57gpcV3rfP+Ie71rD7X02 CESQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bbklp3w91AZnxV0DVY+ehnYj/Fm0IUkDRzdevgcjq84=; b=UgkyzKHMcVePMchc5tXUeFR2kU3/qQZrviNmdX+vhoi8nhEb9jwVKszYWckaz7rNwp DMHPo0z6QJqq1qnbId9Ps00oMimM1dGqCfTwvVLHqfvTa2UINVwac6U1593ivsWK2FYm oiSGgY9bNSZkIuvHucnimPuv9jshcJMR8Q/FiGzY0J9ZiLF84T6p96uxnBdbzOgwUAVe cIzDuiz9GgK7vf1gSTz6QjS3+ozLzPsSP9vy7iE5g+bAO3nAzH/qDL+nAR4lKC7HxjTy pWpTlt/kzPI1/IuH6WhX5Pbyjhri11pzmWXZ+noASviYkAFgB0pOW61DyI71iNoUnarY RCIg== X-Gm-Message-State: AOAM531TBjxA2ZnGP03dO0txCP2C58Vi9e2cbZTcbL1FRwH1hDvOCM9w kJKoN+BE3k3kzpqyB6H6kOjVhT66YPm2hw== X-Received: by 2002:a63:5a47:: with SMTP id k7mr12799222pgm.9.1624683788622; Fri, 25 Jun 2021 22:03:08 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/16] tcg/s390x: Rename from tcg/s390 Date: Fri, 25 Jun 2021 22:02:52 -0700 Message-Id: <20210626050307.2408505-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- meson.build | 2 -- tcg/{s390 => s390x}/tcg-target-con-set.h | 0 tcg/{s390 => s390x}/tcg-target-con-str.h | 0 tcg/{s390 => s390x}/tcg-target.h | 0 tcg/{s390 => s390x}/tcg-target.c.inc | 0 5 files changed, 2 deletions(-) rename tcg/{s390 => s390x}/tcg-target-con-set.h (100%) rename tcg/{s390 => s390x}/tcg-target-con-str.h (100%) rename tcg/{s390 => s390x}/tcg-target.h (100%) rename tcg/{s390 => s390x}/tcg-target.c.inc (100%) -- 2.25.1 diff --git a/meson.build b/meson.build index d8a92666fb..e3677a2fd9 100644 --- a/meson.build +++ b/meson.build @@ -258,8 +258,6 @@ if not get_option('tcg').disabled() tcg_arch = 'tci' elif config_host['ARCH'] == 'sparc64' tcg_arch = 'sparc' - elif config_host['ARCH'] == 's390x' - tcg_arch = 's390' elif config_host['ARCH'] in ['x86_64', 'x32'] tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h similarity index 100% rename from tcg/s390/tcg-target-con-set.h rename to tcg/s390x/tcg-target-con-set.h diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h similarity index 100% rename from tcg/s390/tcg-target-con-str.h rename to tcg/s390x/tcg-target-con-str.h diff --git a/tcg/s390/tcg-target.h b/tcg/s390x/tcg-target.h similarity index 100% rename from tcg/s390/tcg-target.h rename to tcg/s390x/tcg-target.h diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc similarity index 100% rename from tcg/s390/tcg-target.c.inc rename to tcg/s390x/tcg-target.c.inc From patchwork Sat Jun 26 05:02:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467416 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2135937jao; Fri, 25 Jun 2021 22:03:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxqGwHkazxBY5PBiYIO4MN8n7NMOS3fGioea6B0v+3EfytArsJk8g5dT3HNCurvRXsp+v0w X-Received: by 2002:a0c:f008:: with SMTP id z8mr3802557qvk.35.1624683837768; Fri, 25 Jun 2021 22:03:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624683837; cv=none; d=google.com; s=arc-20160816; b=sy/JOKfhmcJQw42Sg0VfbLRCaxCyjrT/k+sf5GxXfJcbup/KH88gJV8BCXG28YiCeg 0V+3h+qseW+CtDKnMxqKGt9+8Q/+9f06lOpOJut8foxPcQf89lJCy45IqcnIfYYhxJis gIwGZjujPN1yoys0AD6vxAXIBerLT97stVOyrgEkmgsI+bc88ID6873RHpivjmkMv+2m 3IHPgWfmCXlZm+wGtyPpdKEtbaFn32TcRMYUZ0CtDdjTrM7XMKBKx342ZwbGUGUJqXgn QMyvvUwbgUIEy71E1hK7Ca1VuUXkEvv7SRopmdjENqqrRUlaYvfRyRQpGLoVUmnZjfev LjFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8cr7+ukGyxymoEJaYC1BtudqoX6QSPAINnUfFXmM69I=; b=i57eletXstcw+vEGDDI4i0FIfov2CGVGfxUvr3QbyNNCM43v7jHL9SfX7YWd5Sw7+k 45eoPOmwlPNf+ZhMIAWqDUYJzCgxH7ymmVZwd5ml/rwpUFgB53IEOKq5JCr1yN5850GC 9h567BVMc75BxRJBOExg+69yqbsfEvKC6PezAQDsLw/JaJHBSGN+lsB8/rc+s4o9J1k0 aOVxqd/25Uh/SzLU6huzcbNk8OyaUeAXHxj7XmFaD4N8MUjJyf/CgQnG3B5Whw4CHCcP dQgGvnE38knXgJ3AS+Dskyn0kOSyHp/K94A9lsUsp0TLQg6G1EEFOciRHqmSjO1EtaM9 yqgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oa24eAsH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 10si5500827qtp.295.2021.06.25.22.03.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:03:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oa24eAsH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0U1-0006pl-6R for patch@linaro.org; Sat, 26 Jun 2021 01:03:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TJ-0006lj-QK for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:13 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:33647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TH-0008Cb-27 for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:13 -0400 Received: by mail-pg1-x535.google.com with SMTP id e20so10022185pgg.0 for ; Fri, 25 Jun 2021 22:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8cr7+ukGyxymoEJaYC1BtudqoX6QSPAINnUfFXmM69I=; b=oa24eAsHTUsCv1VgIyz1HQ1F9rg4//TuarzA0c0uI6nF/9XnubRk8KFqhP43F0r31a iRkyM4otfBVumeY4cQMN47Tr3zqGHn0WsSH5wFTctDQOhS13aX3C4gYCbWrgqFYIbw8W N0KzELPrezLG7HWy35sEn0FTFLXbpvaXZBs3Tg7DNwrF40m8xooZmS8blo3x9HpcR7Kw 4VDX0Kw8OYabzpllhimwTzimG/9HIauqKiZk/A9NX5JhG13AJ2adMU0KBR8zMf2gInbc VmpuWW2chD9WYVsH7V72W05c/thUIAezAqwrVCZKTYJDo1YKBysaegAWia/1Evwe/yKu PDDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8cr7+ukGyxymoEJaYC1BtudqoX6QSPAINnUfFXmM69I=; b=HxT4px6R4/VI0SLrmepepGUE7pdlAPdq8pH22zNpJ5Z2kqAGummjYB8rnZD2/DJpvD dCVFJE4lDkt+HYlEMmtwm02Wg3zwcekHHtj/c92OxWcS5cdVZaV94VCoXgTnoB4fg4FL 1qeN2STdjxK9cXQ/BOBPz3Bjc2KtCJUHQ01OaSBqzAye9JjlcGpDgbUcqzdNMgQJazM4 0R8NVt6SPvLRvFsa1fSF67GfITUS35QwFp080ohGpCoHS/NQsboEscCIfAzppOX5ZrFY Z1oo3QQCNF4RZqOx3k8BnzR6l2OuSdHv9POi9BgpCVt7McqR4vQmfGN1hCKekpZwnVJg L//Q== X-Gm-Message-State: AOAM532PBBD9BMoI02GJI6eDlJ9XvtZP6DxaqQoVb2Y8GcSj2GbvtgpX Eay9MiADXEf1926ijxueX3AMMhmBPAJ24w== X-Received: by 2002:a63:ec43:: with SMTP id r3mr12646947pgj.344.1624683789245; Fri, 25 Jun 2021 22:03:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/16] tcg/s390x: Change FACILITY representation Date: Fri, 25 Jun 2021 22:02:53 -0700 Message-Id: <20210626050307.2408505-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Change name to HAVE_FACILITY (david) --- tcg/s390x/tcg-target.h | 29 ++++++++------- tcg/s390x/tcg-target.c.inc | 74 +++++++++++++++++++------------------- 2 files changed, 52 insertions(+), 51 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index b04b72b7eb..e1209cfef3 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -55,16 +55,19 @@ typedef enum TCGReg { /* A list of relevant facilities used by this translator. Some of these are required for proper operation, and these are checked at startup. */ -#define FACILITY_ZARCH_ACTIVE (1ULL << (63 - 2)) -#define FACILITY_LONG_DISP (1ULL << (63 - 18)) -#define FACILITY_EXT_IMM (1ULL << (63 - 21)) -#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) -#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) +#define FACILITY_ZARCH_ACTIVE 2 +#define FACILITY_LONG_DISP 18 +#define FACILITY_EXT_IMM 21 +#define FACILITY_GEN_INST_EXT 34 +#define FACILITY_LOAD_ON_COND 45 #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND -#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53)) +#define FACILITY_LOAD_ON_COND2 53 -extern uint64_t s390_facilities; +extern uint64_t s390_facilities[1]; + +#define HAVE_FACILITY(X) \ + ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 @@ -85,8 +88,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT) -#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT) +#define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT) +#define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 @@ -99,7 +102,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 -#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT) +#define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div2_i64 1 @@ -120,11 +123,11 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM) +#define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM) #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 -#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT) -#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT) +#define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT) +#define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 5fe073f09a..76630aafc4 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -66,7 +66,7 @@ We don't need this when we have pc-relative loads with the general instructions extension facility. */ #define TCG_REG_TB TCG_REG_R12 -#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) +#define USE_REG_TB (!HAVE_FACILITY(GEN_INST_EXT)) #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 @@ -377,7 +377,7 @@ static void * const qemu_st_helpers[16] = { #endif static const tcg_insn_unit *tb_ret_addr; -uint64_t s390_facilities; +uint64_t s390_facilities[1]; static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -577,7 +577,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } /* Try all 48-bit insns that can load it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (sval == (int32_t)sval) { tcg_out_insn(s, RIL, LGFI, ret, sval); return; @@ -620,7 +620,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } /* Otherwise, stuff it in the constant pool. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { + if (HAVE_FACILITY(GEN_INST_EXT)) { tcg_out_insn(s, RIL, LGRL, ret, 0); new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); } else if (USE_REG_TB && !in_prologue) { @@ -706,7 +706,7 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, { intptr_t addr = (intptr_t)abs; - if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) { + if (HAVE_FACILITY(GEN_INST_EXT) && !(addr & 1)) { ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1; if (disp == (int32_t)disp) { if (type == TCG_TYPE_I32) { @@ -740,7 +740,7 @@ static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LGBR, dest, src); return; } @@ -760,7 +760,7 @@ static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LLGCR, dest, src); return; } @@ -780,7 +780,7 @@ static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LGHR, dest, src); return; } @@ -800,7 +800,7 @@ static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LLGHR, dest, src); return; } @@ -888,7 +888,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) tgen_ext32u(s, dest, dest); return; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if ((val & valid) == 0xff) { tgen_ext8u(s, TCG_TYPE_I64, dest, dest); return; @@ -909,7 +909,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { for (i = 0; i < 2; i++) { tcg_target_ulong mask = ~(0xffffffffull << i*32); if (((val | ~valid) & mask) == mask) { @@ -918,7 +918,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } } } - if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) { + if (HAVE_FACILITY(GEN_INST_EXT) && risbg_mask(val)) { tgen_andi_risbg(s, dest, dest, val); return; } @@ -967,7 +967,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { for (i = 0; i < 2; i++) { tcg_target_ulong mask = (0xffffffffull << i*32); if ((val & mask) != 0 && (val & ~mask) == 0) { @@ -992,7 +992,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit masks in each half. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); tgen_ori(s, type, dest, val & 0x00000000ffffffffull); tgen_ori(s, type, dest, val & 0xffffffff00000000ull); } @@ -1001,7 +1001,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) { /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if ((val & 0xffffffff00000000ull) == 0) { tcg_out_insn(s, RIL, XILF, dest, val); return; @@ -1025,7 +1025,7 @@ static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) tcg_tbrel_diff(s, NULL)); } else { /* Perform the xor by parts. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); if (val & 0xffffffff) { tcg_out_insn(s, RIL, XILF, dest, val); } @@ -1059,7 +1059,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, goto exit; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (type == TCG_TYPE_I32) { op = (is_unsigned ? RIL_CLFI : RIL_CFI); tcg_out_insn_RIL(s, op, r1, c2); @@ -1122,7 +1122,7 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, bool have_loc; /* With LOC2, we can always emit the minimum 3 insns. */ - if (s390_facilities & FACILITY_LOAD_ON_COND2) { + if (HAVE_FACILITY(LOAD_ON_COND2)) { /* Emit: d = 0, d = (cc ? 1 : d). */ cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); tcg_out_movi(s, TCG_TYPE_I64, dest, 0); @@ -1130,7 +1130,7 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, return; } - have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0; + have_loc = HAVE_FACILITY(LOAD_ON_COND); /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ restart: @@ -1216,7 +1216,7 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, TCGArg v3, int v3const) { int cc; - if (s390_facilities & FACILITY_LOAD_ON_COND) { + if (HAVE_FACILITY(LOAD_ON_COND)) { cc = tgen_cmp(s, type, c, c1, c2, c2const, false); if (v3const) { tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); @@ -1249,7 +1249,7 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, } else { tcg_out_mov(s, TCG_TYPE_I64, dest, a2); } - if (s390_facilities & FACILITY_LOAD_ON_COND) { + if (HAVE_FACILITY(LOAD_ON_COND)) { /* Emit: if (one bit found) dest = r0. */ tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2); } else { @@ -1325,7 +1325,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, { int cc; - if (s390_facilities & FACILITY_GEN_INST_EXT) { + if (HAVE_FACILITY(GEN_INST_EXT)) { bool is_unsigned = is_unsigned_cond(c); bool in_range; S390Opcode opc; @@ -1519,7 +1519,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, cross pages using the address of the last byte of the access. */ a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask); tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; - if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) { + if (HAVE_FACILITY(GEN_INST_EXT) && a_off == 0) { tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); } else { tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); @@ -1810,7 +1810,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, RI, AHI, a0, a2); break; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RIL, AFI, a0, a2); break; } @@ -2034,7 +2034,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, RI, AGHI, a0, a2); break; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (a2 == (int32_t)a2) { tcg_out_insn(s, RIL, AGFI, a0, a2); break; @@ -2259,8 +2259,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ if (args[0] & TCG_MO_ST_LD) { - tcg_out_insn(s, RR, BCR, - s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); + tcg_out_insn(s, RR, BCR, HAVE_FACILITY(FAST_BCR_SER) ? 14 : 15, 0); } break; @@ -2323,7 +2322,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS + return (HAVE_FACILITY(DISTINCT_OPS) ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ri)); @@ -2331,19 +2330,19 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT + return (HAVE_FACILITY(GEN_INST_EXT) ? C_O1_I2(r, 0, ri) : C_O1_I2(r, 0, rI)); case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT + return (HAVE_FACILITY(GEN_INST_EXT) ? C_O1_I2(r, 0, rJ) : C_O1_I2(r, 0, rI)); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS + return (HAVE_FACILITY(DISTINCT_OPS) ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ri)); @@ -2387,7 +2386,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return (s390_facilities & FACILITY_LOAD_ON_COND2 + return (HAVE_FACILITY(LOAD_ON_COND2) ? C_O1_I4(r, r, ri, rI, 0) : C_O1_I4(r, r, ri, r, 0)); @@ -2402,13 +2401,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM + return (HAVE_FACILITY(EXT_IMM) ? C_O2_I4(r, r, 0, 1, ri, r) : C_O2_I4(r, r, 0, 1, r, r)); case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM + return (HAVE_FACILITY(EXT_IMM) ? C_O2_I4(r, r, 0, 1, rA, r) : C_O2_I4(r, r, 0, 1, r, r)); @@ -2424,13 +2423,12 @@ static void query_s390_facilities(void) /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this is present on all 64-bit systems, but let's check for it anyway. */ if (hwcap & HWCAP_S390_STFLE) { - register int r0 __asm__("0"); - register void *r1 __asm__("1"); + register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; + register void *r1 __asm__("1") = s390_facilities; /* stfle 0(%r1) */ - r1 = &s390_facilities; asm volatile(".word 0xb2b0,0x1000" - : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); + : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); } } From patchwork Sat Jun 26 05:02:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467420 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2136911jao; Fri, 25 Jun 2021 22:05:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx8SXYQf25O12qzjj4RE6yUubIroHet3fp2UvLW5LGrXy1AxzuVY1j4EgWp75doK5EUQpJq X-Received: by 2002:a05:622a:84:: with SMTP id o4mr12650068qtw.360.1624683953598; Fri, 25 Jun 2021 22:05:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624683953; cv=none; d=google.com; s=arc-20160816; b=jV+XOrXLDS6nM7Wt8Djg+jSMNZgSgEc+d2sJsCSJdn2RqOde/UCeiz1RIwTX/dWXkj RzxihLx0OUM6Jjl6koP1Xk+sJ0vlE+s3uOOSTVwonoBeAeLusPcC4rcBbDkKzTB584Mf xa6t2K33M6zggxGiQx6jdaGXmJG3ldBwEeYPT8a6PCj7TajAZvCRQkLASVaRMKhT7h9h W5zjSMssYUSClqOoBTHWce6TdZyMwqxrB7yOgHhz6JvNAAs8Ven6f9H6fam2NtS5p+H7 GKkMMTAVIxShd3Grqx313AnXslUsu0Q9A1M0UpQQJP2uMl7rvUopUea9IkbCoqa7bFN4 F83w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=QOIjP++pUZAecpRcUAi86x58Btt1FbABLnvHLDjfasY=; b=Ph0HMBdmpMT+Hdza6iNv2zBNh8y+dTL5eewhIbCmJ0Zx2mm2i2kSjXiaje+t6G2cqz tLgfU+yAIywVMAFW9m4Hff0o/ITNNukiJvrjWfK3RO894iPQwIuJUrouYra1egTabPVD EPuBZ/rZjsireyFFepEA/uF8M2t1LQCt6B+9fuQ6KsZsqtWoSlA047jMNH19eJ1F1QSv /foewkeTSveTkIMO1JHjg6AjxySHTu0PCVrZ0362xf8wTvXU/JGiN9hSkOAhsYCSvj2j x7XWgPG74dX7LVIEqROAgx0c0MXgDps//jMvybVOZFzvExzL/EkT0izkuvOQQ6J3Jg+p laKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jp0vbH6t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 22si2138779qtp.131.2021.06.25.22.05.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:05:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jp0vbH6t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0Vt-0003rz-2K for patch@linaro.org; Sat, 26 Jun 2021 01:05:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TJ-0006lE-59 for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:13 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:34425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TH-0008Ci-8W for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:12 -0400 Received: by mail-pf1-x432.google.com with SMTP id i6so9151856pfq.1 for ; Fri, 25 Jun 2021 22:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QOIjP++pUZAecpRcUAi86x58Btt1FbABLnvHLDjfasY=; b=jp0vbH6tPVp3cRq2mC41TTHIRI0lHDH0Rrp2S8dkDO16hhTZxZbR1OUAiobH0ukofC PZ7Jcuw/t8WelgXZIvzQcc0dutO9Jhmq2ZTt5LCLtWBCe90Or2RXsHj+BoCHFKPqAoYy V2vaCevlK1fOjtbJQQPNrHPIONBqegLFdWiKTLc0r2ujhFJf+wrg5MsqPJGE808eEBeh 9f1+2LKcJZmGBeJEPHCotIY9y4a1vEPUy0s3JXxywPAT+WPxKJDR92NzRUFvGLN0chlS suyjHHqGYJMc0bfBJnkF8JFjBIskVRTvBnULyTs7boiizjebD3bazL7kPm1vvMdHGAST s/IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QOIjP++pUZAecpRcUAi86x58Btt1FbABLnvHLDjfasY=; b=BxXxsOOET9iWSslGN+tWISdGj5Gdiy9ejjlHhdyq8y7nfwqcI0iTroBWzFEGkXuQje TfwUyk5iM89AO5j0KzK1q/w6MHTQS3urSbV5nfV1Obkq31czzx0SnNpecwRW5gEJGN3p LanCYwDo16oBxYzRkslMHsFEfN/WWvtSlQfM7RKi7PsTO6yw8RGv/ELNLfbHG+flp5lU 7KgD5JNfoo2jdxXLVVbnGkJHk3vycSsNQpSeIhaLv3Xy4f0+xV79aJ8xFhd7d1Ix3lVW y++7KArAjza6cXXZH2i7KuYL67kCeVUD8YBtkkRGHvcvcd+Fzhs1ZAntTPV5cYfc87OF Mc7g== X-Gm-Message-State: AOAM531i9DmYuy0L1q19bzX8qzaOWQaB+K23BWzltO/fB6ixx8IAFhii hoa3Bb+m+nK8u7Npz1C01VLG7wY1qxuXvw== X-Received: by 2002:aa7:8509:0:b029:2e5:8cfe:bc17 with SMTP id v9-20020aa785090000b02902e58cfebc17mr13914652pfn.2.1624683789926; Fri, 25 Jun 2021 22:03:09 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Date: Fri, 25 Jun 2021 22:02:54 -0700 Message-Id: <20210626050307.2408505-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" They are rightly values in the same enumeration. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e1209cfef3..eb17657994 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -32,22 +32,13 @@ #define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB) typedef enum TCGReg { - TCG_REG_R0 = 0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_R15 + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, + TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, + TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, + TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + + TCG_AREG0 = TCG_REG_R10, + TCG_REG_CALL_STACK = TCG_REG_R15 } TCGReg; #define TCG_TARGET_NB_REGS 16 @@ -139,7 +130,6 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_HAS_mulsh_i64 0 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_R15 #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 @@ -148,10 +138,6 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) -enum { - TCG_AREG0 = TCG_REG_R10, -}; - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) { From patchwork Sat Jun 26 05:02:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467423 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2137722jao; Fri, 25 Jun 2021 22:07:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxd8gOYw8DS4OUj+BGNfLT3QHlgGYlJW1yhmmopZ8EM+acd27DcNyIaLVOUHjDy8Nk2ym58 X-Received: by 2002:ad4:5143:: with SMTP id g3mr8044238qvq.0.1624684047454; Fri, 25 Jun 2021 22:07:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684047; cv=none; d=google.com; s=arc-20160816; b=l/e1Mr8v7pPpF6GhZ+SGqoVHfLcVSKvzmyH2r3ci7L46k6eSm3wW7mce8FvQ9UOem1 jDdVjI/UzSjNTwPgkO7a6nYe3rAm6JzHVftBnxsb1hdG29P76AQoa3/2faZ2CDhgn17j YnsAIyrk5Klg1MVM3yCrMojeqjYIItBJuIf77GRlQQtoofnGHnbZKTeC4G47j3tQKeHy iWKXZ69nCKpK5UEs1JR1khsp4Xv5xOQ6SXSTHQwiDNyKBpm8+RnuY+Q0vwAicq6mOfQz xrPhfO+QKZjLgjsdzs6P9q2Mjw2Vy2LUk9xl011nA5ikrW2bceyfQjCfHKibUDfEM8El m0xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HI71YspAl1Jx0wr1OoLasphGq250eOZ/+r/m038xuek=; b=XBlHOFTcHGd0zzcCnWg87YncncSnUG5gQEFpGqBot83XlrDJ4dYO8beyFcLQed26DA xwA2JbVR7QT4rutwyM1aTJaprGGoHgW6qEqvOlGpvEzRqeZiN1HbisLix1/fMrP0NEmQ fi41qey9RhpTaH44N0Yyo21QlPHj59ATPh18XfBZjg49Ja42ZwRsCJ132en7nP1S5cR8 GhLbMGc03aexuo2PNmvvEzGwVGK07dD3vipdqTR8dA3PMlnO0pEGJYNkf9/3txBOrmDq tTLkRPfbF/ySzEXPuxpVc/Zd2qN0U7Y3W7FQ2EpoSRO3SrOQdnPIXodd0yICJAg9zUcb DuMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HkDkrUfm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b1si1382654qtb.392.2021.06.25.22.07.27 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:07:27 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HkDkrUfm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0XO-0001TJ-S7 for patch@linaro.org; Sat, 26 Jun 2021 01:07:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TM-0006rk-6Z for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:16 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:39683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TH-0008DQ-Qy for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:15 -0400 Received: by mail-pf1-x431.google.com with SMTP id g192so9127602pfb.6 for ; Fri, 25 Jun 2021 22:03:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HI71YspAl1Jx0wr1OoLasphGq250eOZ/+r/m038xuek=; b=HkDkrUfmojETXIQhaa8EoHMYfPopXit+imU5XsTLEJMeTcThpJi3tJthGQXGeIvbVc 273XuvFcCE6FFH5w2+zLJ6kmqi4mqfovXFxmQs3kKtwrAys5eFGA4arfu3L5Jd68rAxO 0sLDdPX2A3qPsPPKhh9XwEZBQ9cN45KSfDwMz2VvA6R+vAdsGLqacPt9XLDUXiaqAuoD RwKs4QKmaAaN1ToKIu4BwIWs9neDDrn/wR5gKYHv+hi2A8yLFIHF/2BgSWzMtY/YfoTf PA8wFtmn0O6NrUwIUCuw2z6cADmL1vxOUOk1boG15v427JQZ07lMkct63vLCA+62UncE KYUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HI71YspAl1Jx0wr1OoLasphGq250eOZ/+r/m038xuek=; b=shMvP09rfVzcfLWopEX2ZazfNjPJl39Te52G7G3Fon3DSaMI5Y7Q8VfLrFj6yqNRuW inq/gSggLetPF8rbnSCqeaI+tH/oD8nQiaU9eWqia+U8yztVh11gKScczKyPWsW25RB1 u+SawLfuZidXn0StGaZ26rOb//zcYU+fBDzmxK4OUN2s2/tstfJsLR67wmyLwVYEVJoF IBVz557XmdJPf1AAZRZ+GsVJvZbjC25/dEpHfxwIjbKwhg/bVWpaAE6Rujs6Ykx/uxeT bCsDFrZHqYa1BKxt3mgu0BWI3QrXiYwk6bRB125PK5QM3ls4UFKtaliEIr9e006JjAd8 n8/w== X-Gm-Message-State: AOAM531goBDvUXbrlpWKmNtAkKEXpWgnFo+NmXpLWtwuAlPMBY8DO1J2 IGC3r7VTB0ZW9ygBfEhnqydkZlAiCfrywA== X-Received: by 2002:a65:4244:: with SMTP id d4mr12727479pgq.83.1624683790470; Fri, 25 Jun 2021 22:03:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/16] tcg/s390x: Add host vector framework Date: Fri, 25 Jun 2021 22:02:55 -0700 Message-Id: <20210626050307.2408505-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 4 + tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.h | 35 ++++++++- tcg/s390x/tcg-target.opc.h | 12 +++ tcg/s390x/tcg-target.c.inc | 137 ++++++++++++++++++++++++++++++++- 5 files changed, 184 insertions(+), 5 deletions(-) create mode 100644 tcg/s390x/tcg-target.opc.h -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 31985e4903..ce9432cfe3 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -13,13 +13,17 @@ C_O0_I1(r) C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) +C_O0_I2(v, r) C_O1_I1(r, L) C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) +C_O1_I2(v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(b, a, 0, r) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 892d8f8c06..8bb0358ae5 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -10,6 +10,7 @@ */ REGS('r', ALL_GENERAL_REGS) REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) +REGS('v', ALL_VECTOR_REGS) /* * A (single) even/odd pair for division. * TODO: Add something to the register allocator to allow diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index eb17657994..db54266da0 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -37,11 +37,20 @@ typedef enum TCGReg { TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, + TCG_AREG0 = TCG_REG_R10, TCG_REG_CALL_STACK = TCG_REG_R15 } TCGReg; -#define TCG_TARGET_NB_REGS 16 +#define TCG_TARGET_NB_REGS 64 /* A list of relevant facilities used by this translator. Some of these are required for proper operation, and these are checked at startup. */ @@ -54,8 +63,9 @@ typedef enum TCGReg { #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND #define FACILITY_LOAD_ON_COND2 53 +#define FACILITY_VECTOR 129 -extern uint64_t s390_facilities[1]; +extern uint64_t s390_facilities[3]; #define HAVE_FACILITY(X) \ ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) @@ -129,6 +139,27 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) +#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h new file mode 100644 index 0000000000..67afc82a93 --- /dev/null +++ b/tcg/s390x/tcg-target.opc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 76630aafc4..18233c628d 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -43,6 +43,8 @@ #define TCG_CT_CONST_ZERO 0x800 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) +#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) + /* * For softmmu, we need to avoid conflicts with the first 3 * argument registers to perform the tlb lookup, and to call @@ -268,8 +270,13 @@ typedef enum S390Opcode { #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", - "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15" + "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", + "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", + "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", + "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", }; #endif @@ -295,6 +302,32 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R4, TCG_REG_R3, TCG_REG_R2, + + /* V8-V15 are call saved, and omitted. */ + TCG_REG_V0, + TCG_REG_V1, + TCG_REG_V2, + TCG_REG_V3, + TCG_REG_V4, + TCG_REG_V5, + TCG_REG_V6, + TCG_REG_V7, + TCG_REG_V16, + TCG_REG_V17, + TCG_REG_V18, + TCG_REG_V19, + TCG_REG_V20, + TCG_REG_V21, + TCG_REG_V22, + TCG_REG_V23, + TCG_REG_V24, + TCG_REG_V25, + TCG_REG_V26, + TCG_REG_V27, + TCG_REG_V28, + TCG_REG_V29, + TCG_REG_V30, + TCG_REG_V31, }; static const int tcg_target_call_iarg_regs[] = { @@ -377,7 +410,7 @@ static void * const qemu_st_helpers[16] = { #endif static const tcg_insn_unit *tb_ret_addr; -uint64_t s390_facilities[1]; +uint64_t s390_facilities[3]; static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -2271,6 +2304,42 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src) +{ + g_assert_not_reached(); +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg base, intptr_t offset) +{ + g_assert_not_reached(); +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t val) +{ + g_assert_not_reached(); +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + g_assert_not_reached(); +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + return 0; +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + g_assert_not_reached(); +} + static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { @@ -2411,11 +2480,34 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) ? C_O2_I4(r, r, 0, 1, rA, r) : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_ld_vec: + case INDEX_op_dupm_vec: + return C_O1_I1(v, r); + case INDEX_op_dup_vec: + return C_O1_I1(v, vr); + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_cmp_vec: + return C_O1_I2(v, v, v); + default: g_assert_not_reached(); } } +/* + * Mainline glibc added HWCAP_S390_VX before it was kernel abi. + * Some distros have fixed this up locally, others have not. + */ +#ifndef HWCAP_S390_VXRS +#define HWCAP_S390_VXRS 2048 +#endif + static void query_s390_facilities(void) { unsigned long hwcap = qemu_getauxval(AT_HWCAP); @@ -2430,6 +2522,16 @@ static void query_s390_facilities(void) asm volatile(".word 0xb2b0,0x1000" : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); } + + /* + * Use of vector registers requires os support beyond the facility bit. + * If the kernel does not advertise support, disable the facility bits. + * There is nothing else we currently care about in the 3rd word, so + * disable VECTOR with one store. + */ + if (1 || !(hwcap & HWCAP_S390_VXRS)) { + s390_facilities[2] = 0; + } } static void tcg_target_init(TCGContext *s) @@ -2438,6 +2540,10 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; + if (HAVE_FACILITY(VECTOR)) { + tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; + } tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); @@ -2452,6 +2558,31 @@ static void tcg_target_init(TCGContext *s) /* The return register can be considered call-clobbered. */ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); + s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* XXX many insns can't be used with R0, so we better avoid it for now */ From patchwork Sat Jun 26 05:02:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467419 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2136616jao; Fri, 25 Jun 2021 22:05:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwfUq48IdtT8Pf4DEN6C1DywsuA3FiHpk3Xuml0p5xD2KrzF3TQsfIcSh8D8DHZZerZV7yX X-Received: by 2002:a37:64c1:: with SMTP id y184mr12056806qkb.154.1624683916607; Fri, 25 Jun 2021 22:05:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624683916; cv=none; d=google.com; s=arc-20160816; b=hz0RJCArETr6zC+UBV+pQGvyIybhY9t2cIwTFYf3IbetV/wQBZUGrAaXP3zLJH02kQ J+W9AUTxQOnewxYwSN9+CPZNmNuJkptK9N2I7bI1BWLnYgZoIJYs5kwGKDthaRDjq3Hu r4nN0Q3Fteq7OgpFZUA52aZcB/V+mXe8/GVKBOPHHzjjFAzj8nS4ek/MBd2H3eh003ii K54SkEs/BCBKWwMGXueE/eGKrLPpUxnG7Q4E8ZOG/hLCnEBKOXst1dC2SsmWEmWansB1 OMqO4wj+LnGG6DjaGMn/q/Pn3r3euUCRRegou/kk+FQN0/qzvYbLec05rMXavex6rkQn kqHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5RsDo5LOvqHfddwDWLUBaPmdje4xPxYC9ARF5xmGDlE=; b=PlCzdFzAQbl5jCfghmsqoDOQoUiuyGTtJ616dQahGygq4xGl0VI9dgACpTKkcAaym8 Qlbopnw/vGpU5GGzPoWcoqrWC+p7CUAdBaMAZGTsE9b+yXyETRfXEA0Q8huFL3P6hLcP MZPKJNMupuS4w3VDxu09agmkl4pO7Pnzkzo1CCZUynlpbVIp7teBBPIRqh5FZwG/hcIO gkuIr0ocYIL//H5qy74Ptbu0AoyYUNz67UR0U/wkG/m25OsD7JTzBV1RaxzSFwCnVZZ1 BDzHDvDdpz7Nxu/r5pFSnTiD/x0Hbi0i7B2tpcO70j7fZSkRaFyWcx76R+PDkiKF19Xg OGDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bNMoAUkg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v11si3063930qtc.147.2021.06.25.22.05.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:05:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bNMoAUkg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0VI-0004GK-4H for patch@linaro.org; Sat, 26 Jun 2021 01:05:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45096) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TL-0006qV-Nl for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:15 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:33582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TI-0008E1-68 for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:15 -0400 Received: by mail-pf1-x42f.google.com with SMTP id s14so7866025pfg.0 for ; Fri, 25 Jun 2021 22:03:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5RsDo5LOvqHfddwDWLUBaPmdje4xPxYC9ARF5xmGDlE=; b=bNMoAUkgFs5oi9tfKZcsGVyTbdZnz5OZz3X/4Vuep7USfxmG++T3M++JVClyXtnm6Z 7X2ujjTxATisxb35PQz0h/VfqcHCEFLmftVpTu6gS/ss6F7djhGXJwNBwdvZkrW74ryX npNyHg+V/PbWj7GGp/ichpOvO4MuPXzp2mYj4QP6XduF4oOQnkhDW9XR54+Q6feYg7HD JS6PGu47ezlJQWo4Q2/TePWk5i+dai8LbTrG03GNPJBkMEQqBEeJ/81qBcDRYUlpfvXP zpEB7OP0sanKtLy8Scr2iOestN84VNbm9J/lLBlvluKoC4T1qHRwUqDRrGqa+o7xR2nA mq5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5RsDo5LOvqHfddwDWLUBaPmdje4xPxYC9ARF5xmGDlE=; b=oin7YnBh0Fnu5ecZfqPtAxOIcyKjKHzBsxHwUuQgNDoZkR1cDYJE3onsI/HuuOE4dO bagWVl5Ael17ppUBwPG/rxZbjTN5tF1KX6EgzfVEH4/kGnrmYnCa0mieVdTikfLsMXla 2mI0XOqNnMBblOxf8tBcgWjbzE0qUzrb5w+LY5CcVxnD66QgM+923YT+PXlPb1OHPcwA TOUT2ISe41mBukoAHG6xHKUCChwebwfX2OT5JqSYAA/Uj9daAmrIHg6UY6sy1CQyrphB TuTWmPOEAOPYOKo/jobWMkjmSwndzijvNGHtnzbCpfEL3ZNawamr2RrZKellVxlThjgJ qlTQ== X-Gm-Message-State: AOAM531Nr1q5qUWfTkKpffJ/y2cxpHXJFoOcGdGdtV0ug8hjfv+TkInU EVBfY4tCiFLSHQaTO7/7eAk3K/uRwztVng== X-Received: by 2002:a62:7a49:0:b029:302:c04b:36d1 with SMTP id v70-20020a627a490000b0290302c04b36d1mr13897942pfc.27.1624683790956; Fri, 25 Jun 2021 22:03:10 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types Date: Fri, 25 Jun 2021 22:02:56 -0700 Message-Id: <20210626050307.2408505-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 +++++++++++++++++++++++++++++++++---- 1 file changed, 110 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 18233c628d..b6ea129e14 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,6 +265,12 @@ typedef enum S390Opcode { RX_STC = 0x42, RX_STH = 0x40, + VRX_VL = 0xe706, + VRX_VLLEZ = 0xe704, + VRX_VST = 0xe70e, + VRX_VSTEF = 0xe70b, + VRX_VSTEG = 0xe70a, + NOP = 0x0707, } S390Opcode; @@ -529,6 +535,31 @@ static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, #define tcg_out_insn_RX tcg_out_insn_RS #define tcg_out_insn_RXY tcg_out_insn_RSY +static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) +{ + /* + * Shift bit 4 of each regno to its corresponding bit of RXB. + * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4 + * is the left-shift of the 4th operand. + */ + return ((v1 & 0x10) << (4 + 3)) + | ((v2 & 0x10) << (4 + 2)) + | ((v3 & 0x10) << (4 + 1)) + | ((v4 & 0x10) << (4 + 0)); +} + +static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, + TCGReg b2, TCGReg x2, intptr_t d2, int m3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(x2 <= TCG_REG_R15); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | x2); + tcg_out16(s, (b2 << 12) | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); +} + /* Emit an opcode with "type-checking" of the format. */ #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) @@ -705,25 +736,92 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, } } +static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, + TCGReg data, TCGReg base, TCGReg index, + tcg_target_long ofs, int m3) +{ + if (ofs < 0 || ofs >= 0x1000) { + if (ofs >= -0x80000 && ofs < 0x80000) { + tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); + base = TCG_TMP0; + index = TCG_REG_NONE; + ofs = 0; + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); + if (index != TCG_REG_NONE) { + tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); + } + index = TCG_TMP0; + ofs = 0; + } + } + tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); +} /* load data without address translation or endianness conversion */ -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) { - if (type == TCG_TYPE_I32) { - tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); + switch (type) { + case TCG_TYPE_I32: + if (likely(data < 16)) { + tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); + break; + } + tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); + break; + + case TCG_TYPE_I64: + if (likely(data < 16)) { + tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); + break; + + case TCG_TYPE_V128: + /* Hint quadword aligned. */ + tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); + break; + + default: + g_assert_not_reached(); } } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) { - if (type == TCG_TYPE_I32) { - tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); + switch (type) { + case TCG_TYPE_I32: + if (likely(data < 16)) { + tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); + } else { + tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); + } + break; + + case TCG_TYPE_I64: + if (likely(data < 16)) { + tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); + break; + + case TCG_TYPE_V128: + /* Hint quadword aligned. */ + tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); + break; + + default: + g_assert_not_reached(); } } From patchwork Sat Jun 26 05:02:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467415 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2135688jao; Fri, 25 Jun 2021 22:03:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAbMB1Q9FF4djktQe/s2T8O+8pG297c68V6HFtdCyz5plRcoCj44eWjFzwffwLd0H8UT/A X-Received: by 2002:a37:5cc6:: with SMTP id q189mr14975824qkb.305.1624683810465; Fri, 25 Jun 2021 22:03:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624683810; cv=none; d=google.com; s=arc-20160816; b=UE3rZcFpOC3WP1+yY1wjRCHz49G0h/mSA5EAWTXOZkkydiVC9fnpJJ3PscIdjEmlb1 r5T37Ni9NRQgg3uQBbX/vkh1H99P+x2BA5AV1R9WbkXWzfnlHZesupqCFAok0vZr2Dt2 KHMjALlaQzjul3jUrOU2u9VVKHUZS8v4vpk+3+2Cl+N7Of2g7bHbDmTxVX9nUWD+Q1Ah Dd8nXgiYdE59KfHjAQIVF0ql5lTH8Ody8XKkGjygsQq50vLjRLp8sa796MF5va0d+lPI xxGnyvkdIr/F8oO9QYew/RB1c8ItFEYi7Bf7cFTOl2SSqyP9YTreNGn9MsSJx102ceiI FZOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3nfkczzkS4RCP30J/oNDtjtKPmz4zWVXF5NhXJHdqeQ=; b=LvYQJk5Lirjo2giyX8jfBoUvEmkowritddEEY2kB3YPVD3Xubc81ZA2QT2vxw+opi4 pXSPo5Nj4ZF54XCjq/CXZmoGLYqpFdm8G7ZB+AfglM+WScOn+WRuuEQrtbOR02/sY2Vl AcRsHGB8QVhbm9JumJKqDdsTT7BuyyqguH9DSxS9dIXQjb03dElVZswaJ/NF2j/wQc5x vNUdgb6iEM93FjKRgrqHY9lvTRbCa6Ilol3OPOKRSgoobdvklKxYhv9O+YMQSSDDo1cw UIXbhbzXhcGds59ZWBlyksZbq/0hZf47+0X1NsXwuwtPhbcEcml+J6qCOb6QlvM27N4p 8J9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Txtc993j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u1si5533918qvf.125.2021.06.25.22.03.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:03:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Txtc993j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36342 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0TZ-0006tV-UY for patch@linaro.org; Sat, 26 Jun 2021 01:03:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45068) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TK-0006nS-KE for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:14 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:41700) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TI-0008F2-TL for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:14 -0400 Received: by mail-pg1-x533.google.com with SMTP id u190so9994373pgd.8 for ; Fri, 25 Jun 2021 22:03:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3nfkczzkS4RCP30J/oNDtjtKPmz4zWVXF5NhXJHdqeQ=; b=Txtc993j1Uhio4TA+HR/lpMNQAPg/orT+jvb/uTK8Zi8EUp1LMvNDk90y8U8HTv3yM H6pJRe/0Vzl60oJd/EY3zuTV7oGXanigmPIxK2jPbpHBobhxdfVuVvdvDJ32DaNM1kj3 gHuAhB0LAiTEmQZ2PmiUsmkOL9B1K5Iq0c3kjb8Khhq03mUW2/Hqu68Vl4QQfYpiidZV jnuQFyB2drD9etl7C8cl7osx9IHrelxOQoTV766ti5Hg9BkK1dKO0nAzAzK9Qa1nnCnH B+c2UMfomvgamEOj56+GXk3h7a0OS15BEymsJEIZRxoaGQIZZzT+QdQ+SbKuGahk+/id Qytw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3nfkczzkS4RCP30J/oNDtjtKPmz4zWVXF5NhXJHdqeQ=; b=gAF8Wf9nLoRfjVYCZFnvoSX0GKLLCRP9qSkT+RY54kyg9sH6L/6ORoyH+Ir9hVghBU qKhw/BRvBqX2W+/byfBMNBlcDybadyVFTHuqjL1B5HxwbJwR6119XW8ig9EdtCuq9MUp Rosk2MZaDfF6L2+E2GOD0r3PeXD3Zm8Kfk3WhqOJhB2d4oC6AiyCegUsRQtitPO+IEt5 U+BnVSiWe3njhvSBOfMtfE0azNm85SQImzx2z5cbrHlCO+XJS3DGVODJgc0uIAv4VTnx gSCnLQsIf5UJSkCbZ4bwYIXgHzOj5ek6AMQFo9ZPOcXydQJKKd8eUhQ6t+q2S3SsfuTV tgDQ== X-Gm-Message-State: AOAM53213zg7La94D5DrWFvCovgtAxIeTxfuz1PApU12EEcSJRm+ooKP do4D3uw2Y6X41FCuv9bhJymhDTHtfPgudQ== X-Received: by 2002:a63:f54f:: with SMTP id e15mr12918663pgk.64.1624683791485; Fri, 25 Jun 2021 22:03:11 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/16] tcg/s390x: Implement tcg_out_mov for vector types Date: Fri, 25 Jun 2021 22:02:57 -0700 Message-Id: <20210626050307.2408505-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 72 +++++++++++++++++++++++++++++++++++--- 1 file changed, 68 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b6ea129e14..c4e12a57f3 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,6 +265,11 @@ typedef enum S390Opcode { RX_STC = 0x42, RX_STH = 0x40, + VRRa_VLR = 0xe756, + + VRSb_VLVG = 0xe722, + VRSc_VLGV = 0xe721, + VRX_VL = 0xe706, VRX_VLLEZ = 0xe704, VRX_VST = 0xe70e, @@ -548,6 +553,39 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) | ((v4 & 0x10) << (4 + 0)); } +static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, int m3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); +} + +static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, + intptr_t d2, TCGReg b2, TCGReg r3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_debug_assert(r3 <= TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r3); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); +} + +static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, + intptr_t d2, TCGReg b2, TCGReg v3, int m4) +{ + tcg_debug_assert(r1 <= TCG_REG_R15); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 15)); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg b2, TCGReg x2, intptr_t d2, int m3) { @@ -581,12 +619,38 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) { - if (src != dst) { - if (type == TCG_TYPE_I32) { + if (src == dst) { + return true; + } + switch (type) { + case TCG_TYPE_I32: + if (likely(dst < 16 && src < 16)) { tcg_out_insn(s, RR, LR, dst, src); - } else { - tcg_out_insn(s, RRE, LGR, dst, src); + break; } + /* fallthru */ + + case TCG_TYPE_I64: + if (likely(dst < 16)) { + if (likely(src < 16)) { + tcg_out_insn(s, RRE, LGR, dst, src); + } else { + tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); + } + break; + } else if (src < 16) { + tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_out_insn(s, VRRa, VLR, dst, src, 0); + break; + + default: + g_assert_not_reached(); } return true; } From patchwork Sat Jun 26 05:02:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467417 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2136572jao; Fri, 25 Jun 2021 22:05:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxaqhSjaXNyAAgTX54gWBlKpNCAl/0xDsR5ZrlFS4ar78V4bLaHf7uOfZwO9k60Mc1zgQtS X-Received: by 2002:ae9:c219:: with SMTP id j25mr14740827qkg.313.1624683910849; Fri, 25 Jun 2021 22:05:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624683910; cv=none; d=google.com; s=arc-20160816; b=btteDggeMN9OHfmySGhQs0xWT51wmLfoWonw1V2PGRz/EjQ8ouOMJa4AYu5UjGZ5M7 mjqWcJC1ioY2I1Xyj5alIMdNQYevutxDACCitlSbQmKGRDgdfqg2DGo6rkMX0mVXdTFW lC2N6hOKpahV5zZ2a82hEc8Jv0WDXWMVC45ikLggypitEBEAQAgVVMLX5sX3EXCLu/la IW3sWr+x2xd+JpV2YlvEO0bNN3yDD60vXeZihtqBxtVBEfiWTJma706EAbSTcdaLpLr5 UOKlboa5eLv0fhtmjjoovvO1k6oqICUFeyBG3toHKaP4BxxkOQd1bcyOtPYHCWwr+YWt ATdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BbcFUradXh47LTNqrpbiX+7rM/MXo7sQwZti2q7+rTM=; b=yuJMdNt/ubSxeYI6S3Z44FlWQQuYIkjVFuAHjao4xMaJdIpfIrNkUaTsVTXP651suM B9AY8sL0p9ma7+ZcIVppgVL5m+YyiRFjRA3wa9MhzF7NSZkHYfV4rY5bQxfvcwlZUcJk 3+FObWLWkuuSx3mqLG8dZYxUOAuifPzd0SEvutaztuXVDyIhPwmfYn81H8UzaDe1gokV bY/4j6yIm8CC3tyiHNw3ksFB0uauxaLY3zABQ3en3PYUufnyQctwQHvO62zEJZtCjW22 6GzAWmORBsIyVvOM891QhUHtBFtcZyxpzh4oWpeZhUupI4FXVlJXiwdEWCjUrbJvoX8m onbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M+l7amu4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m8si6384303qkg.337.2021.06.25.22.05.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:05:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M+l7amu4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0VC-000408-BP for patch@linaro.org; Sat, 26 Jun 2021 01:05:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TM-0006ti-Tl for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:17 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:45968) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TJ-0008FQ-HO for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:16 -0400 Received: by mail-pj1-x1036.google.com with SMTP id z3-20020a17090a3983b029016bc232e40bso6744109pjb.4 for ; Fri, 25 Jun 2021 22:03:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BbcFUradXh47LTNqrpbiX+7rM/MXo7sQwZti2q7+rTM=; b=M+l7amu4/cG0Tv8Kzx2ZHm2wT2YPV4ImcqDuxPwKzOwGFVWBqNfFh0iT+DHrMXYBr0 UD3JkIiMyq1b62vWatFY69UYrxj9tKrCrHPttGUqQOMNsh5z4A5d6lpxWIkYGuTiSpWT iMXAyjbSd/s7zCx5BY4xOf3ghBQOpI92E2m98tk7/Adem3FyGV913XdUgj8Rs9WL9JV5 uhfeId/1fCcIUkCLIeJ7npFJONGYr3lgqEwu4d1BluvFNMeORc2egF8xDi0edw/YnUQY YXSRX9TNMm/ttk3ohZ7TpzaLGc7Nl1CD3YvdVDIZDKB4JZeYU2jF2qlLu4YPXFuoOLx/ 7KRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BbcFUradXh47LTNqrpbiX+7rM/MXo7sQwZti2q7+rTM=; b=p8TvGBEo+bJg9p52nEbAdoUoxIcw8KW9juCBJsYhTle9y4DplHjkYJowrn9SLooL8f gnvBU/xxDATgf8e6pbgqRveMGp+z0SmRWx7m0PcSumQ0oEJp87jsMP6YKYgQO4QE7uUZ ApU7KK9T1hsZI+gmStCkE4UeNJY7U1s4EZH/nKZsMiTQ5boKz6n1u2ZbM5SQcOGJ80z9 BtMwgA8ECAVx+81iPJ7zwROzEDHSEadDQ7c/+3MOO+Q9ccoPhLXb19vqt6CleMAbl43U tV0zjhau+q4Ak990goVqyjmgi3sbtgNTYisPYtn1X6K/AX92zObjFDd9yK3qbX8mK7xt +tNg== X-Gm-Message-State: AOAM533vKZJhT7HM/Car9Vka/z8/VtmirysaqJ5gJEmLCFDTvMuWEaYf gun/fmBA04WNXxkBU/6dzEeopUSPgLak5Q== X-Received: by 2002:a17:90a:4890:: with SMTP id b16mr24221113pjh.211.1624683792106; Fri, 25 Jun 2021 22:03:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/16] tcg/s390x: Implement tcg_out_dup*_vec Date: Fri, 25 Jun 2021 22:02:58 -0700 Message-Id: <20210626050307.2408505-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 ++++++++++++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c4e12a57f3..76216eb5bc 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,13 +265,20 @@ typedef enum S390Opcode { RX_STC = 0x42, RX_STH = 0x40, + VRIa_VGBM = 0xe744, + VRIa_VREPI = 0xe745, + VRIb_VGM = 0xe746, + VRIc_VREP = 0xe74d, + VRRa_VLR = 0xe756, + VRRf_VLVGP = 0xe762, VRSb_VLVG = 0xe722, VRSc_VLGV = 0xe721, VRX_VL = 0xe706, VRX_VLLEZ = 0xe704, + VRX_VLREP = 0xe705, VRX_VST = 0xe70e, VRX_VSTEF = 0xe70b, VRX_VSTEG = 0xe70a, @@ -553,6 +560,34 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) | ((v4 & 0x10) << (4 + 0)); } +static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, int m3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); +} + +static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, + TCGReg v1, uint8_t i2, uint8_t i3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4)); + tcg_out16(s, (i2 << 8) | (i3 & 0xff)); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); +} + +static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v3 & 15)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg v2, int m3) { @@ -562,6 +597,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); } +static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg r2, TCGReg r3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(r2 <= TCG_REG_R15); + tcg_debug_assert(r3 <= TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r2); + tcg_out16(s, r3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); +} + static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, intptr_t d2, TCGReg b2, TCGReg r3, int m4) { @@ -2469,19 +2515,89 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { - g_assert_not_reached(); + if (src < 16) { + /* Replicate general register into two MO_64. */ + tcg_out_insn(s, VRRf, VLVGP, dst, src, src); + if (vece == MO_64) { + return true; + } + } + + /* + * Recall that the "standard" integer, within a vector, is the + * rightmost element of the leftmost doubleword, a-la VLLEZ. + */ + tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); + return true; } static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset) { - g_assert_not_reached(); + tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); + return true; } static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, int64_t val) { - g_assert_not_reached(); + int i, mask, msb, lsb; + + /* Look for int16_t elements. */ + if (vece <= MO_16 || + (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { + tcg_out_insn(s, VRIa, VREPI, dst, val, vece); + return; + } + + /* Look for bit masks. */ + if (vece == MO_32) { + if (risbg_mask((int32_t)val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x80000001u) == 0x80000001u) { + msb = 32 - ctz32(~val); + lsb = clz32(~val) - 1; + } else { + msb = clz32(val); + lsb = 31 - ctz32(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32); + return; + } + } else { + if (risbg_mask(val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { + /* Handle wraparound by swapping msb and lsb. */ + msb = 64 - ctz64(~val); + lsb = clz64(~val) - 1; + } else { + msb = clz64(val); + lsb = 63 - ctz64(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64); + return; + } + } + + /* Look for all bytes 0x00 or 0xff. */ + for (i = mask = 0; i < 8; i++) { + uint8_t byte = val >> (i * 8); + if (byte == 0xff) { + mask |= 1 << i; + } else if (byte != 0) { + break; + } + } + if (i == 8) { + tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); + return; + } + + /* Otherwise, stuff it in the constant pool. */ + tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); + new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); + tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); } static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, From patchwork Sat Jun 26 05:02:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467426 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2139248jao; Fri, 25 Jun 2021 22:10:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy20QI7uKR42544ni6rGPlqMdkUefaJ2ZH6REn8PoBaY0RGOR0MEeapB6LfL2RXttKgcY8Q X-Received: by 2002:ac8:5755:: with SMTP id 21mr12837709qtx.267.1624684208305; Fri, 25 Jun 2021 22:10:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684208; cv=none; d=google.com; s=arc-20160816; b=Y5KxwgpSThsj1JuOBFEz+yfTupQpH1gPz1B+lSjWBCWXWYtse7dLSRK+DfteWMZNIf gb5aLKwTOx43zq1sg5Nvlg8R+lnA8Tuztt0IKdur/KBwgOj6wtcAet9TIHxYJqG6nglN 3lOz7yJvXG15w5ymC4o+k4tl0TIhK+jQCxV4HiTdz8LVanokO1FltnG5GDRvWB/sCSwW IJU33gemvk2qaCfRFOd5m0frqJ0SwBV5+elsspEUpmAtxJcQtcacNuAwuGWCATX3JnIe ThypIlP2cmJbzHzABpyxfAV4nGfpFcZFoDuFEI010MsiTjMnLV61GAXHmTOBDYokMI4a LbUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iz0hHW1GRCz2N3YuVmCJPXt6iqzvf0SB2va/9hRf/0k=; b=en3LGVrAkf5YXkwhpjMHDL4zzpfsXjJa+7pjaKqYvvbR7iVBOPCLS5EBHNfqJW1wKO lt6wFVWRgZs1lJcHi0VR2wId2pozMJRYXMdLkQljvxL7U3TJoffXhNnlNlNhzoL4msN0 W0yLYkrpVJp91NR65AP+rcdzC2cTylhaqYR7GqOiT74QhAg/miR4oijtSxxlBm8akAiM PrLG3ckgsG9b3FrbCXYodz6dsJ1Zfa0BTjN6yjdR9wo+6qCOVD0TWJhnc6ihGFlvRL5q 1ycZ4MBTCQ+fHvmYn5CxjUS2OKXUhesgkzTTciy6jHqZkhgcQuC41Y4EFkUG/cshRjzR zGhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ap99dlQ+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a21si3362502qko.289.2021.06.25.22.10.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:10:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ap99dlQ+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0Zz-0000Eb-Aa for patch@linaro.org; Sat, 26 Jun 2021 01:10:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TN-0006vH-Rx for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:17 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:44638) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TJ-0008Fj-VI for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:17 -0400 Received: by mail-pl1-x62b.google.com with SMTP id x22so5777060pll.11 for ; Fri, 25 Jun 2021 22:03:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iz0hHW1GRCz2N3YuVmCJPXt6iqzvf0SB2va/9hRf/0k=; b=ap99dlQ+tyy4+pKWklFukqcOLxK15bzXadbPiCqqPj/IcwHBhmgmppso62t5PMI150 tFA7dEAtReDVbZ6Tl2YcenZ6qbFbrDzUGPoQMwdPfuASgPMkdfpl3lqOcj8JdiK0keFn bDPQNJ60/GZyGkCvriIinpJExg681i0LrWU4YJtDEvvQWsg0mg/PCfBVfPiRNx761msR M8ZQ4Lj3MUadsKee172HPC3VliWZB2YnsLvGEwux4i9jNzh9MDYQpY0PwZi6ZAbZP/rI NKmlk6Zz8ZncHmPXu0k/CLt744xlErbsQCVsr0w5AoOt8CKDLdaLPzzTtpPNIomhF+6+ /Vuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iz0hHW1GRCz2N3YuVmCJPXt6iqzvf0SB2va/9hRf/0k=; b=c5i5KB+9Ch2+mzVEoRnByJR9kEdu32fSRDUf5KsqhE9FPFjV0Xn+1izir8u/6I2txB lEK1CMvnTaKlsO6VWWUJj09pOMglkULfwFyG6MmW8SRuLueOkSkT7ISw8WRdDyhKapiK /GjFcmvih7PjdMFBjc2PbmWkbTw6TwE4xcXD92nPe3+hVS86DPQ41LCMqm7Vw0QdgkiH iUk4IokpGSezc9EKJCEoZJfFC0DZRN+ziYEKf35JNTHgiTtVQtGV2atrX3Y8er0qa9p5 2QeT9ylzAoIdLkcReAUX/8FvyelZjzj1+bn8NmX+ctJAw76z1Iv/zOaarQH6JiswKmpm rBZg== X-Gm-Message-State: AOAM531xbcjAx49BkkZ5/EEPmIP8FsaYdQEMkpr0ixhIAWaUFXjGGtz2 BzbJ85BksSH8Jft1IE4zy6oksMDh6aXwfA== X-Received: by 2002:a17:90b:2282:: with SMTP id kx2mr14365377pjb.60.1624683792713; Fri, 25 Jun 2021 22:03:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/16] tcg/s390x: Implement minimal vector operations Date: Fri, 25 Jun 2021 22:02:59 -0700 Message-Id: <20210626050307.2408505-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 154 ++++++++++++++++++++++++++++++++++++- 1 file changed, 150 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 76216eb5bc..c0622daaa0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -271,6 +271,14 @@ typedef enum S390Opcode { VRIc_VREP = 0xe74d, VRRa_VLR = 0xe756, + VRRc_VA = 0xe7f3, + VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ + VRRc_VCH = 0xe7fb, /* " */ + VRRc_VCHL = 0xe7f9, /* " */ + VRRc_VN = 0xe768, + VRRc_VO = 0xe76a, + VRRc_VS = 0xe7f7, + VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, VRSb_VLVG = 0xe722, @@ -597,6 +605,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); } +static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out16(s, v3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg r2, TCGReg r3) { @@ -2604,18 +2623,145 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) { - g_assert_not_reached(); + TCGType type = vecl + TCG_TYPE_V64; + TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; + + case INDEX_op_add_vec: + tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); + break; + case INDEX_op_sub_vec: + tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); + break; + case INDEX_op_and_vec: + tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); + break; + case INDEX_op_or_vec: + tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); + break; + case INDEX_op_xor_vec: + tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); + break; + + case INDEX_op_cmp_vec: + switch ((TCGCond)args[3]) { + case TCG_COND_EQ: + tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); + break; + case TCG_COND_GT: + tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); + break; + case TCG_COND_GTU: + tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); + break; + default: + g_assert_not_reached(); + } + break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } } int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { - return 0; + switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return 1; + case INDEX_op_cmp_vec: + return -1; + default: + return 0; + } +} + +static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + bool need_swap = false, need_inv = false; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv = true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap = true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap = need_inv = true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond = tcg_invert_cond(cond); + } + if (need_swap) { + TCGv_vec t1; + t1 = v1, v1 = v2, v2 = t1; + cond = tcg_swap_cond(cond); + } + + vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + + return need_inv; +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { + tcg_gen_not_vec(vece, v0, v0); + } } void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { - g_assert_not_reached(); + va_list va; + TCGv_vec v0, v1, v2; + + va_start(va, a0); + v0 = temp_tcgv_vec(arg_temp(a0)); + v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + + switch (opc) { + case INDEX_op_cmp_vec: + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + + default: + g_assert_not_reached(); + } + va_end(va); } static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) @@ -2807,7 +2953,7 @@ static void query_s390_facilities(void) * There is nothing else we currently care about in the 3rd word, so * disable VECTOR with one store. */ - if (1 || !(hwcap & HWCAP_S390_VXRS)) { + if (!(hwcap & HWCAP_S390_VXRS)) { s390_facilities[2] = 0; } } From patchwork Sat Jun 26 05:03:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467424 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2138487jao; Fri, 25 Jun 2021 22:08:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwpWcfM5b1DaE2ALXcJHfy9o/psU+iU5nJdjqzqeI7Q45/qtgrEeKCddJrYoozY6Q2E3tk4 X-Received: by 2002:ae9:f50e:: with SMTP id o14mr15480675qkg.141.1624684122354; Fri, 25 Jun 2021 22:08:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684122; cv=none; d=google.com; s=arc-20160816; b=nMXwq6qyNtHllJ1/ZcM1HH1EtZd9Gdc/Hu9+yDeZUwJ6BqNjgiF4PFSHdX1bBkNviy LhAzaj/mq9MPHMK/611fGqKY+Nh5Isu5COqDerNeLF3msI3Ox0nvAO5E6hfRWteOMnp5 zoxH7IKqDrd3rU2h7TRqb0RUNFPxeG+kpko/f+571X1DIZnscGqn2RZwBihE2VoW3huY GnpMu/uakk6QhCAn+vGWcLgx9u3fjjNxJa2HXLrZZeSgQdxTQ7h1hx9tROERRHlkggGJ ZilNBJcePYlrZlCp8JRruZEisUJ/l0e2XLMVMgE17LSLw5ORjXD1p9ZLWHtkn949JFT9 tmgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IypcM1ipm+f5DR2LZmBwkjxviEK3lr9idsjwsPboDZI=; b=f7aJQwnY2xYM5W3OM4/+s02PwcSIptZoEejcS4KGiTmA0WtzSy1Ob17/asVojlR5Ve 8i/1vRSMJ8zgwUQ7YFIsyVy3EAunro+oVAWHofx1R0q2NU8L8TYr43EP4TXAJSfbGSvz iU1qQ/KTLvXzbljuTJDM03EvYe6xyxzSH+FGw/61rNWegwcvFJDcj6j32zeLJDxASR60 NivGrXP4Q51taBgwQlsvy3KXWFDm9VG+IKbINdlLjhxjOyqv61CY1qQziIkskWxN38D8 RNxFAdfMXm4RQSbreiz/fnkWaa7iScVBObkU7+7oaUsIs8QKkL6QykMAN7SgUhzdsrLT IWjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QZZUujXr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x6si6082617qkd.188.2021.06.25.22.08.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:08:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QZZUujXr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59826 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0Yb-0005bS-SK for patch@linaro.org; Sat, 26 Jun 2021 01:08:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TO-0006yA-MP for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:18 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:45763) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TK-0008Fr-HN for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:18 -0400 Received: by mail-pf1-x42e.google.com with SMTP id k6so9101311pfk.12 for ; Fri, 25 Jun 2021 22:03:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IypcM1ipm+f5DR2LZmBwkjxviEK3lr9idsjwsPboDZI=; b=QZZUujXrmvJtQzw7MLq9j4juBlcOJntZrvNXblpyaEQ4CVa2XdoUZ+OSSlQVnHa7tQ C7PS9NnOLlGEBYc1+aW+SMhoTNr27io3xizFsrmnVkrb/JXc90a9NENQdf1w+KtG6h8+ LWIU0hzHc1IjC9X7jvKddObWlnN5DbBFd4P9SDTElFtjMWjMF0REI3vCSeER3su2VDdC 1UvvFpeLr5tBrjTsW+fpGZxjD9g6Ob3Gov7gOuT4Ymy6cM5KQda71MysJrqsn8LPVJpF KooXz301S11fLjYcpTbkvPjJNaGrnbPXgFigOE9h0aIbDeifwzhlsoRf80i9+nU7Hjnr i/Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IypcM1ipm+f5DR2LZmBwkjxviEK3lr9idsjwsPboDZI=; b=bhwHb+2n4w9H5a7hccFW8qq1mjjg+M9Vgqrkr/2S1mKZtfDIlJNxiion3a4nYeDAAe DpirVNjjZFYD+/n4+GJiBiv4OlZ80dn/StGuAw+KpJ42V29LkgRinISvadcsxuy4bIi8 mv8zLT6kKzRrJ5rjKS0iORjfCFx/BK7Wey5F66A76aTTShWs1b+1iBIQnbD46BWZrE0H XDuMUYAfT/M/W6CvFQsiV6RjbAWanZgPwGqRD4fjMt7mHunyAUNs2b4vPkyEbSRuF3ZC ki7GIn71gJuVDLPBz4ouTbcFcaaUsYhbX2EMhuCAE4YhIbX0+59wNNPVv+Y6VTHsIddU 3pRw== X-Gm-Message-State: AOAM530fGrFjTo0PPGUpB4TNzsjmuNrcoSOfM87fS7kouRgrMR8vNBtO 9PGiZf+YWy2aS44UyaZSwAmp4Ueq9Xr0BQ== X-Received: by 2002:a63:195b:: with SMTP id 27mr12800664pgz.450.1624683793335; Fri, 25 Jun 2021 22:03:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations Date: Fri, 25 Jun 2021 22:03:00 -0700 Message-Id: <20210626050307.2408505-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These logical and arithmetic operations are optional but trivial. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 10 +++++----- tcg/s390x/tcg-target.c.inc | 34 +++++++++++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 6 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index ce9432cfe3..cb953896d5 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -17,6 +17,7 @@ C_O0_I2(v, r) C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) +C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index db54266da0..a3d4b5111f 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -143,11 +143,11 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v256 0 -#define TCG_TARGET_HAS_andc_vec 0 -#define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_andc_vec 1 +#define TCG_TARGET_HAS_orc_vec 1 +#define TCG_TARGET_HAS_not_vec 1 +#define TCG_TARGET_HAS_neg_vec 1 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c0622daaa0..040690abe2 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -270,13 +270,18 @@ typedef enum S390Opcode { VRIb_VGM = 0xe746, VRIc_VREP = 0xe74d, + VRRa_VLC = 0xe7de, + VRRa_VLP = 0xe7df, VRRa_VLR = 0xe756, VRRc_VA = 0xe7f3, VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH = 0xe7fb, /* " */ VRRc_VCHL = 0xe7f9, /* " */ VRRc_VN = 0xe768, + VRRc_VNC = 0xe769, + VRRc_VNO = 0xe76b, VRRc_VO = 0xe76a, + VRRc_VOC = 0xe76f, VRRc_VS = 0xe7f7, VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, @@ -2637,6 +2642,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; + case INDEX_op_abs_vec: + tcg_out_insn(s, VRRa, VLP, a0, a1, vece); + break; + case INDEX_op_neg_vec: + tcg_out_insn(s, VRRa, VLC, a0, a1, vece); + break; + case INDEX_op_not_vec: + tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); + break; + case INDEX_op_add_vec: tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); break; @@ -2646,9 +2661,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_and_vec: tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); break; + case INDEX_op_andc_vec: + tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); + break; case INDEX_op_or_vec: tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); break; + case INDEX_op_orc_vec: + tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); + break; case INDEX_op_xor_vec: tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); break; @@ -2679,10 +2700,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_abs_vec: case INDEX_op_add_vec: - case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: + case INDEX_op_sub_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: @@ -2911,10 +2937,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I1(v, r); case INDEX_op_dup_vec: return C_O1_I1(v, vr); + case INDEX_op_abs_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: + return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_cmp_vec: return C_O1_I2(v, v, v); From patchwork Sat Jun 26 05:03:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467425 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2138853jao; Fri, 25 Jun 2021 22:09:21 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFGsrWyNbIBMZxhJdHHwlRS4u+JLngB3awNMJwMMoBqueteitPaxkSJX1ogmIQEtaBMoi+ X-Received: by 2002:ae9:d883:: with SMTP id u125mr10688772qkf.318.1624684161163; Fri, 25 Jun 2021 22:09:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684161; cv=none; d=google.com; s=arc-20160816; b=a+pDITMKmTuD9kjBhvltGvx6s/9nRAQkCoAIGPS1Rtoj9o5y7bq+WsKSHHVAbK9EiW H9l0Xas+a6aAh5OaPWRtTEHrOHDIw0iFTl6bL0BolfPu2jGiFGCi2T5c2VbLRuNTgjhr gXxO1FxSBI8MlbEAMc3ZFnQlkwAe19QI8TP1qUxPSwdMvHDIbBSXQDcCiAHK3II9v4+g wasjknV70xP1VtX5smqBoIHJ035xurftqBWW0iiEdJhSuMaHo3JxG7OXBpWiPw5rzMC+ FPhRz/nXerWHqBcN6SoQXQNs5lwUIf75Ktnr0G+bpxZgo4+xLOUXAIAssya5fqlSK/kd DBNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Es5BtYJvhqewprYdclINQtXx7YeJnyuEDH0/5n/RZtA=; b=Rz74odvlfiq6WmWtSTugI31En/JS1KrN/8xwxZdYNDvsD4XbwchmTIjjMfyCiyDG5l ajB9KezVaYiTpTILnP3896kxxao5r9nuSCyRykZw6ID1BaBSnyIjDxeGiJ1gXFuyqBL6 WspY4eT4LkKIcBq32L3kAbTe5lZLLbyG/BGZwy1l6f65QEOdYefBHPQbubLeCCgsArYa 7zUC5hPUjdaxK+jbGjrPMhJVlEMJbOTglBy2uRoKIO6AoFZ+Jr16Xdkyi0J4QQpB2ipX CO8BAZQ4BQ6e90YosGyf/BWOPfSIXRpPKPvsK0miz6sRLI1RnQgmLkIP8cOeHJPS5k2w xDIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iyG4QPHl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s13si5752520qkm.158.2021.06.25.22.09.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:09:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iyG4QPHl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0ZE-0005pw-Ng for patch@linaro.org; Sat, 26 Jun 2021 01:09:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45132) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TN-0006uL-A2 for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:17 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:36762) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TL-0008GM-6V for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:16 -0400 Received: by mail-pg1-x52e.google.com with SMTP id e33so9997784pgm.3 for ; Fri, 25 Jun 2021 22:03:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Es5BtYJvhqewprYdclINQtXx7YeJnyuEDH0/5n/RZtA=; b=iyG4QPHltHZTQkiXN/OJTj3hEQA+55gKZGKTKUkrZwxCA18NvwNGoonRRoE5bbLXPj 5B0IOYCUqqbHLt90GHmECPW52LE2+Vt5sK5oYvFXdii1jQGKP6h7usuU4INEDrKa+EyC pFfK/K6xQjBsHwpvjbSZHbA7PUma/ZtJkMx0O2ns+6oFWsAZF3gcJmvvw7nJh1HevmSO yhKPF4OVbOTX0rq6MqaQ6WDHQHIagElBmA82itiSaB0PiD/3lUXwxLLy9b6MjD5f4GiP PJWHLmpLk6I+DqvvAlwZ0sff5mPgceBdKDOwIk8tqVEonhZDbtQ7cDEKnd/xIxL35kv7 1uPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Es5BtYJvhqewprYdclINQtXx7YeJnyuEDH0/5n/RZtA=; b=MoGItzmQjvkfAKLRXBXshzwF31++Dkk9b48eEymM1rvldtxY3SrPx6rHT13qFDRujl gbkslsDZNBocebdYW0RthmfBDgrGRGPalEErre+SYheru6/8Q/I580Erfb8DzvptKdbz BBUJfRUaOvfK6DePBxHCZysIU7sbLjnCVvo2xk08yPplRjTX8tV3/5qFzeuHIzZQZyH9 GT9hyc1PfbzxBTubk3ZPCPNoo/Za602v3P264DMAUrnqTb8Ebt5owm2F1K6582xqa5vl H9Un+MOksraLek13moie4XWtQqwljvY46heP64KALB4Q6Zq7xryDZ0Hxy4L2M4SnG9nB dHrg== X-Gm-Message-State: AOAM530QLFdvTUFUSv8/9LWxQG0cWe9ne13K5NDVtNQp3t5HsI6rRAnK puP308d/qY4r6kvYcA65j2deGye5p+sorg== X-Received: by 2002:aa7:8d86:0:b029:2ec:82d2:5805 with SMTP id i6-20020aa78d860000b02902ec82d25805mr14027763pfr.11.1624683793928; Fri, 25 Jun 2021 22:03:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Date: Fri, 25 Jun 2021 22:03:01 -0700 Message-Id: <20210626050307.2408505-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index a3d4b5111f..cb14a011c7 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -154,7 +154,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 040690abe2..c142279bb8 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -277,6 +277,7 @@ typedef enum S390Opcode { VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH = 0xe7fb, /* " */ VRRc_VCHL = 0xe7f9, /* " */ + VRRc_VML = 0xe7a2, VRRc_VN = 0xe768, VRRc_VNC = 0xe769, VRRc_VNO = 0xe76b, @@ -2664,6 +2665,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_vec: tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); break; + case INDEX_op_mul_vec: + tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); + break; case INDEX_op_or_vec: tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); break; @@ -2713,6 +2717,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) return 1; case INDEX_op_cmp_vec: return -1; + case INDEX_op_mul_vec: + return vece < MO_64; default: return 0; } @@ -2949,6 +2955,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: return C_O1_I2(v, v, v); default: From patchwork Sat Jun 26 05:03:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467422 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2137688jao; Fri, 25 Jun 2021 22:07:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzCUOohSF/5ux22zWdc8X6WFaZmdjvzC8lHA7BuR7gnO72+rdKg4omthp9IOehOhaA16oJ X-Received: by 2002:a05:622a:1747:: with SMTP id l7mr12659207qtk.225.1624684043453; Fri, 25 Jun 2021 22:07:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684043; cv=none; d=google.com; s=arc-20160816; b=cbh7IRT5YdMeAzEc/IEKrSotUtZfYaPjgqn/gq7jrLA79218G0+vlHijGIx8AKab1r tLFrnZLfgX96bUdEays7RcgG928+cOWpw7CBR0wqjJs/N3qoewzB/TiLpBLXmhCx9pA2 BHdPhkZtdi70o5jOD6ga4RG2CzfOaqX4YZEVJhBlXvjVrPakxHWy+mHcxfZRBlR+lAck /hYkhC+pNd/RwaWN2BTUV96c095WIVPNu3t8xtdnrMf8sAGiSIOI3hm35E+o2rxGgtFy uPqq1edrR7fzjPp0rclET1cxfUqAqZz5lS9Bo29lceg1J48avWb4Cj+pKEEumRm6pj7D KTKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CFGDGCwhvAJbpWWCsNcb9mvpCKGl7HMW0/Cb9Q6KSow=; b=KNWafKRzh4rk7havbaZQoe+E7FYEctTmS5xZkXSJ34RR03/jiSPFCrVcbrug7/uzNu XIpgcfQO+5rVd+35t09Q332vVGxsjBB6Aguh2NdP8TzGmm3RqwHQvRmsHLksYHm9DkK4 MtgBm3XrWoYNu/wbvxxsTb4FlUJ1aBF/VZAaTWI0sMN+T45MC3ingStLMBBXbDN6EhkA kRQSg84R9u3k+hM5dGEZ9A0z8AS75amtDaZXux/auelkhF3J0JbAgRu5dolmPChR++ns 7CAH2zB0HL3IFxlMz8I58fsqztmMFFKe6wQ1wgOWo/02WUnKCVkt28PAeGxqjBSe3Xb3 VUFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oGnkyJ/X"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q19si7161475qtl.367.2021.06.25.22.07.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:07:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oGnkyJ/X"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0XK-0001CE-Ud for patch@linaro.org; Sat, 26 Jun 2021 01:07:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TO-0006xT-H5 for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:18 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:39676) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TL-0008HS-TT for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:18 -0400 Received: by mail-pf1-x429.google.com with SMTP id g192so9127707pfb.6 for ; Fri, 25 Jun 2021 22:03:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CFGDGCwhvAJbpWWCsNcb9mvpCKGl7HMW0/Cb9Q6KSow=; b=oGnkyJ/X7KUZ4dBgAMAVRh1btlbdffT1OAWmeQRJsnXUI8gAglQYhk3lTp+v9ngkYu QxJDku2sdfKzAVzIU/Jdgjw65rAfMBHrfVROIikTQuVApbcELscTJYtKMkkSjdi94Fa4 Rc5LjeHCDVdihJQVpsIo9Xyh3erzTLb5zuUCT/A6SrbjOP5vmbq3O2HCx3RqkRlEje2g S6YMJNYOLCNSFtJtvFnK87g2U6/3tLy0jgT2c7IVda5fu/zL0wpRoUR/WWWlZFnYglm7 DGsM5kXCvbLWmvOaVVr4T4+vv25JfgrwmGAx/9Vh+InVeXDJlqqaryz57r2gmPSEnUIs p0LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CFGDGCwhvAJbpWWCsNcb9mvpCKGl7HMW0/Cb9Q6KSow=; b=YVZh/iltS00wE0ZzSQJasBa/zyYGxn9svcVyohpsKurzH4pCcfx1tjD/fo0XVAn9P5 ebAGNPyEHRBev+V/9AwLbDWXyt8MKZZhrz6YQEnZzGCt5eEdzPeSCiBq5pyQ8a0tcHet RBHI+u5SIE3vezqfHLxCx6mg5Wg8qK1Vs2AnNQxF6mJ/l8TnBJfhjGa6htdCwUm2l3Yf Uqp4pAxOJJ5mApsgPAOOc5e7qyoOMCuICV9zsI4XJnR9xqr45DnlEjMeNhZ8jEoZ/nGl ak4skY9015LTcQmX5wOnd06DUmRRWB1dx0+8oSAxBytew8S0jJxsaem+96VCP4ZlHdlm K/nw== X-Gm-Message-State: AOAM533WQGcec78NdjXt7RYpo2Ek4MwioszHcuybzhH7PusmQ+G4KKbP itxum/HMMol5+3Xnp4Ml+TR5Lx5SjndVjQ== X-Received: by 2002:a62:7e05:0:b029:2ea:57f:ec86 with SMTP id z5-20020a627e050000b02902ea057fec86mr13963827pfc.37.1624683794596; Fri, 25 Jun 2021 22:03:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/16] tcg/s390x: Implement vector shift operations Date: Fri, 25 Jun 2021 22:03:02 -0700 Message-Id: <20210626050307.2408505-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 12 ++--- tcg/s390x/tcg-target.c.inc | 93 +++++++++++++++++++++++++++++++++- 3 files changed, 99 insertions(+), 7 deletions(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index cb953896d5..49b98f33b9 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) +C_O1_I2(v, v, r) C_O1_I2(v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index cb14a011c7..8dce6af5af 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -148,12 +148,12 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 -#define TCG_TARGET_HAS_roti_vec 0 -#define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_roti_vec 1 +#define TCG_TARGET_HAS_rots_vec 1 +#define TCG_TARGET_HAS_rotv_vec 1 +#define TCG_TARGET_HAS_shi_vec 1 +#define TCG_TARGET_HAS_shs_vec 1 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c142279bb8..b9d12e579b 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -277,6 +277,10 @@ typedef enum S390Opcode { VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH = 0xe7fb, /* " */ VRRc_VCHL = 0xe7f9, /* " */ + VRRc_VERLLV = 0xe773, + VRRc_VESLV = 0xe770, + VRRc_VESRAV = 0xe77a, + VRRc_VESRLV = 0xe778, VRRc_VML = 0xe7a2, VRRc_VN = 0xe768, VRRc_VNC = 0xe769, @@ -287,6 +291,10 @@ typedef enum S390Opcode { VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, + VRSa_VERLL = 0xe733, + VRSa_VESL = 0xe730, + VRSa_VESRA = 0xe73a, + VRSa_VESRL = 0xe738, VRSb_VLVG = 0xe722, VRSc_VLGV = 0xe721, @@ -633,6 +641,18 @@ static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); } +static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, + intptr_t d2, TCGReg b2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v3 & 15)); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, intptr_t d2, TCGReg b2, TCGReg r3, int m4) { @@ -2678,6 +2698,43 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); break; + case INDEX_op_shli_vec: + tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_shri_vec: + tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_sari_vec: + tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_rotli_vec: + tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_shls_vec: + tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); + break; + case INDEX_op_shrs_vec: + tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); + break; + case INDEX_op_sars_vec: + tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); + break; + case INDEX_op_rotls_vec: + tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); + break; + case INDEX_op_shlv_vec: + tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); + break; + case INDEX_op_shrv_vec: + tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); + break; + case INDEX_op_sarv_vec: + tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); + break; + case INDEX_op_rotlv_vec: + tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2712,10 +2769,23 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_not_vec: case INDEX_op_or_vec: case INDEX_op_orc_vec: + case INDEX_op_rotli_vec: + case INDEX_op_rotls_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_sari_vec: + case INDEX_op_sars_vec: + case INDEX_op_sarv_vec: + case INDEX_op_shli_vec: + case INDEX_op_shls_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shri_vec: + case INDEX_op_shrs_vec: + case INDEX_op_shrv_vec: case INDEX_op_sub_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: return vece < MO_64; @@ -2778,7 +2848,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2; + TCGv_vec v0, v1, v2, t0; va_start(va, a0); v0 = temp_tcgv_vec(arg_temp(a0)); @@ -2790,6 +2860,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_rotrv_vec: + t0 = tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t0, v2); + tcg_gen_rotlv_vec(vece, v0, v1, t0); + tcg_temp_free_vec(t0); + break; + default: g_assert_not_reached(); } @@ -2946,6 +3023,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_abs_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: + case INDEX_op_rotli_vec: + case INDEX_op_sari_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2956,7 +3037,17 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_xor_vec: case INDEX_op_cmp_vec: case INDEX_op_mul_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return C_O1_I2(v, v, v); + case INDEX_op_rotls_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return C_O1_I2(v, v, r); default: g_assert_not_reached(); From patchwork Sat Jun 26 05:03:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467427 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2139408jao; Fri, 25 Jun 2021 22:10:23 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzeWt/P6qsH0CPssx1thoqzl0Thh7U2pXwCnvrfd/v3XtKCLB/qGgUBfA5ePj3bdb0cWIv9 X-Received: by 2002:ad4:5004:: with SMTP id s4mr15018376qvo.8.1624684223151; Fri, 25 Jun 2021 22:10:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684223; cv=none; d=google.com; s=arc-20160816; b=j6wn6LD+NhJYJ7srP4WJ8PPeD7+bqsy1Qk0AR5cQMuafgpogS6avZFJ5+UUqP3JAsL yZ6uuceYSIez13okwJrDL/EgYWzzTqQeQ/Eyg4ylBp8VagUMFvniZft/Ybkuq0u/03p2 8v3U4SitgBfyOs8u1G2yjeGBTj1V7M+zYUL7RYzvMLAq6NLNTroOYBgB7Cf/EdNYGPYL u3nNaYyEPyENmWg7JHCdZDnIeJI+t9v+g603X6UH2M4ghKMb4liYHdYq1Q1Gvs1qiVsh pJJUnd9kjMmVNFO3TMsWaz0AMysH0QujKnPBPNRDcRHeXOrgq25iISSUIjAhdoew78vY /okA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=efBLLD49qr2p/LDJOapeQP0oKHtNvdFQQbTOrF6f0FM=; b=aMmR2Eyyep3VqXUtHDYJp7kdlmKHmqXreRreS6CT1rZIoFzfCY1GGQuSUhZeGxPFSk Y08WepU0Zgyc4twIbT257+uQ8/J95uxBR8SaSacZRYpQElBO55FP5gnPC+xxbBaYqeqp pA6s3p4N0JITPxcifZd6Ocjt6/rhmKAGBSyoX4VE+8tq7TvOs2RKp+ZBw37aHsmHoSbC TUA6SRGoO/pG+wS6UAu03CGggxIBOtfzXcIG2QV7BGui8vGOJbmRxbP/qhqvryZDz3zR YouJX+jH7N/DAFfA655YVs5hhPXTEZHIkOqJqe2SdeOwGN3ixDNG1Y1CSZJzwcbwL3E0 MTMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KxXU1DPU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m185si6102897qke.254.2021.06.25.22.10.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:10:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KxXU1DPU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0aE-0008TV-KR for patch@linaro.org; Sat, 26 Jun 2021 01:10:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TP-0006z5-0k for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:19 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:44639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TM-0008Ha-NM for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:18 -0400 Received: by mail-pl1-x62c.google.com with SMTP id x22so5777094pll.11 for ; Fri, 25 Jun 2021 22:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=efBLLD49qr2p/LDJOapeQP0oKHtNvdFQQbTOrF6f0FM=; b=KxXU1DPUhbaFYpbICG4QVSc7ObSRfOFu26NsfTlAKBM65H6vTaC6kciKhocgZ9SJ0M Wa2Q9PrF3FVTFauseshO2MR6q0fo5Gr60S2jfecFEdHWuXYmxSFazzsXqWhusIdLEKVf 8EuXhowNAwcCDr5vxXWIwcAod/DLp3oTZBGdqufw6UIG1Q9DxmQQGeIduzSMl+E2a4rl 7YKNZdzjulNUpTi0QEnu5Zt6hJ32Wz4tjF9IulxjgfTfy6sUv3ymSa0e7m9D3/2OeMTS Ej27cbN+I+c9uD0vrrjLYSFKXJ36WJEQ9kgkAUKskRxzMaXA3Exa7AvrKZt+XNJ1fQWk PZ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=efBLLD49qr2p/LDJOapeQP0oKHtNvdFQQbTOrF6f0FM=; b=M+6cqKQeHBg5larp/GaX6dBudVQzCdWS2oKak48MEDN3zs2T/iIuZk/9zfAZyoCzWk je8iYjnjXXwL7ssrvktSle1O9mpOvjUfIEEACilT+Asgpa3fZfi/elUySTQqL3HwjUPO W/P55IDcbGiRdFcTcMGkrnG3DjgT+YF3IqoFmbbTz8/LOhF6P3mXP5jDKBuorizYAjcq mCPSYqK8XD3hAbhmXPiO/F4jnAP3xMve576ZqaVAHAG8xzxelg4+zEjv8+l+4m65oXhQ W4sJiXWjaMgDMiXuvn2UZGQ6PbXdqRqpzW/UMClvBvggshmthzDj8M3nnpH7V8JTok7F 7sQA== X-Gm-Message-State: AOAM530yo5nrWqgqx/JmlLfgWfw8BY9yzHihf7UZIl8LGdjDxqOCRx+v hxuRjBfYnc2mfn3EsvFjbPoE8n6W8WbyVQ== X-Received: by 2002:a17:90a:420b:: with SMTP id o11mr14551385pjg.201.1624683795157; Fri, 25 Jun 2021 22:03:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Date: Fri, 25 Jun 2021 22:03:03 -0700 Message-Id: <20210626050307.2408505-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: David Hildenbrand diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 8dce6af5af..275f980cee 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -156,7 +156,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b9d12e579b..b96128760f 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -282,6 +282,10 @@ typedef enum S390Opcode { VRRc_VESRAV = 0xe77a, VRRc_VESRLV = 0xe778, VRRc_VML = 0xe7a2, + VRRc_VMN = 0xe7fe, + VRRc_VMNL = 0xe7fc, + VRRc_VMX = 0xe7ff, + VRRc_VMXL = 0xe7fd, VRRc_VN = 0xe768, VRRc_VNC = 0xe769, VRRc_VNO = 0xe76b, @@ -2735,6 +2739,19 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); break; + case INDEX_op_smin_vec: + tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); + break; + case INDEX_op_smax_vec: + tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); + break; + case INDEX_op_umin_vec: + tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); + break; + case INDEX_op_umax_vec: + tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2781,7 +2798,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shri_vec: case INDEX_op_shrs_vec: case INDEX_op_shrv_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: case INDEX_op_sub_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: @@ -3042,6 +3063,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, v); case INDEX_op_rotls_vec: case INDEX_op_shls_vec: From patchwork Sat Jun 26 05:03:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467421 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2137533jao; Fri, 25 Jun 2021 22:07:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxnQ2KjMnje67h8+fUh0i8Pj5v9GB8YPSQoEXkIgXRZ/CXA0Yy8cKuFxlFqgB9ZlngQ0MOF X-Received: by 2002:ae9:f50e:: with SMTP id o14mr15476455qkg.141.1624684024373; Fri, 25 Jun 2021 22:07:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684024; cv=none; d=google.com; s=arc-20160816; b=jnNy9ZMU3CQ7dOjBtBPqygbHyJSmTUP/L+G37vMeq+C+1JFfKr4Nvt98hW4xRfftxm NIBhPBjMfkptpwIH4ls6IEIfrEYKVkwk9y03P9p3e+ZeZ02KrBHoOuZ95QBNpg9tJipE LhzQqMOAnWc/l59vx3J34GbOzqqxsW9dRaTjVetz/dHsVFuiue3Pr7H+BC7q0oiX4eIu fYFEM9Ebeu16xj0ymT4kFpT7x4wFtf1Jd4x6utJNlSRsgAJrWCupz83idDbPQUV/owUm UdDQH+YwoY7DdZKnOHLxUE94H8DCXBP/6PnRiADKb6L+pjQ3BlRFVavwjZipTJQLIGVa tizQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lhsY62Axz8P4uEG2iGxE1nxCZRsB4mKyTgfXOvjyYjw=; b=kzhQdzuTqdYMsvQIYVIzkA0fbzJxTajdHSg/5Fod5ye6/39MwyqHDJg9jvfowjCCP1 tb9Axx02ZuE+sPk75zwb9HT/yMGsPO+ZIZJ1uFSSlWsctzYRg4RAIPCKDdfs75+OcRGi O3fr3JcvZT7rvZfRt40oH7KhwoCxI3NbFCtWW0hleSxhfSxbRwuekVN++GcodKDEPKlm Lyj0FFlnIxorYLFpW21L5m5a2SIcq1lxknf/qsP8Emb4voNLuk7F/9EriCco0DBNmlie xAzCBE43nTi9wAYjuOupmBqMUG77VE4tmmFDtv4/VOTIqzGQ0zq1nqYGX7nnCABnCfHk VMGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="a/00Azyr"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 66si6353694qta.25.2021.06.25.22.07.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:07:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="a/00Azyr"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0X1-0001SI-Rs for patch@linaro.org; Sat, 26 Jun 2021 01:07:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TQ-000746-FH for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:20 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:38639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TN-0008IL-32 for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:20 -0400 Received: by mail-pf1-x436.google.com with SMTP id c8so9140217pfp.5 for ; Fri, 25 Jun 2021 22:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lhsY62Axz8P4uEG2iGxE1nxCZRsB4mKyTgfXOvjyYjw=; b=a/00AzyrKg2sXXifK8rvABidCYpujudF5re+4qmV15W1VkOlaLx9Ipu9IMkEWbpkQ8 somlR2OMZ+QuIr5L/wj/keWRucCNB3S5GqdvxH9SbDoXVQT20m24xyxYbvFs/EHzbUgb u1k8anGncFjHG9AwrW6otl10CohibYn6JlPqeLnyDvHbt7RNURQQKWIsxbx3kA2oyE5N /x/iT1cXlNzjIQVL8iI+d0Y5wf/FfOkHHj6+xyN6iUXbtUzy6Dv2f1NWiyGXVglbx0Tr UdeKdUF2jdyPYW6T/zswPtwIFWeN3FQQ1iTSO5JtsJPZ9/Nh/dITHpMvQP/FH9RQ/C37 /4Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lhsY62Axz8P4uEG2iGxE1nxCZRsB4mKyTgfXOvjyYjw=; b=RDd9M0cFwVMFmkY1j51vipRygHOyvGcxFjm/xxUw97EZvmQFGF4l88ISkqwQqFG9FY kT2p01M86aIXpRCeKLph2uuNTx+26SY6yUgrwaFVyvw7+uIFe+P8eSmxiNwnTDgB1Nn1 KzjAEjrjJL/oBLCbz53Hc24j3WD94RHPSusg3l0XNUl2jIcW4uT0R6pMvDESNhUkdaMc CbtxsbbIhleqZGZO0k7vYPyRFLRN+f6pZNg5B7aGeb9KlokNw54Vnhz6nLEFQYUWcT+T 7KfQuJAdFHE3t/ovkBD2bpdzyeVLO87rpg5k3ElTuKP+pTSvxfNvOBtJV8JcGALJ6IqH lUzg== X-Gm-Message-State: AOAM531jYfZaxsDCKbQWFhkMZ8rZxkDj17uCTbhpXXWZxFPcaZnXHXAy 4bvAU/ClPbxrBrB676sCIhz2c9b3LAeUUw== X-Received: by 2002:a63:312:: with SMTP id 18mr12892136pgd.33.1624683795797; Fri, 25 Jun 2021 22:03:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/16] tcg: Expand usadd/ussub with umin/umax Date: Fri, 25 Jun 2021 22:03:04 -0700 Message-Id: <20210626050307.2408505-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For usadd, we only have to consider overflow. Since ~B + B == -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 15e026ae49..7705a49c0b 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -119,6 +119,18 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, continue; } break; + case INDEX_op_usadd_vec: + if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece) || + tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; + case INDEX_op_ussub_vec: + if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece) || + tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; case INDEX_op_cmpsel_vec: case INDEX_op_smin_vec: case INDEX_op_smax_vec: @@ -603,7 +615,18 @@ void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_usadd_vec); + if (!do_op3(vece, r, a, b, INDEX_op_usadd_vec)) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); + TCGv_vec t = tcg_temp_new_vec_matching(r); + + /* usadd(a, b) = min(a, ~b) + b */ + tcg_gen_not_vec(vece, t, b); + tcg_gen_umin_vec(vece, t, t, a); + tcg_gen_add_vec(vece, r, r, b); + + tcg_temp_free_vec(t); + tcg_swap_vecop_list(hold_list); + } } void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) @@ -613,7 +636,17 @@ void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec); + if (!do_op3(vece, r, a, b, INDEX_op_ussub_vec)) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); + TCGv_vec t = tcg_temp_new_vec_matching(r); + + /* ussub(a, b) = max(a, b) - b */ + tcg_gen_umax_vec(vece, t, a, b); + tcg_gen_sub_vec(vece, r, t, b); + + tcg_temp_free_vec(t); + tcg_swap_vecop_list(hold_list); + } } static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a, From patchwork Sat Jun 26 05:03:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467418 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2136598jao; Fri, 25 Jun 2021 22:05:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwzkt/FBRg8iaB7Wq41y+Yxyb4Mmjat37iW/WPPjEl3YOozYQGSYjsultp0WecTHXMsNRcN X-Received: by 2002:ac8:4a8c:: with SMTP id l12mr12641214qtq.234.1624683914690; Fri, 25 Jun 2021 22:05:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624683914; cv=none; d=google.com; s=arc-20160816; b=HoqqhCnys2f1+E8okLlzXkTNbGwEidw/2hj6uq/mxOH+7hA1CSFZx5ZhjHAvGwubMP oQBCDbgPGBmeSEC4/lWWQ2VJVDHFe0W3unDX0f9CyQxEede7r8IvPCvpImesL+5tjQxA IRSKJSFQSyCrqTvdi0iD60n3Vc8YCSepZdPvMwswnxKJA2eQhP47dRvZkEPOLCFdGKBW /vvzCDDvqXkOHZpj/mclesjDmMUHdCD82GLRbD/zf5GVchWIfB9vMu2Wgbfmabp3pGQw DpgPTZEtUFyUyqm8QIt7ipql3vJoUP9yyfF2YvmGZol9Dga/0x28ZeM3KuoyggymhqQp 1BdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=g3h9YxZHLsVNN60AWZleqPTLbakgmZoZFD5TK6oju4Y=; b=IMfkdq41O7s3Hu2mU37KX/uEkvWiy5Un1kFqamTE8Bmh33Qw2KiPh83xHt23nkOzSD XuoayO+1+w6cUxluhXiXlzvPhJDQohzugMeXYUHOP00KclnDMHySW4DbmX36jt9JASAb /H4VXbwLIqiAuvRWc3+Qe5+gOl7+8YRMJBBZRTmROLASxq1qM44kfxjyUDijT7OMOc02 sWENFvHAPh07hvJ/79xkkqpCxs+GxO2bvr5ZzexCSikkhHrtn1UUGc9P/Vr/a0xqXN2l iojQKh+6m+wXYFCt3BQ8KmNHxmR8wJQP8gvJSRQLsoyGmcF53uax3eCEu4bICgCCodrE Txgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sLo9HMVk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 1si5935701qvr.215.2021.06.25.22.05.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:05:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sLo9HMVk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44888 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0VG-00047w-6M for patch@linaro.org; Sat, 26 Jun 2021 01:05:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TP-00070e-JI for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:19 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:36748) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TN-0008Ig-Ld for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:19 -0400 Received: by mail-pf1-x433.google.com with SMTP id 21so9149693pfp.3 for ; Fri, 25 Jun 2021 22:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g3h9YxZHLsVNN60AWZleqPTLbakgmZoZFD5TK6oju4Y=; b=sLo9HMVksCaXtA46fjcs1qjtCEFD+gAA58p1d6I1DSGk6+ojkl9eQ/FnEYfOcs6Bhm qubciNfmM3q9BSuUhw0iPEQ6wimBEpoWvFKVJUtcQ8aH4aWaaVVgO2xcNEhehGdYiQJi C0zeefI4UomIXFa+xXOmPhMff0lIl8G+Ke5MvbI8jYVlY9z2bchgWabfhnXeS2m54q9e Le/OKH9mVuTNAZr12PjZYXu/h7aJ34gKnRYdbc9imzPBkLDtzFEqWW3WJksO8V4H1nev qlPaCZ7mp/irY1Wf3uI/XTxlbm+ZV4rYPUnfqr4HKkmvfSHtrxI7DEHXsTMERUaxuk7B 7z/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g3h9YxZHLsVNN60AWZleqPTLbakgmZoZFD5TK6oju4Y=; b=mgxCgexzrZ80wzQTBsUe90y4yMg8nCnrUK5SuV+W5+wnlJNC3zAhmrnUJdyFiRVMiF X0BGnkuUqN3+bZahu+2zBEJYqV+XvdjVC5TfSr5fhy1WYLNrwQ5o481UZm6NJE+H2HGM mf3zO6BeZvPM4/3RgI9FFF/M7FUI5x7A4YBrdT5PmxIC5X5AEnbk7bkatuP6MIhlMzkj r4PvCVtge5ZR1soVKcqLd0l60f18rUAKPnKUhgTKn+OuSDPAd+5j1sbzL/c6lh5qBqJ+ RNykOkN85cRIx/30SAznmZBZfUhQnvNH4StY71gH49MXwLD3QMMR2kT7oZwFQJ7lZdr/ htZw== X-Gm-Message-State: AOAM533lTOjOykyvpIspksW0E/P6vJLfWdz3xgK9SWdgp9h1eV0PW69k fdoTvXP/pwAgqrF3XU2pQf89W+znx/BBkQ== X-Received: by 2002:a05:6a00:806:b029:307:3ffc:f6bb with SMTP id m6-20020a056a000806b02903073ffcf6bbmr13907366pfk.44.1624683796389; Fri, 25 Jun 2021 22:03:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Date: Fri, 25 Jun 2021 22:03:05 -0700 Message-Id: <20210626050307.2408505-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.opc.h | 3 ++ tcg/s390x/tcg-target.c.inc | 63 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h index 67afc82a93..0eb2350fb3 100644 --- a/tcg/s390x/tcg-target.opc.h +++ b/tcg/s390x/tcg-target.opc.h @@ -10,3 +10,6 @@ * emitted by tcg_expand_vec_op. For those familiar with GCC internals, * consider these to be UNSPEC with names. */ +DEF(s390_vuph_vec, 1, 1, 0, IMPLVEC) +DEF(s390_vupl_vec, 1, 1, 0, IMPLVEC) +DEF(s390_vpks_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b96128760f..31287609cc 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -291,7 +291,10 @@ typedef enum S390Opcode { VRRc_VNO = 0xe76b, VRRc_VO = 0xe76a, VRRc_VOC = 0xe76f, + VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ VRRc_VS = 0xe7f7, + VRRa_VUPH = 0xe7d7, + VRRa_VUPL = 0xe7d6, VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, @@ -2768,6 +2771,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_s390_vuph_vec: + tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); + break; + case INDEX_op_s390_vupl_vec: + tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); + break; + case INDEX_op_s390_vpks_vec: + tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); + break; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2810,6 +2823,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) return -1; case INDEX_op_mul_vec: return vece < MO_64; + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + return vece < MO_64 ? -1 : 0; default: return 0; } @@ -2865,6 +2881,43 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, } } +static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) +{ + TCGv_vec h1 = tcg_temp_new_vec(type); + TCGv_vec h2 = tcg_temp_new_vec(type); + TCGv_vec l1 = tcg_temp_new_vec(type); + TCGv_vec l2 = tcg_temp_new_vec(type); + + tcg_debug_assert (vece < MO_64); + + /* Unpack with sign-extension. */ + vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, + tcgv_vec_arg(h1), tcgv_vec_arg(v1)); + vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, + tcgv_vec_arg(h2), tcgv_vec_arg(v2)); + + vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, + tcgv_vec_arg(l1), tcgv_vec_arg(v1)); + vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, + tcgv_vec_arg(l2), tcgv_vec_arg(v2)); + + /* Arithmetic on a wider element size. */ + vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), + tcgv_vec_arg(h1), tcgv_vec_arg(h2)); + vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), + tcgv_vec_arg(l1), tcgv_vec_arg(l2)); + + /* Pack with saturation. */ + vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, + tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); + + tcg_temp_free_vec(h1); + tcg_temp_free_vec(h2); + tcg_temp_free_vec(l1); + tcg_temp_free_vec(l2); +} + void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -2888,6 +2941,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, tcg_temp_free_vec(t0); break; + case INDEX_op_ssadd_vec: + expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); + break; + case INDEX_op_sssub_vec: + expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); + break; + default: g_assert_not_reached(); } @@ -3048,6 +3108,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sari_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: + case INDEX_op_s390_vuph_vec: + case INDEX_op_s390_vupl_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3067,6 +3129,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_s390_vpks_vec: return C_O1_I2(v, v, v); case INDEX_op_rotls_vec: case INDEX_op_shls_vec: From patchwork Sat Jun 26 05:03:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467429 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2140250jao; Fri, 25 Jun 2021 22:11:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxrX1bGktruenu3pTiDW24zWKvuAup1KllCpi2eojN47NytcY+VFssfrCHDE8FcLqBFcZyw X-Received: by 2002:a05:6214:c89:: with SMTP id r9mr5873028qvr.40.1624684315669; Fri, 25 Jun 2021 22:11:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684315; cv=none; d=google.com; s=arc-20160816; b=opIWbvFVihXLrFNbGyxwuTWzu6jOsjGZ2virN0wbIF0Y+KS63TBl3BF7elzsvdWFe5 oKRbd3VsLc5LqC5bj1JpJcIJjBbYBi5/qvWYUCbsKiu6HKarKHSFBTTC+IEAEnOUz91d tNGdMauMMvW/7TxpGfxFWHhUaepAPpH4Sgu6vZScgrPL4aA5cuiWybeMDHv3AesZbCH1 UtOwk1wmhNIh6ZdeFS1+TjFsDAFkgomgkbLWP9FKNbp0HSxbhclw+F0Gh3MCVlNsaIM/ 76Ffs6gJ3OKEDrx3Q4OyjvzckIq7OEBtPxbFvjzKQHeroKO1QrIm+U4C6hiGV1Z7o3vJ MnOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GzqaqmGUsrCv1+6dFCQ8KH8rRMTBVbDCMJeps2UiJvs=; b=WjHofE0tszYRhF7LOEVQZ1fKd/4g98SaxcrABGK4+4AMBzUJyh8J3IvSTvmCWXkPnW pwdqhCicp7j71pfTW9MSJIV80Z994pOxAkti78663up1QHn0GvVKnOYE69BBT5hhr9nl Oaup3chJfFd97KmGU6OQPZLTuAl69mv9u0OkhOSMRoUk04RzZel1jBG7rZWtWql+OBg2 LihMvJgXXDfVW5Bp5a1fzTqYh2BtsCa6LZrG/IQcfvoErzVtJi3IxjUlI5v1OnEdTFmS Xp9Y9LzUt7wc9NRf5keyUSZ7sdv9ZmQpC4QLgOUXmYzsPf3bp0ms3rmFhrAyRCUVRa8V mKow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="AYrS/7P6"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a22si2223048qtx.257.2021.06.25.22.11.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:11:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="AYrS/7P6"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0bj-0004Bg-1C for patch@linaro.org; Sat, 26 Jun 2021 01:11:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TQ-00073d-Ac for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:20 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:45678) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TO-0008JL-DV for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:19 -0400 Received: by mail-pl1-x633.google.com with SMTP id i4so5774929plt.12 for ; Fri, 25 Jun 2021 22:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GzqaqmGUsrCv1+6dFCQ8KH8rRMTBVbDCMJeps2UiJvs=; b=AYrS/7P6nwql+ZyOZvWQO3x2FuIvGHOdKSOmfL/l0Fup9inxYN6un4jy6PWu6OzO/b n8a8yZpTI8owGfQSclu9Ql2iBy7D8I7n3G3QWfwHILngVWudLim+RgzJnof06/c61llx pTbKiG25GUr3QSH+eCl0zcYvoYYlNrz1nDE+QE7uu+t0MsUw0csEuJkQURUFbpnz2GsT PTkXM+tqlEKDs5zamifGiUJimGcjy530T5Hfptapb0magw8gErBUXHuXwlNmdfeQpM0X 3Bj7oclCAvnEE42qpKzoCS58HDnmgWrPxeA/DZnvZTOf0pYamsdI/I7UkDK8zTixYoXn DY5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GzqaqmGUsrCv1+6dFCQ8KH8rRMTBVbDCMJeps2UiJvs=; b=ehcjEvuIXP+f8+2emxo9QKnhwj9f10IZDWwkfagJmKpUx+ocZe4DgfGq5zQ6UP9THv lOlRzPTCEj5i8YHtCIH1b8FmAbIjZz/rpy6QwCwYwdjqzBo8chjmhESCCcAO7wQVZ9uu iZxIu7JJ6VAtQb5SSbAaEe/4O9GFLFpWWaXe0614XQ6UzO9TKn3/QSauWN+PJmVk9JKY y89O97R2WrxP82Q+hx3btBRVKiRXGkc2IW0jISMzox3c21tpgUhcvKsu7kZI2eN0uWsm KfoyQIlrMwosreMtXaAFGX2oouCiF4G/BDB93GW2WO5K9IrwYPaPiyx7uy6yEUqHub+n 7ypw== X-Gm-Message-State: AOAM531RhlRqfsM2w+AQeBMXeJfmInHIVqn3YmPt4aGao2vQgNEqiORQ gG1Xs7p67ll8i4YXdMtUbxlukN7jk0sUZw== X-Received: by 2002:a17:902:be0d:b029:11d:6614:88cd with SMTP id r13-20020a170902be0db029011d661488cdmr12481628pls.40.1624683796856; Fri, 25 Jun 2021 22:03:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Date: Fri, 25 Jun 2021 22:03:06 -0700 Message-Id: <20210626050307.2408505-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 49b98f33b9..426dd92e51 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -26,6 +26,7 @@ C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) C_O1_I2(v, v, r) C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(b, a, 0, r) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 275f980cee..b38b346319 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -157,7 +157,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 /* used for function call generation */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 31287609cc..4a8d9f2f6a 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -296,6 +296,7 @@ typedef enum S390Opcode { VRRa_VUPH = 0xe7d7, VRRa_VUPL = 0xe7d6, VRRc_VX = 0xe76d, + VRRe_VSEL = 0xe78d, VRRf_VLVGP = 0xe762, VRSa_VERLL = 0xe733, @@ -637,6 +638,18 @@ static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); } +static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_debug_assert(v4 >= TCG_REG_V0 && v4 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out16(s, v3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | ((v4 & 15) << 12)); +} + static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg r2, TCGReg r3) { @@ -2755,6 +2768,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); break; + case INDEX_op_bitsel_vec: + tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2795,6 +2812,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_add_vec: case INDEX_op_and_vec: case INDEX_op_andc_vec: + case INDEX_op_bitsel_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: case INDEX_op_or_vec: @@ -3136,6 +3154,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shrs_vec: case INDEX_op_sars_vec: return C_O1_I2(v, v, r); + case INDEX_op_bitsel_vec: + return C_O1_I3(v, v, v, v); default: g_assert_not_reached(); From patchwork Sat Jun 26 05:03:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 467428 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2140118jao; Fri, 25 Jun 2021 22:11:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhBxrQTFUznaIlqohfWDA1V+KlwyiK7sU3JVV4dhJ0IpWtdTCaaBWTxAXbVsbxs9MkrE0Z X-Received: by 2002:a37:4197:: with SMTP id o145mr15063521qka.75.1624684303375; Fri, 25 Jun 2021 22:11:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1624684303; cv=none; d=google.com; s=arc-20160816; b=SJce+RUPB3hub0WxASH9vLEBfSG+WVq4mmcO/tjGgLxj23sD05agO6R6ZsaO+5l0xa iZzEGS+BbVwdg8d09q48Hpl8FBX8LwIIc+ujmJsa1TCGhjC4RBxVn/0D7WvjQH7NGuZm EgHDkEGsrjf/QAlY7OkyyDGKZZKXovs8tFyGCiBa4Vxs2jJjR4EtFvFXhsEJEEq4wwdF qqkyggS9Sz+7lZEMSDtLQMvZ7Yi9axUpAJ3jYOjk1uqrsCg3g544lQxvbGgZgoPDxBV1 P1Oz26a+s4taWP2FUKHWlEQQOXsFC7oAVzhgIf2J1F9Bp9ENY5IvrGeIhyZgYpVfa+US nmkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=z/5xxE2+UtklPcwCantXm0ZBLWNrDIZBlcYNO8A1mx8=; b=V8y6i2gLDoaOd6BBUHmRLTtXXA5owUXe11GXbdv3QP7l3BGk1yKw5057SVMWtaDGPf kT/iKOwJei62M1qRa/9rS9oIl8IA0pg9vAoZSXutb1WPSWZnsVmT9boSLVVNnJWOULRj ZlVKPBizxi3bmWhdY8TfjI4lcgZYjeEWBPQFd5+eY4UJtfperPSprc1KnghC9LN+OElZ GcxzUVji37GOzuYAFcAcTRE8FxMzPJe2juPMpalKSHhsYvL9oyY2OyXuk74dasMpIEfE aJSpmmSIAwoBZiYimQlFLLCJLMrq+v+2+WcyNJ0isr5Lz6bFWj84ykpsCws4CsWev2KW rLwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bt6glOgv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o15si1235673qtm.372.2021.06.25.22.11.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jun 2021 22:11:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bt6glOgv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lx0bW-0002xG-SG for patch@linaro.org; Sat, 26 Jun 2021 01:11:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lx0TR-0007AN-Pq for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:21 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:38630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lx0TO-0008K1-V4 for qemu-devel@nongnu.org; Sat, 26 Jun 2021 01:03:21 -0400 Received: by mail-pf1-x42c.google.com with SMTP id c8so9140262pfp.5 for ; Fri, 25 Jun 2021 22:03:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z/5xxE2+UtklPcwCantXm0ZBLWNrDIZBlcYNO8A1mx8=; b=bt6glOgvIG2oJr223/IrGDHbnGd27N0+CEm98QCcjhgmKkqvdviTmZEf4QQIZXnQk3 EI9ECEgTF5umcJKH7fWWtuvDbe6Ew6Blw3JK6mrsjqhyy461++0zbV3T800RFp6l9Jcm RgAblrv4MDeoHqJxRVhC60kxLlE1PTdbY2Y+aK3p7BNv9r3pvXPAhF5k9QBVEeWXKUri awnRWgQ1hDDrF1YgbW2KFMx4eWId5N/wxMM9faJRIAWN6e/twJ5yBGLo4EAZUyBQY6UB mGOY/pWn96J1PD7B4raAt2RgrXBSqrGbanm4urhLv2GHZ1O8ANK+e74JLw7GOZUoQ8WG oE+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z/5xxE2+UtklPcwCantXm0ZBLWNrDIZBlcYNO8A1mx8=; b=qb3XIywpV9KDZEMKMXgMM2dMU4eZIwej5koBZaNCOMim6tLqtuys+f+31j6t3hSFow 4fXtxZkOsBIRSkfPKSLuzb9CFu9z2DFASWZUIGhMto/WIT6kx0svitj3UrziDAGvz4jT vXrcvuMKDk3xOF2o3bUcDi4TKUWkuP+aB3qRIU8Q8b5g7nNrh4mzWuz0wibK58x1MUQW PrVNKpVYzvEF3fitdzQZtkkQQracsBKhsc4juS4V8eG2VhNm++W7gpzEgCP7jDVEE2Ly laIYqrBpQTvXqSC+MMuapuO9MboYW7kP8ek1pha7QscXEzjNcHIe8gzE0gp90TImb6rL ruaQ== X-Gm-Message-State: AOAM533FMREOqEcXXTgvzg2Ap+eqYZI72+5Cyjn3vgpYFK23X+Oopt8M hdjljFalvxftBVKoRs709ng9876rHUKFQg== X-Received: by 2002:a63:a551:: with SMTP id r17mr12799059pgu.97.1624683797640; Fri, 25 Jun 2021 22:03:17 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id c62sm7389768pfa.12.2021.06.25.22.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jun 2021 22:03:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Date: Fri, 25 Jun 2021 22:03:07 -0700 Message-Id: <20210626050307.2408505-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626050307.2408505-1-richard.henderson@linaro.org> References: <20210626050307.2408505-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4a8d9f2f6a..2741d6f177 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2837,6 +2837,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: @@ -2899,6 +2900,21 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, } } +static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec c1, TCGv_vec c2, + TCGv_vec v3, TCGv_vec v4, TCGCond cond) +{ + TCGv_vec t = tcg_temp_new_vec(type); + + if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { + /* Invert the sense of the compare by swapping arguments. */ + tcg_gen_bitsel_vec(vece, v0, t, v4, v3); + } else { + tcg_gen_bitsel_vec(vece, v0, t, v3, v4); + } + tcg_temp_free_vec(t); +} + static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) { @@ -2940,7 +2956,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t0; + TCGv_vec v0, v1, v2, v3, v4, t0; va_start(va, a0); v0 = temp_tcgv_vec(arg_temp(a0)); @@ -2952,6 +2968,12 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_cmpsel_vec: + v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); + break; + case INDEX_op_rotrv_vec: t0 = tcg_temp_new_vec(type); tcg_gen_neg_vec(vece, t0, v2);