From patchwork Thu Aug 16 07:54:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144329 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1760449ljj; Thu, 16 Aug 2018 00:55:37 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzKXvQVIQwT0CR3yEg84Y634/1ir2ex9IImfv2oJvLjRw6K0ECUalA4wkCf+Qfz5ZPfmQjv X-Received: by 2002:a62:9c17:: with SMTP id f23-v6mr31303069pfe.209.1534406137601; Thu, 16 Aug 2018 00:55:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534406137; cv=none; d=google.com; s=arc-20160816; b=dWe/kMOFykPIlJa7EAUg+pJ3kCm2Tl05xUR/w4Zz0Ayl/UZH9+e0wkphrdakV80KJt /HuB9J3Jc2q8cWD7ZIRhNUHRzTbivy9p6slNtD8DtUw/1I1ShfqccLdTPsjAoJKcGnQJ IRTf+X1ZEPntY9BT355Kp+P3zGvvWvWScCqum00IlI3ku9rB/To98AUv3SBtU/dyUvGT BF7CmaEtnW09SCydU0F/YdNln0E8+8qZJq4yMTuRmiZP9fC6wllSIkYT2DBJh8MyNhOU 6z0YUKmSYULRgwhHf5tOjQSpUdXncseWWy3B+0YrFNeGGU3BvEB049qCTesO1wZELfJU 9ykw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=CShGfILZiCj5oq6dXKbYu8VopCD8AIo780MxeAwT1rs=; b=gpcp6rFXwjNQXNBDxJ563304iaWTNDnFl6ICZCwvIV10i0awLxqjknChFIUWtyZ4lY duy0kBYF4kC1fQyz9NapmidGpeOHtpJ9FLtmeds95fChN2DeR3zqF5N3oDkhMYd+v9Mk 9BbT9WLg9A+5B093M3igS0pWly22Nl7PdKGc4Is3UaNDfBnfNORDmj2oUIUvevwGC1PN YPg+hCFlY99zEaYoKa3DA/OqDE284dVuaRhLoPNIu2s5McgMJ+X8hLOgxSgD2k/0NEOs 0+iSycFvbaj1V8GJsULD/jevIvEaRyIdFt+mVAEpN0yRa9jkTVLxQLMs3vlRvfMZBAA0 YGqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ET1fJ3XN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v16-v6si25931282pgb.96.2018.08.16.00.55.37; Thu, 16 Aug 2018 00:55:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ET1fJ3XN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389619AbeHPKwQ (ORCPT + 32 others); Thu, 16 Aug 2018 06:52:16 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:41071 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389605AbeHPKwQ (ORCPT ); Thu, 16 Aug 2018 06:52:16 -0400 Received: by mail-pl0-f66.google.com with SMTP id w19-v6so1690041ply.8 for ; Thu, 16 Aug 2018 00:55:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CShGfILZiCj5oq6dXKbYu8VopCD8AIo780MxeAwT1rs=; b=ET1fJ3XNrpoP6VvxveLLPrrofgZYY0LYfb7d89l0/SjPQIAHzRTJf2AhElQBXvTqqt myh19JfuCZmQVf9SgtMGzUNsCsPh/oQ+olmfVTylcOGPvKF5p3K6EI+ARGtan0PQISeK aVqDJAPPONlHV9TpScmes2BmeTkYBAZGRSF68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CShGfILZiCj5oq6dXKbYu8VopCD8AIo780MxeAwT1rs=; b=MRhP7BQVvaOL4ovDqFyR292X9++2GXjW1Jb57XX3ViXV84IG+k3SgTLtY1mHeILtUm CutA4mnx+Q3rrvJ2LXCwJquHLDJ3PmxunB71qtri+hEvaq2H6TkY2Mfzrh8EHXt0AvoH W2jc5UUT7rtoEQ0ghYaSKKV6j5zf0vZ35ltlpRAIddZC/x7h9840/tnPPmmYh9/uAu2D 5Aac/XtilzkAm6LrGAYGfBd8fw0NDuGuMSn3OjmOQPMBj70h3SEs8calRmT/g/TlENw9 7bL4NVcfwe9HWxwxLzNDyhzz8AqFdffq5oZHzmCtY02P/fBm20VobDELyIQOz3EqBBEk xJmQ== X-Gm-Message-State: AOUpUlH6dlVtAsA8Swpi+g5kuQzQu5XnD2ZN/19qzgDiIN7qBbJfjD42 tRWf5uDBtRTVkKfwfC5oOC8zEA== X-Received: by 2002:a17:902:9348:: with SMTP id g8-v6mr27568080plp.302.1534406134469; Thu, 16 Aug 2018 00:55:34 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id i25-v6sm50838137pfi.150.2018.08.16.00.55.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 00:55:33 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang Subject: [PATCH V5 04/10] mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode Date: Thu, 16 Aug 2018 15:54:18 +0800 Message-Id: <1534406064-10065-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> References: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 92 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 12 +++++-- 2 files changed, 78 insertions(+), 26 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 1f0f1e4..1dea1c4 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } +static void sdhci_config_dma(struct sdhci_host *host) +{ + u8 ctrl; + u16 ctrl2; + + if (host->version < SDHCI_SPEC_200) + return; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + + /* + * Always adjust the DMA selection as some controllers + * (e.g. JMicron) can't do PIO properly when the selection + * is ADMA. + */ + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (!(host->flags & SDHCI_REQ_USE_DMA)) + goto out; + + /* Note if DMA Select is zero then SDMA is selected */ + if (host->flags & SDHCI_USE_ADMA) + ctrl |= SDHCI_CTRL_ADMA32; + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + /* + * If v4 mode, all supported DMA can be 64-bit addressing if + * controller supports 64-bit system address, otherwise only + * ADMA can support 64-bit addressing. + */ + if (host->v4_mode) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } else if (host->flags & SDHCI_USE_ADMA) { + /* + * Don't need to undo SDHCI_CTRL_ADMA32 in order to + * set SDHCI_CTRL_ADMA64. + */ + ctrl |= SDHCI_CTRL_ADMA64; + } + } + +out: + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; @@ -913,7 +959,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { - u8 ctrl; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1009,25 +1054,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } } - /* - * Always adjust the DMA selection as some controllers - * (e.g. JMicron) can't do PIO properly when the selection - * is ADMA. - */ - if (host->version >= SDHCI_SPEC_200) { - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); - ctrl &= ~SDHCI_CTRL_DMA_MASK; - if ((host->flags & SDHCI_REQ_USE_DMA) && - (host->flags & SDHCI_USE_ADMA)) { - if (host->flags & SDHCI_USE_64_BIT_DMA) - ctrl |= SDHCI_CTRL_ADMA64; - else - ctrl |= SDHCI_CTRL_ADMA32; - } else { - ctrl |= SDHCI_CTRL_SDMA; - } - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - } + sdhci_config_dma(host); if (!(host->flags & SDHCI_REQ_USE_DMA)) { int flags; @@ -3503,6 +3530,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) +{ + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) + return host->caps & SDHCI_CAN_64BIT_V4; + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3574,7 +3614,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_can_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3608,8 +3648,8 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; @@ -3617,7 +3657,11 @@ int sdhci_setup_host(struct sdhci_host *host) } host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; - buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + /* + * Use zalloc to zero the reserved high 32-bits of 128-bit + * descriptors so that they never need to be written. + */ + buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 5042c23..f95eda2 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -205,6 +206,7 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_SUPPORT_SDR50 0x00000001 @@ -309,8 +311,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Thu Aug 16 07:54:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144330 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1760517ljj; Thu, 16 Aug 2018 00:55:42 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyjb3iCGTWio2oTJloQ9TdoBzL44jNCpzPub8Yo1i1f34X4rvH9LXXksqfc4ZMBTR0Vh13U X-Received: by 2002:a62:9f85:: with SMTP id v5-v6mr31105276pfk.27.1534406142233; Thu, 16 Aug 2018 00:55:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534406142; cv=none; d=google.com; s=arc-20160816; b=rjeXNYzKJNYOHt1KSRVtWbKyJ+VqQWg5TpXMyoBzQIFqiiQ+M7gRZ+k6sUP8piCo3W WpJbHitY9Q7Po2UkvGHGe5Y0QvQXMozdIon67Lgdwl04XRgAp4tzCQt3iVa7L91k2B2u ajmzdQUKE0ntoVOE8CElDbALcXDhUp+5SUUxlqQnPJeuSg967B87uzJfeLJNIg2mz0hW YdWMCsq6bEK+8ik+7wXY5jrxVEEvV9xxMPeUDroWypYLXtCoO6GN4eal/uOZ7K225kWZ 7gB2rHZRCaVYvn7OZ1crxudjpUn9GJWg237o9L6aGjjbmMV/8JxJt2BrtVtdSMn22Xkw fZDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=tfDeQ46/C06dDmQGL2FRTZ/CLblF/VG3NSDxyH8wH4w=; b=hel0XuxiJ4yeZA6JH5q9oFz3TmehA1X01PVfapchbGz95BziyTe+0wA+nTDeP5q+B1 fI99ywIolE2IK+05xMEdbKxJcIA6Bf4ORjM2wfcESGVcil7VyaVZjvjA3/rIShEHs4cF t7GFZTmOJ8tEz7PyArzMH0NXbNE1wYs+IWPqniih6Zh1kJYHSsiduf6U22tC5z4Q0xRA Y1EKqJR/xJpv2OButzsf9RXKdhz5Mr9hsqUSi+Hd81je5eZS125t4DVEZGYk3RmArC1A COPdCRW5vfukq022vAxf9AtM4ndyDA6YfIWp8As5ah9rC1h630B1z/9s6VWAzifdw28V gwZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kBJ4VkwC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r29-v6si24354997pff.24.2018.08.16.00.55.41; Thu, 16 Aug 2018 00:55:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kBJ4VkwC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389636AbeHPKwV (ORCPT + 32 others); Thu, 16 Aug 2018 06:52:21 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:36315 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389621AbeHPKwU (ORCPT ); Thu, 16 Aug 2018 06:52:20 -0400 Received: by mail-pg1-f194.google.com with SMTP id h12-v6so1693612pgs.3 for ; Thu, 16 Aug 2018 00:55:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tfDeQ46/C06dDmQGL2FRTZ/CLblF/VG3NSDxyH8wH4w=; b=kBJ4VkwC9a9Fbirw66Hnp5sdsmCCI8q0uYUhXaBz6N7sE/jng7Q+QbtCGZzCCHbqR6 yCdkD7I0t2B3TkhuYvCfqu0Vz+RZKwo8GIxZk7IIRzt1xu3nY95aYKrQk9ZoeAjsKJdG gGILVBBogtccB3JDBgR6S1crxtgk79kenIIHc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tfDeQ46/C06dDmQGL2FRTZ/CLblF/VG3NSDxyH8wH4w=; b=oPu/jxs9ZfOXlYHtx41DqcfbZwstfc5QLousjZ1F+72IYRmTWZ5ncp2jjaG9Q+3i7i +P9ed7YCKLYZ3WtXLtGhUyRlMjMpqYP5DTlxBwtwjPHmMVcZ7Knoysb3QvFq6EzSgcWy giPnQ/ofk0A1HyJailODDlNddOntIcAZzOzv+nxQawaDRVmHv/jVloTOYBOz/dG+Cs+H Q9Aplnhq2xkvlNPuT0vnHetylsO42kzLEJhGdzxtmXF5doP5Fbu0mF3fUa7adVZJt5qb OGjXJ0oQiIxB+iq6dGBUN9Ic9ulszJ/vyWQnTgGDMFR/3G1W0tb88vW08F2LKzmAk41k l7cA== X-Gm-Message-State: AOUpUlFAsgXKlnq5ibsNkWQEHK8gpQD2yAM+UCFRsn/yLQbQRFV+ZDky Ket5DQHkxcRpBLb4WRCnzuJabA== X-Received: by 2002:a63:5a5e:: with SMTP id k30-v6mr28479313pgm.123.1534406138967; Thu, 16 Aug 2018 00:55:38 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id i25-v6sm50838137pfi.150.2018.08.16.00.55.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 00:55:38 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang Subject: [PATCH V5 05/10] mmc: sdhci: Add 32-bit block count support for v4 mode Date: Thu, 16 Aug 2018 15:54:19 +0800 Message-Id: <1534406064-10065-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> References: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 1dea1c4..b3328ee 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 16-bit Block Count + * register need to be set to zero, 32-bit Block Count register would + * be selected. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f95eda2..d34971ac 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) From patchwork Thu Aug 16 07:54:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144331 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1760578ljj; Thu, 16 Aug 2018 00:55:46 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzszxBjHMtYgEEvtgAonLGVCI7wGOSr69apdyQuCsvqiua95RLbhZMWGUHzrE6XSfW2llDd X-Received: by 2002:a17:902:7587:: with SMTP id j7-v6mr27511574pll.256.1534406145951; Thu, 16 Aug 2018 00:55:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534406145; cv=none; d=google.com; s=arc-20160816; b=fqKKD8fdLlFsPKoWz288FxBhaOxpNJJz+AJFV4ERKmklwR1vZc84o+1ANwqmWQvvLs HeT5VIUeiKWsZUMLa+IXlpZ8BedPtoIUeWQ55nMkjffogAsHy0yI4G9UkOWne+kE0vPq Pp/aKYu0zewQoVUEPlHWMxLviUTeF0RTA9AUEYljWorn2JUg9Lw2bkXqMl7T75pYDoqW F0QRDLwjo8W504aoCyMHfaRnrjqQxwg00w+c4X00rbA3sXM61HxoqiA1Pv0mB3593iUN z+Dqc6VWRcKJp+zstOGhX8N0XKLGAAgxr+dtZPcVC1U4Tho3QFSsCCb5ALVEhSJWWqSq moHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NP825gJ8JNuiSBQ93C487DDun4LcomGeoIeRKjPEd4E=; b=uH1GdnhlnnVqC3oF2oM6drbCuXnI5ULNoqL9938lGSkMlZYhYFO8CYWTi4l4Fa98ut 3tVWh7lh+pGU6HFFr0AlgT2SS6fy+/VdUA6FiCXxH+ANN4AYA2slW2jXfluARPKXIMI6 p2blyguTL5SEYzQy9yLjr4gJRuXdyMlzv6HcMm9MtbvWFobZ3leLdvBtzxdJja2LiDEE vDv2C0hh0CPoyJurnm7ua54iZqFHcHi+IlCaYOCS515AiCGbGce5UDca5ORdMRE9Fxfx 7zn/oSHmKDV0FfYUFXDg2di/9sDuXPAVLZPUZnG2mARe0IYbhC2cVd1cYiBB8hvNjLcM PEQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iDGPLbmI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r29-v6si24354997pff.24.2018.08.16.00.55.45; Thu, 16 Aug 2018 00:55:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iDGPLbmI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389648AbeHPKwY (ORCPT + 32 others); Thu, 16 Aug 2018 06:52:24 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:45427 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387985AbeHPKwY (ORCPT ); Thu, 16 Aug 2018 06:52:24 -0400 Received: by mail-pl0-f65.google.com with SMTP id j8-v6so1688931pll.12 for ; Thu, 16 Aug 2018 00:55:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NP825gJ8JNuiSBQ93C487DDun4LcomGeoIeRKjPEd4E=; b=iDGPLbmIJ0zPSpBy4lvB8EsQDHX7bRIdNAnDQFxtLduf3kOyfVH3f5adiNBSpZKDBF xc9JfZ8EY3ZitZ6p8O7WEMmc+zDD3UHkLp1TQehl7w+U3SRwy50JXNAeh2P7vY43BRSr gZ10x2M0XlKL5jaMHAvZ4vh37FymuwrLdcOuA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NP825gJ8JNuiSBQ93C487DDun4LcomGeoIeRKjPEd4E=; b=fv0Smzx6cnrNhNLa3EL6F7Ihjz3DPPYgzqADMBoWVHxv9hoRAsoY15mNqHNR40yy5L I+wJ5nMhXJvoDJOp5fqW/YTQz4jzVAwJ7itjeENCbRz/J2vnIzXSBgRq2X2CSHa+e24s cXie0lmJw7Hapl/mJPPxvbUoM6F0siHUbBG7sj2m/kDzPgzWnBYlS+fS1+pzTO9bHldv w8H0iRlaP1Rz4OZTiUBx5sMiR+r35PxofVmX6VvDaSkZhPa+KtpobAB3IMA0FMuFeixx UHsAC9k4fyhqjNCru9BnqVoOF+qsL2sybrPwMxULSpel0S8KKKgtHUq/zm2oFE3Tl17Y xl2g== X-Gm-Message-State: AOUpUlEwUV8t3Q5vvoWGgpQpMpQtO7OVdSqj0Fd7PWiFfx0VMvncJo5f VMGHqGuvbz8rugmNUb1p4bWvHg== X-Received: by 2002:a17:902:7d94:: with SMTP id a20-v6mr21648113plm.19.1534406142962; Thu, 16 Aug 2018 00:55:42 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id i25-v6sm50838137pfi.150.2018.08.16.00.55.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 00:55:42 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang Subject: [PATCH V5 06/10] mmc: sdhci: Disable auto-CMD23 if stuff bits is set in CMD23 argument Date: Thu, 16 Aug 2018 15:54:20 +0800 Message-Id: <1534406064-10065-7-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> References: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For version 4.10 and aboves, SDHCI_ARGUMENT2 is also uses to indicate 32-bit number of blocks, it doesn't support stuff bits in argument of CMD23, but only block count for the following command (CMD18/25). Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 9 +++++++++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 10 insertions(+) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index b3328ee..a72ad0d 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1729,6 +1729,15 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) } } + /* + * For version 4.10 and above, ARGUMENT2 register is also used as 32-bit + * block count register which don't support stuff bits of CMD23 argument + */ + if (host->version >= SDHCI_SPEC_410 && + mrq->sbc && (mrq->sbc->arg & SDHCI_ARG2_STUFF) && + (host->flags & SDHCI_AUTO_CMD23)) + host->flags &= ~SDHCI_AUTO_CMD23; + if (!present || host->flags & SDHCI_DEVICE_DEAD) { mrq->cmd->error = -ENOMEDIUM; sdhci_finish_mrq(host, mrq); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index d34971ac..daf8c1e 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_ARG2_STUFF GENMASK(31, 16) #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 From patchwork Thu Aug 16 07:54:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144333 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1760698ljj; Thu, 16 Aug 2018 00:55:54 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyxL4GFWAQSOvpz5Wtngtca/cW5aRYMFBhM+RO3U5EDSLZSO+9/bVsli7IDqy+fkmMjT8jb X-Received: by 2002:a63:c24c:: with SMTP id l12-v6mr563467pgg.255.1534406154431; Thu, 16 Aug 2018 00:55:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534406154; cv=none; d=google.com; s=arc-20160816; b=qx0A4+uOYzmzWHm7+AUOkj7kUEYmlz2qT3WZNoikwH/JWIqmaj6Qw5XycccEKQvj20 RlzMwD6z4gp4HclZkmaAcb534UV52At+sesKmKZEKkMA4isEeTe698qx/c+HfbIiS5C4 1FDa5fU4QOSFCpKnj6BCD0k1QxUueiQm2kHEY88Pn9gZot2K+yiB4VpYDBqY0VyZf/vS RbPbEvdGqhKpLnCWpxyRJwM4v19EMAO1p0AcBy7R6rjDX03Qagd7zP7iuc8kl14YxIZ8 h0jYntXgTFovvUs56JC/nD29W0/U8GxgsiVhq9fLhQ2qYiO6J7u7sqJINR/wUbQVhnaz rhAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SEBlkogmEohz2U3nc5fI7y654TSOo9JJM7mLC82YFnA=; b=moqLAAYNPO+D0l1Dm63f9lBDPldxyfoaJzaQHfIe7H4QPNlYdz+xaxnlM5VqtjfNX6 +K8yEHDJkD+6OV/6MZasAElnBFXZMh/THQWorsIYB96o7tZuemkuLU8aNd5SjdbBAORo 5BjzxmAa0Bu2EKJ05myPe6nUaZ8svmkhOQm7BA7jD26rsJhqzSX6+d2mFTeV/UYUaTsW GjF8Hc4LxvI7oosNquyhgZUkti/hKZWE2+/JdG1BUKHYemuy0l6IKRlIvjUS4+4zMdvL Mm1VMbjerdliQw+PC95h/av+o6v7m1/gH8yIjIi4AiLdsj2bas5nfWQ995np/ywffHJL Rbbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=da46NtEU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f10-v6si23116824pga.559.2018.08.16.00.55.54; Thu, 16 Aug 2018 00:55:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=da46NtEU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389680AbeHPKwd (ORCPT + 32 others); Thu, 16 Aug 2018 06:52:33 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:39113 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389650AbeHPKwc (ORCPT ); Thu, 16 Aug 2018 06:52:32 -0400 Received: by mail-pg1-f196.google.com with SMTP id a11-v6so1686416pgw.6 for ; Thu, 16 Aug 2018 00:55:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SEBlkogmEohz2U3nc5fI7y654TSOo9JJM7mLC82YFnA=; b=da46NtEU5Ug4Om6wZtWuQHwd+hFF2zllHKs+JbYzsDUlbBfD0xGlpAhZf3CM3ZA5x/ +4VSvJ9xt1t5xOgkBwQ8atBx50t44vVkq+hRsOS1eLcbyjXhStvdLGuIrmee0HFgmhOG /VJllXsKy0CVv3XGxjujRG0vKJxMwhtkg+fqY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SEBlkogmEohz2U3nc5fI7y654TSOo9JJM7mLC82YFnA=; b=ss9jpua7krjNNZrcIgvGcXzUdDas1nEslCHMC7K2cRYWhvyiY3V4N4ssgLMDHx+Ujj TVNP2XUXErxadxdZWEIZ2F6XHOF0bWymlqnBfEcvBDawX/WboCakz1jS9AGHeSXmx85y 2s3Go1BjqNJfqIqhFSGm+egEyRl+Sn4iildkb1XseThuMow6JEdg3XHLXqjbRUeMEtrX BTG1T3QgPrJfXj/ghGazPZ5A6e4/LuoiQi4jC+GDSMPjDoYN7IpADhaHREKkGcQqRX6J S40iHmZMAzTyCMJMym4CJdX85+9HpUVnZaRQgdusK1aC6/qaf9zr52V4rqb587/idDEX 8zuQ== X-Gm-Message-State: AOUpUlGsmNgR8mMouy9xExXUFXALFzGKYdgcSG17Uq8Q6FbcM0FA9Zt9 nutSaYLlmfOt8C2hRa+ubgerpg== X-Received: by 2002:a63:28c1:: with SMTP id o184-v6mr27929422pgo.225.1534406151671; Thu, 16 Aug 2018 00:55:51 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id i25-v6sm50838137pfi.150.2018.08.16.00.55.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 00:55:50 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang Subject: [PATCH V5 08/10] mmc: sdhci: SDMA may use Auto-CMD23 in v4 mode Date: Thu, 16 Aug 2018 15:54:22 +0800 Message-Id: <1534406064-10065-9-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> References: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 06c2ae9..4e375ba 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3851,10 +3851,14 @@ int sdhci_setup_host(struct sdhci_host *host) if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) host->flags |= SDHCI_AUTO_CMD12; - /* Auto-CMD23 stuff only works in ADMA or PIO. */ + /* + * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO; + * For v4 mode, SDMA may use Auto-CMD23 as well. + */ if ((host->version >= SDHCI_SPEC_300) && ((host->flags & SDHCI_USE_ADMA) || - !(host->flags & SDHCI_USE_SDMA)) && + (!host->v4_mode && !(host->flags & SDHCI_USE_SDMA)) || + (host->v4_mode && (host->flags & SDHCI_USE_SDMA))) && !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { host->flags |= SDHCI_AUTO_CMD23; DBG("Auto-CMD23 available\n"); From patchwork Thu Aug 16 07:54:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144334 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1760760ljj; Thu, 16 Aug 2018 00:55:59 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyHdYItbGhLuy0MFSCte8IYlShO/8F3OMUUIfBge+yBDBkurvhKVkscUX63xVUl47qqJzOa X-Received: by 2002:a63:7b1b:: with SMTP id w27-v6mr26963535pgc.199.1534406159370; Thu, 16 Aug 2018 00:55:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534406159; cv=none; d=google.com; s=arc-20160816; b=gDv+96O3lMpYboYOuCUd5rjrsnQm7lWZv9mHNVJko1CemaLJsAaVP0YqRO+R0BFzwp 2w03o1oA9J7xzZMbkVM4VtOW0XGe/0cp9cvVYwQ29MKszSfl1LleGuaj8SZh2x5e0WTd XDKgXzVHy08xrfOdoBukbrqPxAaBDHVmVZ+idWJ1QXP+fJ+zGUeX40lregU6h/Br3et5 Ui3VPZbShPaCzCFI8wTD9rqFB6ZIZl1pub4KlHZEfPKtwp2vKa88VXElgzrsoUQOSJBn xRtkMcLIl8NyK47UfDuw4vs0oavwZtnhe5XFcYRE/Krzt7o5Y12uotTAlBNtzYFcmLgN HEGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=AHUpaOKEb5jDX2KGBW/rMugRvPrDszxX1Q49QsA8RoE=; b=idZ7zhyED3fkGA7sy7xvcH+V4ow8Ae9j819yBkkQ4nVXUOZYEqXzEoInmrFG9mwUWH i7Jjq1mV4P7SZ/r122yQ30vOxNG6utQJHtZ1km8POIqlw/Y+KwxoiA8uA8uBD7RKzu6K Y/mpQt6PF1x48bJ/0AXjWeIPR6AksxV3B7EJThvK1zIJOPznM5nCJW0nT9T1W8UTWBTR AaPv0A8fc2kzTAF9RaRL4nUYpZq8NGGCr+eEqXx4cB3QK/b/Tfyx2988kQXvdZczupWS hoWRv9EqVRnZr1DAHjYd0MI4cu2lM4dodz1oO9Ke82cj9GMbEdnsOOj/zRiHCm8x1ljq LnCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EPlBII8d; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 6-v6si25538624pgz.592.2018.08.16.00.55.59; Thu, 16 Aug 2018 00:55:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EPlBII8d; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389696AbeHPKwi (ORCPT + 32 others); Thu, 16 Aug 2018 06:52:38 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:42231 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389682AbeHPKwi (ORCPT ); Thu, 16 Aug 2018 06:52:38 -0400 Received: by mail-pl0-f66.google.com with SMTP id g6-v6so1693595plq.9 for ; Thu, 16 Aug 2018 00:55:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AHUpaOKEb5jDX2KGBW/rMugRvPrDszxX1Q49QsA8RoE=; b=EPlBII8dOyk+Dg94W+AwtwDCjRlGjLRjitSNoPH7lODV4enSnIm4JLcDA/vJLjfSZ/ ZucPBHRD7gNqoRcucT8Nj5WLX/ldwKDBJ1hX63EQv+efpbtQVGggWXY2QJGuTqCA6sbW ju2E9e1RbHK2ORJlyVDN/o6ui/fgNvjiVxnpE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AHUpaOKEb5jDX2KGBW/rMugRvPrDszxX1Q49QsA8RoE=; b=KkwxCzUjt/WNk2ZGcEeT3jpBZJ08G+PkUF6AEu+vg+6Te/LlG9FN1gxTfKaj1UmCQN 8CpAxkOAZlmgP+05WxlJzkZqwpFq9MCkDFdaGBNwJ+PtOCn76AJyHAb/EdQ90kZRe0JC WpISyVywwnqmolirwTNwWpDjpbHJ5i5bu7uSPk8otmtGI2x8t0i7Q053Hf5h7Uhi+lOd s3SrAUOa0oQzsiFtraAfPkh5VHL4xLx05EVJl97IuL+SuHDOu1YKnOllh6K4KlOuEk+e vz+0zEa/zpAcAZm0wASEM1iTAS8GBCvSVIdMi4keYMVWwE+cJq6VI/4SX5NSKU+mRT64 T/ug== X-Gm-Message-State: AOUpUlGqjqFlziJdB1RKYPcb8g+kFt+QspJ7p27okjG7FBT7JkKsalRR Hijh7gkq3T8RlLNsyRhzvvzatA== X-Received: by 2002:a17:902:6ac7:: with SMTP id i7-v6mr28365932plt.288.1534406156047; Thu, 16 Aug 2018 00:55:56 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id i25-v6sm50838137pfi.150.2018.08.16.00.55.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 00:55:55 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang Subject: [PATCH V5 09/10] mmc: sdhci-sprd: Add Spreadtrum's initial host controller Date: Thu, 16 Aug 2018 15:54:23 +0800 Message-Id: <1534406064-10065-10-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> References: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 464 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 478 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd.c -- 2.7.4 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 0581c19..c5424dc 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -581,6 +581,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD + tristate "Spreadtrum SDIO host Controller" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller in Spreadtrum + SoCs, this driver supports R11(IP version: R11P0). + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 85dc132..b0b6802 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o +obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o ifeq ($(CONFIG_CB710_DEBUG),y) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c new file mode 100644 index 0000000..8a5c3bc --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd.c @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK BIT(0) +#define SDHCI_SPRD_BIT_DLL_VAL BIT(1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* + * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is + * reserved, and only used on Spreadtrum's design, the hardware cannot work + * if this bit is cleared. + * 1 : normal work + * 0 : hardware reset + */ +#define SDHCI_HW_RESET_CARD BIT(3) + +#define SDHCI_SPRD_MAX_CUR 0xFFFFFF +#define SDHCI_SPRD_CLK_MAX_DIV 1023 + +#define SDHCI_SPRD_CLK_DEF_RATE 26000000 + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_enable; + u32 base_rate; +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) +{ + /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_BLOCK_COUNT)) + return; + + writew_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + /* + * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the + * standard specification, sdhci_reset() write this register directly + * without checking other reserved bits, that will clear BIT(3) which + * is defined as hardware reset on Spreadtrum's platform and clearing + * it by mistake will lead the card not work. So here we need to work + * around it. + */ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 |= SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 |= SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* + * Note: don't use sdhci_writeb() API here since it is redirected to + * sdhci_sprd_writeb() in which we have a workaround for + * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can + * not be cleared. + */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + /* wait for 10 us */ + usleep_range(10, 20); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + usleep_range(300, 500); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + struct clk *clk; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + host->dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &host->dma_mask; + + host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + ret = mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sprd_host = TO_SPRD_HOST(host); + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_sdio = clk; + sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); + if (!sprd_host->base_rate) + sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_enable = clk; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) + goto pltfm_free; + + clk_prepare_enable(sprd_host->clk_enable); + if (ret) + goto clk_disable; + + sdhci_sprd_init_config(host); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + sdhci_enable_v4_mode(host); + ret = sdhci_add_host(host); + if (ret) { + dev_err(&pdev->dev, "failed to add mmc host: %d\n", ret); + goto pm_runtime_disable; + } + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_enable); + +clk_disable: + clk_disable_unprepare(sprd_host->clk_sdio); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhci-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + int ret; + + ret = clk_prepare_enable(sprd_host->clk_enable); + if (ret) + return ret; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) { + clk_disable_unprepare(sprd_host->clk_enable); + return ret; + } + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11"); From patchwork Thu Aug 16 07:54:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 144335 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1760820ljj; Thu, 16 Aug 2018 00:56:03 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyXQh1rskduii+/ZG6KMV1QfosYW4+uRZCYpp0maVqKoDLproHy/dbZogLhvtvNiJvrdYb9 X-Received: by 2002:a62:9042:: with SMTP id a63-v6mr31311331pfe.52.1534406163437; Thu, 16 Aug 2018 00:56:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[209.132.180.67]) by mx.google.com with ESMTP id 6-v6si25538624pgz.592.2018.08.16.00.56.03; Thu, 16 Aug 2018 00:56:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TNUY490V; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389712AbeHPKwm (ORCPT + 32 others); Thu, 16 Aug 2018 06:52:42 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:37927 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389699AbeHPKwl (ORCPT ); Thu, 16 Aug 2018 06:52:41 -0400 Received: by mail-pl0-f68.google.com with SMTP id u11-v6so1700148plq.5 for ; Thu, 16 Aug 2018 00:56:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iMrql5pChvk0l0OVuaoPU9zdtIybInbwoq7vsafDp1A=; b=TNUY490V5PaPYtEl4kRP+eAAGofj223txKV/xltMRjW9UAIF0Gjyt7nVgWjdZID9hC yw6eBWwK8OLJhR0GxzAiuL+DVBApl3Xg9DEYJl/qQp3waWKcfy3x5YZVNx5n1lP1yBXN b3yEThJhvCcBrNh8rYxmV4iVCoT5i0Y/BShvo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iMrql5pChvk0l0OVuaoPU9zdtIybInbwoq7vsafDp1A=; b=YGNQbR66xnYpc3aPbL2kg7V514Ccw9/FzmwnCv+jN5A12xCth8J2/md9iuBBiImrsm WKtR2+yux1G/WeW5MzJNbKv8uH3reNFmwF3AKjtW7DIaMHIwiCNb8qVCp4eeByFSzJmp ZiaRKHBHN2e+o97NPqykgyglVZdVYfBp/b1zyQa/T79gpNbiRisVY++Txd9VxQp2rT7W PAygmXwSDylcRPQeTGjrCa5ogj7h1bXchFW6lmRRPSLrYUJTxM4DQcQaZPyc+0pwWYU6 bOEcIVE1BFMtjq5jMpnhVUL2KJ0bOsJY548IIL5jEf4H0CRBKl3966YBAHKYOXPYl/x4 LC0w== X-Gm-Message-State: AOUpUlHQsES5ofZuU4o4aLsjr5iIPUI426eM40goeA2xVFw1J+zGtguw ypJiBR+NixdJ0JxpV2GJ3VWicg== X-Received: by 2002:a17:902:1101:: with SMTP id d1-v6mr27431120pla.131.1534406160234; Thu, 16 Aug 2018 00:56:00 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id i25-v6sm50838137pfi.150.2018.08.16.00.55.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 00:55:59 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang Subject: [PATCH V5 10/10] dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller Date: Thu, 16 Aug 2018 15:54:24 +0800 Message-Id: <1534406064-10065-11-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> References: <1534406064-10065-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the device-tree binding documentation for Spreadtrum SDHCI driver. Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt new file mode 100644 index 0000000..45c9978 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt @@ -0,0 +1,41 @@ +* Spreadtrum SDHCI controller (sdhci-sprd) + +The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface +for MMC, SD and SDIO types of cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sprd driver. + +Required properties: +- compatible: Should contain "sprd,sdhci-r11". +- reg: physical base address of the controller and length. +- interrupts: Interrupts used by the SDHCI controller. +- clocks: Should contain phandle for the clock feeding the SDHCI controller +- clock-names: Should contain the following: + "sdio" - SDIO source clock (required) + "enable" - gate clock which used for enabling/disabling the device (required) + +Optional properties: +- assigned-clocks: the same with "sdio" clock +- assigned-clock-parents: the default parent of "sdio" clock + +Examples: + +sdio0: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + status = "okay"; +};