From patchwork Tue Aug 21 04:33:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144672 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4784710ljj; Mon, 20 Aug 2018 21:35:49 -0700 (PDT) X-Google-Smtp-Source: AA+uWPx++f8ok1qwK2zHz3fn+CbrgLbooVW9z+Grt3TzlIQq10iZMynW6ItxNXZc3WKwJJKz6/VY X-Received: by 2002:a37:1adb:: with SMTP id l88-v6mr11249890qkh.43.1534826149666; Mon, 20 Aug 2018 21:35:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534826149; cv=none; d=google.com; s=arc-20160816; b=vEz3ihQzI7wHnEBFLeP5OpnX/Ala0/+dGoa2Jec3aQALAjYue6BNy9pziYSwgeamJ7 WCXlLRy1SlxYzCV0/Vs51SPw9yayKsobEwLY1p+/gUnWw2DMzMOo8ct9Q+hikxsD+KmJ Jk9re9J4Q1jOqZVPmm5OX8sjms/ZV8rJ0U5gdb7D+F/5ElonWKYt5O9uH9V8wEuFv0I1 tnRzfpxVuNujOQiJHofkHb04xqadGzxCwzCoEmeiOmGjDBK+gr0WzPV0MJD55F8kgDty v01JKCuAOr6V+Tdvrsj5HyDBMjd9OXsYfz9Xd61q1Rhud04c/wzvkSyHBimRyVw9oJS5 fDPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=sZTaSTb9OVm8q+jg+7OXO2Lb5HVjSzPX0A9pUcGBU4g=; b=SRN7lwxQzAGoHjgOmgIhyLJNBBxWON4PFQLoNSaVJMXMP+VTzWhv/cZRW9Tn12X34G BX6oUErScuJi40ePg6lsDPqyiAhPb4KmUqoN6n5ODQBuMBAr7omf/y4XAen+SZ2n3X75 rZaClklmRi7ItlTDI3MCovk8INIBL48YvQzEJD3S9oolcHSjmZnTUi+qpduXggFjbeyt G9Q/nWr4Ur+tmmlu8DoEGvVrHiU4yZksuN3mkR3+eTfvmMIVZlhkd/B9CUCIuaybtDTC qKTf26O7AcCMYuCNUrl0BLHa9hKjFMEjGP0QA0WzQCqCrSFFAzubcXlpMYyCdMSNBmeT L1HQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=cbckIeKk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f53-v6si8921211qta.336.2018.08.20.21.35.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:35:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=cbckIeKk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50648 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryOT-0005Oc-35 for patch@linaro.org; Tue, 21 Aug 2018 00:35:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMp-00047S-7R for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMl-0000Ic-0C for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:06 -0400 Received: from ozlabs.org ([203.11.71.1]:53463) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMi-0000ES-Hn; Tue, 21 Aug 2018 00:34:02 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9D3wFQz9sCc; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826032; bh=Km9eXb/mZ2tpaozjbe+pDID9meRNdhppZseGEKNjQC8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cbckIeKk5tjUVfc7rDpBPxDCVLBKX6QuqANPFFHea6qfobFIKxF2AMDLkzHL3InTj GT/BpP0S9mmj7k1pnEbycL7i+8O4VVYi9v7bG4Cx/c1sPOzxszwO0KEv3UaMcY95Mq 8Ei6H4hFBXXAXCOV80WuzG5Z6S5sHEnfDcBOaxyA= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:20 +1000 Message-Id: <20180821043343.7514-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 03/26] target/ppc: Enable fp exceptions for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson While just setting the MSR bits is sufficient, we can tidy the helper code by extracting the MSR test to a helper and then forcing it true for user-only. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 15 ++++++++++++--- target/ppc/translate_init.inc.c | 2 ++ 2 files changed, 14 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 8675d931b6..9b39c4b3e5 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -36,6 +36,15 @@ static inline float128 float128_snan_to_qnan(float128 x) #define float32_snan_to_qnan(x) ((x) | 0x00400000) #define float16_snan_to_qnan(x) ((x) | 0x0200) +static inline bool fp_exceptions_enabled(CPUPPCState *env) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0; +#endif +} + /*****************************************************************************/ /* Floating point operations helpers */ uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) @@ -207,7 +216,7 @@ uint64_t float_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc) if (ve != 0) { /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; - if (msr_fe0 != 0 || msr_fe1 != 0) { + if (fp_exceptions_enabled(env)) { /* GETPC() works here because this is inline */ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op, GETPC()); @@ -225,7 +234,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr) if (fpscr_ze != 0) { /* Update the floating-point enabled exception summary */ env->fpscr |= 1 << FPSCR_FEX; - if (msr_fe0 != 0 || msr_fe1 != 0) { + if (fp_exceptions_enabled(env)) { raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX, raddr); @@ -555,7 +564,7 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) if (cs->exception_index == POWERPC_EXCP_PROGRAM && (env->error_code & POWERPC_EXCP_FP)) { /* Differred floating-point exception after target FPR update */ - if (msr_fe0 != 0 || msr_fe1 != 0) { + if (fp_exceptions_enabled(env)) { raise_exception_err_ra(env, cs->exception_index, env->error_code, raddr); } diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 7813b1b004..fe0cb98e6d 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10278,6 +10278,8 @@ static void ppc_cpu_reset(CPUState *s) #endif #if defined(CONFIG_USER_ONLY) msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ + msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ + msr |= (target_ulong)1 << MSR_FE1; msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ From patchwork Tue Aug 21 04:33:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144673 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4786170ljj; Mon, 20 Aug 2018 21:38:10 -0700 (PDT) X-Google-Smtp-Source: AA+uWPzvRxxOJpA+4oMmFaTgupCrgMVY7TixTw7eH2sxApE1QDN8Z6EOcDu8C+eWvpiw+9uaj6Uo X-Received: by 2002:ac8:8e6:: with SMTP id y35-v6mr7704060qth.408.1534826289943; Mon, 20 Aug 2018 21:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534826289; cv=none; d=google.com; s=arc-20160816; b=O90tPEyOVKrWi6eCNA6nsstx+q2ysh5Or1NFhiuIscGw42EPO4V8CtjxyDDk3BgIfb vNlL5Aci4Wk1C6f33ES0BYoUmemvqUhYl124vyXc54XFlAi0/x6uRqNOQdcTKvRsqK3+ UTMHbOvxVv1brn7cYUl/nwUftKsBi5uhvo8XyYxVjDxE6IEJOeWFYfXkY/KNjcIpWfL7 PrI/gvxCNcJgvS/mW1wWj3u2+rloDr2vrcQiyumzxuBYkpyUhXsni9wyR1XWZqjSSg/w tFh+Xur9xgk7xKjUY7E9NBeSUSke20PGcYHaxO/qSLke+14RnM6DIBvoizRZduRIZ+NA XKkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=QbFz9Ql6gZE7WK+4OYku769ZQp91fASPvMLX0jnekzk=; b=L3ksYdigFFngiruggs5tVeSsm6nPCpiesFOPY9iYb5J6wBDdQzUeMyzRvxdcormwsa sJNP5HyK+nGEKPQlvGD87VX7DL9R/cdbtLCQGI7YK8OOgcv3Of6GVQ2C+xbUojawHOi4 cOZzVph+FvbMVUbgOoBYlEt+ap8IlZ1vYY3qJcOvQGMINVqPZHFecQLyHULiispJG0tK t9y57nNyf1bFY+53T/dhTllj5kwUMDW9QjxV7Qj0z1Nim8ci9dDjItlhiXqJhOUVC0LJ Uxy6agkdEtN4pbv/fQr4Fb/aDXZ5Pv2yqwRpSf3tIwKlnnE6rRrXv8MfCFYdw/9EM9jW 6uGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=PpfQOXNP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m3-v6si600622qtp.325.2018.08.20.21.38.09 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:38:09 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=PpfQOXNP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50651 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryQj-0006Sn-BZ for patch@linaro.org; Tue, 21 Aug 2018 00:38:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMk-00044q-Tj for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMi-0000GS-Ik for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:02 -0400 Received: from ozlabs.org ([203.11.71.1]:37219) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMh-0000DF-Ac; Tue, 21 Aug 2018 00:33:59 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9D2Zfxz9sCP; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826032; bh=yfpLkCnMOb3VM1BxVpF+WUG9zDk2jzfyR0pH5R9o/Sk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PpfQOXNPw0Ytc+mKPOFSbAG1FYoktoO2XVXlq11bX14Z8qdjc+PCBp/w4vTB2gGtP l4FYnlKLR/N58SGXFyfl+4xqU9ZAYZqVnYX82Igh6uMms0lz9AGdC10HbEIMG8hjCT NN2VnV68DEPG1qxcWr9fRlwnkQCFr9qKrc7OibjM= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:21 +1000 Message-Id: <20180821043343.7514-5-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 04/26] target/ppc: Honor fpscr_ze semantics and tidy fdiv X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Divide by zero, exception taken, leaves the destination register unmodified. Therefore we must raise the exception before returning from helper_fdiv. Move the check from do_float_check_status into helper_fdiv. At the same time, tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. At the same time, pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 50 +++++++++++++++++++++++------------------ target/ppc/helper.h | 2 +- 2 files changed, 29 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9b39c4b3e5..c20b9ae672 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -545,9 +545,7 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) int status = get_float_exception_flags(&env->fp_status); bool inexact_happened = false; - if (status & float_flag_divbyzero) { - float_zero_divide_excp(env, raddr); - } else if (status & float_flag_overflow) { + if (status & float_flag_overflow) { float_overflow_excp(env); } else if (status & float_flag_underflow) { float_underflow_excp(env); @@ -661,30 +659,32 @@ uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2) } /* fdiv - fdiv. */ -uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2) +float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { - CPU_DoubleU farg1, farg2; - - farg1.ll = arg1; - farg2.ll = arg2; + float64 ret = float64_div(arg1, arg2, &env->fp_status); + int status = get_float_exception_flags(&env->fp_status); - if (unlikely(float64_is_infinity(farg1.d) && - float64_is_infinity(farg2.d))) { - /* Division of infinity by infinity */ - farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); - } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) { - /* Division of zero by zero */ - farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); - } else { - if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || - float64_is_signaling_nan(farg2.d, &env->fp_status))) { - /* sNaN division */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + if (unlikely(status)) { + if (status & float_flag_invalid) { + /* Determine what kind of invalid operation was seen. */ + if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { + /* Division of infinity by infinity */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); + } else if (float64_is_zero(arg1) && float64_is_zero(arg2)) { + /* Division of zero by zero */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); + } else if (float64_is_signaling_nan(arg1, &env->fp_status) || + float64_is_signaling_nan(arg2, &env->fp_status)) { + /* sNaN division */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + } + } + if (status & float_flag_divbyzero) { + float_zero_divide_excp(env, GETPC()); } - farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status); } - return farg1.ll; + return ret; } @@ -1928,6 +1928,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ tp##_is_signaling_nan(xb.fld, &tstat)) { \ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ } \ + } \ + if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \ + float_zero_divide_excp(env, GETPC()); \ } \ \ if (r2sp) { \ @@ -1978,6 +1981,9 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode) float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); } } + if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + } helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 5706c2497f..1c453fa0f7 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -88,7 +88,7 @@ DEF_HELPER_2(frim, i64, env, i64) DEF_HELPER_3(fadd, i64, env, i64, i64) DEF_HELPER_3(fsub, i64, env, i64, i64) DEF_HELPER_3(fmul, i64, env, i64, i64) -DEF_HELPER_3(fdiv, i64, env, i64, i64) +DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64) From patchwork Tue Aug 21 04:33:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144677 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4791815ljj; Mon, 20 Aug 2018 21:46:29 -0700 (PDT) X-Google-Smtp-Source: AA+uWPxkVtxiJz/5zvqtSsaHJ9gsPA4mPeAoPTCuj4/n+2Iy/SKn3bcR4AQk+x3UFNtzpqybwRCR X-Received: by 2002:ac8:705a:: with SMTP id y26-v6mr48925622qtm.118.1534826789474; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id o80-v6si22843qkl.306.2018.08.20.21.46.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:46:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=is6+Y61H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryYm-0007ri-TB for patch@linaro.org; Tue, 21 Aug 2018 00:46:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56510) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMt-0004C0-S9 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMp-0000Mu-12 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:11 -0400 Received: from ozlabs.org ([203.11.71.1]:43451) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMk-0000FP-Us; Tue, 21 Aug 2018 00:34:05 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9F0586z9sCX; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826033; bh=qQXE9mfBFMcdiGpmvn+88VcQWkxQvr905pQllx6aO2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=is6+Y61H3i0W3RRdjSh3dPHDCVXmpUGds63NIUIU5jCNaDV+IXaCbHf99Y4BPZIS9 2JCKyd+CjOacpWzrs8BkFBzf13perOIW6L5cDi8K9/VwmI75iHZ+WRl5WFWwsai+3E JUXuScsx7k+DauNEV9D9+kG6sWfJVE+3VJNXqKko= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:22 +1000 Message-Id: <20180821043343.7514-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 05/26] target/ppc: Tidy helper_fmul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. Pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 25 +++++++++++-------------- target/ppc/helper.h | 2 +- 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c20b9ae672..b9ee46eb5f 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -635,27 +635,24 @@ uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2) } /* fmul - fmul. */ -uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2) +float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) { - CPU_DoubleU farg1, farg2; - - farg1.ll = arg1; - farg2.ll = arg2; + float64 ret = float64_mul(arg1, arg2, &env->fp_status); + int status = get_float_exception_flags(&env->fp_status); - if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) || - (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) { - /* Multiplication of zero by infinity */ - farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); - } else { - if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || - float64_is_signaling_nan(farg2.d, &env->fp_status))) { + if (unlikely(status & float_flag_invalid)) { + if ((float64_is_infinity(arg1) && float64_is_zero(arg2)) || + (float64_is_zero(arg1) && float64_is_infinity(arg2))) { + /* Multiplication of zero by infinity */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); + } else if (float64_is_signaling_nan(arg1, &env->fp_status) || + float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN multiplication */ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); } - farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status); } - return farg1.ll; + return ret; } /* fdiv - fdiv. */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 1c453fa0f7..e4f7c55db9 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -87,7 +87,7 @@ DEF_HELPER_2(frim, i64, env, i64) DEF_HELPER_3(fadd, i64, env, i64, i64) DEF_HELPER_3(fsub, i64, env, i64, i64) -DEF_HELPER_3(fmul, i64, env, i64, i64) +DEF_HELPER_3(fmul, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) From patchwork Tue Aug 21 04:33:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144675 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4788699ljj; Mon, 20 Aug 2018 21:41:56 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyyB+n2hBLrJnRv5ElrHkIpw+8Q+qXhzKKVjUxmtY9hIUAgEmxoc/d7HuTKZ9Q+Z5HVjw7l X-Received: by 2002:ac8:3759:: with SMTP id p25-v6mr3520813qtb.310.1534826516432; Mon, 20 Aug 2018 21:41:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534826516; cv=none; d=google.com; s=arc-20160816; b=ZppXmAOCKA/MvrcdL5qHqh+jRTY5Bbdk3LdPm7h/OoAvstJCizGIH67CHrc1bOAy9d 6jH858aEWIe1znFrh8DsC/594Cdp0wU4M8ou0oKFdEBL0tQs3roigRloMwbcpzpad54Y Duqyj3u4l0envO9g05MalKNy7YjyLG40NL7z2gZdPLsR2WDCxYWb/7/F3a/55dTe5S6f GTf4TnP7mQf90JAJB62cZKBjZhTWveEMF/cl06pbJcrnHxqoy5hje21LvuXZr5YvQ7oI u5IMYd1YOg2zg1qcbK5G2Dg+/GpdCNQOy+9e/SsaI/wS+txAiunTHBSSDK2wN3EgyOeJ Qsnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8r43H6hFFVb+iQFJUz9/jDRbmehYmP/f9ZMx+fbXi48=; b=iDm9p6Q8pd5TrFANf1r4jGbK/v6J23EQI/XEBO8gAKlw6mKhd73DKvquriUL2KqkYo /0JY4r61tWTdOxCQMJryaa3rgwXgSIO5fqEwXGNtKnDbnt9qIP/z1jsl3kOg8ThGOyv6 zgDBb2gWgc3WYE/SXyZev8vjhCDTPIa/ZsxmTVPm0GK5QIsaTQMXyOHBVtR1lkVk/p+m /OJaY1IhoYDpm0M0jbVKfiY0VDvk9MKK9f3NWL1V+caIGy2whfoI2FjSFgcOqa1V4cJq T3FAU1QUoXGTVqDCniGzIJGr3scSywuSrIRqtc2PcEANe23G/AYlyVe16IIHJD+nR7F9 M4cQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=cnB9OScv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 13-v6si198562qtp.41.2018.08.20.21.41.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:41:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=cnB9OScv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50681 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryUN-000278-QI for patch@linaro.org; Tue, 21 Aug 2018 00:41:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56422) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMp-00047R-7S for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMl-0000Ip-2N for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:06 -0400 Received: from ozlabs.org ([203.11.71.1]:38723) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMk-0000EW-0y; Tue, 21 Aug 2018 00:34:02 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9D5jZ4z9sBj; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826032; bh=1xCO9sniAQIKu/8RLWaQ0XQ6BA6CCwKe+lgydnxTlbQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cnB9OScvLnX8tUx+GO2NvXIVr6rnkP9QF4jN6xuLPli7j1zIkRQZr89pgWJHFMPjM QKkOGZ0h2rB3czNx+aLQQMChOFuan4iOdU3Hz08pjuIMiCNbG5ekjSfl6Aj3DVeU+6 Gb8iJGAIcSgFxqcLqUh91Bhj0kYvWb3zTywI0Flg= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:23 +1000 Message-Id: <20180821043343.7514-7-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 06/26] target/ppc: Tidy helper_fadd, helper_fsub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. Pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Note that because we know float_flag_invalid was set, we do not have to re-check the signs of the infinities. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 50 +++++++++++++++++------------------------ target/ppc/helper.h | 4 ++-- 2 files changed, 23 insertions(+), 31 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index b9ee46eb5f..7758372ecd 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -587,51 +587,43 @@ void helper_reset_fpstatus(CPUPPCState *env) } /* fadd - fadd. */ -uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2) +float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { - CPU_DoubleU farg1, farg2; - - farg1.ll = arg1; - farg2.ll = arg2; + float64 ret = float64_add(arg1, arg2, &env->fp_status); + int status = get_float_exception_flags(&env->fp_status); - if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) && - float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) { - /* Magnitude subtraction of infinities */ - farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); - } else { - if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || - float64_is_signaling_nan(farg2.d, &env->fp_status))) { + if (unlikely(status & float_flag_invalid)) { + if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { + /* Magnitude subtraction of infinities */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + } else if (float64_is_signaling_nan(arg1, &env->fp_status) || + float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN addition */ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); } - farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status); } - return farg1.ll; + return ret; } /* fsub - fsub. */ -uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2) +float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) { - CPU_DoubleU farg1, farg2; - - farg1.ll = arg1; - farg2.ll = arg2; + float64 ret = float64_sub(arg1, arg2, &env->fp_status); + int status = get_float_exception_flags(&env->fp_status); - if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) && - float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) { - /* Magnitude subtraction of infinities */ - farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); - } else { - if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || - float64_is_signaling_nan(farg2.d, &env->fp_status))) { - /* sNaN subtraction */ + if (unlikely(status & float_flag_invalid)) { + if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { + /* Magnitude subtraction of infinities */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + } else if (float64_is_signaling_nan(arg1, &env->fp_status) || + float64_is_signaling_nan(arg2, &env->fp_status)) { + /* sNaN addition */ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); } - farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status); } - return farg1.ll; + return ret; } /* fmul - fmul. */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index e4f7c55db9..d81806dd2c 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -85,8 +85,8 @@ DEF_HELPER_2(friz, i64, env, i64) DEF_HELPER_2(frip, i64, env, i64) DEF_HELPER_2(frim, i64, env, i64) -DEF_HELPER_3(fadd, i64, env, i64, i64) -DEF_HELPER_3(fsub, i64, env, i64, i64) +DEF_HELPER_3(fadd, f64, env, f64, f64) +DEF_HELPER_3(fsub, f64, env, f64, f64) DEF_HELPER_3(fmul, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) From patchwork Tue Aug 21 04:33:24 2018 Content-Type: text/plain; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id b190-v6si1152448qke.317.2018.08.20.21.34.33 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:34:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=S7NknbPB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50636 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryNF-00044s-3P for patch@linaro.org; Tue, 21 Aug 2018 00:34:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56305) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMh-00041f-Jd for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMg-0000E0-6Z for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:33:59 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:38557) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMf-0000AD-Mg; Tue, 21 Aug 2018 00:33:58 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9D01WJz9s7X; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826032; bh=ZHBFLnDftDs3FcvSsrvLiwlkpmtdIs2//4w0Wq+RmX8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S7NknbPBYp6DL7JFtHI453ABNyB0UILYHzhLwaegFRBdkBTGmP5qdYkjkDF2IL8Ak 5AniK01ivcgtnJQgU/AjCiqTrT6j5+vvzc1rGV9NrbKIkMftQkC7JKosK8cmsZdHT3 K4SX/cjPndY1FzdZeUhQhpz3k6GA9u6Cv67xXVig= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:24 +1000 Message-Id: <20180821043343.7514-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 07/26] target/ppc: Tidy helper_fsqrt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. Pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 29 ++++++++++++++--------------- target/ppc/helper.h | 2 +- 2 files changed, 15 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 7758372ecd..44f3fed17d 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -858,25 +858,24 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) } /* fsqrt - fsqrt. */ -uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg) +float64 helper_fsqrt(CPUPPCState *env, float64 arg) { - CPU_DoubleU farg; - - farg.ll = arg; + float64 ret = float64_sqrt(arg, &env->fp_status); + int status = get_float_exception_flags(&env->fp_status); - if (unlikely(float64_is_any_nan(farg.d))) { - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN reciprocal square root */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); - farg.ll = float64_snan_to_qnan(farg.ll); + if (unlikely(status & float_flag_invalid)) { + if (unlikely(float64_is_any_nan(arg))) { + if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) { + /* sNaN square root */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + } + } else { + /* Square root of a negative nonzero number */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); } - } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { - /* Square root of a negative nonzero number */ - farg.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - } else { - farg.d = float64_sqrt(farg.d, &env->fp_status); } - return farg.ll; + + return ret; } /* fre - fre. */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d81806dd2c..7ed72c2337 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -93,7 +93,7 @@ DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fnmsub, i64, env, i64, i64, i64) -DEF_HELPER_2(fsqrt, i64, env, i64) +DEF_HELPER_2(fsqrt, f64, env, f64) DEF_HELPER_2(fre, i64, env, i64) DEF_HELPER_2(fres, i64, env, i64) DEF_HELPER_2(frsqrte, i64, env, i64) From patchwork Tue Aug 21 04:33:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144674 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4788112ljj; Mon, 20 Aug 2018 21:40:58 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyMIFngfOH0Qi0iXMvDBFl8BJ+5dR6tY4ZsiaVmvjqw8WbSaESZW2smwjc58XwZpW0aMSqo X-Received: by 2002:ac8:60d7:: with SMTP id i23-v6mr10224411qtm.403.1534826458698; Mon, 20 Aug 2018 21:40:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534826458; cv=none; d=google.com; s=arc-20160816; b=Vsi22P6BQVxDB1dMbKFUHpx26JSYS5KYar7iiG7lZFEUtRrlsSBXNCR3KGavRUNQ+J Ds9efGg6P6/iVIawJN0sVpDy01rGG5M++U0eTcM1qsoDb7GZCWGj3N3xH8C2onT2oiym O1xjeTdKWrKmipfsClAuU/wUKB97m79NieZvAUXzR51rNghPbA+lB/qAY4Fsqp69+q2A Ik34wdZfdRHl5T6qKHNzDd5OS+23Qy8lZR5s2OX1OJFGYNH4hEDVI79TmsaawbXK2tKr Ul2taYYZ6Ac+V0teyx6pMy//BemrgTZom89fuO+j93Q5CJyQo9ksBMnqNa0X41tPSG1z 6qHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=IXXBaTw69CdLZyuZjS5xhTLSZlGdTS2N2W4F+5gesIk=; b=zXAvNEjxSVgLfkAt+GuYjt6uLR/DrIP6oLEuYC0qwNFTrwD2QNM9emIkSXw0+Puop4 YfAQWZw56ZDY32h7GLR32DqsbbW5imncNqXu0Y01KGcJPVMeGDmwMbdAIcp9Bp5+bJNP O8+/dGfcN02yhMa1sZ6lzGTWF45f2WCqTCReJNJZ/kmEDXdeLCOQyvEc1SQnN5S5iSup SiAGBg3Ql10iTBR0hdX792qGCnclql+XrAS2yyJiV3O0KX89zZgW2aQGwxFNkascVNek aAvQHDl3B/TRQa1KoZRTrR3z+zg2eVgUcEkmjrAv63eJafCRkXPUerAeO8ZO/xKl2nWK TSFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=AmlXoGor; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id g25-v6si8898263qkm.263.2018.08.20.21.40.58 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:40:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=AmlXoGor; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50666 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryTS-0000J8-59 for patch@linaro.org; Tue, 21 Aug 2018 00:40:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56420) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMp-00047P-7K for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMl-0000It-2v for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:06 -0400 Received: from ozlabs.org ([203.11.71.1]:33979) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMk-0000EU-5v; Tue, 21 Aug 2018 00:34:02 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9D4YQdz9s8F; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826032; bh=ymmkFgW2+kau1eTvEWlF10Lv92x+ZQOpCHYcA09KofI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AmlXoGorRRY5xVup48CYOHk8MT1B7PtpHBeuWb/91AloWA0tWtJ4FfCQ+nEMEmBFw 3RndllKVHW4YCAUyVPu6I0uMo0ueLUsYYpwhKN1KVDF9qa3YdA3lCQAjt2jk1WCPKi Z9NFtLDzKmKpSkWftPBHusyCII6N1Z3MZZ2aV+Bg= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:25 +1000 Message-Id: <20180821043343.7514-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 08/26] target/ppc: Honor fpscr_ze semantics and tidy fre, fresqrt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Divide by zero, exception taken, leaves the destination register unmodified. Therefore we must raise the exception before returning from the respective helpers. >From helper_fre, divide by zero exception not taken, return the documented +/- 0.5. At the same time, tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. At the same time, pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 62 ++++++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 44f3fed17d..5af5241ab0 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -879,18 +879,27 @@ float64 helper_fsqrt(CPUPPCState *env, float64 arg) } /* fre - fre. */ -uint64_t helper_fre(CPUPPCState *env, uint64_t arg) +float64 helper_fre(CPUPPCState *env, float64 arg) { - CPU_DoubleU farg; - - farg.ll = arg; + /* "Estimate" the reciprocal with actual division. */ + float64 ret = float64_div(float64_one, arg, &env->fp_status); + int status = get_float_exception_flags(&env->fp_status); - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + if (unlikely(status)) { + if (status & float_flag_invalid) { + if (float64_is_signaling_nan(arg, &env->fp_status)) { + /* sNaN reciprocal */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + } + } + if (status & float_flag_divbyzero) { + float_zero_divide_excp(env, GETPC()); + /* For FPSCR.ZE == 0, the result is 1/2. */ + ret = float64_set_sign(float64_half, float64_is_neg(arg)); + } } - farg.d = float64_div(float64_one, farg.d, &env->fp_status); - return farg.d; + + return ret; } /* fres - fres. */ @@ -913,27 +922,30 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) } /* frsqrte - frsqrte. */ -uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg) +float64 helper_frsqrte(CPUPPCState *env, float64 arg) { - CPU_DoubleU farg; - - farg.ll = arg; + /* "Estimate" the reciprocal with actual division. */ + float64 rets = float64_sqrt(arg, &env->fp_status); + float64 retd = float64_div(float64_one, rets, &env->fp_status); + int status = get_float_exception_flags(&env->fp_status); - if (unlikely(float64_is_any_nan(farg.d))) { - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN reciprocal square root */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); - farg.ll = float64_snan_to_qnan(farg.ll); + if (unlikely(status)) { + if (status & float_flag_invalid) { + if (float64_is_signaling_nan(arg, &env->fp_status)) { + /* sNaN reciprocal */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + } else { + /* Square root of a negative nonzero number */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + } + } + if (status & float_flag_divbyzero) { + /* Reciprocal of (square root of) zero. */ + float_zero_divide_excp(env, GETPC()); } - } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) { - /* Reciprocal square root of a negative nonzero number */ - farg.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - } else { - farg.d = float64_sqrt(farg.d, &env->fp_status); - farg.d = float64_div(float64_one, farg.d, &env->fp_status); } - return farg.ll; + return retd; } /* fsel - fsel. */ From patchwork Tue Aug 21 04:33:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144676 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4790678ljj; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w3-v6si782042qvw.271.2018.08.20.21.44.56 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:44:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@gibson.dropbear.id.au header.s=201602 header.b=LmbYxYXh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50699 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryXH-0006M0-V6 for patch@linaro.org; Tue, 21 Aug 2018 00:44:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56520) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMt-0004C7-Tn for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMp-0000MW-03 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:11 -0400 Received: from ozlabs.org ([203.11.71.1]:39101) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMk-0000Gk-Ss; Tue, 21 Aug 2018 00:34:05 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9F4ql2z9sCh; Tue, 21 Aug 2018 14:33:51 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826033; bh=nvjBLhRZ4TSfC5LLasaHiomTJbRKh1sOGnFknL/Leqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LmbYxYXh7cnN0e7JbnhbY/ciVQnLmoeG/Z/5ZuRVJ1FQy8bFejq+vxWq3NKFBCKqu PLtt8bQbTjxxNO2jB6hgi7vEev7fqwRorwlhGKSFAdr6VPuSMCqwYAL0BHs8J9fWvS Njx1GtoivABIrTWfpKqGpYqgTk0VfrhvK5Kg0NRc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:26 +1000 Message-Id: <20180821043343.7514-10-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 09/26] target/ppc: Use non-arithmetic conversions for fp load/store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, Richard Henderson , groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Memory operations have no side effects on fp state. The use of a "real" conversions between float64 and float32 would raise exceptions for SNaN and out-of-range inputs. Signed-off-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/fpu_helper.c | 61 ++++++++++++++++++++++++------ target/ppc/helper.h | 4 +- target/ppc/translate/fp-impl.inc.c | 26 +++++-------- 3 files changed, 61 insertions(+), 30 deletions(-) -- 2.17.1 diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 5af5241ab0..b9bb1b856e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -47,24 +47,61 @@ static inline bool fp_exceptions_enabled(CPUPPCState *env) /*****************************************************************************/ /* Floating point operations helpers */ -uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) + +/* + * This is the non-arithmatic conversion that happens e.g. on loads. + * In the Power ISA pseudocode, this is called DOUBLE. + */ +uint64_t helper_todouble(uint32_t arg) { - CPU_FloatU f; - CPU_DoubleU d; + uint32_t abs_arg = arg & 0x7fffffff; + uint64_t ret; - f.l = arg; - d.d = float32_to_float64(f.f, &env->fp_status); - return d.ll; + if (likely(abs_arg >= 0x00800000)) { + /* Normalized operand, or Inf, or NaN. */ + ret = (uint64_t)extract32(arg, 30, 2) << 62; + ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59; + ret |= (uint64_t)extract32(arg, 0, 30) << 29; + } else { + /* Zero or Denormalized operand. */ + ret = (uint64_t)extract32(arg, 31, 1) << 63; + if (unlikely(abs_arg != 0)) { + /* Denormalized operand. */ + int shift = clz32(abs_arg) - 9; + int exp = -126 - shift + 1023; + ret |= (uint64_t)exp << 52; + ret |= abs_arg << (shift + 29); + } + } + return ret; } -uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg) +/* + * This is the non-arithmatic conversion that happens e.g. on stores. + * In the Power ISA pseudocode, this is called SINGLE. + */ +uint32_t helper_tosingle(uint64_t arg) { - CPU_FloatU f; - CPU_DoubleU d; + int exp = extract64(arg, 52, 11); + uint32_t ret; - d.ll = arg; - f.f = float64_to_float32(d.d, &env->fp_status); - return f.l; + if (likely(exp > 896)) { + /* No denormalization required (includes Inf, NaN). */ + ret = extract64(arg, 62, 2) << 30; + ret |= extract64(arg, 29, 30); + } else { + /* Zero or Denormal result. If the exponent is in bounds for + * a single-precision denormal result, extract the proper bits. + * If the input is not zero, and the exponent is out of bounds, + * then the result is undefined; this underflows to zero. + */ + ret = extract64(arg, 63, 1) << 31; + if (unlikely(exp >= 874)) { + /* Denormal result. */ + ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp); + } + } + return ret; } static inline int ppc_float32_get_unbiased_exp(float32 f) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7ed72c2337..ef64248bc4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -61,8 +61,8 @@ DEF_HELPER_2(compute_fprf_float64, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) DEF_HELPER_2(fpscr_clrbit, void, env, i32) DEF_HELPER_2(fpscr_setbit, void, env, i32) -DEF_HELPER_2(float64_to_float32, i32, env, i64) -DEF_HELPER_2(float32_to_float64, i64, env, i32) +DEF_HELPER_FLAGS_1(todouble, TCG_CALL_NO_RWG_SE, i64, i32) +DEF_HELPER_FLAGS_1(tosingle, TCG_CALL_NO_RWG_SE, i32, i64) DEF_HELPER_4(fcmpo, void, env, i64, i64, i32) DEF_HELPER_4(fcmpu, void, env, i64, i64, i32) diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c index 2fbd4d4f38..a6f522b85c 100644 --- a/target/ppc/translate/fp-impl.inc.c +++ b/target/ppc/translate/fp-impl.inc.c @@ -660,15 +660,12 @@ GEN_LDUF(name, ldop, op | 0x21, type); \ GEN_LDUXF(name, ldop, op | 0x01, type); \ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) -static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) { - TCGv t0 = tcg_temp_new(); - TCGv_i32 t1 = tcg_temp_new_i32(); - gen_qemu_ld32u(ctx, t0, arg2); - tcg_gen_trunc_tl_i32(t1, t0); - tcg_temp_free(t0); - gen_helper_float32_to_float64(arg1, cpu_env, t1); - tcg_temp_free_i32(t1); + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + gen_helper_todouble(dest, tmp); + tcg_temp_free_i32(tmp); } /* lfd lfdu lfdux lfdx */ @@ -836,15 +833,12 @@ GEN_STUF(name, stop, op | 0x21, type); \ GEN_STUXF(name, stop, op | 0x01, type); \ GEN_STXF(name, stop, 0x17, op | 0x00, type) -static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) +static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr) { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv t1 = tcg_temp_new(); - gen_helper_float64_to_float32(t0, cpu_env, arg1); - tcg_gen_extu_i32_tl(t1, t0); - tcg_temp_free_i32(t0); - gen_qemu_st32(ctx, t1, arg2); - tcg_temp_free(t1); + TCGv_i32 tmp = tcg_temp_new_i32(); + gen_helper_tosingle(tmp, src); + tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + tcg_temp_free_i32(tmp); } /* stfd stfdu stfdux stfdx */ From patchwork Tue Aug 21 04:33:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144680 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4797871ljj; Mon, 20 Aug 2018 21:55:23 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYE4eDk2eiS3PjnVdG+UlZ464RhS56XL7wbt8wsa63u78lL7l1Ey3EDwl8zwqShtuygmY0r X-Received: by 2002:ac8:74cf:: with SMTP id j15-v6mr392018qtr.386.1534827323115; Mon, 20 Aug 2018 21:55:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534827323; cv=none; d=google.com; s=arc-20160816; b=rpw/GdpMJDxZKP6Dk1q2UXx7O+c/fSu9HN9dwPe2PdZYhY4dB8O1kI5alogKV8LEFc dqBLHbQRfXF8F8N1xfBtHMbtwhNsI+02KdzwnBLE44wBcHODF0Pq6xD2R9rE8KQW7zPX 8nGr9778NugrG7ubAJf+CNXMcro3LRQrnLm19FX1VklgOhZXmuYiVBWTcymh3bwFF5G8 HkZc+XaxDT7EAv9RrP+eDM2QqsqEE0Cn/JEe7Ca9Iuv0I3uI0/tuWZAzdT2jNNrggh/v 89Ffcn+X7iaDl2cX0eyrhBGVxBGHk8BraWoRnLx2h1UsmMx+NwAGjz1Eicmtt93suFdf aCsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=GCuiNbhg2Z7it7vh9UxVSeyoTyGzlbsUv7ztrvBGAHw=; b=Qy+XVbO8YI3men7RTlxLzyt16JMs5Gq/x7284n5QUyU5Qx/OiPmZCEj1LdOmEJ8c0Y M01x7sFiTWTUZy/6SUBbie6MEy+svAlU29mQY4bJE02/Melcq1vS5noBr2xn+BFgtd0W Vq9HNtWvEnvOcZQwUo8qBubf9M1rSPx8+o8VnN0sTBaHZbSR+TqBW9DiQJBjNHfp19jA a6yPPzMYJJbsG+atBuYft0Iiz8eWkNBHeXwJQbZG9rhWHwdCVoxU3KVOpQMAqXd1mN4f PGYUFFmk8dFr+rClkmYiBxbSuudVqIMFq8F682nY2F3NY/npTOgde+8kJMl5n/ZCLYmm cayA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=MGgJe88h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id v35-v6si6343759qtv.322.2018.08.20.21.55.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:55:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=MGgJe88h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryhO-0007eM-Jp for patch@linaro.org; Tue, 21 Aug 2018 00:55:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56803) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryN0-0004Jy-OJ for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMx-0000VF-5u for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:18 -0400 Received: from ozlabs.org ([203.11.71.1]:55333) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMv-0000Rz-Vq; Tue, 21 Aug 2018 00:34:14 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9H33tRz9sDJ; Tue, 21 Aug 2018 14:33:52 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826035; bh=AEgPcPl2PEoVlsrISFrfbB7P0pVFwLHR3cDKUtGZvt8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MGgJe88hDlzbB1q8E8sdEhaY8hvvdxh1HF3mcly8YRUcNhGJlAoG8oR+dmWDbuQEf lg9xKmVNtenkoISVLuRXgl6vwHuqr06JyQXTkOhkZIkogtg0V5mAaGeHwSxsh6mv3V yc/I9E+3xObu1RGvFoDVE2V8Akg6ost3UjbGQXvY= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:33 +1000 Message-Id: <20180821043343.7514-17-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 16/26] hw/ppc/prep: Remove ifdeffed-out stub of XCSR code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell The prep machine has some code which is stubs of accessors for XCSR registers. This has been disabled via #if 0 since commit b6b8bd1819ff in 2004, and doesn't have any actual interesting content. It also uses the deprecated old_mmio accessor functions. Remove it entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Hervé Poussineau Signed-off-by: David Gibson --- hw/ppc/prep.c | 97 +++------------------------------------------------ 1 file changed, 4 insertions(+), 93 deletions(-) -- 2.17.1 diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 3401570d98..b26138e5c4 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -78,94 +78,6 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; /* ISA IO ports bridge */ #define PPC_IO_BASE 0x80000000 -/* PowerPC control and status registers */ -#if 0 // Not used -static struct { - /* IDs */ - uint32_t veni_devi; - uint32_t revi; - /* Control and status */ - uint32_t gcsr; - uint32_t xcfr; - uint32_t ct32; - uint32_t mcsr; - /* General purpose registers */ - uint32_t gprg[6]; - /* Exceptions */ - uint32_t feen; - uint32_t fest; - uint32_t fema; - uint32_t fecl; - uint32_t eeen; - uint32_t eest; - uint32_t eecl; - uint32_t eeint; - uint32_t eemck0; - uint32_t eemck1; - /* Error diagnostic */ -} XCSR; - -static void PPC_XCSR_writeb (void *opaque, - hwaddr addr, uint32_t value) -{ - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, - value); -} - -static void PPC_XCSR_writew (void *opaque, - hwaddr addr, uint32_t value) -{ - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, - value); -} - -static void PPC_XCSR_writel (void *opaque, - hwaddr addr, uint32_t value) -{ - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, - value); -} - -static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) -{ - uint32_t retval = 0; - - printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, - retval); - - return retval; -} - -static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) -{ - uint32_t retval = 0; - - printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, - retval); - - return retval; -} - -static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) -{ - uint32_t retval = 0; - - printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, - retval); - - return retval; -} - -static const MemoryRegionOps PPC_XCSR_ops = { - .old_mmio = { - .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, - .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, - }, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -#endif - /* Fake super-io ports for PREP platform (Intel 82378ZB) */ typedef struct sysctrl_t { qemu_irq reset_irq; @@ -648,11 +560,10 @@ static void ppc_prep_init(MachineState *machine) portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); - /* PowerPC control and status register group */ -#if 0 - memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); - memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); -#endif + /* + * PowerPC control and status register group: unimplemented, + * would be at address 0xFEFF0000. + */ if (machine_usb(machine)) { pci_create_simple(pci_bus, -1, "pci-ohci"); From patchwork Tue Aug 21 04:33:34 2018 Content-Type: text/plain; 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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id n126-v6si1448982qkn.229.2018.08.20.21.50.42 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:50:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=JQST4MEm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50738 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1frycs-0004aU-4O for patch@linaro.org; Tue, 21 Aug 2018 00:50:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56666) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMx-0004GV-J5 for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMu-0000SX-Hn for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:15 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:54287) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMt-0000NT-NG; Tue, 21 Aug 2018 00:34:12 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9G2QwDz9sD2; Tue, 21 Aug 2018 14:33:52 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826034; bh=u9+8wiIsB3zZnSI+qXgfH/HDGlBY8LVD7m9bJU2ac00=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JQST4MEmLVsGSExFQ+rlP9PjGmO6tZENQiEJrYdN65FuC/hwqqENwi6sFZ0tuaCxa UrmmbAhnfcyb/dLbTJDxw3SRnykPnWQ+0HQjPprkiaoETN7s+j+yHLNrrBoA5oJzod /hpm54pjckIwl+mEIZsn2FSsNICHyAVw9yLIOyDc= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:34 +1000 Message-Id: <20180821043343.7514-18-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 17/26] hw/ppc/ppc_boards: Don't use old_mmio for ref405ep_fpga X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Switch the ref405ep_fpga device away from using the old_mmio MemoryRegion accessors. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/ppc/ppc405_boards.c | 60 +++++++----------------------------------- 1 file changed, 10 insertions(+), 50 deletions(-) -- 2.17.1 diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 70111075b3..f5a9c24b6c 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -66,7 +66,7 @@ struct ref405ep_fpga_t { uint8_t reg1; }; -static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) +static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) { ref405ep_fpga_t *fpga; uint32_t ret; @@ -87,8 +87,8 @@ static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) return ret; } -static void ref405ep_fpga_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ref405ep_fpga_t *fpga; @@ -105,54 +105,14 @@ static void ref405ep_fpga_writeb (void *opaque, } } -static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret = ref405ep_fpga_readb(opaque, addr) << 8; - ret |= ref405ep_fpga_readb(opaque, addr + 1); - - return ret; -} - -static void ref405ep_fpga_writew (void *opaque, - hwaddr addr, uint32_t value) -{ - ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); -} - -static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret = ref405ep_fpga_readb(opaque, addr) << 24; - ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16; - ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8; - ret |= ref405ep_fpga_readb(opaque, addr + 3); - - return ret; -} - -static void ref405ep_fpga_writel (void *opaque, - hwaddr addr, uint32_t value) -{ - ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); -} - static const MemoryRegionOps ref405ep_fpga_ops = { - .old_mmio = { - .read = { - ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, - }, - .write = { - ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel, - }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, + .read = ref405ep_fpga_readb, + .write = ref405ep_fpga_writeb, + .impl.min_access_size = 1, + .impl.max_access_size = 1, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .endianness = DEVICE_BIG_ENDIAN, }; static void ref405ep_fpga_reset (void *opaque) From patchwork Tue Aug 21 04:33:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 144678 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp4792151ljj; Mon, 20 Aug 2018 21:47:01 -0700 (PDT) X-Google-Smtp-Source: AA+uWPyKbHqoyLMlhZtczXzAyfO7efjv4p1wiYcUytUKWQq64U4+POWahChAw8I9KBpXlLAWwPFV X-Received: by 2002:ae9:df81:: with SMTP id t123-v6mr44301383qkf.55.1534826821028; Mon, 20 Aug 2018 21:47:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1534826821; cv=none; d=google.com; s=arc-20160816; b=jrGJVJF6A3Xt9toSp8ENWAW/QZPg0QX4NZxEiwMwG+Kae38rR+IupYQjAyi4iWUVna PtfZaKuZcbLp0Q9iEHL2rqM58qAgSGsTUOH3OrGHGwE2Sjl9JttZqX/zyrYsGak1+CFj iPZ+ed78lRHVJpufEWPIVkeOH6fwcvtE3ox81qvtbRsEHCmcOUxw4xtzFa9fKCYcalKm GUrK41Hn99kyH+iwSFS5ohcCJj4ykFI2VZD9ncXK/+p2vueVTeawUekPTxkZInQ9TcTO mIPPnZlRf0rI0iqcBqihWYKNqZQ51+bW0R1wY7o3TL30kk4j0GJ4Yi+5BGR6/94CJC4y EHWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=n0IpqfTDLwrZpq3IEzjOQB6/W2QKG+ZrJ3uMebrzv3o=; b=krT2rC4uukXenmVIwM6PkSXzOMWRbrL65/GF2MhiW76xMIVfeVhCgWReGY83yEngjA ef2dUVHFzdoq6e18klpPuQ5wKZXyNtCnkgDpv8D4ekJ/TH8NqBTmzrFr3UqgLrEii35K 5/mvK3xzooRq/wHZgnMp2nKWS7YG47CB5Rszp8p7+Y7DMFqzhsS4GFDKOye310e60lg8 f9yBNbmQi1yRL6Kb99mbN1oO6ZPYClLUOGYvcWwIWPleThUZmYbLQWZZr+b1FX+SWRmO KE95AuRLOa1JUriH37Nkdzgu4XsUQOA/rm4HN7ooq+7xP6e6IgAoJwWWy0gKGxg3IESW FVow== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=CatbMSuV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 57-v6si9455252qtz.128.2018.08.20.21.47.00 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 20 Aug 2018 21:47:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gibson.dropbear.id.au header.s=201602 header.b=CatbMSuV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:50715 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryZI-0000dg-F0 for patch@linaro.org; Tue, 21 Aug 2018 00:47:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fryMt-0004C1-SV for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fryMp-0000NM-9o for qemu-devel@nongnu.org; Tue, 21 Aug 2018 00:34:11 -0400 Received: from ozlabs.org ([203.11.71.1]:46965) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fryMo-0000JH-6U; Tue, 21 Aug 2018 00:34:06 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 41vd9G1msRz9sD7; Tue, 21 Aug 2018 14:33:52 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1534826034; bh=d+8xQmTWasCBYoO3Op9r5ttTiFZD2waYkZal7DNyHh8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CatbMSuVvgJqDyAomf1z+dQZnFceRLFYWgr3NLuI/1QrMYYEX5UpClDzWbq5gAer8 Tpt9ba2dXHCl/9D/HzxIn9y8/wVJqh0Rl/HwSCdGq+8vy+Yr2x3P1bDCFHI5y1Mnnw XeqXZ3qSn2cbj1r3CR9MQmVo85HM2IlArO8AFlzM= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 21 Aug 2018 14:33:35 +1000 Message-Id: <20180821043343.7514-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180821043343.7514-1-david@gibson.dropbear.id.au> References: <20180821043343.7514-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PULL 18/26] hw/ppc/ppc405_uc: Convert away from old_mmio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, groug@kaod.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Convert the devices in ppc405_uc away from using the old_mmio MemoryRegion accessors: * opba's 32-bit and 16-bit accessors were just calling the 8-bit accessors and assembling a big-endian order number, which we can do by setting the .impl.max_access_size to 1 and the endianness to DEVICE_BIG_ENDIAN, and letting the core memory code do the assembly * ppc405_gpio's accessors were all just stubs * ppc4xx_gpt's 8-bit and 16-bit accessors were treating the access as invalid, which we can do by setting the .valid.min_access_size and .valid.max_access_size fields Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/ppc/ppc405_uc.c | 173 +++++++-------------------------------------- 1 file changed, 25 insertions(+), 148 deletions(-) -- 2.17.1 diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 4bd9fbcc1e..5c58415cf1 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -283,7 +283,7 @@ struct ppc4xx_opba_t { uint8_t pr; }; -static uint32_t opba_readb (void *opaque, hwaddr addr) +static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { ppc4xx_opba_t *opba; uint32_t ret; @@ -307,8 +307,8 @@ static uint32_t opba_readb (void *opaque, hwaddr addr) return ret; } -static void opba_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ppc4xx_opba_t *opba; @@ -328,61 +328,14 @@ static void opba_writeb (void *opaque, break; } } - -static uint32_t opba_readw (void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret = opba_readb(opaque, addr) << 8; - ret |= opba_readb(opaque, addr + 1); - - return ret; -} - -static void opba_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba_writeb(opaque, addr, value >> 8); - opba_writeb(opaque, addr + 1, value); -} - -static uint32_t opba_readl (void *opaque, hwaddr addr) -{ - uint32_t ret; - -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - ret = opba_readb(opaque, addr) << 24; - ret |= opba_readb(opaque, addr + 1) << 16; - - return ret; -} - -static void opba_writel (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba_writeb(opaque, addr, value >> 24); - opba_writeb(opaque, addr + 1, value >> 16); -} - static const MemoryRegionOps opba_ops = { - .old_mmio = { - .read = { opba_readb, opba_readw, opba_readl, }, - .write = { opba_writeb, opba_writew, opba_writel, }, - }, - .endianness = DEVICE_NATIVE_ENDIAN, + .read = opba_readb, + .write = opba_writeb, + .impl.min_access_size = 1, + .impl.max_access_size = 1, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .endianness = DEVICE_BIG_ENDIAN, }; static void ppc4xx_opba_reset (void *opaque) @@ -750,65 +703,27 @@ struct ppc405_gpio_t { uint32_t isr1l; }; -static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr) +static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { #ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); + printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); #endif return 0; } -static void ppc405_gpio_writeb (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif -} - -static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr) +static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { #ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - - return 0; -} - -static void ppc405_gpio_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif -} - -static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - - return 0; -} - -static void ppc405_gpio_writel (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); + printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", + __func__, addr, size, value); #endif } static const MemoryRegionOps ppc405_gpio_ops = { - .old_mmio = { - .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, }, - .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, }, - }, + .read = ppc405_gpio_read, + .write = ppc405_gpio_write, .endianness = DEVICE_NATIVE_ENDIAN, }; @@ -1017,44 +932,6 @@ struct ppc4xx_gpt_t { uint32_t mask[5]; }; -static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - /* XXX: generate a bus fault */ - return -1; -} - -static void ppc4xx_gpt_writeb (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - /* XXX: generate a bus fault */ -} - -static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr) -{ -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - /* XXX: generate a bus fault */ - return -1; -} - -static void ppc4xx_gpt_writew (void *opaque, - hwaddr addr, uint32_t value) -{ -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - /* XXX: generate a bus fault */ -} - static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) { /* XXX: TODO */ @@ -1107,7 +984,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) /* XXX: TODO */ } -static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) +static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { ppc4xx_gpt_t *gpt; uint32_t ret; @@ -1162,8 +1039,8 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr) return ret; } -static void ppc4xx_gpt_writel (void *opaque, - hwaddr addr, uint32_t value) +static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ppc4xx_gpt_t *gpt; int idx; @@ -1225,10 +1102,10 @@ static void ppc4xx_gpt_writel (void *opaque, } static const MemoryRegionOps gpt_ops = { - .old_mmio = { - .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, }, - .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, }, - }, + .read = ppc4xx_gpt_read, + .write = ppc4xx_gpt_write, + .valid.min_access_size = 4, + .valid.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, };