From patchwork Mon Jul 12 01:34:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 473368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC1B2C07E9E for ; Mon, 12 Jul 2021 01:38:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B857A61075 for ; Mon, 12 Jul 2021 01:38:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233017AbhGLBlg (ORCPT ); Sun, 11 Jul 2021 21:41:36 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6910 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232305AbhGLBlO (ORCPT ); Sun, 11 Jul 2021 21:41:14 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4GNRCK4mqgz78w3; Mon, 12 Jul 2021 09:34:53 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Mon, 12 Jul 2021 09:38:25 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 12 Jul 2021 09:38:24 +0800 From: Guangbin Huang To: , , CC: , , , , Subject: [PATCH net-next 3/9] net: hns3: add support for registering devlink for VF Date: Mon, 12 Jul 2021 09:34:52 +0800 Message-ID: <1626053698-46849-4-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> References: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Yufeng Mo Add devlink register support for HNS3 ethernet VF driver. Signed-off-by: Yufeng Mo Signed-off-by: Guangbin Huang --- .../net/ethernet/hisilicon/hns3/hns3vf/Makefile | 2 +- .../hisilicon/hns3/hns3vf/hclgevf_devlink.c | 54 ++++++++++++++++++++++ .../hisilicon/hns3/hns3vf/hclgevf_devlink.h | 15 ++++++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 8 ++++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 3 ++ 5 files changed, 81 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile b/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile index 2c26ea607a53..51ff7d86ee90 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile @@ -7,4 +7,4 @@ ccflags-y := -I $(srctree)/drivers/net/ethernet/hisilicon/hns3 ccflags-y += -I $(srctree)/$(src) obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o -hclgevf-objs = hclgevf_main.o hclgevf_cmd.o hclgevf_mbx.o +hclgevf-objs = hclgevf_main.o hclgevf_cmd.o hclgevf_mbx.o hclgevf_devlink.o diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c new file mode 100644 index 000000000000..55337a975981 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2021 Hisilicon Limited. */ + +#include + +#include "hclgevf_devlink.h" + +static const struct devlink_ops hclgevf_devlink_ops = { +}; + +int hclgevf_devlink_init(struct hclgevf_dev *hdev) +{ + struct pci_dev *pdev = hdev->pdev; + struct hclgevf_devlink_priv *priv; + struct devlink *devlink; + int ret; + + devlink = devlink_alloc(&hclgevf_devlink_ops, + sizeof(struct hclgevf_devlink_priv)); + if (!devlink) + return -ENOMEM; + + priv = devlink_priv(devlink); + priv->hdev = hdev; + + ret = devlink_register(devlink, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "failed to register devlink, ret = %d\n", + ret); + goto out_reg_fail; + } + + hdev->devlink = devlink; + + return 0; + +out_reg_fail: + devlink_free(devlink); + return ret; +} + +void hclgevf_devlink_uninit(struct hclgevf_dev *hdev) +{ + struct devlink *devlink = hdev->devlink; + + if (!devlink) + return; + + devlink_unregister(devlink); + + devlink_free(devlink); + + hdev->devlink = NULL; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h new file mode 100644 index 000000000000..e09ea3d8a963 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2021 Hisilicon Limited. */ + +#ifndef __HCLGEVF_DEVLINK_H +#define __HCLGEVF_DEVLINK_H + +#include "hclgevf_main.h" + +struct hclgevf_devlink_priv { + struct hclgevf_dev *hdev; +}; + +int hclgevf_devlink_init(struct hclgevf_dev *hdev); +void hclgevf_devlink_uninit(struct hclgevf_dev *hdev); +#endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c index 52eaf82b7cd7..1e03c4d16125 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c @@ -8,6 +8,7 @@ #include "hclgevf_main.h" #include "hclge_mbx.h" #include "hnae3.h" +#include "hclgevf_devlink.h" #define HCLGEVF_NAME "hclgevf" @@ -3327,6 +3328,10 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) if (ret) return ret; + ret = hclgevf_devlink_init(hdev); + if (ret) + goto err_devlink_init; + ret = hclgevf_cmd_queue_init(hdev); if (ret) goto err_cmd_queue_init; @@ -3431,6 +3436,8 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) err_cmd_init: hclgevf_cmd_uninit(hdev); err_cmd_queue_init: + hclgevf_devlink_uninit(hdev); +err_devlink_init: hclgevf_pci_uninit(hdev); clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state); return ret; @@ -3452,6 +3459,7 @@ static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev) } hclgevf_cmd_uninit(hdev); + hclgevf_devlink_uninit(hdev); hclgevf_pci_uninit(hdev); hclgevf_uninit_mac_list(hdev); } diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h index d7d02848d674..6f222a3a0bf2 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h @@ -6,6 +6,7 @@ #include #include #include +#include #include "hclge_mbx.h" #include "hclgevf_cmd.h" #include "hnae3.h" @@ -330,6 +331,8 @@ struct hclgevf_dev { u32 flag; unsigned long serv_processed_cnt; unsigned long last_serv_processed; + + struct devlink *devlink; }; static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev) From patchwork Mon Jul 12 01:34:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 473371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 337F6C07E96 for ; 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Mon, 12 Jul 2021 09:38:25 +0800 From: Guangbin Huang To: , , CC: , , , , Subject: [PATCH net-next 6/9] net: hns3: add devlink reload support for PF Date: Mon, 12 Jul 2021 09:34:55 +0800 Message-ID: <1626053698-46849-7-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> References: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Hao Chen Add devlink reload support for HNS3 ethernet PF driver. Signed-off-by: Hao Chen Signed-off-by: Guangbin Huang --- .../ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c index 7de423d510c5..facb10aea4e6 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c @@ -34,8 +34,75 @@ static int hclge_devlink_info_get(struct devlink *devlink, version_str); } +static int hclge_devlink_reload_down(struct devlink *devlink, bool netns_change, + enum devlink_reload_action action, + enum devlink_reload_limit limit, + struct netlink_ext_ack *extack) +{ + struct hclge_devlink_priv *priv = devlink_priv(devlink); + struct hclge_dev *hdev = priv->hdev; + struct hnae3_handle *h = &hdev->vport->nic; + struct pci_dev *pdev = hdev->pdev; + int ret; + + if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { + dev_err(&pdev->dev, "reset is handling\n"); + return -EBUSY; + } + + switch (action) { + case DEVLINK_RELOAD_ACTION_DRIVER_REINIT: + rtnl_lock(); + ret = hdev->nic_client->ops->reset_notify(h, HNAE3_DOWN_CLIENT); + if (ret) { + rtnl_unlock(); + return ret; + } + + ret = hdev->nic_client->ops->reset_notify(h, + HNAE3_UNINIT_CLIENT); + rtnl_unlock(); + return ret; + default: + return -EOPNOTSUPP; + } +} + +static int hclge_devlink_reload_up(struct devlink *devlink, + enum devlink_reload_action action, + enum devlink_reload_limit limit, + u32 *actions_performed, + struct netlink_ext_ack *extack) +{ + struct hclge_devlink_priv *priv = devlink_priv(devlink); + struct hclge_dev *hdev = priv->hdev; + struct hnae3_handle *h = &hdev->vport->nic; + int ret; + + *actions_performed = BIT(action); + switch (action) { + case DEVLINK_RELOAD_ACTION_DRIVER_REINIT: + hclge_devlink_get_param_setting(devlink); + rtnl_lock(); + ret = hdev->nic_client->ops->reset_notify(h, HNAE3_INIT_CLIENT); + if (ret) { + rtnl_unlock(); + return ret; + } + + ret = hdev->nic_client->ops->reset_notify(h, HNAE3_UP_CLIENT); + rtnl_unlock(); + return ret; + default: + return -EOPNOTSUPP; + } +} + static const struct devlink_ops hclge_devlink_ops = { .info_get = hclge_devlink_info_get, + .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT), + .reload_down = hclge_devlink_reload_down, + .reload_up = hclge_devlink_reload_up, }; int hclge_devlink_init(struct hclge_dev *hdev) @@ -62,6 +129,8 @@ int hclge_devlink_init(struct hclge_dev *hdev) hdev->devlink = devlink; + devlink_reload_enable(devlink); + return 0; out_reg_fail: @@ -76,6 +145,8 @@ void hclge_devlink_uninit(struct hclge_dev *hdev) if (!devlink) return; + devlink_reload_disable(devlink); + devlink_unregister(devlink); devlink_free(devlink); From patchwork Mon Jul 12 01:34:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 473370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9B1BC07E96 for ; Mon, 12 Jul 2021 01:38:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 927A961042 for ; Mon, 12 Jul 2021 01:38:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232828AbhGLBlU (ORCPT ); Sun, 11 Jul 2021 21:41:20 -0400 Received: from szxga08-in.huawei.com ([45.249.212.255]:11255 "EHLO szxga08-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232432AbhGLBlO (ORCPT ); Sun, 11 Jul 2021 21:41:14 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4GNR8z0jY2z1CHsW; Mon, 12 Jul 2021 09:32:51 +0800 (CST) Received: from dggemi759-chm.china.huawei.com (10.1.198.145) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Mon, 12 Jul 2021 09:38:25 +0800 Received: from localhost.localdomain (10.67.165.24) by dggemi759-chm.china.huawei.com (10.1.198.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 12 Jul 2021 09:38:25 +0800 From: Guangbin Huang To: , , CC: , , , , Subject: [PATCH net-next 8/9] net: hns3: add support for PF setting rx/tx buffer size by devlink param Date: Mon, 12 Jul 2021 09:34:57 +0800 Message-ID: <1626053698-46849-9-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> References: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Hao Chen Add support for PF setting rx/tx buffer size by devlink param Signed-off-by: Hao Chen Signed-off-by: Guangbin Huang --- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 1 + drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 8 +- .../ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c | 88 +++++++++++++++++++++- .../ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h | 7 ++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 3 + 5 files changed, 104 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index e0b7c3c44e7b..14934db9c59a 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -763,6 +763,7 @@ struct hnae3_knic_private_info { u16 num_tx_desc; u16 num_rx_desc; u32 tx_spare_buf_size; + u32 devlink_tx_spare_buf_size; struct hnae3_tc_info tc_info; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c index cdb5f14fb6bc..cdb473d26bcc 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c @@ -1037,8 +1037,12 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) dma_addr_t dma; int order; - alloc_size = tx_spare_buf_size ? tx_spare_buf_size : - ring->tqp->handle->kinfo.tx_spare_buf_size; + if (ring->tqp->handle->kinfo.devlink_tx_spare_buf_size) + alloc_size = ring->tqp->handle->kinfo.devlink_tx_spare_buf_size; + else if (tx_spare_buf_size) + alloc_size = tx_spare_buf_size; + else + alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size; if (!alloc_size) return; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c index facb10aea4e6..0fef8dec5327 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c @@ -34,6 +34,37 @@ static int hclge_devlink_info_get(struct devlink *devlink, version_str); } +static void hclge_devlink_get_param_setting(struct devlink *devlink) +{ + struct hclge_devlink_priv *priv = devlink_priv(devlink); + struct hclge_dev *hdev = priv->hdev; + struct pci_dev *pdev = hdev->pdev; + union devlink_param_value val; + int i, ret; + + ret = devlink_param_driverinit_value_get(devlink, + HCLGE_DEVLINK_PARAM_ID_RX_BUF_LEN, + &val); + if (!ret) { + hdev->rx_buf_len = val.vu32; + hdev->vport->nic.kinfo.rx_buf_len = hdev->rx_buf_len; + for (i = 0; i < hdev->num_tqps; i++) + hdev->htqp[i].q.buf_size = hdev->rx_buf_len; + } else { + dev_err(&pdev->dev, + "failed to get rx buffer size, ret = %d\n", ret); + } + + ret = devlink_param_driverinit_value_get(devlink, + HCLGE_DEVLINK_PARAM_ID_TX_BUF_SIZE, + &val); + if (!ret) + hdev->vport->nic.kinfo.devlink_tx_spare_buf_size = val.vu32; + else + dev_err(&pdev->dev, + "failed to get tx buffer size, ret = %d\n", ret); +} + static int hclge_devlink_reload_down(struct devlink *devlink, bool netns_change, enum devlink_reload_action action, enum devlink_reload_limit limit, @@ -105,6 +136,49 @@ static const struct devlink_ops hclge_devlink_ops = { .reload_up = hclge_devlink_reload_up, }; +static int hclge_devlink_rx_buffer_size_validate(struct devlink *devlink, + u32 id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ +#define HCLGE_RX_BUF_LEN_2K 2048 +#define HCLGE_RX_BUF_LEN_4K 4096 + + if (val.vu32 != HCLGE_RX_BUF_LEN_2K && + val.vu32 != HCLGE_RX_BUF_LEN_4K) { + NL_SET_ERR_MSG_MOD(extack, "Supported size is 2048 or 4096"); + return -EOPNOTSUPP; + } + + return 0; +} + +static const struct devlink_param hclge_devlink_params[] = { + DEVLINK_PARAM_DRIVER(HCLGE_DEVLINK_PARAM_ID_RX_BUF_LEN, + "rx_buffer_len", DEVLINK_PARAM_TYPE_U32, + BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), + NULL, NULL, + hclge_devlink_rx_buffer_size_validate), + DEVLINK_PARAM_DRIVER(HCLGE_DEVLINK_PARAM_ID_TX_BUF_SIZE, + "tx_buffer_size", DEVLINK_PARAM_TYPE_U32, + BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), + NULL, NULL, NULL), +}; + +void hclge_devlink_set_params_init_values(struct hclge_dev *hdev) +{ + union devlink_param_value value; + + value.vu32 = hdev->rx_buf_len; + devlink_param_driverinit_value_set(hdev->devlink, + HCLGE_DEVLINK_PARAM_ID_RX_BUF_LEN, + value); + value.vu32 = hdev->tx_spare_buf_size; + devlink_param_driverinit_value_set(hdev->devlink, + HCLGE_DEVLINK_PARAM_ID_TX_BUF_SIZE, + value); +} + int hclge_devlink_init(struct hclge_dev *hdev) { struct pci_dev *pdev = hdev->pdev; @@ -129,10 +203,20 @@ int hclge_devlink_init(struct hclge_dev *hdev) hdev->devlink = devlink; + ret = devlink_params_register(devlink, hclge_devlink_params, + ARRAY_SIZE(hclge_devlink_params)); + if (ret) { + dev_err(&pdev->dev, + "failed to register devlink params, ret = %d\n", ret); + goto out_param_reg_fail; + } + devlink_reload_enable(devlink); return 0; - +out_param_reg_fail: + hdev->devlink = NULL; + devlink_unregister(devlink); out_reg_fail: devlink_free(devlink); return ret; @@ -147,6 +231,8 @@ void hclge_devlink_uninit(struct hclge_dev *hdev) devlink_reload_disable(devlink); + devlink_params_unregister(devlink, hclge_devlink_params, + ARRAY_SIZE(hclge_devlink_params)); devlink_unregister(devlink); devlink_free(devlink); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h index 918be04507a5..e81402e68aa7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h @@ -6,10 +6,17 @@ #include "hclge_main.h" +enum hclge_devlink_param_id { + HCLGE_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + HCLGE_DEVLINK_PARAM_ID_RX_BUF_LEN, + HCLGE_DEVLINK_PARAM_ID_TX_BUF_SIZE, +}; + struct hclge_devlink_priv { struct hclge_dev *hdev; }; int hclge_devlink_init(struct hclge_dev *hdev); +void hclge_devlink_set_params_init_values(struct hclge_dev *hdev); void hclge_devlink_uninit(struct hclge_dev *hdev); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index adc20d6a23c3..fdf14470a846 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -11510,6 +11510,9 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) goto err_cmd_uninit; } + hclge_devlink_set_params_init_values(hdev); + devlink_params_publish(hdev->devlink); + ret = hclge_init_msi(hdev); if (ret) { dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); From patchwork Mon Jul 12 01:34:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "huangguangbin \(A\)" X-Patchwork-Id: 473369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5018C07E96 for ; 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Mon, 12 Jul 2021 09:38:25 +0800 From: Guangbin Huang To: , , CC: , , , , Subject: [PATCH net-next 9/9] net: hns3: add support for VF setting rx/tx buffer size by devlink param Date: Mon, 12 Jul 2021 09:34:58 +0800 Message-ID: <1626053698-46849-10-git-send-email-huangguangbin2@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> References: <1626053698-46849-1-git-send-email-huangguangbin2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To dggemi759-chm.china.huawei.com (10.1.198.145) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Hao Chen Add support for VF setting rx/tx buffer size by devlink param Signed-off-by: Hao Chen Signed-off-by: Guangbin Huang --- .../hisilicon/hns3/hns3vf/hclgevf_devlink.c | 88 +++++++++++++++++++++- .../hisilicon/hns3/hns3vf/hclgevf_devlink.h | 7 ++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 3 + 3 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c index bce598913dc3..4c364055e464 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c @@ -34,6 +34,37 @@ static int hclgevf_devlink_info_get(struct devlink *devlink, version_str); } +static void hclgevf_devlink_get_param_setting(struct devlink *devlink) +{ + struct hclgevf_devlink_priv *priv = devlink_priv(devlink); + struct hclgevf_dev *hdev = priv->hdev; + struct pci_dev *pdev = hdev->pdev; + union devlink_param_value val; + int i, ret; + + ret = devlink_param_driverinit_value_get(devlink, + HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + &val); + if (!ret) { + hdev->rx_buf_len = val.vu32; + hdev->nic.kinfo.rx_buf_len = hdev->rx_buf_len; + for (i = 0; i < hdev->num_tqps; i++) + hdev->htqp[i].q.buf_size = hdev->rx_buf_len; + } else { + dev_err(&pdev->dev, + "failed to get rx buffer size, ret = %d\n", ret); + } + + ret = devlink_param_driverinit_value_get(devlink, + HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, + &val); + if (!ret) + hdev->nic.kinfo.devlink_tx_spare_buf_size = val.vu32; + else + dev_err(&pdev->dev, + "failed to get tx buffer size, ret = %d\n", ret); +} + static int hclgevf_devlink_reload_down(struct devlink *devlink, bool netns_change, enum devlink_reload_action action, @@ -106,6 +137,49 @@ static const struct devlink_ops hclgevf_devlink_ops = { .reload_up = hclgevf_devlink_reload_up, }; +static int +hclgevf_devlink_rx_buffer_size_validate(struct devlink *devlink, u32 id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ +#define HCLGEVF_RX_BUF_LEN_2K 2048 +#define HCLGEVF_RX_BUF_LEN_4K 4096 + + if (val.vu32 != HCLGEVF_RX_BUF_LEN_2K && + val.vu32 != HCLGEVF_RX_BUF_LEN_4K) { + NL_SET_ERR_MSG_MOD(extack, "Supported size is 2048 or 4096"); + return -EOPNOTSUPP; + } + + return 0; +} + +static const struct devlink_param hclgevf_devlink_params[] = { + DEVLINK_PARAM_DRIVER(HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + "rx_buffer_len", DEVLINK_PARAM_TYPE_U32, + BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), + NULL, NULL, + hclgevf_devlink_rx_buffer_size_validate), + DEVLINK_PARAM_DRIVER(HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, + "tx_buffer_size", DEVLINK_PARAM_TYPE_U32, + BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), + NULL, NULL, NULL), +}; + +void hclgevf_devlink_set_params_init_values(struct hclgevf_dev *hdev) +{ + union devlink_param_value value; + + value.vu32 = hdev->rx_buf_len; + devlink_param_driverinit_value_set(hdev->devlink, + HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + value); + value.vu32 = 0; + devlink_param_driverinit_value_set(hdev->devlink, + HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, + value); +} + int hclgevf_devlink_init(struct hclgevf_dev *hdev) { struct pci_dev *pdev = hdev->pdev; @@ -130,10 +204,20 @@ int hclgevf_devlink_init(struct hclgevf_dev *hdev) hdev->devlink = devlink; + ret = devlink_params_register(devlink, hclgevf_devlink_params, + ARRAY_SIZE(hclgevf_devlink_params)); + if (ret) { + dev_err(&pdev->dev, + "failed to register devlink params, ret = %d\n", ret); + goto out_param_reg_fail; + } + devlink_reload_enable(devlink); return 0; - +out_param_reg_fail: + hdev->devlink = NULL; + devlink_unregister(devlink); out_reg_fail: devlink_free(devlink); return ret; @@ -148,6 +232,8 @@ void hclgevf_devlink_uninit(struct hclgevf_dev *hdev) devlink_reload_disable(devlink); + devlink_params_unregister(devlink, hclgevf_devlink_params, + ARRAY_SIZE(hclgevf_devlink_params)); devlink_unregister(devlink); devlink_free(devlink); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h index e09ea3d8a963..2159ec4a3523 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h @@ -6,10 +6,17 @@ #include "hclgevf_main.h" +enum hclgevf_devlink_param_id { + HCLGEVF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + HCLGEVF_DEVLINK_PARAM_ID_RX_BUF_LEN, + HCLGEVF_DEVLINK_PARAM_ID_TX_BUF_SIZE, +}; + struct hclgevf_devlink_priv { struct hclgevf_dev *hdev; }; +void hclgevf_devlink_set_params_init_values(struct hclgevf_dev *hdev); int hclgevf_devlink_init(struct hclgevf_dev *hdev); void hclgevf_devlink_uninit(struct hclgevf_dev *hdev); #endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c index 1e03c4d16125..ce7d652594e1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c @@ -3374,6 +3374,9 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev) goto err_config; } + hclgevf_devlink_set_params_init_values(hdev); + devlink_params_publish(hdev->devlink); + ret = hclgevf_alloc_tqps(hdev); if (ret) { dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);